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Mini Shell
Mini Shell
| Direktori : /usr/lib32/ |
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| Current File : //usr/lib32/libpmc_p.a |
!<arch>
/ 0 0 0 0 1022 `
2 c c c c
p_pmc_name_of_event pmc_allocate pmc_attach pmc_capabilities pmc_close_logfile pmc_configure_logfile pmc_cpuinfo pmc_detach pmc_disable pmc_enable pmc_event_names_of_class pmc_flush_logfile pmc_get_driver_stats pmc_get_msr pmc_init pmc_name_of_capability pmc_name_of_class pmc_name_of_cputype pmc_name_of_disposition pmc_name_of_event pmc_name_of_mode pmc_name_of_state pmc_ncpu pmc_npmc pmc_pmcinfo pmc_read pmc_release pmc_rw pmc_set pmc_start pmc_stop pmc_width pmc_write pmc_writelog pmclog_close pmclog_feed pmclog_open pmclog_read pmc_pmu_enabled pmc_pmu_event_get_by_idx pmc_pmu_idx_get_by_event pmc_pmu_pmcallocate pmc_pmu_print_counter_desc pmc_pmu_print_counter_desc_long pmc_pmu_print_counter_full pmc_pmu_print_counters pmc_pmu_sample_rate_get pmc_pmu_stat_mode _Z13event_to_jsonP9pmclog_ev pmu_events_map // 38 `
libpmc_pmu_util.po/
libpmc_events.po/
libpmc.po/ 0 0 0 100644 220856 `
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hwpmc INSTR_RETIRED_ANY CPU_CLK_UNHALTED_CORE CPU_CLK_UNHALTED_REF TSC FP_DISPATCHED_FPU_OPS FP_CYCLES_WITH_NO_FPU_OPS_RETIRED FP_DISPATCHED_FPU_FAST_FLAG_OPS LS_SEGMENT_REGISTER_LOAD LS_MICROARCHITECTURAL_RESYNC_BY_SELF_MODIFYING_CODE LS_MICROARCHITECTURAL_RESYNC_BY_SNOOP LS_BUFFER2_FULL LS_LOCKED_OPERATION LS_MICROARCHITECTURAL_LATE_CANCEL LS_RETIRED_CFLUSH_INSTRUCTIONS LS_RETIRED_CPUID_INSTRUCTIONS DC_ACCESS DC_MISS DC_REFILL_FROM_L2 DC_REFILL_FROM_SYSTEM DC_COPYBACK DC_L1_DTLB_MISS_AND_L2_DTLB_HIT DC_L1_DTLB_MISS_AND_L2_DTLB_MISS DC_MISALIGNED_DATA_REFERENCE DC_MICROARCHITECTURAL_LATE_CANCEL DC_MICROARCHITECTURAL_EARLY_CANCEL DC_ONE_BIT_ECC_ERROR DC_DISPATCHED_PREFETCH_INSTRUCTIONS DC_DCACHE_ACCESSES_BY_LOCKS BU_CPU_CLK_UNHALTED BU_INTERNAL_L2_REQUEST BU_FILL_REQUEST_L2_MISS BU_FILL_INTO_L2 IC_FETCH IC_MISS IC_REFILL_FROM_L2 IC_REFILL_FROM_SYSTEM IC_L1_ITLB_MISS_AND_L2_ITLB_HIT IC_L1_ITLB_MISS_AND_L2_ITLB_MISS IC_MICROARCHITECTURAL_RESYNC_BY_SNOOP IC_INSTRUCTION_FETCH_STALL IC_RETURN_STACK_HIT IC_RETURN_STACK_OVERFLOW FR_RETIRED_X86_INSTRUCTIONS FR_RETIRED_UOPS FR_RETIRED_BRANCHES FR_RETIRED_BRANCHES_MISPREDICTED FR_RETIRED_TAKEN_BRANCHES FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED FR_RETIRED_FAR_CONTROL_TRANSFERS FR_RETIRED_RESYNCS FR_RETIRED_NEAR_RETURNS FR_RETIRED_NEAR_RETURNS_MISPREDICTED FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED_BY_ADDR_MISCOMPARE FR_RETIRED_FPU_INSTRUCTIONS FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS FR_INTERRUPTS_MASKED_CYCLES FR_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES FR_TAKEN_HARDWARE_INTERRUPTS FR_DECODER_EMPTY FR_DISPATCH_STALLS FR_DISPATCH_STALL_FROM_BRANCH_ABORT_TO_RETIRE FR_DISPATCH_STALL_FOR_SERIALIZATION FR_DISPATCH_STALL_FOR_SEGMENT_LOAD FR_DISPATCH_STALL_WHEN_REORDER_BUFFER_IS_FULL FR_DISPATCH_STALL_WHEN_RESERVATION_STATIONS_ARE_FULL FR_DISPATCH_STALL_WHEN_FPU_IS_FULL FR_DISPATCH_STALL_WHEN_LS_IS_FULL FR_DISPATCH_STALL_WHEN_WAITING_FOR_ALL_TO_BE_QUIET FR_DISPATCH_STALL_WHEN_FAR_XFER_OR_RESYNC_BRANCH_PENDING FR_FPU_EXCEPTIONS FR_NUMBER_OF_BREAKPOINTS_FOR_DR0 FR_NUMBER_OF_BREAKPOINTS_FOR_DR1 FR_NUMBER_OF_BREAKPOINTS_FOR_DR2 FR_NUMBER_OF_BREAKPOINTS_FOR_DR3 NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT NB_MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOW NB_MEMORY_CONTROLLER_DRAM_COMMAND_SLOTS_MISSED NB_MEMORY_CONTROLLER_TURNAROUND NB_MEMORY_CONTROLLER_BYPASS_SATURATION NB_SIZED_COMMANDS NB_PROBE_RESULT NB_HT_BUS0_BANDWIDTH NB_HT_BUS1_BANDWIDTH NB_HT_BUS2_BANDWIDTH PMNC_SW_INCR L1_ICACHE_REFILL ITLB_REFILL L1_DCACHE_REFILL L1_DCACHE_ACCESS DTLB_REFILL MEM_READ MEM_WRITE EXC_TAKEN EXC_EXECUTED CID_WRITE PC_WRITE PC_IMM_BRANCH MEM_UNALIGNED_ACCESS PC_BRANCH_MIS_PRED CLOCK_CYCLES PC_BRANCH_PRED INSTR_EXECUTED PC_PROC_RETURN MEM_ACCESS L1_ICACHE_ACCESS L1_DCACHE_WB L2_CACHE_ACCESS L2_CACHE_REFILL L2_CACHE_WB BUS_ACCESS MEM_ERROR INSTR_SPEC TTBR_WRITE BUS_CYCLES CPU_CYCLES WRITE_BUF_FULL L2_STORE_MERGED L2_STORE_BUFFERABLE L2_ACCESS L2_CACHE_MISS AXI_READ AXI_WRITE MEM_REPLAY_EVT MEM_UNALIGNED_ACCESS_REPLAY L1_DCACHE_HASH_MISS L1_ICACHE_HASH_MISS L1_CACHE_PAGECOL_ALIAS L1_DCACHE_NEON_ACCESS L1_DCACHE_NEON_CACHEABLE L2_CACHE_NEON_MEM_ACCESS L2_CACHE_NEON_HIT L1_CACHE_ACCESS_NOCP15 RET_STACK_MISPREDICT BRANCH_DIR_MISPREDICT PRED_BRANCH_PRED_TAKEN PRED_BRANCH_EXEC_TAKEN OPS_ISSUED CYCLES_NO_INSTRUCTION INSTRUCTIONS_ISSUED_CYCLE CYCLES_STALLED_NEON_MRC CYCLES_STALLED_NEON_FULLQ CYCLES_NONIDLE_NEON_INT PMUEXTIN0_EVT PMUEXTIN1_EVT PMUEXTIN_EVT JAVA_BYTECODE SOFTWARE_JAVA_BYTECODE JAZELLE_BACKWARD_BRANCH COHERENT_LINEFILL_MISSC COHERENT_LINEFILL_HITC INSTR_CACHE_DEPENDENT_STALL DATA_CACHE_DEPENDENT_STALL MAIN_TLB_MISS_STALL STREX_PASSED STREX_FAILED DATA_EVICTION ISSUE_DNOT_DISPATCH_ANY_INSTR ISSUE_IS_EMPTY INSTR_RENAMED PREDICTABLE_FUNCTION_RETURN MAIN_EXECUTION_UNIT_PIPE SECOND_EXECUTION_UNIT_PIPE LOAD_STORE_PIPE FLOATING_POINT_INSTR_RENAMED NEON_INSTRS_RENAMED PLD_STALL WRITE_STALL INSTR_MAIN_TLB_MISS_STALL DATA_MAIN_TLB_MISS_STALL INSTR_MICRO_TLB_MISS_STALL DATA_MICRO_TLB_MISS_STALL DMB_STALL INTEGER_CORE_CLOCK_ENABLED DATA_ENGINE_CLOCK_ENABLED ISB DSB DMB EXTERNAL_INTERRUPT PLE_CACHE_LINE_REQ_COMPLETED PLE_CACHE_LINE_REQ_SKIPPED PLE_FIFO_FLUSH PLE_REQUEST_COMPLETED PLE_FIFO_OVERFLOW PLE_REQUEST_PROGRAMMED SW_INCR L1I_CACHE_REFILL L1I_TLB_REFILL L1D_CACHE_REFILL L1D_CACHE L1D_TLB_REFILL INST_RETIRED EXC_RETURN CID_WRITE_RETIRED BR_MIS_PRED BR_PRED L1I_CACHE L1D_CACHE_WB L2D_CACHE L2D_CACHE_REFILL L2D_CACHE_WB MEMORY_ERROR CHAIN BUS_ACCESS_LD BUS_ACCESS_ST BR_INDIRECT_SPEC EXC_IRQ EXC_FIQ LD_RETIRED ST_RETIRED PC_WRITE_RETIRED BR_IMMED_RETIRED BR_RETURN_RETIRED UNALIGNED_LDST_RETIRED INST_SPEC TTBR_WRITE_RETIRED L1D_CACHE_LD L1D_CACHE_ST L1D_CACHE_REFILL_LD L1D_CACHE_REFILL_ST L1D_CACHE_WB_VICTIM L1D_CACHE_WB_CLEAN L1D_CACHE_INVAL L1D_TLB_REFILL_LD L1D_TLB_REFILL_ST L2D_CACHE_LD L2D_CACHE_ST L2D_CACHE_REFILL_LD L2D_CACHE_REFILL_ST L2D_CACHE_WB_VICTIM L2D_CACHE_WB_CLEAN L2D_CACHE_INVAL MEM_ACCESS_LD MEM_ACCESS_ST UNALIGNED_LD_SPEC UNALIGNED_ST_SPEC UNALIGNED_LDST_SPEC LDREX_SPEC STREX_PASS_SPEC STREX_FAIL_SPEC LD_SPEC ST_SPEC LDST_SPEC DP_SPEC ASE_SPEC VFP_SPEC PC_WRITE_SPEC CRYPTO_SPEC BR_IMMED_SPEC BR_RETURN_SPEC ISB_SPEC DSB_SPEC DMB_SPEC EXC_UNDEF EXC_SVC EXC_PABORT EXC_DABORT EXC_SMC EXC_HVC EXC_TRAP_PABORT EXC_TRAP_DABORT EXC_TRAP_OTHER EXC_TRAP_IRQ EXC_TRAP_FIQ RC_LD_SPEC RC_ST_SPEC BUS_ACCESS_SHARED BUS_ACCESS_NOT_SHARED BUS_ACCESS_NORMAL BUS_ACCESS_PERIPH L2D_CACHE_ALLOCATE BR_RETIRED BR_MIS_PRED_RETIRED STALL_FRONTEND STALL_BACKEND L1D_TLB L1I_TLB L3D_CACHE_ALLOCATE L3D_CACHE_REFILL L3D_CACHE L2D_TLB_REFILL L2D_TLB REMOTE_ACCESS DTLB_WALK ITLB_WALK LL_CACHE_RD LL_CACHE_MISS_RD L1D_CACHE_REFILL_INNER L1D_CACHE_REFILL_OUTER L1D_TLB_RD L1D_TLB_WR L2D_TLB_REFILL_RD L2D_TLB_REFILL_WR L2D_TLB_RD L2D_TLB_WR STREX_SPEC L3_CACHE_RD CYCLE INST INST_USER INST_KERNEL IMPRECISE_SETBOUNDS UNREPRESENTABLE_CAPS ITLB_MISS DTLB_MISS ICACHE_WRITE_HIT ICACHE_WRITE_MISS ICACHE_READ_HIT ICACHE_READ_MISS ICACHE_EVICT DCACHE_WRITE_HIT DCACHE_WRITE_MISS DCACHE_READ_HIT DCACHE_READ_MISS DCACHE_EVICT DCACHE_SET_TAG_WRITE DCACHE_SET_TAG_READ L2CACHE_WRITE_HIT L2CACHE_WRITE_MISS L2CACHE_READ_HIT L2CACHE_READ_MISS L2CACHE_EVICT L2CACHE_SET_TAG_WRITE L2CACHE_SET_TAG_READ MEM_BYTE_READ MEM_BYTE_WRITE MEM_HWORD_READ MEM_HWORD_WRITE MEM_WORD_READ MEM_WORD_WRITE MEM_DWORD_READ MEM_DWORD_WRITE MEM_CAP_READ MEM_CAP_WRITE MEM_CAP_READ_TAG_SET MEM_CAP_WRITE_TAG_SET TAGCACHE_WRITE_HIT TAGCACHE_WRITE_MISS TAGCACHE_READ_HIT TAGCACHE_READ_MISS TAGCACHE_EVICT L2CACHEMASTER_READ_REQ L2CACHEMASTER_WRITE_REQ L2CACHEMASTER_WRITE_REQ_FLIT L2CACHEMASTER_READ_RSP L2CACHEMASTER_READ_RSP_FLIT L2CACHEMASTER_WRITE_RSP TAGCACHEMASTER_READ_REQ TAGCACHEMASTER_WRITE_REQ TAGCACHEMASTER_WRITE_REQ_FLIT TAGCACHEMASTER_READ_RSP TAGCACHEMASTER_READ_RSP_FLIT TAGCACHEMASTER_WRITE_RSP BRANCH_COMPLETED BRANCH_MISPRED RETURN RETURN_MISPRED RETURN_NOT_31 RETURN_NOTPRED ITLB_ACCESS DTLB_ACCESS JTLB_IACCESS JTLB_IMISS JTLB_DACCESS JTLB_DMISS DC_LOADSTORE DC_WRITEBACK STORE_MISS LOAD_MISS INTEGER_COMPLETED FP_COMPLETED LOAD_COMPLETED STORE_COMPLETED BARRIER_COMPLETED MIPS16_COMPLETED NOP_COMPLETED INTEGER_MULDIV_COMPLETED RF_STALL INSTR_REFETCH STORE_COND_COMPLETED STORE_COND_FAILED ICACHE_REQUESTS ICACHE_HIT L2_WRITEBACK L2_MISS L2_ERR_CORRECTED EXCEPTIONS RF_CYCLES_STALLED IFU_CYCLES_STALLED ALU_CYCLES_STALLED UNCACHED_LOAD UNCACHED_STORE CP2_REG_TO_REG_COMPLETED MFTC_COMPLETED IC_BLOCKED_CYCLES DC_BLOCKED_CYCLES L2_IMISS_STALL_CYCLES L2_DMISS_STALL_CYCLES DMISS_CYCLES L2_MISS_CYCLES UNCACHED_BLOCK_CYCLES MDU_STALL_CYCLES FPU_STALL_CYCLES CP2_STALL_CYCLES COREXTEND_STALL_CYCLES ISPRAM_STALL_CYCLES DSPRAM_STALL_CYCLES CACHE_STALL_CYCLES LOAD_TO_USE_STALLS BASE_MISPRED_STALLS CPO_READ_STALLS BRANCH_MISPRED_CYCLES IFETCH_BUFFER_FULL FETCH_BUFFER_ALLOCATED EJTAG_ITRIGGER EJTAG_DTRIGGER FSB_LT_QUARTER FSB_QUARTER_TO_HALF FSB_GT_HALF FSB_FULL_PIPELINE_STALLS LDQ_LT_QUARTER LDQ_QUARTER_TO_HALF LDQ_GT_HALF LDQ_FULL_PIPELINE_STALLS WBB_LT_QUARTER WBB_QUARTER_TO_HALF WBB_GT_HALF WBB_FULL_PIPELINE_STALLS REQUEST_LATENCY REQUEST_COUNT CYCLES PREDICTED_JR_31 JR_31_MISPREDICTIONS REDIRECT_STALLS JR_31_NO_PREDICTIONS ITLB_ACCESSES ITLB_MISSES JTLB_INSN_MISSES ICACHE_ACCESSES ICACHE_MISSES ICACHE_MISS_STALLS UNCACHED_IFETCH_STALLS PDTRACE_BACK_STALLS IFU_REPLAYS KILLED_FETCH_SLOTS IFU_IDU_MISS_PRED_UPSTREAM_CYCLES IFU_IDU_NO_FETCH_CYCLES IFU_IDU_CLOGED_DOWNSTREAM_CYCLES DDQ0_FULL_DR_STALLS DDQ1_FULL_DR_STALLS ALCB_FULL_DR_STALLS AGCB_FULL_DR_STALLS CLDQ_FULL_DR_STALLS IODQ_FULL_DR_STALLS ALU_EMPTY_CYCLES AGEN_EMPTY_CYCLES ALU_OPERANDS_NOT_READY_CYCLES AGEN_OPERANDS_NOT_READY_CYCLES ALU_NO_ISSUES_CYCLES AGEN_NO_ISSUES_CYCLES ALU_BUBBLE_CYCLES AGEN_BUBBLE_CYCLES SINGLE_ISSUE_CYCLES DUAL_ISSUE_CYCLES OOO_ALU_ISSUE_CYCLES OOO_AGEN_ISSUE_CYCLES JALR_JALR_HB_INSNS DCACHE_LINE_REFILL_REQUESTS DCACHE_LOAD_ACCESSES DCACHE_ACCESSES DCACHE_WRITEBACKS DCACHE_MISSES JTLB_DATA_ACCESSES JTLB_DATA_MISSES LOAD_STORE_REPLAYS VA_TRANSALTION_CORNER_CASES LOAD_STORE_BLOCKED_CYCLES LOAD_STORE_NO_FILL_REQUESTS L2_CACHE_WRITEBACKS L2_CACHE_ACCESSES L2_CACHE_MISSES L2_CACHE_MISS_CYCLES FSB_FULL_STALLS FSB_OVER_50_FULL LDQ_FULL_STALLS LDQ_OVER_50_FULL WBB_FULL_STALLS WBB_OVER_50_FULL LOAD_MISS_CONSUMER_REPLAYS CP1_CP2_LOAD_INSNS JR_NON_31_INSNS MISPREDICTED_JR_31_INSNS BRANCH_INSNS CP1_CP2_COND_BRANCH_INSNS BRANCH_LIKELY_INSNS MISPREDICTED_BRANCH_LIKELY_INSNS COND_BRANCH_INSNS MISPREDICTED_BRANCH_INSNS INTEGER_INSNS FPU_INSNS LOAD_INSNS STORE_INSNS J_JAL_INSNS MIPS16_INSNS NOP_INSNS NT_MUL_DIV_INSNS DSP_INSNS ALU_DSP_SATURATION_INSNS DSP_BRANCH_INSNS MDU_DSP_SATURATION_INSNS UNCACHED_LOAD_INSNS UNCACHED_STORE_INSNS EJTAG_INSN_TRIGGERS CP1_BRANCH_MISPREDICTIONS SC_INSNS FAILED_SC_INSNS PREFETCH_INSNS CACHE_HIT_PREFETCH_INSNS NO_INSN_CYCLES LOAD_MISS_INSNS ONE_INSN_CYCLES TWO_INSNS_CYCLES GFIFO_BLOCKED_CYCLES CP1_CP2_STORE_INSNS MISPREDICTION_STALLS MISPREDICTED_BRANCH_INSNS_CYCLES EXCEPTIONS_TAKEN GRADUATION_REPLAYS COREEXTEND_EVENTS ISPRAM_EVENTS DSPRAM_EVENTS L2_CACHE_SINGLE_BIT_ERRORS SYSTEM_EVENT_0 SYSTEM_EVENT_1 SYSTEM_EVENT_2 SYSTEM_EVENT_3 SYSTEM_EVENT_4 SYSTEM_EVENT_5 SYSTEM_EVENT_6 SYSTEM_EVENT_7 OCP_ALL_REQUESTS OCP_ALL_CACHEABLE_REQUESTS OCP_READ_REQUESTS OCP_READ_CACHEABLE_REQUESTS OCP_WRITE_REQUESTS OCP_WRITE_CACHEABLE_REQUESTS FSB_LESS_25_FULL FSB_25_50_FULL LDQ_LESS_25_FULL LDQ_25_50_FULL WBB_LESS_25_FULL WBB_25_50_FULL CLK ISSUE RET NISSUE SISSUE DISSUE IFI BR BRMIS J JMIS REPLAY IUNA TRAP UULOAD UUSTORE ULOAD USTORE EC MC CC CSRC CFETCH CPREF ICA II IP CIMISS WBUF WDAT WBUFLD WBUFFL WBUFTR BADD BADDL2 BFILL DDIDS IDIDS DIDNA LDS LMLDS IOLDS DMLDS STS LMSTS IOSTS IOBDMA DTLB DTLBAD ITLB SYNC SYNCIOB SYNCW INSTR_COMPLETED TLB_BIT_TRANSITIONS INSTR_DISPATCHED PMON_EXCEPT PMON_SIG VPU_INSTR_COMPLETED VFPU_INSTR_COMPLETED VIU1_INSTR_COMPLETED VIU2_INSTR_COMPLETED MTVSCR_INSTR_COMPLETED MTVRSAVE_INSTR_COMPLETED VPU_INSTR_WAIT_CYCLES VFPU_INSTR_WAIT_CYCLES VIU1_INSTR_WAIT_CYCLES VIU2_INSTR_WAIT_CYCLES MFVSCR_SYNC_CYCLES VSCR_SAT_SET STORE_INSTR_COMPLETED L1_INSTR_CACHE_MISSES L1_DATA_SNOOPS UNRESOLVED_BRANCHES SPEC_BUFFER_CYCLES BRANCH_UNIT_STALL_CYCLES TRUE_BRANCH_TARGET_HITS BRANCH_LINK_STAC_PREDICTED GPR_ISSUE_QUEUE_DISPATCHES CYCLES_THREE_INSTR_DISPATCHED THRESHOLD_INSTR_QUEUE_ENTRIES_CYCLES THRESHOLD_VEC_INSTR_QUEUE_ENTRIES_CYCLES CYCLES_NO_COMPLETED_INSTRS IU2_INSTR_COMPLETED BRANCHES_COMPLETED EIEIO_INSTR_COMPLETED MTSPR_INSTR_COMPLETED SC_INSTR_COMPLETED LS_LM_COMPLETED ITLB_HW_TABLE_SEARCH_CYCLES DTLB_HW_SEARCH_CYCLES_OVER_THRESHOLD L1_INSTR_CACHE_ACCESSES INSTR_BKPT_MATCHES L1_DATA_CACHE_LOAD_MISS_CYCLES_OVER_THRESHOLD L1_DATA_SNOOP_HIT_ON_MODIFIED LOAD_MISS_ALIAS LOAD_MISS_ALIAS_ON_TOUCH TOUCH_ALIAS L1_DATA_SNOOP_HIT_CASTOUT_QUEUE L1_DATA_SNOOP_HIT_CASTOUT L1_DATA_SNOOP_HITS WRITE_THROUGH_STORES CACHE_INHIBITED_STORES L1_DATA_LOAD_HIT L1_DATA_TOUCH_HIT L1_DATA_STORE_HIT L1_DATA_TOTAL_HITS DST_INSTR_DISPATCHED REFRESHED_DSTS SUCCESSFUL_DST_TABLE_SEARCHES DSS_INSTR_COMPLETED DST_STREAM_0_CACHE_LINE_FETCHES VTQ_SUSPENDS_DUE_TO_CTX_CHANGE VTQ_LINE_FETCH_HIT VEC_LOAD_INSTR_COMPLETED FP_STORE_INSTR_COMPLETED_IN_LSU FPU_RENORMALIZATION FPU_DENORMALIZATION FP_STORE_CAUSES_STALL_IN_LSU LD_ST_TRUE_ALIAS_STALL LSU_INDEXED_ALIAS_STALL LSU_ALIAS_VS_FSQ_WB0_WB1 LSU_ALIAS_VS_CSQ LSU_LOAD_HIT_LINE_ALIAS_VS_CSQ0 LSU_LOAD_MISS_LINE_ALIAS_VS_CSQ0 LSU_TOUCH_LINE_ALIAS_VS_FSQ_WB0_WB1 LSU_TOUCH_ALIAS_VS_CSQ LSU_LMQ_FULL_STALL FP_LOAD_INSTR_COMPLETED_IN_LSU FP_LOAD_SINGLE_INSTR_COMPLETED_IN_LSU FP_LOAD_DOUBLE_COMPLETED_IN_LSU LSU_RA_LATCH_STALL LSU_LOAD_VS_STORE_QUEUE_ALIAS_STALL LSU_LMQ_INDEX_ALIAS LSU_STORE_QUEUE_INDEX_ALIAS LSU_CSQ_FORWARDING LSU_MISALIGNED_LOAD_FINISH LSU_MISALIGN_STORE_COMPLETED LSU_MISALIGN_STALL FP_ONE_QUARTER_FPSCR_RENAMES_BUSY FP_ONE_HALF_FPSCR_RENAMES_BUSY FP_THREE_QUARTERS_FPSCR_RENAMES_BUSY FP_ALL_FPSCR_RENAMES_BUSY FP_DENORMALIZED_RESULT L1_DATA_TOTAL_MISSES DISPATCHES_TO_FPR_ISSUE_QUEUE LSU_INSTR_COMPLETED LOAD_INSTR_COMPLETED SS_SM_INSTR_COMPLETED TLBIE_INSTR_COMPLETED LWARX_INSTR_COMPLETED MFSPR_INSTR_COMPLETED REFETCH_SERIALIZATION COMPLETION_QUEUE_ENTRIES_OVER_THRESHOLD CYCLES_ONE_INSTR_DISPATCHED CYCLES_TWO_INSTR_COMPLETED ITLB_NON_SPECULATIVE_MISSES CYCLES_WAITING_FROM_L1_INSTR_CACHE_MISS L1_DATA_LOAD_ACCESS_MISS L1_DATA_TOUCH_MISS L1_DATA_STORE_MISS L1_DATA_TOUCH_MISS_CYCLES L1_DATA_CYCLES_USED DST_STREAM_1_CACHE_LINE_FETCHES VTQ_STREAM_CANCELED_PREMATURELY VTQ_RESUMES_DUE_TO_CTX_CHANGE VTQ_LINE_FETCH_MISS VTQ_LINE_FETCH TLBIE_SNOOPS L1_INSTR_CACHE_RELOADS L1_DATA_CACHE_RELOADS L1_DATA_CACHE_CASTOUTS_TO_L2 STORE_MERGE_GATHER CACHEABLE_STORE_MERGE_TO_32_BYTES DATA_BKPT_MATCHES FALL_THROUGH_BRANCHES_PROCESSED FIRST_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLY SECOND_SPECULATION_BUFFER_ACTIVE BPU_STALL_ON_LR_DEPENDENCY BTIC_MISS BRANCH_LINK_STACK_CORRECTLY_RESOLVED FPR_ISSUE_STALLED SWITCHES_BETWEEN_PRIV_USER LSU_COMPLETES_FP_STORE_SINGLE VR_ISSUE_QUEUE_DISPATCHES VR_STALLS GPR_RENAME_BUFFER_ENTRIES_OVER_THRESHOLD FPR_ISSUE_QUEUE_ENTRIES FPU_INSTR_COMPLETED STWCX_INSTR_COMPLETED LS_LM_INSTR_PIECES ITLB_HW_SEARCH_CYCLES_OVER_THRESHOLD DTLB_MISSES CANCELLED_L1_INSTR_CACHE_MISSES L1_DATA_CACHE_OP_HIT L1_DATA_LOAD_MISS_CYCLES L1_DATA_PUSHES L1_DATA_TOTAL_MISS VT2_FETCHES TAKEN_BRANCHES_PROCESSED BRANCH_FLUSHES SECOND_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLY THIRD_SPECULATION_BUFFER_ACTIVE BRANCH_UNIT_STALL_ON_CTR_DEPENDENCY FAST_BTIC_HIT BRANCH_LINK_STACK_MISPREDICTED CYCLES_THREE_INSTR_COMPLETED CYCLES_NO_INSTR_DISPATCHED GPR_ISSUE_QUEUE_ENTRIES_OVER_THRESHOLD GPR_ISSUE_QUEUE_STALLED IU1_INSTR_COMPLETED DSSALL_INSTR_COMPLETED TLBSYNC_INSTR_COMPLETED SYNC_INSTR_COMPLETED SS_SM_INSTR_PIECES DTLB_HW_SEARCH_CYCLES SNOOP_RETRIES SUCCESSFUL_STWCX DST_STREAM_3_CACHE_LINE_FETCHES THIRD_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLY MISPREDICTED_BRANCHES FOLDED_BRANCHES FP_STORE_DOUBLE_COMPLETES_IN_LSU L2_CACHE_HITS L3_CACHE_HITS L2_INSTR_CACHE_MISSES L3_INSTR_CACHE_MISSES L2_DATA_CACHE_MISSES L3_DATA_CACHE_MISSES L2_LOAD_HITS L2_STORE_HITS L3_LOAD_HITS L3_STORE_HITS L2_TOUCH_HITS L3_TOUCH_HITS SNOOP_MODIFIED SNOOP_VALID INTERVENTION L3_CACHE_MISSES L2_CACHE_CASTOUTS L3_CACHE_CASTOUTS L2SQ_FULL_CYCLES L3SQ_FULL_CYCLES RAQ_FULL_CYCLES WAQ_FULL_CYCLES L1_EXTERNAL_INTERVENTIONS L2_EXTERNAL_INTERVENTIONS L3_EXTERNAL_INTERVENTIONS EXTERNAL_INTERVENTIONS EXTERNAL_PUSHES EXTERNAL_SNOOP_RETRY DTQ_FULL_CYCLES BUS_RETRY L2_VALID_REQUEST BORDQ_FULL BUS_TAS_FOR_READS BUS_TAS_FOR_WRITES BUS_READS_NOT_RETRIED BUS_WRITES_NOT_RETRIED BUS_READS_WRITES_NOT_RETRIED BUS_RETRY_DUE_TO_L1_RETRY BUS_RETRY_DUE_TO_PREVIOUS_ADJACENT BUS_RETRY_DUE_TO_COLLISION BUS_RETRY_DUE_TO_INTERVENTION_ORDERING SNOOP_REQUESTS PREFETCH_ENGINE_REQUEST PREFETCH_ENGINE_COLLISION_VS_LOAD PREFETCH_ENGINE_COLLISION_VS_STORE PREFETCH_ENGINE_COLLISION_VS_INSTR_FETCH PREFETCH_ENGINE_COLLISION_VS_LOAD_STORE_INSTR_FETCH PREFETCH_ENGINE_FULL MARKED_GROUP_DISPATCH MARKED_STORE_COMPLETED GCT_EMPTY RUN_CYCLES OVERFLOW THRESHOLD_TIMEOUT GROUP_DISPATCH BR_MARKED_INSTR_FINISH GCT_EMPTY_BY_SRQ_FULL STOP_COMPLETION LSU_EMPTY MARKED_STORE_WITH_INTR CYCLES_IN_SUPER VPU_MARKED_INSTR_COMPLETED FXU0_IDLE_FXU1_BUSY SRQ_EMPTY MARKED_GROUP_COMPLETED CR_MARKED_INSTR_FINISH DISPATCH_SUCCESS FXU0_IDLE_FXU1_IDLE ONE_PLUS_INSTR_COMPLETED GROUP_MARKED_IDU MARKED_GROUP_COMPLETE_TIMEOUT FXU0_BUSY_FXU1_BUSY MARKED_STORE_SENT_TO_STS FXU_MARKED_INSTR_FINISHED MARKED_GROUP_ISSUED FXU0_BUSY_FXU1_IDLE GROUP_COMPLETED FPU_MARKED_INSTR_COMPLETED MARKED_INSTR_FINISH_ANY_UNIT GROUP_DISPATCH_REJECT LSU_MARKED_INSTR_FINISH TIMEBASE_EVENT LSU_COMPLETION_STALL FXU_COMPLETION_STALL DCACHE_MISS_COMPLETION_STALL FPU_COMPLETION_STALL FXU_LONG_INSTR_COMPLETION_STALL REJECT_COMPLETION_STALL FPU_LONG_INSTR_COMPLETION_STALL GCT_EMPTY_BY_ICACHE_MISS REJECT_COMPLETION_STALL_ERAT_MISS GCT_EMPTY_BY_BRANCH_MISS_PREDICT BUS_HIGH BUS_LOW ADDER CYCLES_WITH_INSTRS_COMPLETED ERAT_INSTR_MISS CYCLES_IDLE CYCLES_WITH_ANY_THREAD_RUNNING CYCLES_RUNNING ERAT_DATA_MISS BRANCH_TAKEN L1_INSTR_MISS L2_LOAD_MISS STORE_NO_REAL_ADDR INSTR_COMPLETED_WITH_ALL_THREADS_RUNNING L1_LOAD_MISS L3_INSTR_MISS TLB_DATA_MISS L3_LOAD_MISS LOAD_NO_REAL_ADDR CYCLES_WITH_INSTRS_DISPATCHED CYCLES_RUNNING_PURR_INC BRANCH_MISPREDICTED PREFETCHED_INSTRS_DISCARDED INSTR_COMPLETED_RUNNING TLB_INSTR_MISS CACHE_LOAD_MISS UOPS_COMPLETED INSTR_FETCHED UOPS_DECODED PM_EVENT_TRANSITIONS PM_EVENT_CYCLES BRANCH_INSTRS_COMPLETED LOAD_UOPS_COMPLETED STORE_UOPS_COMPLETED CQ_REDIRECTS BRANCHES_FINISHED TAKEN_BRANCHES_FINISHED FINISHED_UNCOND_BRANCHES_MISS_BTB BTB_BRANCH_MISPRED_FROM_DIRECTION BTB_HITS_PSEUDO_HITS CYCLES_DECODE_STALLED CYCLES_ISSUE_STALLED CYCLES_BRANCH_ISSUE_STALLED CYCLES_SU1_SCHED_STALLED CYCLES_SU2_SCHED_STALLED CYCLES_MU_SCHED_STALLED CYCLES_LRU_SCHED_STALLED CYCLES_BU_SCHED_STALLED TOTAL_TRANSLATED LOADS_TRANSLATED STORES_TRANSLATED TOUCHES_TRANSLATED CACHEOPS_TRANSLATED CACHE_INHIBITED_ACCESS_TRANSLATED GUARDED_LOADS_TRANSLATED WRITE_THROUGH_STORES_TRANSLATED MISALIGNED_LOAD_STORE_ACCESS_TRANSLATED TOTAL_ALLOCATED_TO_DLFB LOADS_TRANSLATED_ALLOCATED_TO_DLFB STORES_COMPLETED_ALLOCATED_TO_DLFB TOUCHES_TRANSLATED_ALLOCATED_TO_DLFB STORES_COMPLETED DATA_L1_CACHE_LOCKS DATA_L1_CACHE_RELOADS DATA_L1_CACHE_CASTOUTS LOAD_MISS_DLFB_FULL LOAD_MISS_LDQ_FULL LOAD_GUARDED_MISS STORE_TRANSLATE_WHEN_QUEUE_FULL ADDRESS_COLLISION DATA_MMU_MISS DATA_MMU_BUSY PART2_MISALIGNED_CACHE_ACCESS LOAD_MISS_DLFB_FULL_CYCLES LOAD_MISS_LDQ_FULL_CYCLES LOAD_GUARDED_MISS_CYCLES STORE_TRANSLATE_WHEN_QUEUE_FULL_CYCLES ADDRESS_COLLISION_CYCLES DATA_MMU_MISS_CYCLES DATA_MMU_BUSY_CYCLES PART2_MISALIGNED_CACHE_ACCESS_CYCLES INSTR_L1_CACHE_LOCKS INSTR_L1_CACHE_RELOADS INSTR_L1_CACHE_FETCHES INSTR_MMU_TLB4K_RELOADS INSTR_MMU_VSP_RELOADS DATA_MMU_TLB4K_RELOADS DATA_MMU_VSP_RELOADS L2MMU_MISSES BIU_MASTER_REQUESTS BIU_MASTER_INSTR_SIDE_REQUESTS BIU_MASTER_DATA_SIDE_REQUESTS BIU_MASTER_DATA_SIDE_CASTOUT_REQUESTS BIU_MASTER_RETRIES SNOOP_HITS SNOOP_PUSHES DLFB_LOAD_MISS_CYCLES ILFB_FETCH_MISS_CYCLES EXT_INPU_INTR_LATENCY_CYCLES CRIT_INPUT_INTR_LATENCY_CYCLES EXT_INPUT_INTR_PENDING_LATENCY_CYCLES CRIT_INPUT_INTR_PENDING_LATENCY_CYCLES PMC0_OVERFLOW PMC1_OVERFLOW PMC2_OVERFLOW PMC3_OVERFLOW INTERRUPTS_TAKEN EXT_INPUT_INTR_TAKEN CRIT_INPUT_INTR_TAKEN SYSCALL_TRAP_INTR L2_LINEFILL_BUFFER LV2_VS CASTOUTS_RELEASED INTV_ALLOCATIONS DLFB_RETRIES_TO_MBAR STORE_RETRIES STASH_L1_HITS STASH_L2_HITS STASH_BUSY_1 STASH_BUSY_2 STASH_BUSY_3 STASH_HITS STASH_HIT_DLFB STASH_REQUESTS STASH_REQUESTS_L1 STASH_REQUESTS_L2 STALLS_NO_CAQ_OR_COB L2_HIT_CACHE_ACCESSES L2_CACHE_DATA_ACCESSES L2_CACHE_DATA_HITS L2_CACHE_INSTR_ACCESSES L2_CACHE_INSTR_HITS L2_CACHE_ALLOCATIONS L2_CACHE_DATA_ALLOCATIONS L2_CACHE_DIRTY_DATA_ALLOCATIONS L2_CACHE_INSTR_ALLOCATIONS L2_CACHE_UPDATES L2_CACHE_CLEAN_UPDATES L2_CACHE_DIRTY_UPDATES L2_CACHE_CLEAN_REDUNDANT_UPDATES L2_CACHE_DIRTY_REDUNDANT_UPDATES L2_CACHE_LOCKS L2_CACHE_DATA_DIRTY_HITS INSTR_LFB_WENT_HIGH_PRIORITY SNOOP_THROTTLING_TURNED_ON L2_CLEAN_LINE_INVALIDATIONS L2_INCOHERENT_LINE_INVALIDATIONS L2_COHERENT_LINE_INVALIDATIONS COHERENT_LOOKUP_MISS_DUE_TO_VALID_BUT_INCOHERENT_MATCHES IAC1S_DETECTED IAC2S_DETECTED DAC1S_DTECTED DAC2S_DTECTED DVT0_DETECTED DVT1_DETECTED DVT2_DETECTED DVT3_DETECTED DVT4_DETECTED DVT5_DETECTED DVT6_DETECTED DVT7_DETECTED CYCLES_COMPLETION_STALLED_NEXUS_FIFO_FULL FPU_DOUBLE_PUMP FPU_FINISH FPU_DIVIDE_CYCLES FPU_DENORM_INPUT_CYCLES FPU_RESULT_STALL_CYCLES FPU_FPSCR_FULL_STALL FPU_PIPE_SYNC_STALLS FPU_INPUT_DATA_STALLS DECORATED_LOADS DECORATED_STORES LOAD_RETRIES STWCX_SUCCESSES STWCX_FAILURES SOFT- TSC- branches k8-fr-retired-taken-branches branch-mispredicts k8-fr-retired-taken-branches-mispredicted cycles tsc dc-misses k8-dc-miss ic-misses k8-ic-miss instructions k8-fr-retired-x86-instructions interrupts k8-fr-taken-hardware-interrupts unhalted-cycles k8-bu-cpu-clk-unhalted K8- count= edge inv mask= os usr add-pipe-excluding-junk-ops multiply-pipe-excluding-junk-ops store-pipe-excluding-junk-ops add-pipe-junk-ops multiply-pipe-junk-ops store-pipe-junk-ops es cs ss ds fs gs hs locked-instructions cycles-in-request cycles-to-complete invalid shared exclusive owner modified scrubber piggyback load store nta accesses misses ic-fill dc-fill tlb-reload tag-snoop cancelled dirty-l2-victim victim-from-l2 x87 mmx-3dnow packed-sse-sse2 scalar-sse-sse2 low-op-pos-0 low-op-pos-1 low-op-pos-2 x87-reclass-microfaults sse-retype-microfaults sse-reclass-microfaults sse-and-x87-microtraps page-hit page-miss page-conflict dimm-turnaround read-to-write-turnaround write-to-read-turnaround memory-controller-hi-pri-bypass memory-controller-lo-pri-bypass dram-controller-interface-bypass dram-controller-queue-bypass nonpostwrszbyte nonpostwrszdword postwrszbyte postwrszdword rdszbyte rdszdword rdmodwr probe-miss probe-hit probe-hit-dirty-no-memory-cancel probe-hit-dirty-with-memory-cancel command data buffer-release nop + SOFT-CLOCK.HARD INTERRUPT USER SYSTEM EDGE THRESHOLD READ WRITE INVERT QUALIFIER PRECISE TAGGING CASCADE K7 K8 P5 P6 P4 IAF IAP UCF UCP XSCALE MIPS24K OCTEON PPC7450 PPC970 SOFT ARMV7 ARMV8 MIPS74K E500 BERI POWER8 AMD_K7 AMD_K8 INTEL_P5 INTEL_P6 INTEL_CL INTEL_PII INTEL_PIII INTEL_PM INTEL_PIV INTEL_CORE INTEL_CORE2 INTEL_CORE2EXTREME INTEL_ATOM INTEL_COREI7 INTEL_WESTMERE INTEL_SANDYBRIDGE INTEL_IVYBRIDGE INTEL_SANDYBRIDGE_XEON INTEL_IVYBRIDGE_XEON INTEL_HASWELL INTEL_ATOM_SILVERMONT INTEL_NEHALEM_EX INTEL_WESTMERE_EX INTEL_HASWELL_XEON INTEL_BROADWELL INTEL_BROADWELL_XEON INTEL_SKYLAKE INTEL_SKYLAKE_XEON INTEL_ATOM_GOLDMONT INTEL_XSCALE MIPS_24K MIPS_OCTEON MIPS_74K MIPS_BERI PPC_7450 PPC_E500 PPC_970 PPC_POWER8 GENERIC ARMV7_CORTEX_A5 ARMV7_CORTEX_A7 ARMV7_CORTEX_A8 ARMV7_CORTEX_A9 ARMV7_CORTEX_A15 ARMV7_CORTEX_A17 ARMV8_CORTEX_A53 ARMV8_CORTEX_A57 ARMV8_CORTEX_A76 STANDALONE FREE THREAD UNKNOWN SS SC TS TC DISABLED ALLOCATED STOPPED RUNNING DELETED W
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( - FreeBSD clang version 11.0.1 (git@github.com:llvm/llvm-project.git llvmorg-11.0.1-0-g43ff75f2c3fe) /usr/src/lib/libpmc/libpmc.c /usr/obj/usr/src/amd64.amd64/obj-lib32/lib/libpmc pmc_mdep_event_aliases pm_alias char pm_spec pmc_event_alias soft_event_table pm_ev_name pm_ev_code unsigned int PMC_EV_TSC__BLOCK_START PMC_EV_TSC_TSC PMC_EV_IAF__BLOCK_START PMC_EV_IAF_INSTR_RETIRED_ANY PMC_EV_IAF_CPU_CLK_UNHALTED_CORE PMC_EV_IAF_CPU_CLK_UNHALTED_REF PMC_EV_K7__BLOCK_START PMC_EV_K7_DC_ACCESSES PMC_EV_K7_DC_MISSES PMC_EV_K7_DC_REFILLS_FROM_L2 PMC_EV_K7_DC_REFILLS_FROM_SYSTEM PMC_EV_K7_DC_WRITEBACKS PMC_EV_K7_L1_DTLB_MISS_AND_L2_DTLB_HITS PMC_EV_K7_L1_AND_L2_DTLB_MISSES PMC_EV_K7_MISALIGNED_REFERENCES PMC_EV_K7_IC_FETCHES PMC_EV_K7_IC_MISSES PMC_EV_K7_L1_ITLB_MISSES PMC_EV_K7_L1_L2_ITLB_MISSES PMC_EV_K7_RETIRED_INSTRUCTIONS PMC_EV_K7_RETIRED_OPS PMC_EV_K7_RETIRED_BRANCHES PMC_EV_K7_RETIRED_BRANCHES_MISPREDICTED PMC_EV_K7_RETIRED_TAKEN_BRANCHES PMC_EV_K7_RETIRED_TAKEN_BRANCHES_MISPREDICTED PMC_EV_K7_RETIRED_FAR_CONTROL_TRANSFERS PMC_EV_K7_RETIRED_RESYNC_BRANCHES PMC_EV_K7_INTERRUPTS_MASKED_CYCLES PMC_EV_K7_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES PMC_EV_K7_HARDWARE_INTERRUPTS PMC_EV_K8__BLOCK_START PMC_EV_K8_FP_DISPATCHED_FPU_OPS PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD PMC_EV_K8_LS_MICROARCHITECTURAL_RESYNC_BY_SELF_MODIFYING_CODE PMC_EV_K8_LS_MICROARCHITECTURAL_RESYNC_BY_SNOOP PMC_EV_K8_LS_BUFFER2_FULL PMC_EV_K8_LS_LOCKED_OPERATION PMC_EV_K8_LS_MICROARCHITECTURAL_LATE_CANCEL PMC_EV_K8_LS_RETIRED_CFLUSH_INSTRUCTIONS PMC_EV_K8_LS_RETIRED_CPUID_INSTRUCTIONS PMC_EV_K8_DC_ACCESS PMC_EV_K8_DC_MISS PMC_EV_K8_DC_REFILL_FROM_L2 PMC_EV_K8_DC_REFILL_FROM_SYSTEM PMC_EV_K8_DC_COPYBACK PMC_EV_K8_DC_L1_DTLB_MISS_AND_L2_DTLB_HIT PMC_EV_K8_DC_L1_DTLB_MISS_AND_L2_DTLB_MISS PMC_EV_K8_DC_MISALIGNED_DATA_REFERENCE PMC_EV_K8_DC_MICROARCHITECTURAL_LATE_CANCEL PMC_EV_K8_DC_MICROARCHITECTURAL_EARLY_CANCEL PMC_EV_K8_DC_ONE_BIT_ECC_ERROR PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS PMC_EV_K8_BU_CPU_CLK_UNHALTED PMC_EV_K8_BU_INTERNAL_L2_REQUEST PMC_EV_K8_BU_FILL_REQUEST_L2_MISS PMC_EV_K8_BU_FILL_INTO_L2 PMC_EV_K8_IC_FETCH PMC_EV_K8_IC_MISS PMC_EV_K8_IC_REFILL_FROM_L2 PMC_EV_K8_IC_REFILL_FROM_SYSTEM PMC_EV_K8_IC_L1_ITLB_MISS_AND_L2_ITLB_HIT PMC_EV_K8_IC_L1_ITLB_MISS_AND_L2_ITLB_MISS PMC_EV_K8_IC_MICROARCHITECTURAL_RESYNC_BY_SNOOP PMC_EV_K8_IC_INSTRUCTION_FETCH_STALL PMC_EV_K8_IC_RETURN_STACK_HIT PMC_EV_K8_IC_RETURN_STACK_OVERFLOW PMC_EV_K8_FR_RETIRED_X86_INSTRUCTIONS PMC_EV_K8_FR_RETIRED_UOPS PMC_EV_K8_FR_RETIRED_BRANCHES PMC_EV_K8_FR_RETIRED_BRANCHES_MISPREDICTED PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED PMC_EV_K8_FR_RETIRED_FAR_CONTROL_TRANSFERS PMC_EV_K8_FR_RETIRED_RESYNCS PMC_EV_K8_FR_RETIRED_NEAR_RETURNS PMC_EV_K8_FR_RETIRED_NEAR_RETURNS_MISPREDICTED PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED_BY_ADDR_MISCOMPARE PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS PMC_EV_K8_FR_INTERRUPTS_MASKED_CYCLES PMC_EV_K8_FR_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES PMC_EV_K8_FR_TAKEN_HARDWARE_INTERRUPTS PMC_EV_K8_FR_DECODER_EMPTY PMC_EV_K8_FR_DISPATCH_STALLS PMC_EV_K8_FR_DISPATCH_STALL_FROM_BRANCH_ABORT_TO_RETIRE PMC_EV_K8_FR_DISPATCH_STALL_FOR_SERIALIZATION PMC_EV_K8_FR_DISPATCH_STALL_FOR_SEGMENT_LOAD PMC_EV_K8_FR_DISPATCH_STALL_WHEN_REORDER_BUFFER_IS_FULL PMC_EV_K8_FR_DISPATCH_STALL_WHEN_RESERVATION_STATIONS_ARE_FULL PMC_EV_K8_FR_DISPATCH_STALL_WHEN_FPU_IS_FULL PMC_EV_K8_FR_DISPATCH_STALL_WHEN_LS_IS_FULL PMC_EV_K8_FR_DISPATCH_STALL_WHEN_WAITING_FOR_ALL_TO_BE_QUIET PMC_EV_K8_FR_DISPATCH_STALL_WHEN_FAR_XFER_OR_RESYNC_BRANCH_PENDING PMC_EV_K8_FR_FPU_EXCEPTIONS PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR0 PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR1 PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR2 PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR3 PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOW PMC_EV_K8_NB_MEMORY_CONTROLLER_DRAM_COMMAND_SLOTS_MISSED PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION PMC_EV_K8_NB_SIZED_COMMANDS PMC_EV_K8_NB_PROBE_RESULT PMC_EV_K8_NB_HT_BUS0_BANDWIDTH PMC_EV_K8_NB_HT_BUS1_BANDWIDTH PMC_EV_K8_NB_HT_BUS2_BANDWIDTH PMC_EV_MIPS24K__BLOCK_START PMC_EV_MIPS24K_CYCLE PMC_EV_MIPS24K_INSTR_EXECUTED PMC_EV_MIPS24K_BRANCH_COMPLETED PMC_EV_MIPS24K_BRANCH_MISPRED PMC_EV_MIPS24K_RETURN PMC_EV_MIPS24K_RETURN_MISPRED PMC_EV_MIPS24K_RETURN_NOT_31 PMC_EV_MIPS24K_RETURN_NOTPRED PMC_EV_MIPS24K_ITLB_ACCESS PMC_EV_MIPS24K_ITLB_MISS PMC_EV_MIPS24K_DTLB_ACCESS PMC_EV_MIPS24K_DTLB_MISS PMC_EV_MIPS24K_JTLB_IACCESS PMC_EV_MIPS24K_JTLB_IMISS PMC_EV_MIPS24K_JTLB_DACCESS PMC_EV_MIPS24K_JTLB_DMISS PMC_EV_MIPS24K_IC_FETCH PMC_EV_MIPS24K_IC_MISS PMC_EV_MIPS24K_DC_LOADSTORE PMC_EV_MIPS24K_DC_WRITEBACK PMC_EV_MIPS24K_DC_MISS PMC_EV_MIPS24K_STORE_MISS PMC_EV_MIPS24K_LOAD_MISS PMC_EV_MIPS24K_INTEGER_COMPLETED PMC_EV_MIPS24K_FP_COMPLETED PMC_EV_MIPS24K_LOAD_COMPLETED PMC_EV_MIPS24K_STORE_COMPLETED PMC_EV_MIPS24K_BARRIER_COMPLETED PMC_EV_MIPS24K_MIPS16_COMPLETED PMC_EV_MIPS24K_NOP_COMPLETED PMC_EV_MIPS24K_INTEGER_MULDIV_COMPLETED PMC_EV_MIPS24K_RF_STALL PMC_EV_MIPS24K_INSTR_REFETCH PMC_EV_MIPS24K_STORE_COND_COMPLETED PMC_EV_MIPS24K_STORE_COND_FAILED PMC_EV_MIPS24K_ICACHE_REQUESTS PMC_EV_MIPS24K_ICACHE_HIT PMC_EV_MIPS24K_L2_WRITEBACK PMC_EV_MIPS24K_L2_ACCESS PMC_EV_MIPS24K_L2_MISS PMC_EV_MIPS24K_L2_ERR_CORRECTED PMC_EV_MIPS24K_EXCEPTIONS PMC_EV_MIPS24K_RF_CYCLES_STALLED PMC_EV_MIPS24K_IFU_CYCLES_STALLED PMC_EV_MIPS24K_ALU_CYCLES_STALLED PMC_EV_MIPS24K_UNCACHED_LOAD PMC_EV_MIPS24K_UNCACHED_STORE PMC_EV_MIPS24K_CP2_REG_TO_REG_COMPLETED PMC_EV_MIPS24K_MFTC_COMPLETED PMC_EV_MIPS24K_IC_BLOCKED_CYCLES PMC_EV_MIPS24K_DC_BLOCKED_CYCLES PMC_EV_MIPS24K_L2_IMISS_STALL_CYCLES PMC_EV_MIPS24K_L2_DMISS_STALL_CYCLES PMC_EV_MIPS24K_DMISS_CYCLES PMC_EV_MIPS24K_L2_MISS_CYCLES PMC_EV_MIPS24K_UNCACHED_BLOCK_CYCLES PMC_EV_MIPS24K_MDU_STALL_CYCLES PMC_EV_MIPS24K_FPU_STALL_CYCLES PMC_EV_MIPS24K_CP2_STALL_CYCLES PMC_EV_MIPS24K_COREXTEND_STALL_CYCLES PMC_EV_MIPS24K_ISPRAM_STALL_CYCLES PMC_EV_MIPS24K_DSPRAM_STALL_CYCLES PMC_EV_MIPS24K_CACHE_STALL_CYCLES PMC_EV_MIPS24K_LOAD_TO_USE_STALLS PMC_EV_MIPS24K_BASE_MISPRED_STALLS PMC_EV_MIPS24K_CPO_READ_STALLS PMC_EV_MIPS24K_BRANCH_MISPRED_CYCLES PMC_EV_MIPS24K_IFETCH_BUFFER_FULL PMC_EV_MIPS24K_FETCH_BUFFER_ALLOCATED PMC_EV_MIPS24K_EJTAG_ITRIGGER PMC_EV_MIPS24K_EJTAG_DTRIGGER PMC_EV_MIPS24K_FSB_LT_QUARTER PMC_EV_MIPS24K_FSB_QUARTER_TO_HALF PMC_EV_MIPS24K_FSB_GT_HALF PMC_EV_MIPS24K_FSB_FULL_PIPELINE_STALLS PMC_EV_MIPS24K_LDQ_LT_QUARTER PMC_EV_MIPS24K_LDQ_QUARTER_TO_HALF PMC_EV_MIPS24K_LDQ_GT_HALF PMC_EV_MIPS24K_LDQ_FULL_PIPELINE_STALLS PMC_EV_MIPS24K_WBB_LT_QUARTER PMC_EV_MIPS24K_WBB_QUARTER_TO_HALF PMC_EV_MIPS24K_WBB_GT_HALF PMC_EV_MIPS24K_WBB_FULL_PIPELINE_STALLS PMC_EV_MIPS24K_REQUEST_LATENCY PMC_EV_MIPS24K_REQUEST_COUNT PMC_EV_OCTEON__BLOCK_START PMC_EV_OCTEON_CLK PMC_EV_OCTEON_ISSUE PMC_EV_OCTEON_RET PMC_EV_OCTEON_NISSUE PMC_EV_OCTEON_SISSUE PMC_EV_OCTEON_DISSUE PMC_EV_OCTEON_IFI PMC_EV_OCTEON_BR PMC_EV_OCTEON_BRMIS PMC_EV_OCTEON_J PMC_EV_OCTEON_JMIS PMC_EV_OCTEON_REPLAY PMC_EV_OCTEON_IUNA PMC_EV_OCTEON_TRAP PMC_EV_OCTEON_UULOAD PMC_EV_OCTEON_UUSTORE PMC_EV_OCTEON_ULOAD PMC_EV_OCTEON_USTORE PMC_EV_OCTEON_EC PMC_EV_OCTEON_MC PMC_EV_OCTEON_CC PMC_EV_OCTEON_CSRC PMC_EV_OCTEON_CFETCH PMC_EV_OCTEON_CPREF PMC_EV_OCTEON_ICA PMC_EV_OCTEON_II PMC_EV_OCTEON_IP PMC_EV_OCTEON_CIMISS PMC_EV_OCTEON_WBUF PMC_EV_OCTEON_WDAT PMC_EV_OCTEON_WBUFLD PMC_EV_OCTEON_WBUFFL PMC_EV_OCTEON_WBUFTR PMC_EV_OCTEON_BADD PMC_EV_OCTEON_BADDL2 PMC_EV_OCTEON_BFILL PMC_EV_OCTEON_DDIDS PMC_EV_OCTEON_IDIDS PMC_EV_OCTEON_DIDNA PMC_EV_OCTEON_LDS PMC_EV_OCTEON_LMLDS PMC_EV_OCTEON_IOLDS PMC_EV_OCTEON_DMLDS PMC_EV_OCTEON_STS PMC_EV_OCTEON_LMSTS PMC_EV_OCTEON_IOSTS PMC_EV_OCTEON_IOBDMA PMC_EV_OCTEON_DTLB PMC_EV_OCTEON_DTLBAD PMC_EV_OCTEON_ITLB PMC_EV_OCTEON_SYNC PMC_EV_OCTEON_SYNCIOB PMC_EV_OCTEON_SYNCW PMC_EV_MIPS74K__BLOCK_START PMC_EV_MIPS74K_CYCLES PMC_EV_MIPS74K_INSTR_EXECUTED PMC_EV_MIPS74K_PREDICTED_JR_31 PMC_EV_MIPS74K_JR_31_MISPREDICTIONS PMC_EV_MIPS74K_REDIRECT_STALLS PMC_EV_MIPS74K_JR_31_NO_PREDICTIONS PMC_EV_MIPS74K_ITLB_ACCESSES PMC_EV_MIPS74K_ITLB_MISSES PMC_EV_MIPS74K_JTLB_INSN_MISSES PMC_EV_MIPS74K_ICACHE_ACCESSES PMC_EV_MIPS74K_ICACHE_MISSES PMC_EV_MIPS74K_ICACHE_MISS_STALLS PMC_EV_MIPS74K_UNCACHED_IFETCH_STALLS PMC_EV_MIPS74K_PDTRACE_BACK_STALLS PMC_EV_MIPS74K_IFU_REPLAYS PMC_EV_MIPS74K_KILLED_FETCH_SLOTS PMC_EV_MIPS74K_IFU_IDU_MISS_PRED_UPSTREAM_CYCLES PMC_EV_MIPS74K_IFU_IDU_NO_FETCH_CYCLES PMC_EV_MIPS74K_IFU_IDU_CLOGED_DOWNSTREAM_CYCLES PMC_EV_MIPS74K_DDQ0_FULL_DR_STALLS PMC_EV_MIPS74K_DDQ1_FULL_DR_STALLS PMC_EV_MIPS74K_ALCB_FULL_DR_STALLS PMC_EV_MIPS74K_AGCB_FULL_DR_STALLS PMC_EV_MIPS74K_CLDQ_FULL_DR_STALLS PMC_EV_MIPS74K_IODQ_FULL_DR_STALLS PMC_EV_MIPS74K_ALU_EMPTY_CYCLES PMC_EV_MIPS74K_AGEN_EMPTY_CYCLES PMC_EV_MIPS74K_ALU_OPERANDS_NOT_READY_CYCLES PMC_EV_MIPS74K_AGEN_OPERANDS_NOT_READY_CYCLES PMC_EV_MIPS74K_ALU_NO_ISSUES_CYCLES PMC_EV_MIPS74K_AGEN_NO_ISSUES_CYCLES PMC_EV_MIPS74K_ALU_BUBBLE_CYCLES PMC_EV_MIPS74K_AGEN_BUBBLE_CYCLES PMC_EV_MIPS74K_SINGLE_ISSUE_CYCLES PMC_EV_MIPS74K_DUAL_ISSUE_CYCLES PMC_EV_MIPS74K_OOO_ALU_ISSUE_CYCLES PMC_EV_MIPS74K_OOO_AGEN_ISSUE_CYCLES PMC_EV_MIPS74K_JALR_JALR_HB_INSNS PMC_EV_MIPS74K_DCACHE_LINE_REFILL_REQUESTS PMC_EV_MIPS74K_DCACHE_LOAD_ACCESSES PMC_EV_MIPS74K_DCACHE_ACCESSES PMC_EV_MIPS74K_DCACHE_WRITEBACKS PMC_EV_MIPS74K_DCACHE_MISSES PMC_EV_MIPS74K_JTLB_DATA_ACCESSES PMC_EV_MIPS74K_JTLB_DATA_MISSES PMC_EV_MIPS74K_LOAD_STORE_REPLAYS PMC_EV_MIPS74K_VA_TRANSALTION_CORNER_CASES PMC_EV_MIPS74K_LOAD_STORE_BLOCKED_CYCLES PMC_EV_MIPS74K_LOAD_STORE_NO_FILL_REQUESTS PMC_EV_MIPS74K_L2_CACHE_WRITEBACKS PMC_EV_MIPS74K_L2_CACHE_ACCESSES PMC_EV_MIPS74K_L2_CACHE_MISSES PMC_EV_MIPS74K_L2_CACHE_MISS_CYCLES PMC_EV_MIPS74K_FSB_FULL_STALLS PMC_EV_MIPS74K_FSB_OVER_50_FULL PMC_EV_MIPS74K_LDQ_FULL_STALLS PMC_EV_MIPS74K_LDQ_OVER_50_FULL PMC_EV_MIPS74K_WBB_FULL_STALLS PMC_EV_MIPS74K_WBB_OVER_50_FULL PMC_EV_MIPS74K_LOAD_MISS_CONSUMER_REPLAYS PMC_EV_MIPS74K_CP1_CP2_LOAD_INSNS PMC_EV_MIPS74K_JR_NON_31_INSNS PMC_EV_MIPS74K_MISPREDICTED_JR_31_INSNS PMC_EV_MIPS74K_BRANCH_INSNS PMC_EV_MIPS74K_CP1_CP2_COND_BRANCH_INSNS PMC_EV_MIPS74K_BRANCH_LIKELY_INSNS PMC_EV_MIPS74K_MISPREDICTED_BRANCH_LIKELY_INSNS PMC_EV_MIPS74K_COND_BRANCH_INSNS PMC_EV_MIPS74K_MISPREDICTED_BRANCH_INSNS PMC_EV_MIPS74K_INTEGER_INSNS PMC_EV_MIPS74K_FPU_INSNS PMC_EV_MIPS74K_LOAD_INSNS PMC_EV_MIPS74K_STORE_INSNS PMC_EV_MIPS74K_J_JAL_INSNS PMC_EV_MIPS74K_MIPS16_INSNS PMC_EV_MIPS74K_NOP_INSNS PMC_EV_MIPS74K_NT_MUL_DIV_INSNS PMC_EV_MIPS74K_DSP_INSNS PMC_EV_MIPS74K_ALU_DSP_SATURATION_INSNS PMC_EV_MIPS74K_DSP_BRANCH_INSNS PMC_EV_MIPS74K_MDU_DSP_SATURATION_INSNS PMC_EV_MIPS74K_UNCACHED_LOAD_INSNS PMC_EV_MIPS74K_UNCACHED_STORE_INSNS PMC_EV_MIPS74K_EJTAG_INSN_TRIGGERS PMC_EV_MIPS74K_CP1_BRANCH_MISPREDICTIONS PMC_EV_MIPS74K_SC_INSNS PMC_EV_MIPS74K_FAILED_SC_INSNS PMC_EV_MIPS74K_PREFETCH_INSNS PMC_EV_MIPS74K_CACHE_HIT_PREFETCH_INSNS PMC_EV_MIPS74K_NO_INSN_CYCLES PMC_EV_MIPS74K_LOAD_MISS_INSNS PMC_EV_MIPS74K_ONE_INSN_CYCLES PMC_EV_MIPS74K_TWO_INSNS_CYCLES PMC_EV_MIPS74K_GFIFO_BLOCKED_CYCLES PMC_EV_MIPS74K_CP1_CP2_STORE_INSNS PMC_EV_MIPS74K_MISPREDICTION_STALLS PMC_EV_MIPS74K_MISPREDICTED_BRANCH_INSNS_CYCLES PMC_EV_MIPS74K_EXCEPTIONS_TAKEN PMC_EV_MIPS74K_GRADUATION_REPLAYS PMC_EV_MIPS74K_COREEXTEND_EVENTS PMC_EV_MIPS74K_ISPRAM_EVENTS PMC_EV_MIPS74K_DSPRAM_EVENTS PMC_EV_MIPS74K_L2_CACHE_SINGLE_BIT_ERRORS PMC_EV_MIPS74K_SYSTEM_EVENT_0 PMC_EV_MIPS74K_SYSTEM_EVENT_1 PMC_EV_MIPS74K_SYSTEM_EVENT_2 PMC_EV_MIPS74K_SYSTEM_EVENT_3 PMC_EV_MIPS74K_SYSTEM_EVENT_4 PMC_EV_MIPS74K_SYSTEM_EVENT_5 PMC_EV_MIPS74K_SYSTEM_EVENT_6 PMC_EV_MIPS74K_SYSTEM_EVENT_7 PMC_EV_MIPS74K_OCP_ALL_REQUESTS PMC_EV_MIPS74K_OCP_ALL_CACHEABLE_REQUESTS PMC_EV_MIPS74K_OCP_READ_REQUESTS PMC_EV_MIPS74K_OCP_READ_CACHEABLE_REQUESTS PMC_EV_MIPS74K_OCP_WRITE_REQUESTS PMC_EV_MIPS74K_OCP_WRITE_CACHEABLE_REQUESTS PMC_EV_MIPS74K_FSB_LESS_25_FULL PMC_EV_MIPS74K_FSB_25_50_FULL PMC_EV_MIPS74K_LDQ_LESS_25_FULL PMC_EV_MIPS74K_LDQ_25_50_FULL PMC_EV_MIPS74K_WBB_LESS_25_FULL PMC_EV_MIPS74K_WBB_25_50_FULL PMC_EV_BERI__BLOCK_START PMC_EV_BERI_CYCLE PMC_EV_BERI_INST PMC_EV_BERI_INST_USER PMC_EV_BERI_INST_KERNEL PMC_EV_BERI_IMPRECISE_SETBOUNDS PMC_EV_BERI_UNREPRESENTABLE_CAPS PMC_EV_BERI_ITLB_MISS PMC_EV_BERI_DTLB_MISS PMC_EV_BERI_ICACHE_WRITE_HIT PMC_EV_BERI_ICACHE_WRITE_MISS PMC_EV_BERI_ICACHE_READ_HIT PMC_EV_BERI_ICACHE_READ_MISS PMC_EV_BERI_ICACHE_EVICT PMC_EV_BERI_DCACHE_WRITE_HIT PMC_EV_BERI_DCACHE_WRITE_MISS PMC_EV_BERI_DCACHE_READ_HIT PMC_EV_BERI_DCACHE_READ_MISS PMC_EV_BERI_DCACHE_EVICT PMC_EV_BERI_DCACHE_SET_TAG_WRITE PMC_EV_BERI_DCACHE_SET_TAG_READ PMC_EV_BERI_L2CACHE_WRITE_HIT PMC_EV_BERI_L2CACHE_WRITE_MISS PMC_EV_BERI_L2CACHE_READ_HIT PMC_EV_BERI_L2CACHE_READ_MISS PMC_EV_BERI_L2CACHE_EVICT PMC_EV_BERI_L2CACHE_SET_TAG_WRITE PMC_EV_BERI_L2CACHE_SET_TAG_READ PMC_EV_BERI_MEM_BYTE_READ PMC_EV_BERI_MEM_BYTE_WRITE PMC_EV_BERI_MEM_HWORD_READ PMC_EV_BERI_MEM_HWORD_WRITE PMC_EV_BERI_MEM_WORD_READ PMC_EV_BERI_MEM_WORD_WRITE PMC_EV_BERI_MEM_DWORD_READ PMC_EV_BERI_MEM_DWORD_WRITE PMC_EV_BERI_MEM_CAP_READ PMC_EV_BERI_MEM_CAP_WRITE PMC_EV_BERI_MEM_CAP_READ_TAG_SET PMC_EV_BERI_MEM_CAP_WRITE_TAG_SET PMC_EV_BERI_TAGCACHE_WRITE_HIT PMC_EV_BERI_TAGCACHE_WRITE_MISS PMC_EV_BERI_TAGCACHE_READ_HIT PMC_EV_BERI_TAGCACHE_READ_MISS PMC_EV_BERI_TAGCACHE_EVICT PMC_EV_BERI_L2CACHEMASTER_READ_REQ PMC_EV_BERI_L2CACHEMASTER_WRITE_REQ PMC_EV_BERI_L2CACHEMASTER_WRITE_REQ_FLIT PMC_EV_BERI_L2CACHEMASTER_READ_RSP PMC_EV_BERI_L2CACHEMASTER_READ_RSP_FLIT PMC_EV_BERI_L2CACHEMASTER_WRITE_RSP PMC_EV_BERI_TAGCACHEMASTER_READ_REQ PMC_EV_BERI_TAGCACHEMASTER_WRITE_REQ PMC_EV_BERI_TAGCACHEMASTER_WRITE_REQ_FLIT PMC_EV_BERI_TAGCACHEMASTER_READ_RSP PMC_EV_BERI_TAGCACHEMASTER_READ_RSP_FLIT PMC_EV_BERI_TAGCACHEMASTER_WRITE_RSP PMC_EV_UCP__BLOCK_START PMC_EV_UCP_EVENT_0CH_04H_E PMC_EV_UCP_EVENT_0CH_04H_F PMC_EV_UCP_EVENT_0CH_04H_M PMC_EV_UCP_EVENT_0CH_04H_S PMC_EV_UCP_EVENT_0CH_08H_E PMC_EV_UCP_EVENT_0CH_08H_F PMC_EV_UCP_EVENT_0CH_08H_M PMC_EV_UCP_EVENT_0CH_08H_S PMC_EV_PPC7450__BLOCK_START PMC_EV_PPC7450_CYCLE PMC_EV_PPC7450_INSTR_COMPLETED PMC_EV_PPC7450_TLB_BIT_TRANSITIONS PMC_EV_PPC7450_INSTR_DISPATCHED PMC_EV_PPC7450_PMON_EXCEPT PMC_EV_PPC7450_PMON_SIG PMC_EV_PPC7450_VPU_INSTR_COMPLETED PMC_EV_PPC7450_VFPU_INSTR_COMPLETED PMC_EV_PPC7450_VIU1_INSTR_COMPLETED PMC_EV_PPC7450_VIU2_INSTR_COMPLETED PMC_EV_PPC7450_MTVSCR_INSTR_COMPLETED PMC_EV_PPC7450_MTVRSAVE_INSTR_COMPLETED PMC_EV_PPC7450_VPU_INSTR_WAIT_CYCLES PMC_EV_PPC7450_VFPU_INSTR_WAIT_CYCLES PMC_EV_PPC7450_VIU1_INSTR_WAIT_CYCLES PMC_EV_PPC7450_VIU2_INSTR_WAIT_CYCLES PMC_EV_PPC7450_MFVSCR_SYNC_CYCLES PMC_EV_PPC7450_VSCR_SAT_SET PMC_EV_PPC7450_STORE_INSTR_COMPLETED PMC_EV_PPC7450_L1_INSTR_CACHE_MISSES PMC_EV_PPC7450_L1_DATA_SNOOPS PMC_EV_PPC7450_UNRESOLVED_BRANCHES PMC_EV_PPC7450_SPEC_BUFFER_CYCLES PMC_EV_PPC7450_BRANCH_UNIT_STALL_CYCLES PMC_EV_PPC7450_TRUE_BRANCH_TARGET_HITS PMC_EV_PPC7450_BRANCH_LINK_STAC_PREDICTED PMC_EV_PPC7450_GPR_ISSUE_QUEUE_DISPATCHES PMC_EV_PPC7450_CYCLES_THREE_INSTR_DISPATCHED PMC_EV_PPC7450_THRESHOLD_INSTR_QUEUE_ENTRIES_CYCLES PMC_EV_PPC7450_THRESHOLD_VEC_INSTR_QUEUE_ENTRIES_CYCLES PMC_EV_PPC7450_CYCLES_NO_COMPLETED_INSTRS PMC_EV_PPC7450_IU2_INSTR_COMPLETED PMC_EV_PPC7450_BRANCHES_COMPLETED PMC_EV_PPC7450_EIEIO_INSTR_COMPLETED PMC_EV_PPC7450_MTSPR_INSTR_COMPLETED PMC_EV_PPC7450_SC_INSTR_COMPLETED PMC_EV_PPC7450_LS_LM_COMPLETED PMC_EV_PPC7450_ITLB_HW_TABLE_SEARCH_CYCLES PMC_EV_PPC7450_DTLB_HW_SEARCH_CYCLES_OVER_THRESHOLD PMC_EV_PPC7450_L1_INSTR_CACHE_ACCESSES PMC_EV_PPC7450_INSTR_BKPT_MATCHES PMC_EV_PPC7450_L1_DATA_CACHE_LOAD_MISS_CYCLES_OVER_THRESHOLD PMC_EV_PPC7450_L1_DATA_SNOOP_HIT_ON_MODIFIED PMC_EV_PPC7450_LOAD_MISS_ALIAS PMC_EV_PPC7450_LOAD_MISS_ALIAS_ON_TOUCH PMC_EV_PPC7450_TOUCH_ALIAS PMC_EV_PPC7450_L1_DATA_SNOOP_HIT_CASTOUT_QUEUE PMC_EV_PPC7450_L1_DATA_SNOOP_HIT_CASTOUT PMC_EV_PPC7450_L1_DATA_SNOOP_HITS PMC_EV_PPC7450_WRITE_THROUGH_STORES PMC_EV_PPC7450_CACHE_INHIBITED_STORES PMC_EV_PPC7450_L1_DATA_LOAD_HIT PMC_EV_PPC7450_L1_DATA_TOUCH_HIT PMC_EV_PPC7450_L1_DATA_STORE_HIT PMC_EV_PPC7450_L1_DATA_TOTAL_HITS PMC_EV_PPC7450_DST_INSTR_DISPATCHED PMC_EV_PPC7450_REFRESHED_DSTS PMC_EV_PPC7450_SUCCESSFUL_DST_TABLE_SEARCHES PMC_EV_PPC7450_DSS_INSTR_COMPLETED PMC_EV_PPC7450_DST_STREAM_0_CACHE_LINE_FETCHES PMC_EV_PPC7450_VTQ_SUSPENDS_DUE_TO_CTX_CHANGE PMC_EV_PPC7450_VTQ_LINE_FETCH_HIT PMC_EV_PPC7450_VEC_LOAD_INSTR_COMPLETED PMC_EV_PPC7450_FP_STORE_INSTR_COMPLETED_IN_LSU PMC_EV_PPC7450_FPU_RENORMALIZATION PMC_EV_PPC7450_FPU_DENORMALIZATION PMC_EV_PPC7450_FP_STORE_CAUSES_STALL_IN_LSU PMC_EV_PPC7450_LD_ST_TRUE_ALIAS_STALL PMC_EV_PPC7450_LSU_INDEXED_ALIAS_STALL PMC_EV_PPC7450_LSU_ALIAS_VS_FSQ_WB0_WB1 PMC_EV_PPC7450_LSU_ALIAS_VS_CSQ PMC_EV_PPC7450_LSU_LOAD_HIT_LINE_ALIAS_VS_CSQ0 PMC_EV_PPC7450_LSU_LOAD_MISS_LINE_ALIAS_VS_CSQ0 PMC_EV_PPC7450_LSU_TOUCH_LINE_ALIAS_VS_FSQ_WB0_WB1 PMC_EV_PPC7450_LSU_TOUCH_ALIAS_VS_CSQ PMC_EV_PPC7450_LSU_LMQ_FULL_STALL PMC_EV_PPC7450_FP_LOAD_INSTR_COMPLETED_IN_LSU PMC_EV_PPC7450_FP_LOAD_SINGLE_INSTR_COMPLETED_IN_LSU PMC_EV_PPC7450_FP_LOAD_DOUBLE_COMPLETED_IN_LSU PMC_EV_PPC7450_LSU_RA_LATCH_STALL PMC_EV_PPC7450_LSU_LOAD_VS_STORE_QUEUE_ALIAS_STALL PMC_EV_PPC7450_LSU_LMQ_INDEX_ALIAS PMC_EV_PPC7450_LSU_STORE_QUEUE_INDEX_ALIAS PMC_EV_PPC7450_LSU_CSQ_FORWARDING PMC_EV_PPC7450_LSU_MISALIGNED_LOAD_FINISH PMC_EV_PPC7450_LSU_MISALIGN_STORE_COMPLETED PMC_EV_PPC7450_LSU_MISALIGN_STALL PMC_EV_PPC7450_FP_ONE_QUARTER_FPSCR_RENAMES_BUSY PMC_EV_PPC7450_FP_ONE_HALF_FPSCR_RENAMES_BUSY PMC_EV_PPC7450_FP_THREE_QUARTERS_FPSCR_RENAMES_BUSY PMC_EV_PPC7450_FP_ALL_FPSCR_RENAMES_BUSY PMC_EV_PPC7450_FP_DENORMALIZED_RESULT PMC_EV_PPC7450_L1_DATA_TOTAL_MISSES PMC_EV_PPC7450_DISPATCHES_TO_FPR_ISSUE_QUEUE PMC_EV_PPC7450_LSU_INSTR_COMPLETED PMC_EV_PPC7450_LOAD_INSTR_COMPLETED PMC_EV_PPC7450_SS_SM_INSTR_COMPLETED PMC_EV_PPC7450_TLBIE_INSTR_COMPLETED PMC_EV_PPC7450_LWARX_INSTR_COMPLETED PMC_EV_PPC7450_MFSPR_INSTR_COMPLETED PMC_EV_PPC7450_REFETCH_SERIALIZATION PMC_EV_PPC7450_COMPLETION_QUEUE_ENTRIES_OVER_THRESHOLD PMC_EV_PPC7450_CYCLES_ONE_INSTR_DISPATCHED PMC_EV_PPC7450_CYCLES_TWO_INSTR_COMPLETED PMC_EV_PPC7450_ITLB_NON_SPECULATIVE_MISSES PMC_EV_PPC7450_CYCLES_WAITING_FROM_L1_INSTR_CACHE_MISS PMC_EV_PPC7450_L1_DATA_LOAD_ACCESS_MISS PMC_EV_PPC7450_L1_DATA_TOUCH_MISS PMC_EV_PPC7450_L1_DATA_STORE_MISS PMC_EV_PPC7450_L1_DATA_TOUCH_MISS_CYCLES PMC_EV_PPC7450_L1_DATA_CYCLES_USED PMC_EV_PPC7450_DST_STREAM_1_CACHE_LINE_FETCHES PMC_EV_PPC7450_VTQ_STREAM_CANCELED_PREMATURELY PMC_EV_PPC7450_VTQ_RESUMES_DUE_TO_CTX_CHANGE PMC_EV_PPC7450_VTQ_LINE_FETCH_MISS PMC_EV_PPC7450_VTQ_LINE_FETCH PMC_EV_PPC7450_TLBIE_SNOOPS PMC_EV_PPC7450_L1_INSTR_CACHE_RELOADS PMC_EV_PPC7450_L1_DATA_CACHE_RELOADS PMC_EV_PPC7450_L1_DATA_CACHE_CASTOUTS_TO_L2 PMC_EV_PPC7450_STORE_MERGE_GATHER PMC_EV_PPC7450_CACHEABLE_STORE_MERGE_TO_32_BYTES PMC_EV_PPC7450_DATA_BKPT_MATCHES PMC_EV_PPC7450_FALL_THROUGH_BRANCHES_PROCESSED PMC_EV_PPC7450_FIRST_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLY PMC_EV_PPC7450_SECOND_SPECULATION_BUFFER_ACTIVE PMC_EV_PPC7450_BPU_STALL_ON_LR_DEPENDENCY PMC_EV_PPC7450_BTIC_MISS PMC_EV_PPC7450_BRANCH_LINK_STACK_CORRECTLY_RESOLVED PMC_EV_PPC7450_FPR_ISSUE_STALLED PMC_EV_PPC7450_SWITCHES_BETWEEN_PRIV_USER PMC_EV_PPC7450_LSU_COMPLETES_FP_STORE_SINGLE PMC_EV_PPC7450_VR_ISSUE_QUEUE_DISPATCHES PMC_EV_PPC7450_VR_STALLS PMC_EV_PPC7450_GPR_RENAME_BUFFER_ENTRIES_OVER_THRESHOLD PMC_EV_PPC7450_FPR_ISSUE_QUEUE_ENTRIES PMC_EV_PPC7450_FPU_INSTR_COMPLETED PMC_EV_PPC7450_STWCX_INSTR_COMPLETED PMC_EV_PPC7450_LS_LM_INSTR_PIECES PMC_EV_PPC7450_ITLB_HW_SEARCH_CYCLES_OVER_THRESHOLD PMC_EV_PPC7450_DTLB_MISSES PMC_EV_PPC7450_CANCELLED_L1_INSTR_CACHE_MISSES PMC_EV_PPC7450_L1_DATA_CACHE_OP_HIT PMC_EV_PPC7450_L1_DATA_LOAD_MISS_CYCLES PMC_EV_PPC7450_L1_DATA_PUSHES PMC_EV_PPC7450_L1_DATA_TOTAL_MISS PMC_EV_PPC7450_VT2_FETCHES PMC_EV_PPC7450_TAKEN_BRANCHES_PROCESSED PMC_EV_PPC7450_BRANCH_FLUSHES PMC_EV_PPC7450_SECOND_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLY PMC_EV_PPC7450_THIRD_SPECULATION_BUFFER_ACTIVE PMC_EV_PPC7450_BRANCH_UNIT_STALL_ON_CTR_DEPENDENCY PMC_EV_PPC7450_FAST_BTIC_HIT PMC_EV_PPC7450_BRANCH_LINK_STACK_MISPREDICTED PMC_EV_PPC7450_CYCLES_THREE_INSTR_COMPLETED PMC_EV_PPC7450_CYCLES_NO_INSTR_DISPATCHED PMC_EV_PPC7450_GPR_ISSUE_QUEUE_ENTRIES_OVER_THRESHOLD PMC_EV_PPC7450_GPR_ISSUE_QUEUE_STALLED PMC_EV_PPC7450_IU1_INSTR_COMPLETED PMC_EV_PPC7450_DSSALL_INSTR_COMPLETED PMC_EV_PPC7450_TLBSYNC_INSTR_COMPLETED PMC_EV_PPC7450_SYNC_INSTR_COMPLETED PMC_EV_PPC7450_SS_SM_INSTR_PIECES PMC_EV_PPC7450_DTLB_HW_SEARCH_CYCLES PMC_EV_PPC7450_SNOOP_RETRIES PMC_EV_PPC7450_SUCCESSFUL_STWCX PMC_EV_PPC7450_DST_STREAM_3_CACHE_LINE_FETCHES PMC_EV_PPC7450_THIRD_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLY PMC_EV_PPC7450_MISPREDICTED_BRANCHES PMC_EV_PPC7450_FOLDED_BRANCHES PMC_EV_PPC7450_FP_STORE_DOUBLE_COMPLETES_IN_LSU PMC_EV_PPC7450_L2_CACHE_HITS PMC_EV_PPC7450_L3_CACHE_HITS PMC_EV_PPC7450_L2_INSTR_CACHE_MISSES PMC_EV_PPC7450_L3_INSTR_CACHE_MISSES PMC_EV_PPC7450_L2_DATA_CACHE_MISSES PMC_EV_PPC7450_L3_DATA_CACHE_MISSES PMC_EV_PPC7450_L2_LOAD_HITS PMC_EV_PPC7450_L2_STORE_HITS PMC_EV_PPC7450_L3_LOAD_HITS PMC_EV_PPC7450_L3_STORE_HITS PMC_EV_PPC7450_L2_TOUCH_HITS PMC_EV_PPC7450_L3_TOUCH_HITS PMC_EV_PPC7450_SNOOP_MODIFIED PMC_EV_PPC7450_SNOOP_VALID PMC_EV_PPC7450_INTERVENTION PMC_EV_PPC7450_L2_CACHE_MISSES PMC_EV_PPC7450_L3_CACHE_MISSES PMC_EV_PPC7450_L2_CACHE_CASTOUTS PMC_EV_PPC7450_L3_CACHE_CASTOUTS PMC_EV_PPC7450_L2SQ_FULL_CYCLES PMC_EV_PPC7450_L3SQ_FULL_CYCLES PMC_EV_PPC7450_RAQ_FULL_CYCLES PMC_EV_PPC7450_WAQ_FULL_CYCLES PMC_EV_PPC7450_L1_EXTERNAL_INTERVENTIONS PMC_EV_PPC7450_L2_EXTERNAL_INTERVENTIONS PMC_EV_PPC7450_L3_EXTERNAL_INTERVENTIONS PMC_EV_PPC7450_EXTERNAL_INTERVENTIONS PMC_EV_PPC7450_EXTERNAL_PUSHES PMC_EV_PPC7450_EXTERNAL_SNOOP_RETRY PMC_EV_PPC7450_DTQ_FULL_CYCLES PMC_EV_PPC7450_BUS_RETRY PMC_EV_PPC7450_L2_VALID_REQUEST PMC_EV_PPC7450_BORDQ_FULL PMC_EV_PPC7450_BUS_TAS_FOR_READS PMC_EV_PPC7450_BUS_TAS_FOR_WRITES PMC_EV_PPC7450_BUS_READS_NOT_RETRIED PMC_EV_PPC7450_BUS_WRITES_NOT_RETRIED PMC_EV_PPC7450_BUS_READS_WRITES_NOT_RETRIED PMC_EV_PPC7450_BUS_RETRY_DUE_TO_L1_RETRY PMC_EV_PPC7450_BUS_RETRY_DUE_TO_PREVIOUS_ADJACENT PMC_EV_PPC7450_BUS_RETRY_DUE_TO_COLLISION PMC_EV_PPC7450_BUS_RETRY_DUE_TO_INTERVENTION_ORDERING PMC_EV_PPC7450_SNOOP_REQUESTS PMC_EV_PPC7450_PREFETCH_ENGINE_REQUEST PMC_EV_PPC7450_PREFETCH_ENGINE_COLLISION_VS_LOAD PMC_EV_PPC7450_PREFETCH_ENGINE_COLLISION_VS_STORE PMC_EV_PPC7450_PREFETCH_ENGINE_COLLISION_VS_INSTR_FETCH PMC_EV_PPC7450_PREFETCH_ENGINE_COLLISION_VS_LOAD_STORE_INSTR_FETCH PMC_EV_PPC7450_PREFETCH_ENGINE_FULL PMC_EV_PPC970__BLOCK_START PMC_EV_PPC970_INSTR_COMPLETED PMC_EV_PPC970_MARKED_GROUP_DISPATCH PMC_EV_PPC970_MARKED_STORE_COMPLETED PMC_EV_PPC970_GCT_EMPTY PMC_EV_PPC970_RUN_CYCLES PMC_EV_PPC970_OVERFLOW PMC_EV_PPC970_CYCLES PMC_EV_PPC970_THRESHOLD_TIMEOUT PMC_EV_PPC970_GROUP_DISPATCH PMC_EV_PPC970_BR_MARKED_INSTR_FINISH PMC_EV_PPC970_GCT_EMPTY_BY_SRQ_FULL PMC_EV_PPC970_STOP_COMPLETION PMC_EV_PPC970_LSU_EMPTY PMC_EV_PPC970_MARKED_STORE_WITH_INTR PMC_EV_PPC970_CYCLES_IN_SUPER PMC_EV_PPC970_VPU_MARKED_INSTR_COMPLETED PMC_EV_PPC970_FXU0_IDLE_FXU1_BUSY PMC_EV_PPC970_SRQ_EMPTY PMC_EV_PPC970_MARKED_GROUP_COMPLETED PMC_EV_PPC970_CR_MARKED_INSTR_FINISH PMC_EV_PPC970_DISPATCH_SUCCESS PMC_EV_PPC970_FXU0_IDLE_FXU1_IDLE PMC_EV_PPC970_ONE_PLUS_INSTR_COMPLETED PMC_EV_PPC970_GROUP_MARKED_IDU PMC_EV_PPC970_MARKED_GROUP_COMPLETE_TIMEOUT PMC_EV_PPC970_FXU0_BUSY_FXU1_BUSY PMC_EV_PPC970_MARKED_STORE_SENT_TO_STS PMC_EV_PPC970_FXU_MARKED_INSTR_FINISHED PMC_EV_PPC970_MARKED_GROUP_ISSUED PMC_EV_PPC970_FXU0_BUSY_FXU1_IDLE PMC_EV_PPC970_GROUP_COMPLETED PMC_EV_PPC970_FPU_MARKED_INSTR_COMPLETED PMC_EV_PPC970_MARKED_INSTR_FINISH_ANY_UNIT PMC_EV_PPC970_EXTERNAL_INTERRUPT PMC_EV_PPC970_GROUP_DISPATCH_REJECT PMC_EV_PPC970_LSU_MARKED_INSTR_FINISH PMC_EV_PPC970_TIMEBASE_EVENT PMC_EV_PPC970_LSU_COMPLETION_STALL PMC_EV_PPC970_FXU_COMPLETION_STALL PMC_EV_PPC970_DCACHE_MISS_COMPLETION_STALL PMC_EV_PPC970_FPU_COMPLETION_STALL PMC_EV_PPC970_FXU_LONG_INSTR_COMPLETION_STALL PMC_EV_PPC970_REJECT_COMPLETION_STALL PMC_EV_PPC970_FPU_LONG_INSTR_COMPLETION_STALL PMC_EV_PPC970_GCT_EMPTY_BY_ICACHE_MISS PMC_EV_PPC970_REJECT_COMPLETION_STALL_ERAT_MISS PMC_EV_PPC970_GCT_EMPTY_BY_BRANCH_MISS_PREDICT PMC_EV_PPC970_BUS_HIGH PMC_EV_PPC970_BUS_LOW PMC_EV_PPC970_ADDER PMC_EV_POWER8__BLOCK_START PMC_EV_POWER8_CYCLES PMC_EV_POWER8_CYCLES_WITH_INSTRS_COMPLETED PMC_EV_POWER8_FPU_INSTR_COMPLETED PMC_EV_POWER8_ERAT_INSTR_MISS PMC_EV_POWER8_CYCLES_IDLE PMC_EV_POWER8_CYCLES_WITH_ANY_THREAD_RUNNING PMC_EV_POWER8_STORE_COMPLETED PMC_EV_POWER8_INSTR_DISPATCHED PMC_EV_POWER8_CYCLES_RUNNING PMC_EV_POWER8_ERAT_DATA_MISS PMC_EV_POWER8_EXTERNAL_INTERRUPT PMC_EV_POWER8_BRANCH_TAKEN PMC_EV_POWER8_L1_INSTR_MISS PMC_EV_POWER8_L2_LOAD_MISS PMC_EV_POWER8_STORE_NO_REAL_ADDR PMC_EV_POWER8_INSTR_COMPLETED_WITH_ALL_THREADS_RUNNING PMC_EV_POWER8_L1_LOAD_MISS PMC_EV_POWER8_TIMEBASE_EVENT PMC_EV_POWER8_L3_INSTR_MISS PMC_EV_POWER8_TLB_DATA_MISS PMC_EV_POWER8_L3_LOAD_MISS PMC_EV_POWER8_LOAD_NO_REAL_ADDR PMC_EV_POWER8_CYCLES_WITH_INSTRS_DISPATCHED PMC_EV_POWER8_CYCLES_RUNNING_PURR_INC PMC_EV_POWER8_BRANCH_MISPREDICTED PMC_EV_POWER8_PREFETCHED_INSTRS_DISCARDED PMC_EV_POWER8_INSTR_COMPLETED_RUNNING PMC_EV_POWER8_TLB_INSTR_MISS PMC_EV_POWER8_CACHE_LOAD_MISS PMC_EV_POWER8_INSTR_COMPLETED PMC_EV_E500__BLOCK_START PMC_EV_E500_CYCLES PMC_EV_E500_INSTR_COMPLETED PMC_EV_E500_UOPS_COMPLETED PMC_EV_E500_INSTR_FETCHED PMC_EV_E500_UOPS_DECODED PMC_EV_E500_PM_EVENT_TRANSITIONS PMC_EV_E500_PM_EVENT_CYCLES PMC_EV_E500_BRANCH_INSTRS_COMPLETED PMC_EV_E500_LOAD_UOPS_COMPLETED PMC_EV_E500_STORE_UOPS_COMPLETED PMC_EV_E500_CQ_REDIRECTS PMC_EV_E500_BRANCHES_FINISHED PMC_EV_E500_TAKEN_BRANCHES_FINISHED PMC_EV_E500_FINISHED_UNCOND_BRANCHES_MISS_BTB PMC_EV_E500_BRANCH_MISPRED PMC_EV_E500_BTB_BRANCH_MISPRED_FROM_DIRECTION PMC_EV_E500_BTB_HITS_PSEUDO_HITS PMC_EV_E500_CYCLES_DECODE_STALLED PMC_EV_E500_CYCLES_ISSUE_STALLED PMC_EV_E500_CYCLES_BRANCH_ISSUE_STALLED PMC_EV_E500_CYCLES_SU1_SCHED_STALLED PMC_EV_E500_CYCLES_SU2_SCHED_STALLED PMC_EV_E500_CYCLES_MU_SCHED_STALLED PMC_EV_E500_CYCLES_LRU_SCHED_STALLED PMC_EV_E500_CYCLES_BU_SCHED_STALLED PMC_EV_E500_TOTAL_TRANSLATED PMC_EV_E500_LOADS_TRANSLATED PMC_EV_E500_STORES_TRANSLATED PMC_EV_E500_TOUCHES_TRANSLATED PMC_EV_E500_CACHEOPS_TRANSLATED PMC_EV_E500_CACHE_INHIBITED_ACCESS_TRANSLATED PMC_EV_E500_GUARDED_LOADS_TRANSLATED PMC_EV_E500_WRITE_THROUGH_STORES_TRANSLATED PMC_EV_E500_MISALIGNED_LOAD_STORE_ACCESS_TRANSLATED PMC_EV_E500_TOTAL_ALLOCATED_TO_DLFB PMC_EV_E500_LOADS_TRANSLATED_ALLOCATED_TO_DLFB PMC_EV_E500_STORES_COMPLETED_ALLOCATED_TO_DLFB PMC_EV_E500_TOUCHES_TRANSLATED_ALLOCATED_TO_DLFB PMC_EV_E500_STORES_COMPLETED PMC_EV_E500_DATA_L1_CACHE_LOCKS PMC_EV_E500_DATA_L1_CACHE_RELOADS PMC_EV_E500_DATA_L1_CACHE_CASTOUTS PMC_EV_E500_LOAD_MISS_DLFB_FULL PMC_EV_E500_LOAD_MISS_LDQ_FULL PMC_EV_E500_LOAD_GUARDED_MISS PMC_EV_E500_STORE_TRANSLATE_WHEN_QUEUE_FULL PMC_EV_E500_ADDRESS_COLLISION PMC_EV_E500_DATA_MMU_MISS PMC_EV_E500_DATA_MMU_BUSY PMC_EV_E500_PART2_MISALIGNED_CACHE_ACCESS PMC_EV_E500_LOAD_MISS_DLFB_FULL_CYCLES PMC_EV_E500_LOAD_MISS_LDQ_FULL_CYCLES PMC_EV_E500_LOAD_GUARDED_MISS_CYCLES PMC_EV_E500_STORE_TRANSLATE_WHEN_QUEUE_FULL_CYCLES PMC_EV_E500_ADDRESS_COLLISION_CYCLES PMC_EV_E500_DATA_MMU_MISS_CYCLES PMC_EV_E500_DATA_MMU_BUSY_CYCLES PMC_EV_E500_PART2_MISALIGNED_CACHE_ACCESS_CYCLES PMC_EV_E500_INSTR_L1_CACHE_LOCKS PMC_EV_E500_INSTR_L1_CACHE_RELOADS PMC_EV_E500_INSTR_L1_CACHE_FETCHES PMC_EV_E500_INSTR_MMU_TLB4K_RELOADS PMC_EV_E500_INSTR_MMU_VSP_RELOADS PMC_EV_E500_DATA_MMU_TLB4K_RELOADS PMC_EV_E500_DATA_MMU_VSP_RELOADS PMC_EV_E500_L2MMU_MISSES PMC_EV_E500_BIU_MASTER_REQUESTS PMC_EV_E500_BIU_MASTER_INSTR_SIDE_REQUESTS PMC_EV_E500_BIU_MASTER_DATA_SIDE_REQUESTS PMC_EV_E500_BIU_MASTER_DATA_SIDE_CASTOUT_REQUESTS PMC_EV_E500_BIU_MASTER_RETRIES PMC_EV_E500_SNOOP_REQUESTS PMC_EV_E500_SNOOP_HITS PMC_EV_E500_SNOOP_PUSHES PMC_EV_E500_SNOOP_RETRIES PMC_EV_E500_DLFB_LOAD_MISS_CYCLES PMC_EV_E500_ILFB_FETCH_MISS_CYCLES PMC_EV_E500_EXT_INPU_INTR_LATENCY_CYCLES PMC_EV_E500_CRIT_INPUT_INTR_LATENCY_CYCLES PMC_EV_E500_EXT_INPUT_INTR_PENDING_LATENCY_CYCLES PMC_EV_E500_CRIT_INPUT_INTR_PENDING_LATENCY_CYCLES PMC_EV_E500_PMC0_OVERFLOW PMC_EV_E500_PMC1_OVERFLOW PMC_EV_E500_PMC2_OVERFLOW PMC_EV_E500_PMC3_OVERFLOW PMC_EV_E500_INTERRUPTS_TAKEN PMC_EV_E500_EXT_INPUT_INTR_TAKEN PMC_EV_E500_CRIT_INPUT_INTR_TAKEN PMC_EV_E500_SYSCALL_TRAP_INTR PMC_EV_E500_TLB_BIT_TRANSITIONS PMC_EV_E500_L2_LINEFILL_BUFFER PMC_EV_E500_LV2_VS PMC_EV_E500_CASTOUTS_RELEASED PMC_EV_E500_INTV_ALLOCATIONS PMC_EV_E500_DLFB_RETRIES_TO_MBAR PMC_EV_E500_STORE_RETRIES PMC_EV_E500_STASH_L1_HITS PMC_EV_E500_STASH_L2_HITS PMC_EV_E500_STASH_BUSY_1 PMC_EV_E500_STASH_BUSY_2 PMC_EV_E500_STASH_BUSY_3 PMC_EV_E500_STASH_HITS PMC_EV_E500_STASH_HIT_DLFB PMC_EV_E500_STASH_REQUESTS PMC_EV_E500_STASH_REQUESTS_L1 PMC_EV_E500_STASH_REQUESTS_L2 PMC_EV_E500_STALLS_NO_CAQ_OR_COB PMC_EV_E500_L2_CACHE_ACCESSES PMC_EV_E500_L2_HIT_CACHE_ACCESSES PMC_EV_E500_L2_CACHE_DATA_ACCESSES PMC_EV_E500_L2_CACHE_DATA_HITS PMC_EV_E500_L2_CACHE_INSTR_ACCESSES PMC_EV_E500_L2_CACHE_INSTR_HITS PMC_EV_E500_L2_CACHE_ALLOCATIONS PMC_EV_E500_L2_CACHE_DATA_ALLOCATIONS PMC_EV_E500_L2_CACHE_DIRTY_DATA_ALLOCATIONS PMC_EV_E500_L2_CACHE_INSTR_ALLOCATIONS PMC_EV_E500_L2_CACHE_UPDATES PMC_EV_E500_L2_CACHE_CLEAN_UPDATES PMC_EV_E500_L2_CACHE_DIRTY_UPDATES PMC_EV_E500_L2_CACHE_CLEAN_REDUNDANT_UPDATES PMC_EV_E500_L2_CACHE_DIRTY_REDUNDANT_UPDATES PMC_EV_E500_L2_CACHE_LOCKS PMC_EV_E500_L2_CACHE_CASTOUTS PMC_EV_E500_L2_CACHE_DATA_DIRTY_HITS PMC_EV_E500_INSTR_LFB_WENT_HIGH_PRIORITY PMC_EV_E500_SNOOP_THROTTLING_TURNED_ON PMC_EV_E500_L2_CLEAN_LINE_INVALIDATIONS PMC_EV_E500_L2_INCOHERENT_LINE_INVALIDATIONS PMC_EV_E500_L2_COHERENT_LINE_INVALIDATIONS PMC_EV_E500_COHERENT_LOOKUP_MISS_DUE_TO_VALID_BUT_INCOHERENT_MATCHES PMC_EV_E500_IAC1S_DETECTED PMC_EV_E500_IAC2S_DETECTED PMC_EV_E500_DAC1S_DTECTED PMC_EV_E500_DAC2S_DTECTED PMC_EV_E500_DVT0_DETECTED PMC_EV_E500_DVT1_DETECTED PMC_EV_E500_DVT2_DETECTED PMC_EV_E500_DVT3_DETECTED PMC_EV_E500_DVT4_DETECTED PMC_EV_E500_DVT5_DETECTED PMC_EV_E500_DVT6_DETECTED PMC_EV_E500_DVT7_DETECTED PMC_EV_E500_CYCLES_COMPLETION_STALLED_NEXUS_FIFO_FULL PMC_EV_E500_FPU_DOUBLE_PUMP PMC_EV_E500_FPU_FINISH PMC_EV_E500_FPU_DIVIDE_CYCLES PMC_EV_E500_FPU_DENORM_INPUT_CYCLES PMC_EV_E500_FPU_RESULT_STALL_CYCLES PMC_EV_E500_FPU_FPSCR_FULL_STALL PMC_EV_E500_FPU_PIPE_SYNC_STALLS PMC_EV_E500_FPU_INPUT_DATA_STALLS PMC_EV_E500_DECORATED_LOADS PMC_EV_E500_DECORATED_STORES PMC_EV_E500_LOAD_RETRIES PMC_EV_E500_STWCX_SUCCESSES PMC_EV_E500_STWCX_FAILURES PMC_EV_ARMV7__BLOCK_START PMC_EV_ARMV7_EVENT_00H PMC_EV_ARMV7_EVENT_01H PMC_EV_ARMV7_EVENT_02H PMC_EV_ARMV7_EVENT_03H PMC_EV_ARMV7_EVENT_04H PMC_EV_ARMV7_EVENT_05H PMC_EV_ARMV7_EVENT_06H PMC_EV_ARMV7_EVENT_07H PMC_EV_ARMV7_EVENT_08H PMC_EV_ARMV7_EVENT_09H PMC_EV_ARMV7_EVENT_0AH PMC_EV_ARMV7_EVENT_0BH PMC_EV_ARMV7_EVENT_0CH PMC_EV_ARMV7_EVENT_0DH PMC_EV_ARMV7_EVENT_0EH PMC_EV_ARMV7_EVENT_0FH PMC_EV_ARMV7_EVENT_10H PMC_EV_ARMV7_EVENT_11H PMC_EV_ARMV7_EVENT_12H PMC_EV_ARMV7_EVENT_13H PMC_EV_ARMV7_EVENT_14H PMC_EV_ARMV7_EVENT_15H PMC_EV_ARMV7_EVENT_16H PMC_EV_ARMV7_EVENT_17H PMC_EV_ARMV7_EVENT_18H PMC_EV_ARMV7_EVENT_19H PMC_EV_ARMV7_EVENT_1AH PMC_EV_ARMV7_EVENT_1BH PMC_EV_ARMV7_EVENT_1CH PMC_EV_ARMV7_EVENT_1DH PMC_EV_ARMV7_EVENT_1EH PMC_EV_ARMV7_EVENT_1FH PMC_EV_ARMV7_EVENT_20H PMC_EV_ARMV7_EVENT_21H PMC_EV_ARMV7_EVENT_22H PMC_EV_ARMV7_EVENT_23H PMC_EV_ARMV7_EVENT_24H PMC_EV_ARMV7_EVENT_25H PMC_EV_ARMV7_EVENT_26H PMC_EV_ARMV7_EVENT_27H PMC_EV_ARMV7_EVENT_28H PMC_EV_ARMV7_EVENT_29H PMC_EV_ARMV7_EVENT_2AH PMC_EV_ARMV7_EVENT_2BH PMC_EV_ARMV7_EVENT_2CH PMC_EV_ARMV7_EVENT_2DH PMC_EV_ARMV7_EVENT_2EH PMC_EV_ARMV7_EVENT_2FH PMC_EV_ARMV7_EVENT_30H PMC_EV_ARMV7_EVENT_31H PMC_EV_ARMV7_EVENT_32H PMC_EV_ARMV7_EVENT_33H PMC_EV_ARMV7_EVENT_34H PMC_EV_ARMV7_EVENT_35H PMC_EV_ARMV7_EVENT_36H PMC_EV_ARMV7_EVENT_37H PMC_EV_ARMV7_EVENT_38H PMC_EV_ARMV7_EVENT_39H PMC_EV_ARMV7_EVENT_3AH PMC_EV_ARMV7_EVENT_3BH PMC_EV_ARMV7_EVENT_3CH PMC_EV_ARMV7_EVENT_3DH PMC_EV_ARMV7_EVENT_3EH PMC_EV_ARMV7_EVENT_3FH PMC_EV_ARMV7_EVENT_40H PMC_EV_ARMV7_EVENT_41H PMC_EV_ARMV7_EVENT_42H PMC_EV_ARMV7_EVENT_43H PMC_EV_ARMV7_EVENT_44H PMC_EV_ARMV7_EVENT_45H PMC_EV_ARMV7_EVENT_46H PMC_EV_ARMV7_EVENT_47H PMC_EV_ARMV7_EVENT_48H PMC_EV_ARMV7_EVENT_49H PMC_EV_ARMV7_EVENT_4AH PMC_EV_ARMV7_EVENT_4BH PMC_EV_ARMV7_EVENT_4CH PMC_EV_ARMV7_EVENT_4DH PMC_EV_ARMV7_EVENT_4EH PMC_EV_ARMV7_EVENT_4FH PMC_EV_ARMV7_EVENT_50H PMC_EV_ARMV7_EVENT_51H PMC_EV_ARMV7_EVENT_52H PMC_EV_ARMV7_EVENT_53H PMC_EV_ARMV7_EVENT_54H PMC_EV_ARMV7_EVENT_55H PMC_EV_ARMV7_EVENT_56H PMC_EV_ARMV7_EVENT_57H PMC_EV_ARMV7_EVENT_58H PMC_EV_ARMV7_EVENT_59H PMC_EV_ARMV7_EVENT_5AH PMC_EV_ARMV7_EVENT_5BH PMC_EV_ARMV7_EVENT_5CH PMC_EV_ARMV7_EVENT_5DH PMC_EV_ARMV7_EVENT_5EH PMC_EV_ARMV7_EVENT_5FH PMC_EV_ARMV7_EVENT_60H PMC_EV_ARMV7_EVENT_61H PMC_EV_ARMV7_EVENT_62H PMC_EV_ARMV7_EVENT_63H PMC_EV_ARMV7_EVENT_64H PMC_EV_ARMV7_EVENT_65H PMC_EV_ARMV7_EVENT_66H PMC_EV_ARMV7_EVENT_67H PMC_EV_ARMV7_EVENT_68H PMC_EV_ARMV7_EVENT_69H PMC_EV_ARMV7_EVENT_6AH PMC_EV_ARMV7_EVENT_6BH PMC_EV_ARMV7_EVENT_6CH PMC_EV_ARMV7_EVENT_6DH PMC_EV_ARMV7_EVENT_6EH PMC_EV_ARMV7_EVENT_6FH PMC_EV_ARMV7_EVENT_70H PMC_EV_ARMV7_EVENT_71H PMC_EV_ARMV7_EVENT_72H PMC_EV_ARMV7_EVENT_73H PMC_EV_ARMV7_EVENT_74H PMC_EV_ARMV7_EVENT_75H PMC_EV_ARMV7_EVENT_76H PMC_EV_ARMV7_EVENT_77H PMC_EV_ARMV7_EVENT_78H PMC_EV_ARMV7_EVENT_79H PMC_EV_ARMV7_EVENT_7AH PMC_EV_ARMV7_EVENT_7BH PMC_EV_ARMV7_EVENT_7CH PMC_EV_ARMV7_EVENT_7DH PMC_EV_ARMV7_EVENT_7EH PMC_EV_ARMV7_EVENT_7FH PMC_EV_ARMV7_EVENT_80H PMC_EV_ARMV7_EVENT_81H PMC_EV_ARMV7_EVENT_82H PMC_EV_ARMV7_EVENT_83H PMC_EV_ARMV7_EVENT_84H PMC_EV_ARMV7_EVENT_85H PMC_EV_ARMV7_EVENT_86H PMC_EV_ARMV7_EVENT_87H PMC_EV_ARMV7_EVENT_88H PMC_EV_ARMV7_EVENT_89H PMC_EV_ARMV7_EVENT_8AH PMC_EV_ARMV7_EVENT_8BH PMC_EV_ARMV7_EVENT_8CH PMC_EV_ARMV7_EVENT_8DH PMC_EV_ARMV7_EVENT_8EH PMC_EV_ARMV7_EVENT_8FH PMC_EV_ARMV7_EVENT_90H PMC_EV_ARMV7_EVENT_91H PMC_EV_ARMV7_EVENT_92H PMC_EV_ARMV7_EVENT_93H PMC_EV_ARMV7_EVENT_94H PMC_EV_ARMV7_EVENT_95H PMC_EV_ARMV7_EVENT_96H PMC_EV_ARMV7_EVENT_97H PMC_EV_ARMV7_EVENT_98H PMC_EV_ARMV7_EVENT_99H PMC_EV_ARMV7_EVENT_9AH PMC_EV_ARMV7_EVENT_9BH PMC_EV_ARMV7_EVENT_9CH PMC_EV_ARMV7_EVENT_9DH PMC_EV_ARMV7_EVENT_9EH PMC_EV_ARMV7_EVENT_9FH PMC_EV_ARMV7_EVENT_A0H PMC_EV_ARMV7_EVENT_A1H PMC_EV_ARMV7_EVENT_A2H PMC_EV_ARMV7_EVENT_A3H PMC_EV_ARMV7_EVENT_A4H PMC_EV_ARMV7_EVENT_A5H PMC_EV_ARMV7_EVENT_A6H PMC_EV_ARMV7_EVENT_A7H PMC_EV_ARMV7_EVENT_A8H PMC_EV_ARMV7_EVENT_A9H PMC_EV_ARMV7_EVENT_AAH PMC_EV_ARMV7_EVENT_ABH PMC_EV_ARMV7_EVENT_ACH PMC_EV_ARMV7_EVENT_ADH PMC_EV_ARMV7_EVENT_AEH PMC_EV_ARMV7_EVENT_AFH PMC_EV_ARMV7_EVENT_B0H PMC_EV_ARMV7_EVENT_B1H PMC_EV_ARMV7_EVENT_B2H PMC_EV_ARMV7_EVENT_B3H PMC_EV_ARMV7_EVENT_B4H PMC_EV_ARMV7_EVENT_B5H PMC_EV_ARMV7_EVENT_B6H PMC_EV_ARMV7_EVENT_B7H PMC_EV_ARMV7_EVENT_B8H PMC_EV_ARMV7_EVENT_B9H PMC_EV_ARMV7_EVENT_BAH PMC_EV_ARMV7_EVENT_BBH PMC_EV_ARMV7_EVENT_BCH PMC_EV_ARMV7_EVENT_BDH PMC_EV_ARMV7_EVENT_BEH PMC_EV_ARMV7_EVENT_BFH PMC_EV_ARMV7_EVENT_C0H PMC_EV_ARMV7_EVENT_C1H PMC_EV_ARMV7_EVENT_C2H PMC_EV_ARMV7_EVENT_C3H PMC_EV_ARMV7_EVENT_C4H PMC_EV_ARMV7_EVENT_C5H PMC_EV_ARMV7_EVENT_C6H PMC_EV_ARMV7_EVENT_C7H PMC_EV_ARMV7_EVENT_C8H PMC_EV_ARMV7_EVENT_C9H PMC_EV_ARMV7_EVENT_CAH PMC_EV_ARMV7_EVENT_CBH PMC_EV_ARMV7_EVENT_CCH PMC_EV_ARMV7_EVENT_CDH PMC_EV_ARMV7_EVENT_CEH PMC_EV_ARMV7_EVENT_CFH PMC_EV_ARMV7_EVENT_D0H PMC_EV_ARMV7_EVENT_D1H PMC_EV_ARMV7_EVENT_D2H PMC_EV_ARMV7_EVENT_D3H PMC_EV_ARMV7_EVENT_D4H PMC_EV_ARMV7_EVENT_D5H PMC_EV_ARMV7_EVENT_D6H PMC_EV_ARMV7_EVENT_D7H PMC_EV_ARMV7_EVENT_D8H PMC_EV_ARMV7_EVENT_D9H PMC_EV_ARMV7_EVENT_DAH PMC_EV_ARMV7_EVENT_DBH PMC_EV_ARMV7_EVENT_DCH PMC_EV_ARMV7_EVENT_DDH PMC_EV_ARMV7_EVENT_DEH PMC_EV_ARMV7_EVENT_DFH PMC_EV_ARMV7_EVENT_E0H PMC_EV_ARMV7_EVENT_E1H PMC_EV_ARMV7_EVENT_E2H PMC_EV_ARMV7_EVENT_E3H PMC_EV_ARMV7_EVENT_E4H PMC_EV_ARMV7_EVENT_E5H PMC_EV_ARMV7_EVENT_E6H PMC_EV_ARMV7_EVENT_E7H PMC_EV_ARMV7_EVENT_E8H PMC_EV_ARMV7_EVENT_E9H PMC_EV_ARMV7_EVENT_EAH PMC_EV_ARMV7_EVENT_EBH PMC_EV_ARMV7_EVENT_ECH PMC_EV_ARMV7_EVENT_EDH PMC_EV_ARMV7_EVENT_EEH PMC_EV_ARMV7_EVENT_EFH PMC_EV_ARMV7_EVENT_F0H PMC_EV_ARMV7_EVENT_F1H PMC_EV_ARMV7_EVENT_F2H PMC_EV_ARMV7_EVENT_F3H PMC_EV_ARMV7_EVENT_F4H PMC_EV_ARMV7_EVENT_F5H PMC_EV_ARMV7_EVENT_F6H PMC_EV_ARMV7_EVENT_F7H PMC_EV_ARMV7_EVENT_F8H PMC_EV_ARMV7_EVENT_F9H PMC_EV_ARMV7_EVENT_FAH PMC_EV_ARMV7_EVENT_FBH PMC_EV_ARMV7_EVENT_FCH PMC_EV_ARMV7_EVENT_FDH PMC_EV_ARMV7_EVENT_FEH PMC_EV_ARMV7_EVENT_FFH PMC_EV_ARMV8__BLOCK_START PMC_EV_ARMV8_EVENT_00H PMC_EV_ARMV8_EVENT_01H PMC_EV_ARMV8_EVENT_02H PMC_EV_ARMV8_EVENT_03H PMC_EV_ARMV8_EVENT_04H PMC_EV_ARMV8_EVENT_05H PMC_EV_ARMV8_EVENT_06H PMC_EV_ARMV8_EVENT_07H PMC_EV_ARMV8_EVENT_08H PMC_EV_ARMV8_EVENT_09H PMC_EV_ARMV8_EVENT_0AH PMC_EV_ARMV8_EVENT_0BH PMC_EV_ARMV8_EVENT_0CH PMC_EV_ARMV8_EVENT_0DH PMC_EV_ARMV8_EVENT_0EH PMC_EV_ARMV8_EVENT_0FH PMC_EV_ARMV8_EVENT_10H PMC_EV_ARMV8_EVENT_11H PMC_EV_ARMV8_EVENT_12H PMC_EV_ARMV8_EVENT_13H PMC_EV_ARMV8_EVENT_14H PMC_EV_ARMV8_EVENT_15H PMC_EV_ARMV8_EVENT_16H PMC_EV_ARMV8_EVENT_17H PMC_EV_ARMV8_EVENT_18H PMC_EV_ARMV8_EVENT_19H PMC_EV_ARMV8_EVENT_1AH PMC_EV_ARMV8_EVENT_1BH PMC_EV_ARMV8_EVENT_1CH PMC_EV_ARMV8_EVENT_1DH PMC_EV_ARMV8_EVENT_1EH PMC_EV_ARMV8_EVENT_1FH PMC_EV_ARMV8_EVENT_20H PMC_EV_ARMV8_EVENT_21H PMC_EV_ARMV8_EVENT_22H PMC_EV_ARMV8_EVENT_23H PMC_EV_ARMV8_EVENT_24H PMC_EV_ARMV8_EVENT_25H PMC_EV_ARMV8_EVENT_26H PMC_EV_ARMV8_EVENT_27H PMC_EV_ARMV8_EVENT_28H PMC_EV_ARMV8_EVENT_29H PMC_EV_ARMV8_EVENT_2AH PMC_EV_ARMV8_EVENT_2BH PMC_EV_ARMV8_EVENT_2CH PMC_EV_ARMV8_EVENT_2DH PMC_EV_ARMV8_EVENT_2EH PMC_EV_ARMV8_EVENT_2FH PMC_EV_ARMV8_EVENT_30H PMC_EV_ARMV8_EVENT_31H PMC_EV_ARMV8_EVENT_32H PMC_EV_ARMV8_EVENT_33H PMC_EV_ARMV8_EVENT_34H PMC_EV_ARMV8_EVENT_35H PMC_EV_ARMV8_EVENT_36H PMC_EV_ARMV8_EVENT_37H PMC_EV_ARMV8_EVENT_38H PMC_EV_ARMV8_EVENT_39H PMC_EV_ARMV8_EVENT_3AH PMC_EV_ARMV8_EVENT_3BH PMC_EV_ARMV8_EVENT_3CH PMC_EV_ARMV8_EVENT_3DH PMC_EV_ARMV8_EVENT_3EH PMC_EV_ARMV8_EVENT_3FH PMC_EV_ARMV8_EVENT_40H PMC_EV_ARMV8_EVENT_41H PMC_EV_ARMV8_EVENT_42H PMC_EV_ARMV8_EVENT_43H PMC_EV_ARMV8_EVENT_44H PMC_EV_ARMV8_EVENT_45H PMC_EV_ARMV8_EVENT_46H PMC_EV_ARMV8_EVENT_47H PMC_EV_ARMV8_EVENT_48H PMC_EV_ARMV8_EVENT_49H PMC_EV_ARMV8_EVENT_4AH PMC_EV_ARMV8_EVENT_4BH PMC_EV_ARMV8_EVENT_4CH PMC_EV_ARMV8_EVENT_4DH PMC_EV_ARMV8_EVENT_4EH PMC_EV_ARMV8_EVENT_4FH PMC_EV_ARMV8_EVENT_50H PMC_EV_ARMV8_EVENT_51H PMC_EV_ARMV8_EVENT_52H PMC_EV_ARMV8_EVENT_53H PMC_EV_ARMV8_EVENT_54H PMC_EV_ARMV8_EVENT_55H PMC_EV_ARMV8_EVENT_56H PMC_EV_ARMV8_EVENT_57H PMC_EV_ARMV8_EVENT_58H PMC_EV_ARMV8_EVENT_59H PMC_EV_ARMV8_EVENT_5AH PMC_EV_ARMV8_EVENT_5BH PMC_EV_ARMV8_EVENT_5CH PMC_EV_ARMV8_EVENT_5DH PMC_EV_ARMV8_EVENT_5EH PMC_EV_ARMV8_EVENT_5FH PMC_EV_ARMV8_EVENT_60H PMC_EV_ARMV8_EVENT_61H PMC_EV_ARMV8_EVENT_62H PMC_EV_ARMV8_EVENT_63H PMC_EV_ARMV8_EVENT_64H PMC_EV_ARMV8_EVENT_65H PMC_EV_ARMV8_EVENT_66H PMC_EV_ARMV8_EVENT_67H PMC_EV_ARMV8_EVENT_68H PMC_EV_ARMV8_EVENT_69H PMC_EV_ARMV8_EVENT_6AH PMC_EV_ARMV8_EVENT_6BH PMC_EV_ARMV8_EVENT_6CH PMC_EV_ARMV8_EVENT_6DH PMC_EV_ARMV8_EVENT_6EH PMC_EV_ARMV8_EVENT_6FH PMC_EV_ARMV8_EVENT_70H PMC_EV_ARMV8_EVENT_71H PMC_EV_ARMV8_EVENT_72H PMC_EV_ARMV8_EVENT_73H PMC_EV_ARMV8_EVENT_74H PMC_EV_ARMV8_EVENT_75H PMC_EV_ARMV8_EVENT_76H PMC_EV_ARMV8_EVENT_77H PMC_EV_ARMV8_EVENT_78H PMC_EV_ARMV8_EVENT_79H PMC_EV_ARMV8_EVENT_7AH PMC_EV_ARMV8_EVENT_7BH PMC_EV_ARMV8_EVENT_7CH PMC_EV_ARMV8_EVENT_7DH PMC_EV_ARMV8_EVENT_7EH PMC_EV_ARMV8_EVENT_7FH PMC_EV_ARMV8_EVENT_80H PMC_EV_ARMV8_EVENT_81H PMC_EV_ARMV8_EVENT_82H PMC_EV_ARMV8_EVENT_83H PMC_EV_ARMV8_EVENT_84H PMC_EV_ARMV8_EVENT_85H PMC_EV_ARMV8_EVENT_86H PMC_EV_ARMV8_EVENT_87H PMC_EV_ARMV8_EVENT_88H PMC_EV_ARMV8_EVENT_89H PMC_EV_ARMV8_EVENT_8AH PMC_EV_ARMV8_EVENT_8BH PMC_EV_ARMV8_EVENT_8CH PMC_EV_ARMV8_EVENT_8DH PMC_EV_ARMV8_EVENT_8EH PMC_EV_ARMV8_EVENT_8FH PMC_EV_ARMV8_EVENT_90H PMC_EV_ARMV8_EVENT_91H PMC_EV_ARMV8_EVENT_92H PMC_EV_ARMV8_EVENT_93H PMC_EV_ARMV8_EVENT_94H PMC_EV_ARMV8_EVENT_95H PMC_EV_ARMV8_EVENT_96H PMC_EV_ARMV8_EVENT_97H PMC_EV_ARMV8_EVENT_98H PMC_EV_ARMV8_EVENT_99H PMC_EV_ARMV8_EVENT_9AH PMC_EV_ARMV8_EVENT_9BH PMC_EV_ARMV8_EVENT_9CH PMC_EV_ARMV8_EVENT_9DH PMC_EV_ARMV8_EVENT_9EH PMC_EV_ARMV8_EVENT_9FH PMC_EV_ARMV8_EVENT_A0H PMC_EV_ARMV8_EVENT_A1H PMC_EV_ARMV8_EVENT_A2H PMC_EV_ARMV8_EVENT_A3H PMC_EV_ARMV8_EVENT_A4H PMC_EV_ARMV8_EVENT_A5H PMC_EV_ARMV8_EVENT_A6H PMC_EV_ARMV8_EVENT_A7H PMC_EV_ARMV8_EVENT_A8H PMC_EV_ARMV8_EVENT_A9H PMC_EV_ARMV8_EVENT_AAH PMC_EV_ARMV8_EVENT_ABH PMC_EV_ARMV8_EVENT_ACH PMC_EV_ARMV8_EVENT_ADH PMC_EV_ARMV8_EVENT_AEH PMC_EV_ARMV8_EVENT_AFH PMC_EV_ARMV8_EVENT_B0H PMC_EV_ARMV8_EVENT_B1H PMC_EV_ARMV8_EVENT_B2H PMC_EV_ARMV8_EVENT_B3H PMC_EV_ARMV8_EVENT_B4H PMC_EV_ARMV8_EVENT_B5H PMC_EV_ARMV8_EVENT_B6H PMC_EV_ARMV8_EVENT_B7H PMC_EV_ARMV8_EVENT_B8H PMC_EV_ARMV8_EVENT_B9H PMC_EV_ARMV8_EVENT_BAH PMC_EV_ARMV8_EVENT_BBH PMC_EV_ARMV8_EVENT_BCH PMC_EV_ARMV8_EVENT_BDH PMC_EV_ARMV8_EVENT_BEH PMC_EV_ARMV8_EVENT_BFH PMC_EV_ARMV8_EVENT_C0H PMC_EV_ARMV8_EVENT_C1H PMC_EV_ARMV8_EVENT_C2H PMC_EV_ARMV8_EVENT_C3H PMC_EV_ARMV8_EVENT_C4H PMC_EV_ARMV8_EVENT_C5H PMC_EV_ARMV8_EVENT_C6H PMC_EV_ARMV8_EVENT_C7H PMC_EV_ARMV8_EVENT_C8H PMC_EV_ARMV8_EVENT_C9H PMC_EV_ARMV8_EVENT_CAH PMC_EV_ARMV8_EVENT_CBH PMC_EV_ARMV8_EVENT_CCH PMC_EV_ARMV8_EVENT_CDH PMC_EV_ARMV8_EVENT_CEH PMC_EV_ARMV8_EVENT_CFH PMC_EV_ARMV8_EVENT_D0H PMC_EV_ARMV8_EVENT_D1H PMC_EV_ARMV8_EVENT_D2H PMC_EV_ARMV8_EVENT_D3H PMC_EV_ARMV8_EVENT_D4H PMC_EV_ARMV8_EVENT_D5H PMC_EV_ARMV8_EVENT_D6H PMC_EV_ARMV8_EVENT_D7H PMC_EV_ARMV8_EVENT_D8H PMC_EV_ARMV8_EVENT_D9H PMC_EV_ARMV8_EVENT_DAH PMC_EV_ARMV8_EVENT_DBH PMC_EV_ARMV8_EVENT_DCH PMC_EV_ARMV8_EVENT_DDH PMC_EV_ARMV8_EVENT_DEH PMC_EV_ARMV8_EVENT_DFH PMC_EV_ARMV8_EVENT_E0H PMC_EV_ARMV8_EVENT_E1H PMC_EV_ARMV8_EVENT_E2H PMC_EV_ARMV8_EVENT_E3H PMC_EV_ARMV8_EVENT_E4H PMC_EV_ARMV8_EVENT_E5H PMC_EV_ARMV8_EVENT_E6H PMC_EV_ARMV8_EVENT_E7H PMC_EV_ARMV8_EVENT_E8H PMC_EV_ARMV8_EVENT_E9H PMC_EV_ARMV8_EVENT_EAH PMC_EV_ARMV8_EVENT_EBH PMC_EV_ARMV8_EVENT_ECH PMC_EV_ARMV8_EVENT_EDH PMC_EV_ARMV8_EVENT_EEH PMC_EV_ARMV8_EVENT_EFH PMC_EV_ARMV8_EVENT_F0H PMC_EV_ARMV8_EVENT_F1H PMC_EV_ARMV8_EVENT_F2H PMC_EV_ARMV8_EVENT_F3H PMC_EV_ARMV8_EVENT_F4H PMC_EV_ARMV8_EVENT_F5H PMC_EV_ARMV8_EVENT_F6H PMC_EV_ARMV8_EVENT_F7H PMC_EV_ARMV8_EVENT_F8H PMC_EV_ARMV8_EVENT_F9H PMC_EV_ARMV8_EVENT_FAH PMC_EV_ARMV8_EVENT_FBH PMC_EV_ARMV8_EVENT_FCH PMC_EV_ARMV8_EVENT_FDH PMC_EV_ARMV8_EVENT_FEH PMC_EV_ARMV8_EVENT_FFH pmc_event pmc_event_descr __ARRAY_SIZE_TYPE__ pmc_class_table pm_evc_name pm_evc_name_size __uint32_t __size_t size_t pm_evc_class PMC_CLASS_TSC PMC_CLASS_K7 PMC_CLASS_K8 PMC_CLASS_P5 PMC_CLASS_P6 PMC_CLASS_P4 PMC_CLASS_IAF PMC_CLASS_IAP PMC_CLASS_UCF PMC_CLASS_UCP PMC_CLASS_XSCALE PMC_CLASS_MIPS24K PMC_CLASS_OCTEON PMC_CLASS_PPC7450 PMC_CLASS_PPC970 PMC_CLASS_SOFT PMC_CLASS_ARMV7 PMC_CLASS_ARMV8 PMC_CLASS_MIPS74K PMC_CLASS_E500 PMC_CLASS_BERI PMC_CLASS_POWER8 pmc_class pm_evc_event_table pm_evc_event_table_size pm_evc_allocate_pmc int pm_caps uint32_t pm_cpu pm_class pm_ev pm_flags pm_mode PMC_MODE_SS PMC_MODE_SC PMC_MODE_TS PMC_MODE_TC pmc_mode pm_pmcid pmc_id_t pm_count long long unsigned int __uint64_t uint64_t pmc_value_t pm_md pm_amd pm_amd_config pm_amd_sub_class pmc_md_amd_op_pmcallocate pm_iap pm_iap_config pm_iap_rsp pmc_md_iap_op_pmcallocate pm_ucf pm_ucf_flags unsigned short __uint16_t uint16_t pmc_md_ucf_op_pmcallocate pm_ucp pm_ucp_config pmc_md_ucp_op_pmcallocate __pad pmc_md_op_pmcallocate pmc_op_pmcallocate pmc_class_descr pmc_mdep_class_list pmc_mdep_class_list_size cpu_info pm_cputype PMC_CPU_AMD_K7 PMC_CPU_AMD_K8 PMC_CPU_INTEL_P5 PMC_CPU_INTEL_P6 PMC_CPU_INTEL_CL PMC_CPU_INTEL_PII PMC_CPU_INTEL_PIII PMC_CPU_INTEL_PM PMC_CPU_INTEL_PIV PMC_CPU_INTEL_CORE PMC_CPU_INTEL_CORE2 PMC_CPU_INTEL_CORE2EXTREME PMC_CPU_INTEL_ATOM PMC_CPU_INTEL_COREI7 PMC_CPU_INTEL_WESTMERE PMC_CPU_INTEL_SANDYBRIDGE PMC_CPU_INTEL_IVYBRIDGE PMC_CPU_INTEL_SANDYBRIDGE_XEON PMC_CPU_INTEL_IVYBRIDGE_XEON PMC_CPU_INTEL_HASWELL PMC_CPU_INTEL_ATOM_SILVERMONT PMC_CPU_INTEL_NEHALEM_EX PMC_CPU_INTEL_WESTMERE_EX PMC_CPU_INTEL_HASWELL_XEON PMC_CPU_INTEL_BROADWELL PMC_CPU_INTEL_BROADWELL_XEON PMC_CPU_INTEL_SKYLAKE PMC_CPU_INTEL_SKYLAKE_XEON PMC_CPU_INTEL_ATOM_GOLDMONT PMC_CPU_INTEL_XSCALE PMC_CPU_MIPS_24K PMC_CPU_MIPS_OCTEON PMC_CPU_MIPS_74K PMC_CPU_MIPS_BERI PMC_CPU_PPC_7450 PMC_CPU_PPC_E500 PMC_CPU_PPC_970 PMC_CPU_PPC_POWER8 PMC_CPU_GENERIC PMC_CPU_ARMV7_CORTEX_A5 PMC_CPU_ARMV7_CORTEX_A7 PMC_CPU_ARMV7_CORTEX_A8 PMC_CPU_ARMV7_CORTEX_A9 PMC_CPU_ARMV7_CORTEX_A15 PMC_CPU_ARMV7_CORTEX_A17 PMC_CPU_ARMV8_CORTEX_A53 PMC_CPU_ARMV8_CORTEX_A57 PMC_CPU_ARMV8_CORTEX_A76 pmc_cputype pm_ncpu pm_npmc pm_nclass pm_classes pm_width pm_num pmc_classinfo pmc_cpuinfo soft_event_info pm_nevent pm_events pmc_dyn_event_descr pmc_op_getdyneventinfo pmc_syscall iaf_event_table tsc_event_table k8_event_table cortex_a8_event_table cortex_a9_event_table cortex_a53_event_table cortex_a57_event_table cortex_a76_event_table beri_event_table mips24k_event_table mips74k_event_table octeon_event_table ppc7450_event_table ppc970_event_table power8_event_table e500_event_table soft_class_table_descr tsc_class_table_descr k8_aliases k8_pmc_classes k8_class_table_descr k8_mask_fdfo pm_name pm_value pmc_masks k8_mask_lsrl k8_mask_llo k8_mask_dc k8_mask_dobee k8_mask_ddpi k8_mask_dabl k8_mask_bilr k8_mask_bfrlm k8_mask_bfil k8_mask_frfi k8_mask_frfdoi k8_mask_ffe k8_mask_nmcpae k8_mask_nmct k8_mask_nmcbs k8_mask_nsc k8_mask_npr k8_mask_nhbb generic_aliases generic_pmc_classes pmc_capability_names pmc_class_names pmc_class_map pmc_cputype_names pmc_cputype_map pmc_disposition_names pmc_mode_names pmc_state_names PMC_CAP_INTERRUPT PMC_CAP_USER PMC_CAP_SYSTEM PMC_CAP_EDGE PMC_CAP_THRESHOLD PMC_CAP_READ PMC_CAP_WRITE PMC_CAP_INVERT PMC_CAP_QUALIFIER PMC_CAP_PRECISE PMC_CAP_TAGGING PMC_CAP_CASCADE pmc_caps PMC_OP_CONFIGURELOG PMC_OP_FLUSHLOG PMC_OP_GETCPUINFO PMC_OP_GETDRIVERSTATS PMC_OP_GETMODULEVERSION PMC_OP_GETPMCINFO PMC_OP_PMCADMIN PMC_OP_PMCALLOCATE PMC_OP_PMCATTACH PMC_OP_PMCDETACH PMC_OP_PMCGETMSR PMC_OP_PMCRELEASE PMC_OP_PMCRW PMC_OP_PMCSETCOUNT PMC_OP_PMCSTART PMC_OP_PMCSTOP PMC_OP_WRITELOG PMC_OP_CLOSELOG PMC_OP_GETDYNEVENTINFO pmc_ops PMC_STATE_DISABLED PMC_STATE_FREE PMC_STATE_ALLOCATED PMC_STATE_STOPPED PMC_STATE_RUNNING PMC_STATE_DELETED PMC_STATE_MAX pmc_state PMC_DISP_STANDALONE PMC_DISP_FREE PMC_DISP_THREAD PMC_DISP_UNKNOWN pmc_disp __int32_t int32_t pm_pmcs pm_enabled pm_rowdisp pm_ownerpid __pid_t pid_t pm_event pm_reloadcount pmc_info pmc_pmcinfo unsigned char pmc_mdep_is_compatible_class pc n strsep pmc_pmu_enabled pmc_pmu_pmcallocate syscall free errx pmc_match_event_name name canonicalname nc c cc __getCurrentRuneLocale __magic __encoding __sgetrune __ct_rune_t __rune_t __sputrune __invalid_rune __runetype long unsigned int __maplower __mapupper __runetype_ext __nranges __ranges __min __max __map __types _RuneEntry _RuneRange __maplower_ext __mapupper_ext __variable __variable_len _RuneLocale __sbtoupper _c modfind modstat version refs id data intval uintval u_int longval long int ulongval u_long modspecific modspecific_t module_stat pmc_npmc cpu pmc_parse_mask pmask p evmask q r pm pmc_allocate pmc_match_event_class pmc_attach pmc_capabilities pmc_configure_logfile pmc_detach pmc_disable pmc_enable pmc_event_names_of_class pmc_flush_logfile pmc_close_logfile pmc_get_driver_stats pmc_get_msr pmc_init pmc_name_of_capability pmc_name_of_class pmc_name_of_cputype pmc_name_of_disposition _pmc_name_of_event pmc_name_of_event pmc_name_of_mode pmc_name_of_state pmc_ncpu pmc_read pmc_release pmc_rw pmc_set pmc_start pmc_stop pmc_width pmc_write pmc_writelog soft_allocate_pmc tsc_allocate_pmc k8_allocate_pmc pmc_config count pmcid flags mode ctrspec retval spec_copy ctrname alias pcd ev out pmc_attach_args pm_pmc pm_pid pmc_op_pmcattach pid pmc caps i cl cla pm_logfd pmc_op_configurelog fd pci pmc_detach_args ssa pm_state pmc_op_pmcadmin nevents eventnames names gms pm_intr_ignored pm_intr_processed pm_intr_bufferfull pm_syscalls pm_syscall_errors pm_buffer_requests pm_buffer_requests_failed pm_log_sweeps pmc_op_getdriverstats ds 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M M 'M ?M HM UM P cM lM yM M M M M M M M M f L f t f f f f f 4 f \ f f f f f f 8 f ` f f f f f f 0 f P f p f f f f f 8 f d f f f f f ( f L f l f f f pmc_name_of_capability errx pmc_rw .debug_abbrev pmc_ncpu .rel.text pmc_mdep_class_list pmc_start .mcount _pmc_name_of_event .comment pmc_init __mb_sb_limit memset pmc_set k8_mask_nmct modstat pmc_get_driver_stats .bss pmc_match_event_class pmc_event_names_of_class pmc_name_of_class generic_pmc_classes k8_pmc_classes pmc_mdep_event_aliases generic_aliases k8_aliases pmc_capability_names pmc_class_names pmc_disposition_names pmc_state_names pmc_cputype_names pmc_mode_names pmc_capabilities .debug_ranges k8_mask_nmcbs .debug_str .L.str pmc_get_msr k8_mask_npr __error k8_mask_bilr strchr soft_class_table_descr tsc_class_table_descr k8_class_table_descr strdup pmc_stop strcasecmp strncasecmp strsep k8_mask_llo pmc_cpuinfo pmc_pmcinfo cpu_info soft_event_info .rel.debug_info k8_mask_fdfo pmc_name_of_disposition k8_mask_bfrlm k8_mask_lsrl strtol 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O4. +@ 1@ & 0 7 | m 0 7 FreeBSD clang version 11.0.1 (git@github.com:llvm/llvm-project.git llvmorg-11.0.1-0-g43ff75f2c3fe) /usr/src/lib/libpmc/pmclog.c /usr/obj/usr/src/amd64.amd64/obj-lib32/lib/libpmc unsigned int PMCLOG_OK PMCLOG_EOF PMCLOG_REQUIRE_DATA PMCLOG_ERROR pmclog_state PMCLOG_TYPE_CLOSELOG PMCLOG_TYPE_DROPNOTIFY PMCLOG_TYPE_INITIALIZE PMCLOG_TYPE_PMCALLOCATE PMCLOG_TYPE_PMCATTACH PMCLOG_TYPE_PMCDETACH PMCLOG_TYPE_PROCCSW PMCLOG_TYPE_PROCEXEC PMCLOG_TYPE_PROCEXIT PMCLOG_TYPE_PROCFORK PMCLOG_TYPE_SYSEXIT PMCLOG_TYPE_USERDATA PMCLOG_TYPE_MAP_IN PMCLOG_TYPE_MAP_OUT PMCLOG_TYPE_CALLCHAIN PMCLOG_TYPE_PMCALLOCATEDYN PMCLOG_TYPE_THR_CREATE PMCLOG_TYPE_THR_EXIT PMCLOG_TYPE_PROC_CREATE pmclog_type PL_STATE_NEW_RECORD PL_STATE_EXPECTING_HEADER PL_STATE_PARTIAL_RECORD PL_STATE_ERROR pmclog_parser_state PMC_CPU_AMD_K7 PMC_CPU_AMD_K8 PMC_CPU_INTEL_P5 PMC_CPU_INTEL_P6 PMC_CPU_INTEL_CL PMC_CPU_INTEL_PII PMC_CPU_INTEL_PIII PMC_CPU_INTEL_PM PMC_CPU_INTEL_PIV PMC_CPU_INTEL_CORE PMC_CPU_INTEL_CORE2 PMC_CPU_INTEL_CORE2EXTREME PMC_CPU_INTEL_ATOM PMC_CPU_INTEL_COREI7 PMC_CPU_INTEL_WESTMERE PMC_CPU_INTEL_SANDYBRIDGE PMC_CPU_INTEL_IVYBRIDGE PMC_CPU_INTEL_SANDYBRIDGE_XEON PMC_CPU_INTEL_IVYBRIDGE_XEON PMC_CPU_INTEL_HASWELL PMC_CPU_INTEL_ATOM_SILVERMONT PMC_CPU_INTEL_NEHALEM_EX PMC_CPU_INTEL_WESTMERE_EX PMC_CPU_INTEL_HASWELL_XEON PMC_CPU_INTEL_BROADWELL PMC_CPU_INTEL_BROADWELL_XEON PMC_CPU_INTEL_SKYLAKE PMC_CPU_INTEL_SKYLAKE_XEON PMC_CPU_INTEL_ATOM_GOLDMONT PMC_CPU_INTEL_XSCALE PMC_CPU_MIPS_24K PMC_CPU_MIPS_OCTEON PMC_CPU_MIPS_74K PMC_CPU_MIPS_BERI PMC_CPU_PPC_7450 PMC_CPU_PPC_E500 PMC_CPU_PPC_970 PMC_CPU_PPC_POWER8 PMC_CPU_GENERIC PMC_CPU_ARMV7_CORTEX_A5 PMC_CPU_ARMV7_CORTEX_A7 PMC_CPU_ARMV7_CORTEX_A8 PMC_CPU_ARMV7_CORTEX_A9 PMC_CPU_ARMV7_CORTEX_A15 PMC_CPU_ARMV7_CORTEX_A17 PMC_CPU_ARMV8_CORTEX_A53 PMC_CPU_ARMV8_CORTEX_A57 PMC_CPU_ARMV8_CORTEX_A76 pmc_cputype PMC_EV_TSC__BLOCK_START PMC_EV_TSC_TSC PMC_EV_IAF__BLOCK_START PMC_EV_IAF_INSTR_RETIRED_ANY PMC_EV_IAF_CPU_CLK_UNHALTED_CORE PMC_EV_IAF_CPU_CLK_UNHALTED_REF PMC_EV_K7__BLOCK_START PMC_EV_K7_DC_ACCESSES PMC_EV_K7_DC_MISSES PMC_EV_K7_DC_REFILLS_FROM_L2 PMC_EV_K7_DC_REFILLS_FROM_SYSTEM PMC_EV_K7_DC_WRITEBACKS PMC_EV_K7_L1_DTLB_MISS_AND_L2_DTLB_HITS PMC_EV_K7_L1_AND_L2_DTLB_MISSES PMC_EV_K7_MISALIGNED_REFERENCES PMC_EV_K7_IC_FETCHES PMC_EV_K7_IC_MISSES PMC_EV_K7_L1_ITLB_MISSES PMC_EV_K7_L1_L2_ITLB_MISSES PMC_EV_K7_RETIRED_INSTRUCTIONS PMC_EV_K7_RETIRED_OPS PMC_EV_K7_RETIRED_BRANCHES PMC_EV_K7_RETIRED_BRANCHES_MISPREDICTED PMC_EV_K7_RETIRED_TAKEN_BRANCHES PMC_EV_K7_RETIRED_TAKEN_BRANCHES_MISPREDICTED PMC_EV_K7_RETIRED_FAR_CONTROL_TRANSFERS PMC_EV_K7_RETIRED_RESYNC_BRANCHES PMC_EV_K7_INTERRUPTS_MASKED_CYCLES PMC_EV_K7_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES PMC_EV_K7_HARDWARE_INTERRUPTS PMC_EV_K8__BLOCK_START PMC_EV_K8_FP_DISPATCHED_FPU_OPS PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD PMC_EV_K8_LS_MICROARCHITECTURAL_RESYNC_BY_SELF_MODIFYING_CODE PMC_EV_K8_LS_MICROARCHITECTURAL_RESYNC_BY_SNOOP PMC_EV_K8_LS_BUFFER2_FULL PMC_EV_K8_LS_LOCKED_OPERATION PMC_EV_K8_LS_MICROARCHITECTURAL_LATE_CANCEL PMC_EV_K8_LS_RETIRED_CFLUSH_INSTRUCTIONS PMC_EV_K8_LS_RETIRED_CPUID_INSTRUCTIONS PMC_EV_K8_DC_ACCESS PMC_EV_K8_DC_MISS PMC_EV_K8_DC_REFILL_FROM_L2 PMC_EV_K8_DC_REFILL_FROM_SYSTEM PMC_EV_K8_DC_COPYBACK PMC_EV_K8_DC_L1_DTLB_MISS_AND_L2_DTLB_HIT PMC_EV_K8_DC_L1_DTLB_MISS_AND_L2_DTLB_MISS PMC_EV_K8_DC_MISALIGNED_DATA_REFERENCE PMC_EV_K8_DC_MICROARCHITECTURAL_LATE_CANCEL PMC_EV_K8_DC_MICROARCHITECTURAL_EARLY_CANCEL PMC_EV_K8_DC_ONE_BIT_ECC_ERROR PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS PMC_EV_K8_BU_CPU_CLK_UNHALTED PMC_EV_K8_BU_INTERNAL_L2_REQUEST PMC_EV_K8_BU_FILL_REQUEST_L2_MISS PMC_EV_K8_BU_FILL_INTO_L2 PMC_EV_K8_IC_FETCH PMC_EV_K8_IC_MISS PMC_EV_K8_IC_REFILL_FROM_L2 PMC_EV_K8_IC_REFILL_FROM_SYSTEM PMC_EV_K8_IC_L1_ITLB_MISS_AND_L2_ITLB_HIT PMC_EV_K8_IC_L1_ITLB_MISS_AND_L2_ITLB_MISS PMC_EV_K8_IC_MICROARCHITECTURAL_RESYNC_BY_SNOOP PMC_EV_K8_IC_INSTRUCTION_FETCH_STALL PMC_EV_K8_IC_RETURN_STACK_HIT PMC_EV_K8_IC_RETURN_STACK_OVERFLOW PMC_EV_K8_FR_RETIRED_X86_INSTRUCTIONS PMC_EV_K8_FR_RETIRED_UOPS PMC_EV_K8_FR_RETIRED_BRANCHES PMC_EV_K8_FR_RETIRED_BRANCHES_MISPREDICTED PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED PMC_EV_K8_FR_RETIRED_FAR_CONTROL_TRANSFERS PMC_EV_K8_FR_RETIRED_RESYNCS PMC_EV_K8_FR_RETIRED_NEAR_RETURNS PMC_EV_K8_FR_RETIRED_NEAR_RETURNS_MISPREDICTED PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED_BY_ADDR_MISCOMPARE PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS PMC_EV_K8_FR_INTERRUPTS_MASKED_CYCLES PMC_EV_K8_FR_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES PMC_EV_K8_FR_TAKEN_HARDWARE_INTERRUPTS PMC_EV_K8_FR_DECODER_EMPTY PMC_EV_K8_FR_DISPATCH_STALLS PMC_EV_K8_FR_DISPATCH_STALL_FROM_BRANCH_ABORT_TO_RETIRE PMC_EV_K8_FR_DISPATCH_STALL_FOR_SERIALIZATION PMC_EV_K8_FR_DISPATCH_STALL_FOR_SEGMENT_LOAD PMC_EV_K8_FR_DISPATCH_STALL_WHEN_REORDER_BUFFER_IS_FULL PMC_EV_K8_FR_DISPATCH_STALL_WHEN_RESERVATION_STATIONS_ARE_FULL PMC_EV_K8_FR_DISPATCH_STALL_WHEN_FPU_IS_FULL PMC_EV_K8_FR_DISPATCH_STALL_WHEN_LS_IS_FULL PMC_EV_K8_FR_DISPATCH_STALL_WHEN_WAITING_FOR_ALL_TO_BE_QUIET PMC_EV_K8_FR_DISPATCH_STALL_WHEN_FAR_XFER_OR_RESYNC_BRANCH_PENDING PMC_EV_K8_FR_FPU_EXCEPTIONS PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR0 PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR1 PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR2 PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR3 PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOW PMC_EV_K8_NB_MEMORY_CONTROLLER_DRAM_COMMAND_SLOTS_MISSED PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION PMC_EV_K8_NB_SIZED_COMMANDS PMC_EV_K8_NB_PROBE_RESULT PMC_EV_K8_NB_HT_BUS0_BANDWIDTH PMC_EV_K8_NB_HT_BUS1_BANDWIDTH PMC_EV_K8_NB_HT_BUS2_BANDWIDTH PMC_EV_MIPS24K__BLOCK_START PMC_EV_MIPS24K_CYCLE PMC_EV_MIPS24K_INSTR_EXECUTED PMC_EV_MIPS24K_BRANCH_COMPLETED PMC_EV_MIPS24K_BRANCH_MISPRED PMC_EV_MIPS24K_RETURN PMC_EV_MIPS24K_RETURN_MISPRED PMC_EV_MIPS24K_RETURN_NOT_31 PMC_EV_MIPS24K_RETURN_NOTPRED PMC_EV_MIPS24K_ITLB_ACCESS PMC_EV_MIPS24K_ITLB_MISS PMC_EV_MIPS24K_DTLB_ACCESS PMC_EV_MIPS24K_DTLB_MISS PMC_EV_MIPS24K_JTLB_IACCESS PMC_EV_MIPS24K_JTLB_IMISS PMC_EV_MIPS24K_JTLB_DACCESS PMC_EV_MIPS24K_JTLB_DMISS PMC_EV_MIPS24K_IC_FETCH PMC_EV_MIPS24K_IC_MISS PMC_EV_MIPS24K_DC_LOADSTORE PMC_EV_MIPS24K_DC_WRITEBACK PMC_EV_MIPS24K_DC_MISS PMC_EV_MIPS24K_STORE_MISS PMC_EV_MIPS24K_LOAD_MISS PMC_EV_MIPS24K_INTEGER_COMPLETED PMC_EV_MIPS24K_FP_COMPLETED PMC_EV_MIPS24K_LOAD_COMPLETED PMC_EV_MIPS24K_STORE_COMPLETED PMC_EV_MIPS24K_BARRIER_COMPLETED PMC_EV_MIPS24K_MIPS16_COMPLETED PMC_EV_MIPS24K_NOP_COMPLETED PMC_EV_MIPS24K_INTEGER_MULDIV_COMPLETED PMC_EV_MIPS24K_RF_STALL PMC_EV_MIPS24K_INSTR_REFETCH PMC_EV_MIPS24K_STORE_COND_COMPLETED PMC_EV_MIPS24K_STORE_COND_FAILED PMC_EV_MIPS24K_ICACHE_REQUESTS PMC_EV_MIPS24K_ICACHE_HIT PMC_EV_MIPS24K_L2_WRITEBACK PMC_EV_MIPS24K_L2_ACCESS PMC_EV_MIPS24K_L2_MISS PMC_EV_MIPS24K_L2_ERR_CORRECTED PMC_EV_MIPS24K_EXCEPTIONS PMC_EV_MIPS24K_RF_CYCLES_STALLED PMC_EV_MIPS24K_IFU_CYCLES_STALLED PMC_EV_MIPS24K_ALU_CYCLES_STALLED PMC_EV_MIPS24K_UNCACHED_LOAD PMC_EV_MIPS24K_UNCACHED_STORE PMC_EV_MIPS24K_CP2_REG_TO_REG_COMPLETED PMC_EV_MIPS24K_MFTC_COMPLETED PMC_EV_MIPS24K_IC_BLOCKED_CYCLES PMC_EV_MIPS24K_DC_BLOCKED_CYCLES PMC_EV_MIPS24K_L2_IMISS_STALL_CYCLES PMC_EV_MIPS24K_L2_DMISS_STALL_CYCLES PMC_EV_MIPS24K_DMISS_CYCLES PMC_EV_MIPS24K_L2_MISS_CYCLES PMC_EV_MIPS24K_UNCACHED_BLOCK_CYCLES PMC_EV_MIPS24K_MDU_STALL_CYCLES PMC_EV_MIPS24K_FPU_STALL_CYCLES PMC_EV_MIPS24K_CP2_STALL_CYCLES PMC_EV_MIPS24K_COREXTEND_STALL_CYCLES PMC_EV_MIPS24K_ISPRAM_STALL_CYCLES PMC_EV_MIPS24K_DSPRAM_STALL_CYCLES PMC_EV_MIPS24K_CACHE_STALL_CYCLES PMC_EV_MIPS24K_LOAD_TO_USE_STALLS PMC_EV_MIPS24K_BASE_MISPRED_STALLS PMC_EV_MIPS24K_CPO_READ_STALLS PMC_EV_MIPS24K_BRANCH_MISPRED_CYCLES PMC_EV_MIPS24K_IFETCH_BUFFER_FULL PMC_EV_MIPS24K_FETCH_BUFFER_ALLOCATED PMC_EV_MIPS24K_EJTAG_ITRIGGER PMC_EV_MIPS24K_EJTAG_DTRIGGER PMC_EV_MIPS24K_FSB_LT_QUARTER PMC_EV_MIPS24K_FSB_QUARTER_TO_HALF PMC_EV_MIPS24K_FSB_GT_HALF PMC_EV_MIPS24K_FSB_FULL_PIPELINE_STALLS PMC_EV_MIPS24K_LDQ_LT_QUARTER PMC_EV_MIPS24K_LDQ_QUARTER_TO_HALF PMC_EV_MIPS24K_LDQ_GT_HALF PMC_EV_MIPS24K_LDQ_FULL_PIPELINE_STALLS PMC_EV_MIPS24K_WBB_LT_QUARTER PMC_EV_MIPS24K_WBB_QUARTER_TO_HALF PMC_EV_MIPS24K_WBB_GT_HALF PMC_EV_MIPS24K_WBB_FULL_PIPELINE_STALLS PMC_EV_MIPS24K_REQUEST_LATENCY PMC_EV_MIPS24K_REQUEST_COUNT PMC_EV_OCTEON__BLOCK_START PMC_EV_OCTEON_CLK PMC_EV_OCTEON_ISSUE PMC_EV_OCTEON_RET PMC_EV_OCTEON_NISSUE PMC_EV_OCTEON_SISSUE PMC_EV_OCTEON_DISSUE PMC_EV_OCTEON_IFI PMC_EV_OCTEON_BR PMC_EV_OCTEON_BRMIS PMC_EV_OCTEON_J PMC_EV_OCTEON_JMIS PMC_EV_OCTEON_REPLAY PMC_EV_OCTEON_IUNA PMC_EV_OCTEON_TRAP PMC_EV_OCTEON_UULOAD PMC_EV_OCTEON_UUSTORE PMC_EV_OCTEON_ULOAD PMC_EV_OCTEON_USTORE PMC_EV_OCTEON_EC PMC_EV_OCTEON_MC PMC_EV_OCTEON_CC PMC_EV_OCTEON_CSRC PMC_EV_OCTEON_CFETCH PMC_EV_OCTEON_CPREF PMC_EV_OCTEON_ICA PMC_EV_OCTEON_II PMC_EV_OCTEON_IP PMC_EV_OCTEON_CIMISS PMC_EV_OCTEON_WBUF PMC_EV_OCTEON_WDAT PMC_EV_OCTEON_WBUFLD PMC_EV_OCTEON_WBUFFL PMC_EV_OCTEON_WBUFTR PMC_EV_OCTEON_BADD PMC_EV_OCTEON_BADDL2 PMC_EV_OCTEON_BFILL PMC_EV_OCTEON_DDIDS PMC_EV_OCTEON_IDIDS PMC_EV_OCTEON_DIDNA PMC_EV_OCTEON_LDS PMC_EV_OCTEON_LMLDS PMC_EV_OCTEON_IOLDS PMC_EV_OCTEON_DMLDS PMC_EV_OCTEON_STS PMC_EV_OCTEON_LMSTS PMC_EV_OCTEON_IOSTS PMC_EV_OCTEON_IOBDMA PMC_EV_OCTEON_DTLB PMC_EV_OCTEON_DTLBAD PMC_EV_OCTEON_ITLB PMC_EV_OCTEON_SYNC PMC_EV_OCTEON_SYNCIOB PMC_EV_OCTEON_SYNCW PMC_EV_MIPS74K__BLOCK_START PMC_EV_MIPS74K_CYCLES PMC_EV_MIPS74K_INSTR_EXECUTED PMC_EV_MIPS74K_PREDICTED_JR_31 PMC_EV_MIPS74K_JR_31_MISPREDICTIONS PMC_EV_MIPS74K_REDIRECT_STALLS PMC_EV_MIPS74K_JR_31_NO_PREDICTIONS PMC_EV_MIPS74K_ITLB_ACCESSES PMC_EV_MIPS74K_ITLB_MISSES PMC_EV_MIPS74K_JTLB_INSN_MISSES PMC_EV_MIPS74K_ICACHE_ACCESSES PMC_EV_MIPS74K_ICACHE_MISSES PMC_EV_MIPS74K_ICACHE_MISS_STALLS PMC_EV_MIPS74K_UNCACHED_IFETCH_STALLS PMC_EV_MIPS74K_PDTRACE_BACK_STALLS PMC_EV_MIPS74K_IFU_REPLAYS PMC_EV_MIPS74K_KILLED_FETCH_SLOTS PMC_EV_MIPS74K_IFU_IDU_MISS_PRED_UPSTREAM_CYCLES PMC_EV_MIPS74K_IFU_IDU_NO_FETCH_CYCLES PMC_EV_MIPS74K_IFU_IDU_CLOGED_DOWNSTREAM_CYCLES PMC_EV_MIPS74K_DDQ0_FULL_DR_STALLS PMC_EV_MIPS74K_DDQ1_FULL_DR_STALLS PMC_EV_MIPS74K_ALCB_FULL_DR_STALLS PMC_EV_MIPS74K_AGCB_FULL_DR_STALLS PMC_EV_MIPS74K_CLDQ_FULL_DR_STALLS PMC_EV_MIPS74K_IODQ_FULL_DR_STALLS PMC_EV_MIPS74K_ALU_EMPTY_CYCLES PMC_EV_MIPS74K_AGEN_EMPTY_CYCLES PMC_EV_MIPS74K_ALU_OPERANDS_NOT_READY_CYCLES PMC_EV_MIPS74K_AGEN_OPERANDS_NOT_READY_CYCLES PMC_EV_MIPS74K_ALU_NO_ISSUES_CYCLES PMC_EV_MIPS74K_AGEN_NO_ISSUES_CYCLES PMC_EV_MIPS74K_ALU_BUBBLE_CYCLES PMC_EV_MIPS74K_AGEN_BUBBLE_CYCLES PMC_EV_MIPS74K_SINGLE_ISSUE_CYCLES PMC_EV_MIPS74K_DUAL_ISSUE_CYCLES PMC_EV_MIPS74K_OOO_ALU_ISSUE_CYCLES PMC_EV_MIPS74K_OOO_AGEN_ISSUE_CYCLES PMC_EV_MIPS74K_JALR_JALR_HB_INSNS PMC_EV_MIPS74K_DCACHE_LINE_REFILL_REQUESTS PMC_EV_MIPS74K_DCACHE_LOAD_ACCESSES PMC_EV_MIPS74K_DCACHE_ACCESSES PMC_EV_MIPS74K_DCACHE_WRITEBACKS PMC_EV_MIPS74K_DCACHE_MISSES PMC_EV_MIPS74K_JTLB_DATA_ACCESSES PMC_EV_MIPS74K_JTLB_DATA_MISSES PMC_EV_MIPS74K_LOAD_STORE_REPLAYS PMC_EV_MIPS74K_VA_TRANSALTION_CORNER_CASES PMC_EV_MIPS74K_LOAD_STORE_BLOCKED_CYCLES PMC_EV_MIPS74K_LOAD_STORE_NO_FILL_REQUESTS PMC_EV_MIPS74K_L2_CACHE_WRITEBACKS PMC_EV_MIPS74K_L2_CACHE_ACCESSES PMC_EV_MIPS74K_L2_CACHE_MISSES PMC_EV_MIPS74K_L2_CACHE_MISS_CYCLES PMC_EV_MIPS74K_FSB_FULL_STALLS PMC_EV_MIPS74K_FSB_OVER_50_FULL PMC_EV_MIPS74K_LDQ_FULL_STALLS PMC_EV_MIPS74K_LDQ_OVER_50_FULL PMC_EV_MIPS74K_WBB_FULL_STALLS PMC_EV_MIPS74K_WBB_OVER_50_FULL PMC_EV_MIPS74K_LOAD_MISS_CONSUMER_REPLAYS PMC_EV_MIPS74K_CP1_CP2_LOAD_INSNS PMC_EV_MIPS74K_JR_NON_31_INSNS PMC_EV_MIPS74K_MISPREDICTED_JR_31_INSNS PMC_EV_MIPS74K_BRANCH_INSNS PMC_EV_MIPS74K_CP1_CP2_COND_BRANCH_INSNS PMC_EV_MIPS74K_BRANCH_LIKELY_INSNS PMC_EV_MIPS74K_MISPREDICTED_BRANCH_LIKELY_INSNS PMC_EV_MIPS74K_COND_BRANCH_INSNS PMC_EV_MIPS74K_MISPREDICTED_BRANCH_INSNS PMC_EV_MIPS74K_INTEGER_INSNS PMC_EV_MIPS74K_FPU_INSNS PMC_EV_MIPS74K_LOAD_INSNS PMC_EV_MIPS74K_STORE_INSNS PMC_EV_MIPS74K_J_JAL_INSNS PMC_EV_MIPS74K_MIPS16_INSNS PMC_EV_MIPS74K_NOP_INSNS PMC_EV_MIPS74K_NT_MUL_DIV_INSNS PMC_EV_MIPS74K_DSP_INSNS PMC_EV_MIPS74K_ALU_DSP_SATURATION_INSNS PMC_EV_MIPS74K_DSP_BRANCH_INSNS PMC_EV_MIPS74K_MDU_DSP_SATURATION_INSNS PMC_EV_MIPS74K_UNCACHED_LOAD_INSNS PMC_EV_MIPS74K_UNCACHED_STORE_INSNS PMC_EV_MIPS74K_EJTAG_INSN_TRIGGERS PMC_EV_MIPS74K_CP1_BRANCH_MISPREDICTIONS PMC_EV_MIPS74K_SC_INSNS PMC_EV_MIPS74K_FAILED_SC_INSNS PMC_EV_MIPS74K_PREFETCH_INSNS PMC_EV_MIPS74K_CACHE_HIT_PREFETCH_INSNS PMC_EV_MIPS74K_NO_INSN_CYCLES PMC_EV_MIPS74K_LOAD_MISS_INSNS PMC_EV_MIPS74K_ONE_INSN_CYCLES PMC_EV_MIPS74K_TWO_INSNS_CYCLES PMC_EV_MIPS74K_GFIFO_BLOCKED_CYCLES PMC_EV_MIPS74K_CP1_CP2_STORE_INSNS PMC_EV_MIPS74K_MISPREDICTION_STALLS PMC_EV_MIPS74K_MISPREDICTED_BRANCH_INSNS_CYCLES PMC_EV_MIPS74K_EXCEPTIONS_TAKEN PMC_EV_MIPS74K_GRADUATION_REPLAYS PMC_EV_MIPS74K_COREEXTEND_EVENTS PMC_EV_MIPS74K_ISPRAM_EVENTS PMC_EV_MIPS74K_DSPRAM_EVENTS PMC_EV_MIPS74K_L2_CACHE_SINGLE_BIT_ERRORS PMC_EV_MIPS74K_SYSTEM_EVENT_0 PMC_EV_MIPS74K_SYSTEM_EVENT_1 PMC_EV_MIPS74K_SYSTEM_EVENT_2 PMC_EV_MIPS74K_SYSTEM_EVENT_3 PMC_EV_MIPS74K_SYSTEM_EVENT_4 PMC_EV_MIPS74K_SYSTEM_EVENT_5 PMC_EV_MIPS74K_SYSTEM_EVENT_6 PMC_EV_MIPS74K_SYSTEM_EVENT_7 PMC_EV_MIPS74K_OCP_ALL_REQUESTS PMC_EV_MIPS74K_OCP_ALL_CACHEABLE_REQUESTS PMC_EV_MIPS74K_OCP_READ_REQUESTS PMC_EV_MIPS74K_OCP_READ_CACHEABLE_REQUESTS PMC_EV_MIPS74K_OCP_WRITE_REQUESTS PMC_EV_MIPS74K_OCP_WRITE_CACHEABLE_REQUESTS PMC_EV_MIPS74K_FSB_LESS_25_FULL PMC_EV_MIPS74K_FSB_25_50_FULL PMC_EV_MIPS74K_LDQ_LESS_25_FULL PMC_EV_MIPS74K_LDQ_25_50_FULL PMC_EV_MIPS74K_WBB_LESS_25_FULL PMC_EV_MIPS74K_WBB_25_50_FULL PMC_EV_BERI__BLOCK_START PMC_EV_BERI_CYCLE PMC_EV_BERI_INST PMC_EV_BERI_INST_USER PMC_EV_BERI_INST_KERNEL PMC_EV_BERI_IMPRECISE_SETBOUNDS PMC_EV_BERI_UNREPRESENTABLE_CAPS PMC_EV_BERI_ITLB_MISS PMC_EV_BERI_DTLB_MISS PMC_EV_BERI_ICACHE_WRITE_HIT PMC_EV_BERI_ICACHE_WRITE_MISS PMC_EV_BERI_ICACHE_READ_HIT PMC_EV_BERI_ICACHE_READ_MISS PMC_EV_BERI_ICACHE_EVICT PMC_EV_BERI_DCACHE_WRITE_HIT PMC_EV_BERI_DCACHE_WRITE_MISS PMC_EV_BERI_DCACHE_READ_HIT PMC_EV_BERI_DCACHE_READ_MISS PMC_EV_BERI_DCACHE_EVICT PMC_EV_BERI_DCACHE_SET_TAG_WRITE PMC_EV_BERI_DCACHE_SET_TAG_READ PMC_EV_BERI_L2CACHE_WRITE_HIT PMC_EV_BERI_L2CACHE_WRITE_MISS PMC_EV_BERI_L2CACHE_READ_HIT PMC_EV_BERI_L2CACHE_READ_MISS PMC_EV_BERI_L2CACHE_EVICT PMC_EV_BERI_L2CACHE_SET_TAG_WRITE PMC_EV_BERI_L2CACHE_SET_TAG_READ PMC_EV_BERI_MEM_BYTE_READ PMC_EV_BERI_MEM_BYTE_WRITE PMC_EV_BERI_MEM_HWORD_READ PMC_EV_BERI_MEM_HWORD_WRITE PMC_EV_BERI_MEM_WORD_READ PMC_EV_BERI_MEM_WORD_WRITE PMC_EV_BERI_MEM_DWORD_READ PMC_EV_BERI_MEM_DWORD_WRITE PMC_EV_BERI_MEM_CAP_READ PMC_EV_BERI_MEM_CAP_WRITE PMC_EV_BERI_MEM_CAP_READ_TAG_SET PMC_EV_BERI_MEM_CAP_WRITE_TAG_SET PMC_EV_BERI_TAGCACHE_WRITE_HIT PMC_EV_BERI_TAGCACHE_WRITE_MISS PMC_EV_BERI_TAGCACHE_READ_HIT PMC_EV_BERI_TAGCACHE_READ_MISS PMC_EV_BERI_TAGCACHE_EVICT PMC_EV_BERI_L2CACHEMASTER_READ_REQ PMC_EV_BERI_L2CACHEMASTER_WRITE_REQ PMC_EV_BERI_L2CACHEMASTER_WRITE_REQ_FLIT PMC_EV_BERI_L2CACHEMASTER_READ_RSP PMC_EV_BERI_L2CACHEMASTER_READ_RSP_FLIT PMC_EV_BERI_L2CACHEMASTER_WRITE_RSP PMC_EV_BERI_TAGCACHEMASTER_READ_REQ PMC_EV_BERI_TAGCACHEMASTER_WRITE_REQ PMC_EV_BERI_TAGCACHEMASTER_WRITE_REQ_FLIT PMC_EV_BERI_TAGCACHEMASTER_READ_RSP PMC_EV_BERI_TAGCACHEMASTER_READ_RSP_FLIT PMC_EV_BERI_TAGCACHEMASTER_WRITE_RSP PMC_EV_UCP__BLOCK_START PMC_EV_UCP_EVENT_0CH_04H_E PMC_EV_UCP_EVENT_0CH_04H_F PMC_EV_UCP_EVENT_0CH_04H_M PMC_EV_UCP_EVENT_0CH_04H_S PMC_EV_UCP_EVENT_0CH_08H_E PMC_EV_UCP_EVENT_0CH_08H_F PMC_EV_UCP_EVENT_0CH_08H_M PMC_EV_UCP_EVENT_0CH_08H_S PMC_EV_PPC7450__BLOCK_START PMC_EV_PPC7450_CYCLE PMC_EV_PPC7450_INSTR_COMPLETED PMC_EV_PPC7450_TLB_BIT_TRANSITIONS PMC_EV_PPC7450_INSTR_DISPATCHED PMC_EV_PPC7450_PMON_EXCEPT PMC_EV_PPC7450_PMON_SIG PMC_EV_PPC7450_VPU_INSTR_COMPLETED PMC_EV_PPC7450_VFPU_INSTR_COMPLETED PMC_EV_PPC7450_VIU1_INSTR_COMPLETED PMC_EV_PPC7450_VIU2_INSTR_COMPLETED PMC_EV_PPC7450_MTVSCR_INSTR_COMPLETED PMC_EV_PPC7450_MTVRSAVE_INSTR_COMPLETED PMC_EV_PPC7450_VPU_INSTR_WAIT_CYCLES PMC_EV_PPC7450_VFPU_INSTR_WAIT_CYCLES PMC_EV_PPC7450_VIU1_INSTR_WAIT_CYCLES PMC_EV_PPC7450_VIU2_INSTR_WAIT_CYCLES PMC_EV_PPC7450_MFVSCR_SYNC_CYCLES PMC_EV_PPC7450_VSCR_SAT_SET PMC_EV_PPC7450_STORE_INSTR_COMPLETED PMC_EV_PPC7450_L1_INSTR_CACHE_MISSES PMC_EV_PPC7450_L1_DATA_SNOOPS PMC_EV_PPC7450_UNRESOLVED_BRANCHES PMC_EV_PPC7450_SPEC_BUFFER_CYCLES PMC_EV_PPC7450_BRANCH_UNIT_STALL_CYCLES PMC_EV_PPC7450_TRUE_BRANCH_TARGET_HITS PMC_EV_PPC7450_BRANCH_LINK_STAC_PREDICTED PMC_EV_PPC7450_GPR_ISSUE_QUEUE_DISPATCHES PMC_EV_PPC7450_CYCLES_THREE_INSTR_DISPATCHED PMC_EV_PPC7450_THRESHOLD_INSTR_QUEUE_ENTRIES_CYCLES PMC_EV_PPC7450_THRESHOLD_VEC_INSTR_QUEUE_ENTRIES_CYCLES PMC_EV_PPC7450_CYCLES_NO_COMPLETED_INSTRS PMC_EV_PPC7450_IU2_INSTR_COMPLETED PMC_EV_PPC7450_BRANCHES_COMPLETED PMC_EV_PPC7450_EIEIO_INSTR_COMPLETED PMC_EV_PPC7450_MTSPR_INSTR_COMPLETED PMC_EV_PPC7450_SC_INSTR_COMPLETED PMC_EV_PPC7450_LS_LM_COMPLETED PMC_EV_PPC7450_ITLB_HW_TABLE_SEARCH_CYCLES PMC_EV_PPC7450_DTLB_HW_SEARCH_CYCLES_OVER_THRESHOLD PMC_EV_PPC7450_L1_INSTR_CACHE_ACCESSES PMC_EV_PPC7450_INSTR_BKPT_MATCHES PMC_EV_PPC7450_L1_DATA_CACHE_LOAD_MISS_CYCLES_OVER_THRESHOLD PMC_EV_PPC7450_L1_DATA_SNOOP_HIT_ON_MODIFIED PMC_EV_PPC7450_LOAD_MISS_ALIAS PMC_EV_PPC7450_LOAD_MISS_ALIAS_ON_TOUCH PMC_EV_PPC7450_TOUCH_ALIAS PMC_EV_PPC7450_L1_DATA_SNOOP_HIT_CASTOUT_QUEUE PMC_EV_PPC7450_L1_DATA_SNOOP_HIT_CASTOUT PMC_EV_PPC7450_L1_DATA_SNOOP_HITS PMC_EV_PPC7450_WRITE_THROUGH_STORES PMC_EV_PPC7450_CACHE_INHIBITED_STORES PMC_EV_PPC7450_L1_DATA_LOAD_HIT PMC_EV_PPC7450_L1_DATA_TOUCH_HIT PMC_EV_PPC7450_L1_DATA_STORE_HIT PMC_EV_PPC7450_L1_DATA_TOTAL_HITS PMC_EV_PPC7450_DST_INSTR_DISPATCHED PMC_EV_PPC7450_REFRESHED_DSTS PMC_EV_PPC7450_SUCCESSFUL_DST_TABLE_SEARCHES PMC_EV_PPC7450_DSS_INSTR_COMPLETED PMC_EV_PPC7450_DST_STREAM_0_CACHE_LINE_FETCHES PMC_EV_PPC7450_VTQ_SUSPENDS_DUE_TO_CTX_CHANGE PMC_EV_PPC7450_VTQ_LINE_FETCH_HIT PMC_EV_PPC7450_VEC_LOAD_INSTR_COMPLETED PMC_EV_PPC7450_FP_STORE_INSTR_COMPLETED_IN_LSU PMC_EV_PPC7450_FPU_RENORMALIZATION PMC_EV_PPC7450_FPU_DENORMALIZATION PMC_EV_PPC7450_FP_STORE_CAUSES_STALL_IN_LSU PMC_EV_PPC7450_LD_ST_TRUE_ALIAS_STALL PMC_EV_PPC7450_LSU_INDEXED_ALIAS_STALL PMC_EV_PPC7450_LSU_ALIAS_VS_FSQ_WB0_WB1 PMC_EV_PPC7450_LSU_ALIAS_VS_CSQ PMC_EV_PPC7450_LSU_LOAD_HIT_LINE_ALIAS_VS_CSQ0 PMC_EV_PPC7450_LSU_LOAD_MISS_LINE_ALIAS_VS_CSQ0 PMC_EV_PPC7450_LSU_TOUCH_LINE_ALIAS_VS_FSQ_WB0_WB1 PMC_EV_PPC7450_LSU_TOUCH_ALIAS_VS_CSQ PMC_EV_PPC7450_LSU_LMQ_FULL_STALL PMC_EV_PPC7450_FP_LOAD_INSTR_COMPLETED_IN_LSU PMC_EV_PPC7450_FP_LOAD_SINGLE_INSTR_COMPLETED_IN_LSU PMC_EV_PPC7450_FP_LOAD_DOUBLE_COMPLETED_IN_LSU PMC_EV_PPC7450_LSU_RA_LATCH_STALL PMC_EV_PPC7450_LSU_LOAD_VS_STORE_QUEUE_ALIAS_STALL PMC_EV_PPC7450_LSU_LMQ_INDEX_ALIAS PMC_EV_PPC7450_LSU_STORE_QUEUE_INDEX_ALIAS PMC_EV_PPC7450_LSU_CSQ_FORWARDING PMC_EV_PPC7450_LSU_MISALIGNED_LOAD_FINISH PMC_EV_PPC7450_LSU_MISALIGN_STORE_COMPLETED PMC_EV_PPC7450_LSU_MISALIGN_STALL PMC_EV_PPC7450_FP_ONE_QUARTER_FPSCR_RENAMES_BUSY PMC_EV_PPC7450_FP_ONE_HALF_FPSCR_RENAMES_BUSY PMC_EV_PPC7450_FP_THREE_QUARTERS_FPSCR_RENAMES_BUSY PMC_EV_PPC7450_FP_ALL_FPSCR_RENAMES_BUSY PMC_EV_PPC7450_FP_DENORMALIZED_RESULT PMC_EV_PPC7450_L1_DATA_TOTAL_MISSES PMC_EV_PPC7450_DISPATCHES_TO_FPR_ISSUE_QUEUE PMC_EV_PPC7450_LSU_INSTR_COMPLETED PMC_EV_PPC7450_LOAD_INSTR_COMPLETED PMC_EV_PPC7450_SS_SM_INSTR_COMPLETED PMC_EV_PPC7450_TLBIE_INSTR_COMPLETED PMC_EV_PPC7450_LWARX_INSTR_COMPLETED PMC_EV_PPC7450_MFSPR_INSTR_COMPLETED PMC_EV_PPC7450_REFETCH_SERIALIZATION PMC_EV_PPC7450_COMPLETION_QUEUE_ENTRIES_OVER_THRESHOLD PMC_EV_PPC7450_CYCLES_ONE_INSTR_DISPATCHED PMC_EV_PPC7450_CYCLES_TWO_INSTR_COMPLETED PMC_EV_PPC7450_ITLB_NON_SPECULATIVE_MISSES PMC_EV_PPC7450_CYCLES_WAITING_FROM_L1_INSTR_CACHE_MISS PMC_EV_PPC7450_L1_DATA_LOAD_ACCESS_MISS PMC_EV_PPC7450_L1_DATA_TOUCH_MISS PMC_EV_PPC7450_L1_DATA_STORE_MISS PMC_EV_PPC7450_L1_DATA_TOUCH_MISS_CYCLES PMC_EV_PPC7450_L1_DATA_CYCLES_USED PMC_EV_PPC7450_DST_STREAM_1_CACHE_LINE_FETCHES PMC_EV_PPC7450_VTQ_STREAM_CANCELED_PREMATURELY PMC_EV_PPC7450_VTQ_RESUMES_DUE_TO_CTX_CHANGE PMC_EV_PPC7450_VTQ_LINE_FETCH_MISS PMC_EV_PPC7450_VTQ_LINE_FETCH PMC_EV_PPC7450_TLBIE_SNOOPS PMC_EV_PPC7450_L1_INSTR_CACHE_RELOADS PMC_EV_PPC7450_L1_DATA_CACHE_RELOADS PMC_EV_PPC7450_L1_DATA_CACHE_CASTOUTS_TO_L2 PMC_EV_PPC7450_STORE_MERGE_GATHER PMC_EV_PPC7450_CACHEABLE_STORE_MERGE_TO_32_BYTES PMC_EV_PPC7450_DATA_BKPT_MATCHES PMC_EV_PPC7450_FALL_THROUGH_BRANCHES_PROCESSED PMC_EV_PPC7450_FIRST_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLY PMC_EV_PPC7450_SECOND_SPECULATION_BUFFER_ACTIVE PMC_EV_PPC7450_BPU_STALL_ON_LR_DEPENDENCY PMC_EV_PPC7450_BTIC_MISS PMC_EV_PPC7450_BRANCH_LINK_STACK_CORRECTLY_RESOLVED PMC_EV_PPC7450_FPR_ISSUE_STALLED PMC_EV_PPC7450_SWITCHES_BETWEEN_PRIV_USER PMC_EV_PPC7450_LSU_COMPLETES_FP_STORE_SINGLE PMC_EV_PPC7450_VR_ISSUE_QUEUE_DISPATCHES PMC_EV_PPC7450_VR_STALLS PMC_EV_PPC7450_GPR_RENAME_BUFFER_ENTRIES_OVER_THRESHOLD PMC_EV_PPC7450_FPR_ISSUE_QUEUE_ENTRIES PMC_EV_PPC7450_FPU_INSTR_COMPLETED PMC_EV_PPC7450_STWCX_INSTR_COMPLETED PMC_EV_PPC7450_LS_LM_INSTR_PIECES PMC_EV_PPC7450_ITLB_HW_SEARCH_CYCLES_OVER_THRESHOLD PMC_EV_PPC7450_DTLB_MISSES PMC_EV_PPC7450_CANCELLED_L1_INSTR_CACHE_MISSES PMC_EV_PPC7450_L1_DATA_CACHE_OP_HIT PMC_EV_PPC7450_L1_DATA_LOAD_MISS_CYCLES PMC_EV_PPC7450_L1_DATA_PUSHES PMC_EV_PPC7450_L1_DATA_TOTAL_MISS PMC_EV_PPC7450_VT2_FETCHES PMC_EV_PPC7450_TAKEN_BRANCHES_PROCESSED PMC_EV_PPC7450_BRANCH_FLUSHES PMC_EV_PPC7450_SECOND_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLY PMC_EV_PPC7450_THIRD_SPECULATION_BUFFER_ACTIVE PMC_EV_PPC7450_BRANCH_UNIT_STALL_ON_CTR_DEPENDENCY PMC_EV_PPC7450_FAST_BTIC_HIT PMC_EV_PPC7450_BRANCH_LINK_STACK_MISPREDICTED PMC_EV_PPC7450_CYCLES_THREE_INSTR_COMPLETED PMC_EV_PPC7450_CYCLES_NO_INSTR_DISPATCHED PMC_EV_PPC7450_GPR_ISSUE_QUEUE_ENTRIES_OVER_THRESHOLD PMC_EV_PPC7450_GPR_ISSUE_QUEUE_STALLED PMC_EV_PPC7450_IU1_INSTR_COMPLETED PMC_EV_PPC7450_DSSALL_INSTR_COMPLETED PMC_EV_PPC7450_TLBSYNC_INSTR_COMPLETED PMC_EV_PPC7450_SYNC_INSTR_COMPLETED PMC_EV_PPC7450_SS_SM_INSTR_PIECES PMC_EV_PPC7450_DTLB_HW_SEARCH_CYCLES PMC_EV_PPC7450_SNOOP_RETRIES PMC_EV_PPC7450_SUCCESSFUL_STWCX PMC_EV_PPC7450_DST_STREAM_3_CACHE_LINE_FETCHES PMC_EV_PPC7450_THIRD_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLY PMC_EV_PPC7450_MISPREDICTED_BRANCHES PMC_EV_PPC7450_FOLDED_BRANCHES PMC_EV_PPC7450_FP_STORE_DOUBLE_COMPLETES_IN_LSU PMC_EV_PPC7450_L2_CACHE_HITS PMC_EV_PPC7450_L3_CACHE_HITS PMC_EV_PPC7450_L2_INSTR_CACHE_MISSES PMC_EV_PPC7450_L3_INSTR_CACHE_MISSES PMC_EV_PPC7450_L2_DATA_CACHE_MISSES PMC_EV_PPC7450_L3_DATA_CACHE_MISSES PMC_EV_PPC7450_L2_LOAD_HITS PMC_EV_PPC7450_L2_STORE_HITS PMC_EV_PPC7450_L3_LOAD_HITS PMC_EV_PPC7450_L3_STORE_HITS PMC_EV_PPC7450_L2_TOUCH_HITS PMC_EV_PPC7450_L3_TOUCH_HITS PMC_EV_PPC7450_SNOOP_MODIFIED PMC_EV_PPC7450_SNOOP_VALID PMC_EV_PPC7450_INTERVENTION PMC_EV_PPC7450_L2_CACHE_MISSES PMC_EV_PPC7450_L3_CACHE_MISSES PMC_EV_PPC7450_L2_CACHE_CASTOUTS PMC_EV_PPC7450_L3_CACHE_CASTOUTS PMC_EV_PPC7450_L2SQ_FULL_CYCLES PMC_EV_PPC7450_L3SQ_FULL_CYCLES PMC_EV_PPC7450_RAQ_FULL_CYCLES PMC_EV_PPC7450_WAQ_FULL_CYCLES PMC_EV_PPC7450_L1_EXTERNAL_INTERVENTIONS PMC_EV_PPC7450_L2_EXTERNAL_INTERVENTIONS PMC_EV_PPC7450_L3_EXTERNAL_INTERVENTIONS PMC_EV_PPC7450_EXTERNAL_INTERVENTIONS PMC_EV_PPC7450_EXTERNAL_PUSHES PMC_EV_PPC7450_EXTERNAL_SNOOP_RETRY PMC_EV_PPC7450_DTQ_FULL_CYCLES PMC_EV_PPC7450_BUS_RETRY PMC_EV_PPC7450_L2_VALID_REQUEST PMC_EV_PPC7450_BORDQ_FULL PMC_EV_PPC7450_BUS_TAS_FOR_READS PMC_EV_PPC7450_BUS_TAS_FOR_WRITES PMC_EV_PPC7450_BUS_READS_NOT_RETRIED PMC_EV_PPC7450_BUS_WRITES_NOT_RETRIED PMC_EV_PPC7450_BUS_READS_WRITES_NOT_RETRIED PMC_EV_PPC7450_BUS_RETRY_DUE_TO_L1_RETRY PMC_EV_PPC7450_BUS_RETRY_DUE_TO_PREVIOUS_ADJACENT PMC_EV_PPC7450_BUS_RETRY_DUE_TO_COLLISION PMC_EV_PPC7450_BUS_RETRY_DUE_TO_INTERVENTION_ORDERING PMC_EV_PPC7450_SNOOP_REQUESTS PMC_EV_PPC7450_PREFETCH_ENGINE_REQUEST PMC_EV_PPC7450_PREFETCH_ENGINE_COLLISION_VS_LOAD PMC_EV_PPC7450_PREFETCH_ENGINE_COLLISION_VS_STORE PMC_EV_PPC7450_PREFETCH_ENGINE_COLLISION_VS_INSTR_FETCH PMC_EV_PPC7450_PREFETCH_ENGINE_COLLISION_VS_LOAD_STORE_INSTR_FETCH PMC_EV_PPC7450_PREFETCH_ENGINE_FULL PMC_EV_PPC970__BLOCK_START PMC_EV_PPC970_INSTR_COMPLETED PMC_EV_PPC970_MARKED_GROUP_DISPATCH PMC_EV_PPC970_MARKED_STORE_COMPLETED PMC_EV_PPC970_GCT_EMPTY PMC_EV_PPC970_RUN_CYCLES PMC_EV_PPC970_OVERFLOW PMC_EV_PPC970_CYCLES PMC_EV_PPC970_THRESHOLD_TIMEOUT PMC_EV_PPC970_GROUP_DISPATCH PMC_EV_PPC970_BR_MARKED_INSTR_FINISH PMC_EV_PPC970_GCT_EMPTY_BY_SRQ_FULL PMC_EV_PPC970_STOP_COMPLETION PMC_EV_PPC970_LSU_EMPTY PMC_EV_PPC970_MARKED_STORE_WITH_INTR PMC_EV_PPC970_CYCLES_IN_SUPER PMC_EV_PPC970_VPU_MARKED_INSTR_COMPLETED PMC_EV_PPC970_FXU0_IDLE_FXU1_BUSY PMC_EV_PPC970_SRQ_EMPTY PMC_EV_PPC970_MARKED_GROUP_COMPLETED PMC_EV_PPC970_CR_MARKED_INSTR_FINISH PMC_EV_PPC970_DISPATCH_SUCCESS PMC_EV_PPC970_FXU0_IDLE_FXU1_IDLE PMC_EV_PPC970_ONE_PLUS_INSTR_COMPLETED PMC_EV_PPC970_GROUP_MARKED_IDU PMC_EV_PPC970_MARKED_GROUP_COMPLETE_TIMEOUT PMC_EV_PPC970_FXU0_BUSY_FXU1_BUSY PMC_EV_PPC970_MARKED_STORE_SENT_TO_STS PMC_EV_PPC970_FXU_MARKED_INSTR_FINISHED PMC_EV_PPC970_MARKED_GROUP_ISSUED PMC_EV_PPC970_FXU0_BUSY_FXU1_IDLE PMC_EV_PPC970_GROUP_COMPLETED PMC_EV_PPC970_FPU_MARKED_INSTR_COMPLETED PMC_EV_PPC970_MARKED_INSTR_FINISH_ANY_UNIT PMC_EV_PPC970_EXTERNAL_INTERRUPT PMC_EV_PPC970_GROUP_DISPATCH_REJECT PMC_EV_PPC970_LSU_MARKED_INSTR_FINISH PMC_EV_PPC970_TIMEBASE_EVENT PMC_EV_PPC970_LSU_COMPLETION_STALL PMC_EV_PPC970_FXU_COMPLETION_STALL PMC_EV_PPC970_DCACHE_MISS_COMPLETION_STALL PMC_EV_PPC970_FPU_COMPLETION_STALL PMC_EV_PPC970_FXU_LONG_INSTR_COMPLETION_STALL PMC_EV_PPC970_REJECT_COMPLETION_STALL PMC_EV_PPC970_FPU_LONG_INSTR_COMPLETION_STALL PMC_EV_PPC970_GCT_EMPTY_BY_ICACHE_MISS PMC_EV_PPC970_REJECT_COMPLETION_STALL_ERAT_MISS PMC_EV_PPC970_GCT_EMPTY_BY_BRANCH_MISS_PREDICT PMC_EV_PPC970_BUS_HIGH PMC_EV_PPC970_BUS_LOW PMC_EV_PPC970_ADDER PMC_EV_POWER8__BLOCK_START PMC_EV_POWER8_CYCLES PMC_EV_POWER8_CYCLES_WITH_INSTRS_COMPLETED PMC_EV_POWER8_FPU_INSTR_COMPLETED PMC_EV_POWER8_ERAT_INSTR_MISS PMC_EV_POWER8_CYCLES_IDLE PMC_EV_POWER8_CYCLES_WITH_ANY_THREAD_RUNNING PMC_EV_POWER8_STORE_COMPLETED PMC_EV_POWER8_INSTR_DISPATCHED PMC_EV_POWER8_CYCLES_RUNNING PMC_EV_POWER8_ERAT_DATA_MISS PMC_EV_POWER8_EXTERNAL_INTERRUPT PMC_EV_POWER8_BRANCH_TAKEN PMC_EV_POWER8_L1_INSTR_MISS PMC_EV_POWER8_L2_LOAD_MISS PMC_EV_POWER8_STORE_NO_REAL_ADDR PMC_EV_POWER8_INSTR_COMPLETED_WITH_ALL_THREADS_RUNNING PMC_EV_POWER8_L1_LOAD_MISS PMC_EV_POWER8_TIMEBASE_EVENT PMC_EV_POWER8_L3_INSTR_MISS PMC_EV_POWER8_TLB_DATA_MISS PMC_EV_POWER8_L3_LOAD_MISS PMC_EV_POWER8_LOAD_NO_REAL_ADDR PMC_EV_POWER8_CYCLES_WITH_INSTRS_DISPATCHED PMC_EV_POWER8_CYCLES_RUNNING_PURR_INC PMC_EV_POWER8_BRANCH_MISPREDICTED PMC_EV_POWER8_PREFETCHED_INSTRS_DISCARDED PMC_EV_POWER8_INSTR_COMPLETED_RUNNING PMC_EV_POWER8_TLB_INSTR_MISS PMC_EV_POWER8_CACHE_LOAD_MISS PMC_EV_POWER8_INSTR_COMPLETED PMC_EV_E500__BLOCK_START PMC_EV_E500_CYCLES PMC_EV_E500_INSTR_COMPLETED PMC_EV_E500_UOPS_COMPLETED PMC_EV_E500_INSTR_FETCHED PMC_EV_E500_UOPS_DECODED PMC_EV_E500_PM_EVENT_TRANSITIONS PMC_EV_E500_PM_EVENT_CYCLES PMC_EV_E500_BRANCH_INSTRS_COMPLETED PMC_EV_E500_LOAD_UOPS_COMPLETED PMC_EV_E500_STORE_UOPS_COMPLETED PMC_EV_E500_CQ_REDIRECTS PMC_EV_E500_BRANCHES_FINISHED PMC_EV_E500_TAKEN_BRANCHES_FINISHED PMC_EV_E500_FINISHED_UNCOND_BRANCHES_MISS_BTB PMC_EV_E500_BRANCH_MISPRED PMC_EV_E500_BTB_BRANCH_MISPRED_FROM_DIRECTION PMC_EV_E500_BTB_HITS_PSEUDO_HITS PMC_EV_E500_CYCLES_DECODE_STALLED PMC_EV_E500_CYCLES_ISSUE_STALLED PMC_EV_E500_CYCLES_BRANCH_ISSUE_STALLED PMC_EV_E500_CYCLES_SU1_SCHED_STALLED PMC_EV_E500_CYCLES_SU2_SCHED_STALLED PMC_EV_E500_CYCLES_MU_SCHED_STALLED PMC_EV_E500_CYCLES_LRU_SCHED_STALLED PMC_EV_E500_CYCLES_BU_SCHED_STALLED PMC_EV_E500_TOTAL_TRANSLATED PMC_EV_E500_LOADS_TRANSLATED PMC_EV_E500_STORES_TRANSLATED PMC_EV_E500_TOUCHES_TRANSLATED PMC_EV_E500_CACHEOPS_TRANSLATED PMC_EV_E500_CACHE_INHIBITED_ACCESS_TRANSLATED PMC_EV_E500_GUARDED_LOADS_TRANSLATED PMC_EV_E500_WRITE_THROUGH_STORES_TRANSLATED PMC_EV_E500_MISALIGNED_LOAD_STORE_ACCESS_TRANSLATED PMC_EV_E500_TOTAL_ALLOCATED_TO_DLFB PMC_EV_E500_LOADS_TRANSLATED_ALLOCATED_TO_DLFB PMC_EV_E500_STORES_COMPLETED_ALLOCATED_TO_DLFB PMC_EV_E500_TOUCHES_TRANSLATED_ALLOCATED_TO_DLFB PMC_EV_E500_STORES_COMPLETED PMC_EV_E500_DATA_L1_CACHE_LOCKS PMC_EV_E500_DATA_L1_CACHE_RELOADS PMC_EV_E500_DATA_L1_CACHE_CASTOUTS PMC_EV_E500_LOAD_MISS_DLFB_FULL PMC_EV_E500_LOAD_MISS_LDQ_FULL PMC_EV_E500_LOAD_GUARDED_MISS PMC_EV_E500_STORE_TRANSLATE_WHEN_QUEUE_FULL PMC_EV_E500_ADDRESS_COLLISION PMC_EV_E500_DATA_MMU_MISS PMC_EV_E500_DATA_MMU_BUSY PMC_EV_E500_PART2_MISALIGNED_CACHE_ACCESS PMC_EV_E500_LOAD_MISS_DLFB_FULL_CYCLES PMC_EV_E500_LOAD_MISS_LDQ_FULL_CYCLES PMC_EV_E500_LOAD_GUARDED_MISS_CYCLES PMC_EV_E500_STORE_TRANSLATE_WHEN_QUEUE_FULL_CYCLES PMC_EV_E500_ADDRESS_COLLISION_CYCLES PMC_EV_E500_DATA_MMU_MISS_CYCLES PMC_EV_E500_DATA_MMU_BUSY_CYCLES PMC_EV_E500_PART2_MISALIGNED_CACHE_ACCESS_CYCLES PMC_EV_E500_INSTR_L1_CACHE_LOCKS PMC_EV_E500_INSTR_L1_CACHE_RELOADS PMC_EV_E500_INSTR_L1_CACHE_FETCHES PMC_EV_E500_INSTR_MMU_TLB4K_RELOADS PMC_EV_E500_INSTR_MMU_VSP_RELOADS PMC_EV_E500_DATA_MMU_TLB4K_RELOADS PMC_EV_E500_DATA_MMU_VSP_RELOADS PMC_EV_E500_L2MMU_MISSES PMC_EV_E500_BIU_MASTER_REQUESTS PMC_EV_E500_BIU_MASTER_INSTR_SIDE_REQUESTS PMC_EV_E500_BIU_MASTER_DATA_SIDE_REQUESTS PMC_EV_E500_BIU_MASTER_DATA_SIDE_CASTOUT_REQUESTS PMC_EV_E500_BIU_MASTER_RETRIES PMC_EV_E500_SNOOP_REQUESTS PMC_EV_E500_SNOOP_HITS PMC_EV_E500_SNOOP_PUSHES PMC_EV_E500_SNOOP_RETRIES PMC_EV_E500_DLFB_LOAD_MISS_CYCLES PMC_EV_E500_ILFB_FETCH_MISS_CYCLES PMC_EV_E500_EXT_INPU_INTR_LATENCY_CYCLES PMC_EV_E500_CRIT_INPUT_INTR_LATENCY_CYCLES PMC_EV_E500_EXT_INPUT_INTR_PENDING_LATENCY_CYCLES PMC_EV_E500_CRIT_INPUT_INTR_PENDING_LATENCY_CYCLES PMC_EV_E500_PMC0_OVERFLOW PMC_EV_E500_PMC1_OVERFLOW PMC_EV_E500_PMC2_OVERFLOW PMC_EV_E500_PMC3_OVERFLOW PMC_EV_E500_INTERRUPTS_TAKEN PMC_EV_E500_EXT_INPUT_INTR_TAKEN PMC_EV_E500_CRIT_INPUT_INTR_TAKEN PMC_EV_E500_SYSCALL_TRAP_INTR PMC_EV_E500_TLB_BIT_TRANSITIONS PMC_EV_E500_L2_LINEFILL_BUFFER PMC_EV_E500_LV2_VS PMC_EV_E500_CASTOUTS_RELEASED PMC_EV_E500_INTV_ALLOCATIONS PMC_EV_E500_DLFB_RETRIES_TO_MBAR PMC_EV_E500_STORE_RETRIES PMC_EV_E500_STASH_L1_HITS PMC_EV_E500_STASH_L2_HITS PMC_EV_E500_STASH_BUSY_1 PMC_EV_E500_STASH_BUSY_2 PMC_EV_E500_STASH_BUSY_3 PMC_EV_E500_STASH_HITS PMC_EV_E500_STASH_HIT_DLFB PMC_EV_E500_STASH_REQUESTS PMC_EV_E500_STASH_REQUESTS_L1 PMC_EV_E500_STASH_REQUESTS_L2 PMC_EV_E500_STALLS_NO_CAQ_OR_COB PMC_EV_E500_L2_CACHE_ACCESSES PMC_EV_E500_L2_HIT_CACHE_ACCESSES PMC_EV_E500_L2_CACHE_DATA_ACCESSES PMC_EV_E500_L2_CACHE_DATA_HITS PMC_EV_E500_L2_CACHE_INSTR_ACCESSES PMC_EV_E500_L2_CACHE_INSTR_HITS PMC_EV_E500_L2_CACHE_ALLOCATIONS PMC_EV_E500_L2_CACHE_DATA_ALLOCATIONS PMC_EV_E500_L2_CACHE_DIRTY_DATA_ALLOCATIONS PMC_EV_E500_L2_CACHE_INSTR_ALLOCATIONS PMC_EV_E500_L2_CACHE_UPDATES PMC_EV_E500_L2_CACHE_CLEAN_UPDATES PMC_EV_E500_L2_CACHE_DIRTY_UPDATES PMC_EV_E500_L2_CACHE_CLEAN_REDUNDANT_UPDATES PMC_EV_E500_L2_CACHE_DIRTY_REDUNDANT_UPDATES PMC_EV_E500_L2_CACHE_LOCKS PMC_EV_E500_L2_CACHE_CASTOUTS PMC_EV_E500_L2_CACHE_DATA_DIRTY_HITS PMC_EV_E500_INSTR_LFB_WENT_HIGH_PRIORITY PMC_EV_E500_SNOOP_THROTTLING_TURNED_ON PMC_EV_E500_L2_CLEAN_LINE_INVALIDATIONS PMC_EV_E500_L2_INCOHERENT_LINE_INVALIDATIONS PMC_EV_E500_L2_COHERENT_LINE_INVALIDATIONS PMC_EV_E500_COHERENT_LOOKUP_MISS_DUE_TO_VALID_BUT_INCOHERENT_MATCHES PMC_EV_E500_IAC1S_DETECTED PMC_EV_E500_IAC2S_DETECTED PMC_EV_E500_DAC1S_DTECTED PMC_EV_E500_DAC2S_DTECTED PMC_EV_E500_DVT0_DETECTED PMC_EV_E500_DVT1_DETECTED PMC_EV_E500_DVT2_DETECTED PMC_EV_E500_DVT3_DETECTED PMC_EV_E500_DVT4_DETECTED PMC_EV_E500_DVT5_DETECTED PMC_EV_E500_DVT6_DETECTED PMC_EV_E500_DVT7_DETECTED PMC_EV_E500_CYCLES_COMPLETION_STALLED_NEXUS_FIFO_FULL PMC_EV_E500_FPU_DOUBLE_PUMP PMC_EV_E500_FPU_FINISH PMC_EV_E500_FPU_DIVIDE_CYCLES PMC_EV_E500_FPU_DENORM_INPUT_CYCLES PMC_EV_E500_FPU_RESULT_STALL_CYCLES PMC_EV_E500_FPU_FPSCR_FULL_STALL PMC_EV_E500_FPU_PIPE_SYNC_STALLS PMC_EV_E500_FPU_INPUT_DATA_STALLS PMC_EV_E500_DECORATED_LOADS PMC_EV_E500_DECORATED_STORES PMC_EV_E500_LOAD_RETRIES PMC_EV_E500_STWCX_SUCCESSES PMC_EV_E500_STWCX_FAILURES PMC_EV_ARMV7__BLOCK_START PMC_EV_ARMV7_EVENT_00H PMC_EV_ARMV7_EVENT_01H PMC_EV_ARMV7_EVENT_02H PMC_EV_ARMV7_EVENT_03H PMC_EV_ARMV7_EVENT_04H PMC_EV_ARMV7_EVENT_05H PMC_EV_ARMV7_EVENT_06H PMC_EV_ARMV7_EVENT_07H PMC_EV_ARMV7_EVENT_08H PMC_EV_ARMV7_EVENT_09H PMC_EV_ARMV7_EVENT_0AH PMC_EV_ARMV7_EVENT_0BH PMC_EV_ARMV7_EVENT_0CH PMC_EV_ARMV7_EVENT_0DH PMC_EV_ARMV7_EVENT_0EH PMC_EV_ARMV7_EVENT_0FH PMC_EV_ARMV7_EVENT_10H PMC_EV_ARMV7_EVENT_11H PMC_EV_ARMV7_EVENT_12H PMC_EV_ARMV7_EVENT_13H PMC_EV_ARMV7_EVENT_14H PMC_EV_ARMV7_EVENT_15H PMC_EV_ARMV7_EVENT_16H PMC_EV_ARMV7_EVENT_17H PMC_EV_ARMV7_EVENT_18H PMC_EV_ARMV7_EVENT_19H PMC_EV_ARMV7_EVENT_1AH PMC_EV_ARMV7_EVENT_1BH PMC_EV_ARMV7_EVENT_1CH PMC_EV_ARMV7_EVENT_1DH PMC_EV_ARMV7_EVENT_1EH PMC_EV_ARMV7_EVENT_1FH PMC_EV_ARMV7_EVENT_20H PMC_EV_ARMV7_EVENT_21H PMC_EV_ARMV7_EVENT_22H PMC_EV_ARMV7_EVENT_23H PMC_EV_ARMV7_EVENT_24H PMC_EV_ARMV7_EVENT_25H PMC_EV_ARMV7_EVENT_26H PMC_EV_ARMV7_EVENT_27H PMC_EV_ARMV7_EVENT_28H PMC_EV_ARMV7_EVENT_29H PMC_EV_ARMV7_EVENT_2AH PMC_EV_ARMV7_EVENT_2BH PMC_EV_ARMV7_EVENT_2CH PMC_EV_ARMV7_EVENT_2DH PMC_EV_ARMV7_EVENT_2EH PMC_EV_ARMV7_EVENT_2FH PMC_EV_ARMV7_EVENT_30H PMC_EV_ARMV7_EVENT_31H PMC_EV_ARMV7_EVENT_32H PMC_EV_ARMV7_EVENT_33H PMC_EV_ARMV7_EVENT_34H PMC_EV_ARMV7_EVENT_35H PMC_EV_ARMV7_EVENT_36H PMC_EV_ARMV7_EVENT_37H PMC_EV_ARMV7_EVENT_38H PMC_EV_ARMV7_EVENT_39H PMC_EV_ARMV7_EVENT_3AH PMC_EV_ARMV7_EVENT_3BH PMC_EV_ARMV7_EVENT_3CH PMC_EV_ARMV7_EVENT_3DH PMC_EV_ARMV7_EVENT_3EH PMC_EV_ARMV7_EVENT_3FH PMC_EV_ARMV7_EVENT_40H PMC_EV_ARMV7_EVENT_41H PMC_EV_ARMV7_EVENT_42H PMC_EV_ARMV7_EVENT_43H PMC_EV_ARMV7_EVENT_44H PMC_EV_ARMV7_EVENT_45H PMC_EV_ARMV7_EVENT_46H PMC_EV_ARMV7_EVENT_47H PMC_EV_ARMV7_EVENT_48H PMC_EV_ARMV7_EVENT_49H PMC_EV_ARMV7_EVENT_4AH PMC_EV_ARMV7_EVENT_4BH PMC_EV_ARMV7_EVENT_4CH PMC_EV_ARMV7_EVENT_4DH PMC_EV_ARMV7_EVENT_4EH PMC_EV_ARMV7_EVENT_4FH PMC_EV_ARMV7_EVENT_50H PMC_EV_ARMV7_EVENT_51H PMC_EV_ARMV7_EVENT_52H PMC_EV_ARMV7_EVENT_53H PMC_EV_ARMV7_EVENT_54H PMC_EV_ARMV7_EVENT_55H PMC_EV_ARMV7_EVENT_56H PMC_EV_ARMV7_EVENT_57H PMC_EV_ARMV7_EVENT_58H PMC_EV_ARMV7_EVENT_59H PMC_EV_ARMV7_EVENT_5AH PMC_EV_ARMV7_EVENT_5BH PMC_EV_ARMV7_EVENT_5CH PMC_EV_ARMV7_EVENT_5DH PMC_EV_ARMV7_EVENT_5EH PMC_EV_ARMV7_EVENT_5FH PMC_EV_ARMV7_EVENT_60H PMC_EV_ARMV7_EVENT_61H PMC_EV_ARMV7_EVENT_62H PMC_EV_ARMV7_EVENT_63H PMC_EV_ARMV7_EVENT_64H PMC_EV_ARMV7_EVENT_65H PMC_EV_ARMV7_EVENT_66H PMC_EV_ARMV7_EVENT_67H PMC_EV_ARMV7_EVENT_68H PMC_EV_ARMV7_EVENT_69H PMC_EV_ARMV7_EVENT_6AH PMC_EV_ARMV7_EVENT_6BH PMC_EV_ARMV7_EVENT_6CH PMC_EV_ARMV7_EVENT_6DH PMC_EV_ARMV7_EVENT_6EH PMC_EV_ARMV7_EVENT_6FH PMC_EV_ARMV7_EVENT_70H PMC_EV_ARMV7_EVENT_71H PMC_EV_ARMV7_EVENT_72H PMC_EV_ARMV7_EVENT_73H PMC_EV_ARMV7_EVENT_74H PMC_EV_ARMV7_EVENT_75H PMC_EV_ARMV7_EVENT_76H PMC_EV_ARMV7_EVENT_77H PMC_EV_ARMV7_EVENT_78H PMC_EV_ARMV7_EVENT_79H PMC_EV_ARMV7_EVENT_7AH PMC_EV_ARMV7_EVENT_7BH PMC_EV_ARMV7_EVENT_7CH PMC_EV_ARMV7_EVENT_7DH PMC_EV_ARMV7_EVENT_7EH PMC_EV_ARMV7_EVENT_7FH PMC_EV_ARMV7_EVENT_80H PMC_EV_ARMV7_EVENT_81H PMC_EV_ARMV7_EVENT_82H PMC_EV_ARMV7_EVENT_83H PMC_EV_ARMV7_EVENT_84H PMC_EV_ARMV7_EVENT_85H PMC_EV_ARMV7_EVENT_86H PMC_EV_ARMV7_EVENT_87H PMC_EV_ARMV7_EVENT_88H PMC_EV_ARMV7_EVENT_89H PMC_EV_ARMV7_EVENT_8AH PMC_EV_ARMV7_EVENT_8BH PMC_EV_ARMV7_EVENT_8CH PMC_EV_ARMV7_EVENT_8DH PMC_EV_ARMV7_EVENT_8EH PMC_EV_ARMV7_EVENT_8FH PMC_EV_ARMV7_EVENT_90H PMC_EV_ARMV7_EVENT_91H PMC_EV_ARMV7_EVENT_92H PMC_EV_ARMV7_EVENT_93H PMC_EV_ARMV7_EVENT_94H PMC_EV_ARMV7_EVENT_95H PMC_EV_ARMV7_EVENT_96H PMC_EV_ARMV7_EVENT_97H PMC_EV_ARMV7_EVENT_98H PMC_EV_ARMV7_EVENT_99H PMC_EV_ARMV7_EVENT_9AH PMC_EV_ARMV7_EVENT_9BH PMC_EV_ARMV7_EVENT_9CH PMC_EV_ARMV7_EVENT_9DH PMC_EV_ARMV7_EVENT_9EH PMC_EV_ARMV7_EVENT_9FH PMC_EV_ARMV7_EVENT_A0H PMC_EV_ARMV7_EVENT_A1H PMC_EV_ARMV7_EVENT_A2H PMC_EV_ARMV7_EVENT_A3H PMC_EV_ARMV7_EVENT_A4H PMC_EV_ARMV7_EVENT_A5H PMC_EV_ARMV7_EVENT_A6H PMC_EV_ARMV7_EVENT_A7H PMC_EV_ARMV7_EVENT_A8H PMC_EV_ARMV7_EVENT_A9H PMC_EV_ARMV7_EVENT_AAH PMC_EV_ARMV7_EVENT_ABH PMC_EV_ARMV7_EVENT_ACH PMC_EV_ARMV7_EVENT_ADH PMC_EV_ARMV7_EVENT_AEH PMC_EV_ARMV7_EVENT_AFH PMC_EV_ARMV7_EVENT_B0H PMC_EV_ARMV7_EVENT_B1H PMC_EV_ARMV7_EVENT_B2H PMC_EV_ARMV7_EVENT_B3H PMC_EV_ARMV7_EVENT_B4H PMC_EV_ARMV7_EVENT_B5H PMC_EV_ARMV7_EVENT_B6H PMC_EV_ARMV7_EVENT_B7H PMC_EV_ARMV7_EVENT_B8H PMC_EV_ARMV7_EVENT_B9H PMC_EV_ARMV7_EVENT_BAH PMC_EV_ARMV7_EVENT_BBH PMC_EV_ARMV7_EVENT_BCH PMC_EV_ARMV7_EVENT_BDH PMC_EV_ARMV7_EVENT_BEH PMC_EV_ARMV7_EVENT_BFH PMC_EV_ARMV7_EVENT_C0H PMC_EV_ARMV7_EVENT_C1H PMC_EV_ARMV7_EVENT_C2H PMC_EV_ARMV7_EVENT_C3H PMC_EV_ARMV7_EVENT_C4H PMC_EV_ARMV7_EVENT_C5H PMC_EV_ARMV7_EVENT_C6H PMC_EV_ARMV7_EVENT_C7H PMC_EV_ARMV7_EVENT_C8H PMC_EV_ARMV7_EVENT_C9H PMC_EV_ARMV7_EVENT_CAH PMC_EV_ARMV7_EVENT_CBH PMC_EV_ARMV7_EVENT_CCH PMC_EV_ARMV7_EVENT_CDH PMC_EV_ARMV7_EVENT_CEH PMC_EV_ARMV7_EVENT_CFH PMC_EV_ARMV7_EVENT_D0H PMC_EV_ARMV7_EVENT_D1H PMC_EV_ARMV7_EVENT_D2H PMC_EV_ARMV7_EVENT_D3H PMC_EV_ARMV7_EVENT_D4H PMC_EV_ARMV7_EVENT_D5H PMC_EV_ARMV7_EVENT_D6H PMC_EV_ARMV7_EVENT_D7H PMC_EV_ARMV7_EVENT_D8H PMC_EV_ARMV7_EVENT_D9H PMC_EV_ARMV7_EVENT_DAH PMC_EV_ARMV7_EVENT_DBH PMC_EV_ARMV7_EVENT_DCH PMC_EV_ARMV7_EVENT_DDH PMC_EV_ARMV7_EVENT_DEH PMC_EV_ARMV7_EVENT_DFH PMC_EV_ARMV7_EVENT_E0H PMC_EV_ARMV7_EVENT_E1H PMC_EV_ARMV7_EVENT_E2H PMC_EV_ARMV7_EVENT_E3H PMC_EV_ARMV7_EVENT_E4H PMC_EV_ARMV7_EVENT_E5H PMC_EV_ARMV7_EVENT_E6H PMC_EV_ARMV7_EVENT_E7H PMC_EV_ARMV7_EVENT_E8H PMC_EV_ARMV7_EVENT_E9H PMC_EV_ARMV7_EVENT_EAH PMC_EV_ARMV7_EVENT_EBH PMC_EV_ARMV7_EVENT_ECH PMC_EV_ARMV7_EVENT_EDH PMC_EV_ARMV7_EVENT_EEH PMC_EV_ARMV7_EVENT_EFH PMC_EV_ARMV7_EVENT_F0H PMC_EV_ARMV7_EVENT_F1H PMC_EV_ARMV7_EVENT_F2H PMC_EV_ARMV7_EVENT_F3H PMC_EV_ARMV7_EVENT_F4H PMC_EV_ARMV7_EVENT_F5H PMC_EV_ARMV7_EVENT_F6H PMC_EV_ARMV7_EVENT_F7H PMC_EV_ARMV7_EVENT_F8H PMC_EV_ARMV7_EVENT_F9H PMC_EV_ARMV7_EVENT_FAH PMC_EV_ARMV7_EVENT_FBH PMC_EV_ARMV7_EVENT_FCH PMC_EV_ARMV7_EVENT_FDH PMC_EV_ARMV7_EVENT_FEH PMC_EV_ARMV7_EVENT_FFH PMC_EV_ARMV8__BLOCK_START PMC_EV_ARMV8_EVENT_00H PMC_EV_ARMV8_EVENT_01H PMC_EV_ARMV8_EVENT_02H PMC_EV_ARMV8_EVENT_03H PMC_EV_ARMV8_EVENT_04H PMC_EV_ARMV8_EVENT_05H PMC_EV_ARMV8_EVENT_06H PMC_EV_ARMV8_EVENT_07H PMC_EV_ARMV8_EVENT_08H PMC_EV_ARMV8_EVENT_09H PMC_EV_ARMV8_EVENT_0AH PMC_EV_ARMV8_EVENT_0BH PMC_EV_ARMV8_EVENT_0CH PMC_EV_ARMV8_EVENT_0DH PMC_EV_ARMV8_EVENT_0EH PMC_EV_ARMV8_EVENT_0FH PMC_EV_ARMV8_EVENT_10H PMC_EV_ARMV8_EVENT_11H PMC_EV_ARMV8_EVENT_12H PMC_EV_ARMV8_EVENT_13H PMC_EV_ARMV8_EVENT_14H PMC_EV_ARMV8_EVENT_15H PMC_EV_ARMV8_EVENT_16H PMC_EV_ARMV8_EVENT_17H PMC_EV_ARMV8_EVENT_18H PMC_EV_ARMV8_EVENT_19H PMC_EV_ARMV8_EVENT_1AH PMC_EV_ARMV8_EVENT_1BH PMC_EV_ARMV8_EVENT_1CH PMC_EV_ARMV8_EVENT_1DH PMC_EV_ARMV8_EVENT_1EH PMC_EV_ARMV8_EVENT_1FH PMC_EV_ARMV8_EVENT_20H PMC_EV_ARMV8_EVENT_21H PMC_EV_ARMV8_EVENT_22H PMC_EV_ARMV8_EVENT_23H PMC_EV_ARMV8_EVENT_24H PMC_EV_ARMV8_EVENT_25H PMC_EV_ARMV8_EVENT_26H PMC_EV_ARMV8_EVENT_27H PMC_EV_ARMV8_EVENT_28H PMC_EV_ARMV8_EVENT_29H PMC_EV_ARMV8_EVENT_2AH PMC_EV_ARMV8_EVENT_2BH PMC_EV_ARMV8_EVENT_2CH PMC_EV_ARMV8_EVENT_2DH PMC_EV_ARMV8_EVENT_2EH PMC_EV_ARMV8_EVENT_2FH PMC_EV_ARMV8_EVENT_30H PMC_EV_ARMV8_EVENT_31H PMC_EV_ARMV8_EVENT_32H PMC_EV_ARMV8_EVENT_33H PMC_EV_ARMV8_EVENT_34H PMC_EV_ARMV8_EVENT_35H PMC_EV_ARMV8_EVENT_36H PMC_EV_ARMV8_EVENT_37H PMC_EV_ARMV8_EVENT_38H PMC_EV_ARMV8_EVENT_39H PMC_EV_ARMV8_EVENT_3AH PMC_EV_ARMV8_EVENT_3BH PMC_EV_ARMV8_EVENT_3CH PMC_EV_ARMV8_EVENT_3DH PMC_EV_ARMV8_EVENT_3EH PMC_EV_ARMV8_EVENT_3FH PMC_EV_ARMV8_EVENT_40H PMC_EV_ARMV8_EVENT_41H PMC_EV_ARMV8_EVENT_42H PMC_EV_ARMV8_EVENT_43H PMC_EV_ARMV8_EVENT_44H PMC_EV_ARMV8_EVENT_45H PMC_EV_ARMV8_EVENT_46H PMC_EV_ARMV8_EVENT_47H PMC_EV_ARMV8_EVENT_48H PMC_EV_ARMV8_EVENT_49H PMC_EV_ARMV8_EVENT_4AH PMC_EV_ARMV8_EVENT_4BH PMC_EV_ARMV8_EVENT_4CH PMC_EV_ARMV8_EVENT_4DH PMC_EV_ARMV8_EVENT_4EH PMC_EV_ARMV8_EVENT_4FH PMC_EV_ARMV8_EVENT_50H PMC_EV_ARMV8_EVENT_51H PMC_EV_ARMV8_EVENT_52H PMC_EV_ARMV8_EVENT_53H PMC_EV_ARMV8_EVENT_54H PMC_EV_ARMV8_EVENT_55H PMC_EV_ARMV8_EVENT_56H PMC_EV_ARMV8_EVENT_57H PMC_EV_ARMV8_EVENT_58H PMC_EV_ARMV8_EVENT_59H PMC_EV_ARMV8_EVENT_5AH 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PMC_EV_ARMV8_EVENT_DCH PMC_EV_ARMV8_EVENT_DDH PMC_EV_ARMV8_EVENT_DEH PMC_EV_ARMV8_EVENT_DFH PMC_EV_ARMV8_EVENT_E0H PMC_EV_ARMV8_EVENT_E1H PMC_EV_ARMV8_EVENT_E2H PMC_EV_ARMV8_EVENT_E3H PMC_EV_ARMV8_EVENT_E4H PMC_EV_ARMV8_EVENT_E5H PMC_EV_ARMV8_EVENT_E6H PMC_EV_ARMV8_EVENT_E7H PMC_EV_ARMV8_EVENT_E8H PMC_EV_ARMV8_EVENT_E9H PMC_EV_ARMV8_EVENT_EAH PMC_EV_ARMV8_EVENT_EBH PMC_EV_ARMV8_EVENT_ECH PMC_EV_ARMV8_EVENT_EDH PMC_EV_ARMV8_EVENT_EEH PMC_EV_ARMV8_EVENT_EFH PMC_EV_ARMV8_EVENT_F0H PMC_EV_ARMV8_EVENT_F1H PMC_EV_ARMV8_EVENT_F2H PMC_EV_ARMV8_EVENT_F3H PMC_EV_ARMV8_EVENT_F4H PMC_EV_ARMV8_EVENT_F5H PMC_EV_ARMV8_EVENT_F6H PMC_EV_ARMV8_EVENT_F7H PMC_EV_ARMV8_EVENT_F8H PMC_EV_ARMV8_EVENT_F9H PMC_EV_ARMV8_EVENT_FAH PMC_EV_ARMV8_EVENT_FBH PMC_EV_ARMV8_EVENT_FCH PMC_EV_ARMV8_EVENT_FDH PMC_EV_ARMV8_EVENT_FEH PMC_EV_ARMV8_EVENT_FFH pmc_event ps_state ps_arch ps_version __uint32_t uint32_t ps_initialized int ps_count ps_offset long long int __int64_t __off_t off_t ps_saved pl_cc pl_header pl_spare pl_tsc long long unsigned int __uint64_t uint64_t pl_pid pl_tid pl_pmcid pl_cpuflags pl_pc __uintptr_t uintptr_t __ARRAY_SIZE_TYPE__ pmclog_callchain pl_cl pmclog_closelog pl_dn pmclog_dropnotify pl_i pl_version pl_cpu pl_tsc_freq pl_ts tv_sec __int32_t __time_t time_t tv_nsec long int timespec pl_cpuid char pmclog_initialize pl_mi pl_pad pl_start u_int uintfptr_t pl_pathname pmclog_map_in pl_mo pl_end pmclog_map_out pl_a pl_event pl_flags pl_rate pmclog_pmcallocate pl_ad pl_evname pmclog_pmcallocatedyn pl_t pmclog_pmcattach pl_d pmclog_pmcdetach pl_c pl_value pmclog_proccsw pl_pcomm pmclog_proccreate pl_x pmclog_procexec pl_e pmclog_procexit pl_f pl_oldpid pl_newpid pmclog_procfork pl_se pmclog_sysexit pl_tc pl_tdname pmclog_threadcreate pl_te pmclog_threadexit pl_u pl_userdata pmclog_userdata pmclog_entry ps_svcount ps_fd ps_buffer ps_data ps_cpuid ps_len __size_t size_t pmclog_parse_state pmclog_header pmclog_get_record ps data len __ssize_t ssize_t HEADERSIZE avail used src dst copylen recordsize h done error pmclog_get_event cookie ev pl_state pl_offset pl_count pl_type pl_data pl_len pl_cpuflags2 pl_npc pmclog_ev_callchain pmclog_ev_closelog pmclog_ev_dropnotify pl_arch pmclog_ev_initialize __pid_t pid_t pmclog_ev_map_in pmclog_ev_map_out pmc_id_t pmclog_ev_pmcallocate pmclog_ev_pmcallocatedyn pmclog_ev_pmcattach pmclog_ev_pmcdetach pmc_value_t pmclog_ev_proccsw pmclog_ev_proccreate pl_entryaddr pmclog_ev_procexec pmclog_ev_procexit pmclog_ev_procfork pmclog_ev_sysexit pmclog_ev_threadcreate pmclog_ev_threadexit pmclog_ev_userdata pmclog_ev e le ph evlen noop pathlen npc _v read pmc_pmu_event_get_by_idx _pmc_name_of_event free pmclog_read pmclog_feed pmclog_open pmclog_close nread retval refill fd zR | ( AB
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PMC_EV_K7_L1_DTLB_MISS_AND_L2_DTLB_HITS PMC_EV_K7_L1_AND_L2_DTLB_MISSES PMC_EV_K7_MISALIGNED_REFERENCES PMC_EV_K7_IC_FETCHES PMC_EV_K7_IC_MISSES PMC_EV_K7_L1_ITLB_MISSES PMC_EV_K7_L1_L2_ITLB_MISSES PMC_EV_K7_RETIRED_INSTRUCTIONS PMC_EV_K7_RETIRED_OPS PMC_EV_K7_RETIRED_BRANCHES PMC_EV_K7_RETIRED_BRANCHES_MISPREDICTED PMC_EV_K7_RETIRED_TAKEN_BRANCHES PMC_EV_K7_RETIRED_TAKEN_BRANCHES_MISPREDICTED PMC_EV_K7_RETIRED_FAR_CONTROL_TRANSFERS PMC_EV_K7_RETIRED_RESYNC_BRANCHES PMC_EV_K7_INTERRUPTS_MASKED_CYCLES PMC_EV_K7_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES PMC_EV_K7_HARDWARE_INTERRUPTS PMC_EV_K8__BLOCK_START PMC_EV_K8_FP_DISPATCHED_FPU_OPS PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD PMC_EV_K8_LS_MICROARCHITECTURAL_RESYNC_BY_SELF_MODIFYING_CODE PMC_EV_K8_LS_MICROARCHITECTURAL_RESYNC_BY_SNOOP PMC_EV_K8_LS_BUFFER2_FULL PMC_EV_K8_LS_LOCKED_OPERATION PMC_EV_K8_LS_MICROARCHITECTURAL_LATE_CANCEL PMC_EV_K8_LS_RETIRED_CFLUSH_INSTRUCTIONS PMC_EV_K8_LS_RETIRED_CPUID_INSTRUCTIONS PMC_EV_K8_DC_ACCESS PMC_EV_K8_DC_MISS PMC_EV_K8_DC_REFILL_FROM_L2 PMC_EV_K8_DC_REFILL_FROM_SYSTEM PMC_EV_K8_DC_COPYBACK PMC_EV_K8_DC_L1_DTLB_MISS_AND_L2_DTLB_HIT PMC_EV_K8_DC_L1_DTLB_MISS_AND_L2_DTLB_MISS PMC_EV_K8_DC_MISALIGNED_DATA_REFERENCE PMC_EV_K8_DC_MICROARCHITECTURAL_LATE_CANCEL PMC_EV_K8_DC_MICROARCHITECTURAL_EARLY_CANCEL PMC_EV_K8_DC_ONE_BIT_ECC_ERROR PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS PMC_EV_K8_BU_CPU_CLK_UNHALTED PMC_EV_K8_BU_INTERNAL_L2_REQUEST PMC_EV_K8_BU_FILL_REQUEST_L2_MISS PMC_EV_K8_BU_FILL_INTO_L2 PMC_EV_K8_IC_FETCH PMC_EV_K8_IC_MISS PMC_EV_K8_IC_REFILL_FROM_L2 PMC_EV_K8_IC_REFILL_FROM_SYSTEM PMC_EV_K8_IC_L1_ITLB_MISS_AND_L2_ITLB_HIT PMC_EV_K8_IC_L1_ITLB_MISS_AND_L2_ITLB_MISS PMC_EV_K8_IC_MICROARCHITECTURAL_RESYNC_BY_SNOOP PMC_EV_K8_IC_INSTRUCTION_FETCH_STALL PMC_EV_K8_IC_RETURN_STACK_HIT PMC_EV_K8_IC_RETURN_STACK_OVERFLOW PMC_EV_K8_FR_RETIRED_X86_INSTRUCTIONS PMC_EV_K8_FR_RETIRED_UOPS PMC_EV_K8_FR_RETIRED_BRANCHES PMC_EV_K8_FR_RETIRED_BRANCHES_MISPREDICTED PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED PMC_EV_K8_FR_RETIRED_FAR_CONTROL_TRANSFERS PMC_EV_K8_FR_RETIRED_RESYNCS PMC_EV_K8_FR_RETIRED_NEAR_RETURNS PMC_EV_K8_FR_RETIRED_NEAR_RETURNS_MISPREDICTED PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED_BY_ADDR_MISCOMPARE PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS PMC_EV_K8_FR_INTERRUPTS_MASKED_CYCLES PMC_EV_K8_FR_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES PMC_EV_K8_FR_TAKEN_HARDWARE_INTERRUPTS PMC_EV_K8_FR_DECODER_EMPTY PMC_EV_K8_FR_DISPATCH_STALLS PMC_EV_K8_FR_DISPATCH_STALL_FROM_BRANCH_ABORT_TO_RETIRE PMC_EV_K8_FR_DISPATCH_STALL_FOR_SERIALIZATION PMC_EV_K8_FR_DISPATCH_STALL_FOR_SEGMENT_LOAD PMC_EV_K8_FR_DISPATCH_STALL_WHEN_REORDER_BUFFER_IS_FULL PMC_EV_K8_FR_DISPATCH_STALL_WHEN_RESERVATION_STATIONS_ARE_FULL PMC_EV_K8_FR_DISPATCH_STALL_WHEN_FPU_IS_FULL PMC_EV_K8_FR_DISPATCH_STALL_WHEN_LS_IS_FULL PMC_EV_K8_FR_DISPATCH_STALL_WHEN_WAITING_FOR_ALL_TO_BE_QUIET PMC_EV_K8_FR_DISPATCH_STALL_WHEN_FAR_XFER_OR_RESYNC_BRANCH_PENDING PMC_EV_K8_FR_FPU_EXCEPTIONS PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR0 PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR1 PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR2 PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR3 PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOW PMC_EV_K8_NB_MEMORY_CONTROLLER_DRAM_COMMAND_SLOTS_MISSED PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION PMC_EV_K8_NB_SIZED_COMMANDS PMC_EV_K8_NB_PROBE_RESULT PMC_EV_K8_NB_HT_BUS0_BANDWIDTH PMC_EV_K8_NB_HT_BUS1_BANDWIDTH PMC_EV_K8_NB_HT_BUS2_BANDWIDTH PMC_EV_MIPS24K__BLOCK_START PMC_EV_MIPS24K_CYCLE PMC_EV_MIPS24K_INSTR_EXECUTED PMC_EV_MIPS24K_BRANCH_COMPLETED PMC_EV_MIPS24K_BRANCH_MISPRED PMC_EV_MIPS24K_RETURN PMC_EV_MIPS24K_RETURN_MISPRED PMC_EV_MIPS24K_RETURN_NOT_31 PMC_EV_MIPS24K_RETURN_NOTPRED PMC_EV_MIPS24K_ITLB_ACCESS PMC_EV_MIPS24K_ITLB_MISS PMC_EV_MIPS24K_DTLB_ACCESS PMC_EV_MIPS24K_DTLB_MISS PMC_EV_MIPS24K_JTLB_IACCESS PMC_EV_MIPS24K_JTLB_IMISS PMC_EV_MIPS24K_JTLB_DACCESS PMC_EV_MIPS24K_JTLB_DMISS PMC_EV_MIPS24K_IC_FETCH PMC_EV_MIPS24K_IC_MISS PMC_EV_MIPS24K_DC_LOADSTORE PMC_EV_MIPS24K_DC_WRITEBACK PMC_EV_MIPS24K_DC_MISS PMC_EV_MIPS24K_STORE_MISS PMC_EV_MIPS24K_LOAD_MISS PMC_EV_MIPS24K_INTEGER_COMPLETED PMC_EV_MIPS24K_FP_COMPLETED PMC_EV_MIPS24K_LOAD_COMPLETED PMC_EV_MIPS24K_STORE_COMPLETED PMC_EV_MIPS24K_BARRIER_COMPLETED PMC_EV_MIPS24K_MIPS16_COMPLETED PMC_EV_MIPS24K_NOP_COMPLETED PMC_EV_MIPS24K_INTEGER_MULDIV_COMPLETED PMC_EV_MIPS24K_RF_STALL PMC_EV_MIPS24K_INSTR_REFETCH PMC_EV_MIPS24K_STORE_COND_COMPLETED PMC_EV_MIPS24K_STORE_COND_FAILED PMC_EV_MIPS24K_ICACHE_REQUESTS PMC_EV_MIPS24K_ICACHE_HIT PMC_EV_MIPS24K_L2_WRITEBACK PMC_EV_MIPS24K_L2_ACCESS PMC_EV_MIPS24K_L2_MISS PMC_EV_MIPS24K_L2_ERR_CORRECTED PMC_EV_MIPS24K_EXCEPTIONS PMC_EV_MIPS24K_RF_CYCLES_STALLED PMC_EV_MIPS24K_IFU_CYCLES_STALLED PMC_EV_MIPS24K_ALU_CYCLES_STALLED PMC_EV_MIPS24K_UNCACHED_LOAD PMC_EV_MIPS24K_UNCACHED_STORE PMC_EV_MIPS24K_CP2_REG_TO_REG_COMPLETED PMC_EV_MIPS24K_MFTC_COMPLETED PMC_EV_MIPS24K_IC_BLOCKED_CYCLES PMC_EV_MIPS24K_DC_BLOCKED_CYCLES PMC_EV_MIPS24K_L2_IMISS_STALL_CYCLES PMC_EV_MIPS24K_L2_DMISS_STALL_CYCLES PMC_EV_MIPS24K_DMISS_CYCLES PMC_EV_MIPS24K_L2_MISS_CYCLES PMC_EV_MIPS24K_UNCACHED_BLOCK_CYCLES PMC_EV_MIPS24K_MDU_STALL_CYCLES PMC_EV_MIPS24K_FPU_STALL_CYCLES PMC_EV_MIPS24K_CP2_STALL_CYCLES PMC_EV_MIPS24K_COREXTEND_STALL_CYCLES PMC_EV_MIPS24K_ISPRAM_STALL_CYCLES PMC_EV_MIPS24K_DSPRAM_STALL_CYCLES PMC_EV_MIPS24K_CACHE_STALL_CYCLES PMC_EV_MIPS24K_LOAD_TO_USE_STALLS PMC_EV_MIPS24K_BASE_MISPRED_STALLS PMC_EV_MIPS24K_CPO_READ_STALLS PMC_EV_MIPS24K_BRANCH_MISPRED_CYCLES PMC_EV_MIPS24K_IFETCH_BUFFER_FULL PMC_EV_MIPS24K_FETCH_BUFFER_ALLOCATED PMC_EV_MIPS24K_EJTAG_ITRIGGER PMC_EV_MIPS24K_EJTAG_DTRIGGER PMC_EV_MIPS24K_FSB_LT_QUARTER PMC_EV_MIPS24K_FSB_QUARTER_TO_HALF PMC_EV_MIPS24K_FSB_GT_HALF PMC_EV_MIPS24K_FSB_FULL_PIPELINE_STALLS PMC_EV_MIPS24K_LDQ_LT_QUARTER PMC_EV_MIPS24K_LDQ_QUARTER_TO_HALF PMC_EV_MIPS24K_LDQ_GT_HALF PMC_EV_MIPS24K_LDQ_FULL_PIPELINE_STALLS PMC_EV_MIPS24K_WBB_LT_QUARTER PMC_EV_MIPS24K_WBB_QUARTER_TO_HALF PMC_EV_MIPS24K_WBB_GT_HALF PMC_EV_MIPS24K_WBB_FULL_PIPELINE_STALLS PMC_EV_MIPS24K_REQUEST_LATENCY PMC_EV_MIPS24K_REQUEST_COUNT PMC_EV_OCTEON__BLOCK_START PMC_EV_OCTEON_CLK PMC_EV_OCTEON_ISSUE PMC_EV_OCTEON_RET PMC_EV_OCTEON_NISSUE PMC_EV_OCTEON_SISSUE PMC_EV_OCTEON_DISSUE PMC_EV_OCTEON_IFI PMC_EV_OCTEON_BR PMC_EV_OCTEON_BRMIS PMC_EV_OCTEON_J PMC_EV_OCTEON_JMIS PMC_EV_OCTEON_REPLAY PMC_EV_OCTEON_IUNA PMC_EV_OCTEON_TRAP PMC_EV_OCTEON_UULOAD PMC_EV_OCTEON_UUSTORE PMC_EV_OCTEON_ULOAD PMC_EV_OCTEON_USTORE PMC_EV_OCTEON_EC PMC_EV_OCTEON_MC PMC_EV_OCTEON_CC PMC_EV_OCTEON_CSRC PMC_EV_OCTEON_CFETCH PMC_EV_OCTEON_CPREF PMC_EV_OCTEON_ICA PMC_EV_OCTEON_II PMC_EV_OCTEON_IP PMC_EV_OCTEON_CIMISS PMC_EV_OCTEON_WBUF PMC_EV_OCTEON_WDAT PMC_EV_OCTEON_WBUFLD PMC_EV_OCTEON_WBUFFL PMC_EV_OCTEON_WBUFTR PMC_EV_OCTEON_BADD PMC_EV_OCTEON_BADDL2 PMC_EV_OCTEON_BFILL PMC_EV_OCTEON_DDIDS PMC_EV_OCTEON_IDIDS PMC_EV_OCTEON_DIDNA PMC_EV_OCTEON_LDS PMC_EV_OCTEON_LMLDS PMC_EV_OCTEON_IOLDS PMC_EV_OCTEON_DMLDS PMC_EV_OCTEON_STS PMC_EV_OCTEON_LMSTS PMC_EV_OCTEON_IOSTS PMC_EV_OCTEON_IOBDMA PMC_EV_OCTEON_DTLB PMC_EV_OCTEON_DTLBAD PMC_EV_OCTEON_ITLB PMC_EV_OCTEON_SYNC PMC_EV_OCTEON_SYNCIOB PMC_EV_OCTEON_SYNCW PMC_EV_MIPS74K__BLOCK_START PMC_EV_MIPS74K_CYCLES PMC_EV_MIPS74K_INSTR_EXECUTED PMC_EV_MIPS74K_PREDICTED_JR_31 PMC_EV_MIPS74K_JR_31_MISPREDICTIONS PMC_EV_MIPS74K_REDIRECT_STALLS PMC_EV_MIPS74K_JR_31_NO_PREDICTIONS PMC_EV_MIPS74K_ITLB_ACCESSES PMC_EV_MIPS74K_ITLB_MISSES PMC_EV_MIPS74K_JTLB_INSN_MISSES PMC_EV_MIPS74K_ICACHE_ACCESSES PMC_EV_MIPS74K_ICACHE_MISSES PMC_EV_MIPS74K_ICACHE_MISS_STALLS PMC_EV_MIPS74K_UNCACHED_IFETCH_STALLS PMC_EV_MIPS74K_PDTRACE_BACK_STALLS PMC_EV_MIPS74K_IFU_REPLAYS PMC_EV_MIPS74K_KILLED_FETCH_SLOTS PMC_EV_MIPS74K_IFU_IDU_MISS_PRED_UPSTREAM_CYCLES PMC_EV_MIPS74K_IFU_IDU_NO_FETCH_CYCLES PMC_EV_MIPS74K_IFU_IDU_CLOGED_DOWNSTREAM_CYCLES PMC_EV_MIPS74K_DDQ0_FULL_DR_STALLS PMC_EV_MIPS74K_DDQ1_FULL_DR_STALLS PMC_EV_MIPS74K_ALCB_FULL_DR_STALLS PMC_EV_MIPS74K_AGCB_FULL_DR_STALLS PMC_EV_MIPS74K_CLDQ_FULL_DR_STALLS PMC_EV_MIPS74K_IODQ_FULL_DR_STALLS PMC_EV_MIPS74K_ALU_EMPTY_CYCLES PMC_EV_MIPS74K_AGEN_EMPTY_CYCLES PMC_EV_MIPS74K_ALU_OPERANDS_NOT_READY_CYCLES PMC_EV_MIPS74K_AGEN_OPERANDS_NOT_READY_CYCLES PMC_EV_MIPS74K_ALU_NO_ISSUES_CYCLES PMC_EV_MIPS74K_AGEN_NO_ISSUES_CYCLES PMC_EV_MIPS74K_ALU_BUBBLE_CYCLES PMC_EV_MIPS74K_AGEN_BUBBLE_CYCLES PMC_EV_MIPS74K_SINGLE_ISSUE_CYCLES PMC_EV_MIPS74K_DUAL_ISSUE_CYCLES PMC_EV_MIPS74K_OOO_ALU_ISSUE_CYCLES PMC_EV_MIPS74K_OOO_AGEN_ISSUE_CYCLES PMC_EV_MIPS74K_JALR_JALR_HB_INSNS PMC_EV_MIPS74K_DCACHE_LINE_REFILL_REQUESTS PMC_EV_MIPS74K_DCACHE_LOAD_ACCESSES PMC_EV_MIPS74K_DCACHE_ACCESSES PMC_EV_MIPS74K_DCACHE_WRITEBACKS PMC_EV_MIPS74K_DCACHE_MISSES PMC_EV_MIPS74K_JTLB_DATA_ACCESSES PMC_EV_MIPS74K_JTLB_DATA_MISSES PMC_EV_MIPS74K_LOAD_STORE_REPLAYS PMC_EV_MIPS74K_VA_TRANSALTION_CORNER_CASES PMC_EV_MIPS74K_LOAD_STORE_BLOCKED_CYCLES PMC_EV_MIPS74K_LOAD_STORE_NO_FILL_REQUESTS PMC_EV_MIPS74K_L2_CACHE_WRITEBACKS PMC_EV_MIPS74K_L2_CACHE_ACCESSES PMC_EV_MIPS74K_L2_CACHE_MISSES PMC_EV_MIPS74K_L2_CACHE_MISS_CYCLES PMC_EV_MIPS74K_FSB_FULL_STALLS PMC_EV_MIPS74K_FSB_OVER_50_FULL PMC_EV_MIPS74K_LDQ_FULL_STALLS PMC_EV_MIPS74K_LDQ_OVER_50_FULL PMC_EV_MIPS74K_WBB_FULL_STALLS PMC_EV_MIPS74K_WBB_OVER_50_FULL PMC_EV_MIPS74K_LOAD_MISS_CONSUMER_REPLAYS PMC_EV_MIPS74K_CP1_CP2_LOAD_INSNS PMC_EV_MIPS74K_JR_NON_31_INSNS PMC_EV_MIPS74K_MISPREDICTED_JR_31_INSNS PMC_EV_MIPS74K_BRANCH_INSNS PMC_EV_MIPS74K_CP1_CP2_COND_BRANCH_INSNS PMC_EV_MIPS74K_BRANCH_LIKELY_INSNS PMC_EV_MIPS74K_MISPREDICTED_BRANCH_LIKELY_INSNS PMC_EV_MIPS74K_COND_BRANCH_INSNS PMC_EV_MIPS74K_MISPREDICTED_BRANCH_INSNS PMC_EV_MIPS74K_INTEGER_INSNS PMC_EV_MIPS74K_FPU_INSNS PMC_EV_MIPS74K_LOAD_INSNS PMC_EV_MIPS74K_STORE_INSNS PMC_EV_MIPS74K_J_JAL_INSNS PMC_EV_MIPS74K_MIPS16_INSNS PMC_EV_MIPS74K_NOP_INSNS PMC_EV_MIPS74K_NT_MUL_DIV_INSNS PMC_EV_MIPS74K_DSP_INSNS PMC_EV_MIPS74K_ALU_DSP_SATURATION_INSNS PMC_EV_MIPS74K_DSP_BRANCH_INSNS PMC_EV_MIPS74K_MDU_DSP_SATURATION_INSNS PMC_EV_MIPS74K_UNCACHED_LOAD_INSNS PMC_EV_MIPS74K_UNCACHED_STORE_INSNS PMC_EV_MIPS74K_EJTAG_INSN_TRIGGERS PMC_EV_MIPS74K_CP1_BRANCH_MISPREDICTIONS PMC_EV_MIPS74K_SC_INSNS PMC_EV_MIPS74K_FAILED_SC_INSNS PMC_EV_MIPS74K_PREFETCH_INSNS PMC_EV_MIPS74K_CACHE_HIT_PREFETCH_INSNS PMC_EV_MIPS74K_NO_INSN_CYCLES PMC_EV_MIPS74K_LOAD_MISS_INSNS PMC_EV_MIPS74K_ONE_INSN_CYCLES PMC_EV_MIPS74K_TWO_INSNS_CYCLES PMC_EV_MIPS74K_GFIFO_BLOCKED_CYCLES PMC_EV_MIPS74K_CP1_CP2_STORE_INSNS PMC_EV_MIPS74K_MISPREDICTION_STALLS PMC_EV_MIPS74K_MISPREDICTED_BRANCH_INSNS_CYCLES PMC_EV_MIPS74K_EXCEPTIONS_TAKEN PMC_EV_MIPS74K_GRADUATION_REPLAYS PMC_EV_MIPS74K_COREEXTEND_EVENTS PMC_EV_MIPS74K_ISPRAM_EVENTS PMC_EV_MIPS74K_DSPRAM_EVENTS PMC_EV_MIPS74K_L2_CACHE_SINGLE_BIT_ERRORS PMC_EV_MIPS74K_SYSTEM_EVENT_0 PMC_EV_MIPS74K_SYSTEM_EVENT_1 PMC_EV_MIPS74K_SYSTEM_EVENT_2 PMC_EV_MIPS74K_SYSTEM_EVENT_3 PMC_EV_MIPS74K_SYSTEM_EVENT_4 PMC_EV_MIPS74K_SYSTEM_EVENT_5 PMC_EV_MIPS74K_SYSTEM_EVENT_6 PMC_EV_MIPS74K_SYSTEM_EVENT_7 PMC_EV_MIPS74K_OCP_ALL_REQUESTS PMC_EV_MIPS74K_OCP_ALL_CACHEABLE_REQUESTS PMC_EV_MIPS74K_OCP_READ_REQUESTS PMC_EV_MIPS74K_OCP_READ_CACHEABLE_REQUESTS PMC_EV_MIPS74K_OCP_WRITE_REQUESTS PMC_EV_MIPS74K_OCP_WRITE_CACHEABLE_REQUESTS PMC_EV_MIPS74K_FSB_LESS_25_FULL PMC_EV_MIPS74K_FSB_25_50_FULL PMC_EV_MIPS74K_LDQ_LESS_25_FULL PMC_EV_MIPS74K_LDQ_25_50_FULL PMC_EV_MIPS74K_WBB_LESS_25_FULL PMC_EV_MIPS74K_WBB_25_50_FULL PMC_EV_BERI__BLOCK_START PMC_EV_BERI_CYCLE PMC_EV_BERI_INST PMC_EV_BERI_INST_USER PMC_EV_BERI_INST_KERNEL PMC_EV_BERI_IMPRECISE_SETBOUNDS PMC_EV_BERI_UNREPRESENTABLE_CAPS PMC_EV_BERI_ITLB_MISS PMC_EV_BERI_DTLB_MISS PMC_EV_BERI_ICACHE_WRITE_HIT PMC_EV_BERI_ICACHE_WRITE_MISS PMC_EV_BERI_ICACHE_READ_HIT PMC_EV_BERI_ICACHE_READ_MISS PMC_EV_BERI_ICACHE_EVICT PMC_EV_BERI_DCACHE_WRITE_HIT PMC_EV_BERI_DCACHE_WRITE_MISS PMC_EV_BERI_DCACHE_READ_HIT PMC_EV_BERI_DCACHE_READ_MISS PMC_EV_BERI_DCACHE_EVICT PMC_EV_BERI_DCACHE_SET_TAG_WRITE PMC_EV_BERI_DCACHE_SET_TAG_READ PMC_EV_BERI_L2CACHE_WRITE_HIT PMC_EV_BERI_L2CACHE_WRITE_MISS PMC_EV_BERI_L2CACHE_READ_HIT PMC_EV_BERI_L2CACHE_READ_MISS PMC_EV_BERI_L2CACHE_EVICT PMC_EV_BERI_L2CACHE_SET_TAG_WRITE PMC_EV_BERI_L2CACHE_SET_TAG_READ PMC_EV_BERI_MEM_BYTE_READ PMC_EV_BERI_MEM_BYTE_WRITE PMC_EV_BERI_MEM_HWORD_READ PMC_EV_BERI_MEM_HWORD_WRITE PMC_EV_BERI_MEM_WORD_READ PMC_EV_BERI_MEM_WORD_WRITE PMC_EV_BERI_MEM_DWORD_READ PMC_EV_BERI_MEM_DWORD_WRITE PMC_EV_BERI_MEM_CAP_READ PMC_EV_BERI_MEM_CAP_WRITE PMC_EV_BERI_MEM_CAP_READ_TAG_SET PMC_EV_BERI_MEM_CAP_WRITE_TAG_SET PMC_EV_BERI_TAGCACHE_WRITE_HIT PMC_EV_BERI_TAGCACHE_WRITE_MISS PMC_EV_BERI_TAGCACHE_READ_HIT PMC_EV_BERI_TAGCACHE_READ_MISS PMC_EV_BERI_TAGCACHE_EVICT PMC_EV_BERI_L2CACHEMASTER_READ_REQ PMC_EV_BERI_L2CACHEMASTER_WRITE_REQ PMC_EV_BERI_L2CACHEMASTER_WRITE_REQ_FLIT PMC_EV_BERI_L2CACHEMASTER_READ_RSP PMC_EV_BERI_L2CACHEMASTER_READ_RSP_FLIT PMC_EV_BERI_L2CACHEMASTER_WRITE_RSP PMC_EV_BERI_TAGCACHEMASTER_READ_REQ PMC_EV_BERI_TAGCACHEMASTER_WRITE_REQ PMC_EV_BERI_TAGCACHEMASTER_WRITE_REQ_FLIT PMC_EV_BERI_TAGCACHEMASTER_READ_RSP PMC_EV_BERI_TAGCACHEMASTER_READ_RSP_FLIT PMC_EV_BERI_TAGCACHEMASTER_WRITE_RSP PMC_EV_UCP__BLOCK_START PMC_EV_UCP_EVENT_0CH_04H_E PMC_EV_UCP_EVENT_0CH_04H_F PMC_EV_UCP_EVENT_0CH_04H_M PMC_EV_UCP_EVENT_0CH_04H_S PMC_EV_UCP_EVENT_0CH_08H_E PMC_EV_UCP_EVENT_0CH_08H_F PMC_EV_UCP_EVENT_0CH_08H_M PMC_EV_UCP_EVENT_0CH_08H_S PMC_EV_PPC7450__BLOCK_START PMC_EV_PPC7450_CYCLE PMC_EV_PPC7450_INSTR_COMPLETED PMC_EV_PPC7450_TLB_BIT_TRANSITIONS PMC_EV_PPC7450_INSTR_DISPATCHED PMC_EV_PPC7450_PMON_EXCEPT PMC_EV_PPC7450_PMON_SIG PMC_EV_PPC7450_VPU_INSTR_COMPLETED PMC_EV_PPC7450_VFPU_INSTR_COMPLETED PMC_EV_PPC7450_VIU1_INSTR_COMPLETED PMC_EV_PPC7450_VIU2_INSTR_COMPLETED PMC_EV_PPC7450_MTVSCR_INSTR_COMPLETED PMC_EV_PPC7450_MTVRSAVE_INSTR_COMPLETED PMC_EV_PPC7450_VPU_INSTR_WAIT_CYCLES PMC_EV_PPC7450_VFPU_INSTR_WAIT_CYCLES PMC_EV_PPC7450_VIU1_INSTR_WAIT_CYCLES PMC_EV_PPC7450_VIU2_INSTR_WAIT_CYCLES PMC_EV_PPC7450_MFVSCR_SYNC_CYCLES PMC_EV_PPC7450_VSCR_SAT_SET PMC_EV_PPC7450_STORE_INSTR_COMPLETED PMC_EV_PPC7450_L1_INSTR_CACHE_MISSES PMC_EV_PPC7450_L1_DATA_SNOOPS PMC_EV_PPC7450_UNRESOLVED_BRANCHES PMC_EV_PPC7450_SPEC_BUFFER_CYCLES PMC_EV_PPC7450_BRANCH_UNIT_STALL_CYCLES PMC_EV_PPC7450_TRUE_BRANCH_TARGET_HITS PMC_EV_PPC7450_BRANCH_LINK_STAC_PREDICTED PMC_EV_PPC7450_GPR_ISSUE_QUEUE_DISPATCHES PMC_EV_PPC7450_CYCLES_THREE_INSTR_DISPATCHED PMC_EV_PPC7450_THRESHOLD_INSTR_QUEUE_ENTRIES_CYCLES PMC_EV_PPC7450_THRESHOLD_VEC_INSTR_QUEUE_ENTRIES_CYCLES PMC_EV_PPC7450_CYCLES_NO_COMPLETED_INSTRS PMC_EV_PPC7450_IU2_INSTR_COMPLETED PMC_EV_PPC7450_BRANCHES_COMPLETED PMC_EV_PPC7450_EIEIO_INSTR_COMPLETED PMC_EV_PPC7450_MTSPR_INSTR_COMPLETED PMC_EV_PPC7450_SC_INSTR_COMPLETED PMC_EV_PPC7450_LS_LM_COMPLETED PMC_EV_PPC7450_ITLB_HW_TABLE_SEARCH_CYCLES PMC_EV_PPC7450_DTLB_HW_SEARCH_CYCLES_OVER_THRESHOLD PMC_EV_PPC7450_L1_INSTR_CACHE_ACCESSES PMC_EV_PPC7450_INSTR_BKPT_MATCHES PMC_EV_PPC7450_L1_DATA_CACHE_LOAD_MISS_CYCLES_OVER_THRESHOLD PMC_EV_PPC7450_L1_DATA_SNOOP_HIT_ON_MODIFIED PMC_EV_PPC7450_LOAD_MISS_ALIAS PMC_EV_PPC7450_LOAD_MISS_ALIAS_ON_TOUCH PMC_EV_PPC7450_TOUCH_ALIAS PMC_EV_PPC7450_L1_DATA_SNOOP_HIT_CASTOUT_QUEUE PMC_EV_PPC7450_L1_DATA_SNOOP_HIT_CASTOUT PMC_EV_PPC7450_L1_DATA_SNOOP_HITS PMC_EV_PPC7450_WRITE_THROUGH_STORES PMC_EV_PPC7450_CACHE_INHIBITED_STORES PMC_EV_PPC7450_L1_DATA_LOAD_HIT PMC_EV_PPC7450_L1_DATA_TOUCH_HIT PMC_EV_PPC7450_L1_DATA_STORE_HIT PMC_EV_PPC7450_L1_DATA_TOTAL_HITS PMC_EV_PPC7450_DST_INSTR_DISPATCHED PMC_EV_PPC7450_REFRESHED_DSTS PMC_EV_PPC7450_SUCCESSFUL_DST_TABLE_SEARCHES PMC_EV_PPC7450_DSS_INSTR_COMPLETED PMC_EV_PPC7450_DST_STREAM_0_CACHE_LINE_FETCHES PMC_EV_PPC7450_VTQ_SUSPENDS_DUE_TO_CTX_CHANGE PMC_EV_PPC7450_VTQ_LINE_FETCH_HIT PMC_EV_PPC7450_VEC_LOAD_INSTR_COMPLETED PMC_EV_PPC7450_FP_STORE_INSTR_COMPLETED_IN_LSU PMC_EV_PPC7450_FPU_RENORMALIZATION PMC_EV_PPC7450_FPU_DENORMALIZATION PMC_EV_PPC7450_FP_STORE_CAUSES_STALL_IN_LSU PMC_EV_PPC7450_LD_ST_TRUE_ALIAS_STALL PMC_EV_PPC7450_LSU_INDEXED_ALIAS_STALL PMC_EV_PPC7450_LSU_ALIAS_VS_FSQ_WB0_WB1 PMC_EV_PPC7450_LSU_ALIAS_VS_CSQ PMC_EV_PPC7450_LSU_LOAD_HIT_LINE_ALIAS_VS_CSQ0 PMC_EV_PPC7450_LSU_LOAD_MISS_LINE_ALIAS_VS_CSQ0 PMC_EV_PPC7450_LSU_TOUCH_LINE_ALIAS_VS_FSQ_WB0_WB1 PMC_EV_PPC7450_LSU_TOUCH_ALIAS_VS_CSQ PMC_EV_PPC7450_LSU_LMQ_FULL_STALL PMC_EV_PPC7450_FP_LOAD_INSTR_COMPLETED_IN_LSU PMC_EV_PPC7450_FP_LOAD_SINGLE_INSTR_COMPLETED_IN_LSU PMC_EV_PPC7450_FP_LOAD_DOUBLE_COMPLETED_IN_LSU PMC_EV_PPC7450_LSU_RA_LATCH_STALL PMC_EV_PPC7450_LSU_LOAD_VS_STORE_QUEUE_ALIAS_STALL PMC_EV_PPC7450_LSU_LMQ_INDEX_ALIAS PMC_EV_PPC7450_LSU_STORE_QUEUE_INDEX_ALIAS PMC_EV_PPC7450_LSU_CSQ_FORWARDING PMC_EV_PPC7450_LSU_MISALIGNED_LOAD_FINISH PMC_EV_PPC7450_LSU_MISALIGN_STORE_COMPLETED PMC_EV_PPC7450_LSU_MISALIGN_STALL PMC_EV_PPC7450_FP_ONE_QUARTER_FPSCR_RENAMES_BUSY PMC_EV_PPC7450_FP_ONE_HALF_FPSCR_RENAMES_BUSY PMC_EV_PPC7450_FP_THREE_QUARTERS_FPSCR_RENAMES_BUSY PMC_EV_PPC7450_FP_ALL_FPSCR_RENAMES_BUSY PMC_EV_PPC7450_FP_DENORMALIZED_RESULT PMC_EV_PPC7450_L1_DATA_TOTAL_MISSES PMC_EV_PPC7450_DISPATCHES_TO_FPR_ISSUE_QUEUE PMC_EV_PPC7450_LSU_INSTR_COMPLETED PMC_EV_PPC7450_LOAD_INSTR_COMPLETED PMC_EV_PPC7450_SS_SM_INSTR_COMPLETED PMC_EV_PPC7450_TLBIE_INSTR_COMPLETED PMC_EV_PPC7450_LWARX_INSTR_COMPLETED PMC_EV_PPC7450_MFSPR_INSTR_COMPLETED PMC_EV_PPC7450_REFETCH_SERIALIZATION PMC_EV_PPC7450_COMPLETION_QUEUE_ENTRIES_OVER_THRESHOLD PMC_EV_PPC7450_CYCLES_ONE_INSTR_DISPATCHED PMC_EV_PPC7450_CYCLES_TWO_INSTR_COMPLETED PMC_EV_PPC7450_ITLB_NON_SPECULATIVE_MISSES PMC_EV_PPC7450_CYCLES_WAITING_FROM_L1_INSTR_CACHE_MISS PMC_EV_PPC7450_L1_DATA_LOAD_ACCESS_MISS PMC_EV_PPC7450_L1_DATA_TOUCH_MISS PMC_EV_PPC7450_L1_DATA_STORE_MISS PMC_EV_PPC7450_L1_DATA_TOUCH_MISS_CYCLES PMC_EV_PPC7450_L1_DATA_CYCLES_USED PMC_EV_PPC7450_DST_STREAM_1_CACHE_LINE_FETCHES PMC_EV_PPC7450_VTQ_STREAM_CANCELED_PREMATURELY PMC_EV_PPC7450_VTQ_RESUMES_DUE_TO_CTX_CHANGE PMC_EV_PPC7450_VTQ_LINE_FETCH_MISS PMC_EV_PPC7450_VTQ_LINE_FETCH PMC_EV_PPC7450_TLBIE_SNOOPS PMC_EV_PPC7450_L1_INSTR_CACHE_RELOADS PMC_EV_PPC7450_L1_DATA_CACHE_RELOADS PMC_EV_PPC7450_L1_DATA_CACHE_CASTOUTS_TO_L2 PMC_EV_PPC7450_STORE_MERGE_GATHER PMC_EV_PPC7450_CACHEABLE_STORE_MERGE_TO_32_BYTES PMC_EV_PPC7450_DATA_BKPT_MATCHES PMC_EV_PPC7450_FALL_THROUGH_BRANCHES_PROCESSED PMC_EV_PPC7450_FIRST_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLY PMC_EV_PPC7450_SECOND_SPECULATION_BUFFER_ACTIVE PMC_EV_PPC7450_BPU_STALL_ON_LR_DEPENDENCY PMC_EV_PPC7450_BTIC_MISS PMC_EV_PPC7450_BRANCH_LINK_STACK_CORRECTLY_RESOLVED PMC_EV_PPC7450_FPR_ISSUE_STALLED PMC_EV_PPC7450_SWITCHES_BETWEEN_PRIV_USER PMC_EV_PPC7450_LSU_COMPLETES_FP_STORE_SINGLE PMC_EV_PPC7450_VR_ISSUE_QUEUE_DISPATCHES PMC_EV_PPC7450_VR_STALLS PMC_EV_PPC7450_GPR_RENAME_BUFFER_ENTRIES_OVER_THRESHOLD PMC_EV_PPC7450_FPR_ISSUE_QUEUE_ENTRIES PMC_EV_PPC7450_FPU_INSTR_COMPLETED PMC_EV_PPC7450_STWCX_INSTR_COMPLETED PMC_EV_PPC7450_LS_LM_INSTR_PIECES PMC_EV_PPC7450_ITLB_HW_SEARCH_CYCLES_OVER_THRESHOLD PMC_EV_PPC7450_DTLB_MISSES PMC_EV_PPC7450_CANCELLED_L1_INSTR_CACHE_MISSES PMC_EV_PPC7450_L1_DATA_CACHE_OP_HIT PMC_EV_PPC7450_L1_DATA_LOAD_MISS_CYCLES PMC_EV_PPC7450_L1_DATA_PUSHES PMC_EV_PPC7450_L1_DATA_TOTAL_MISS PMC_EV_PPC7450_VT2_FETCHES PMC_EV_PPC7450_TAKEN_BRANCHES_PROCESSED PMC_EV_PPC7450_BRANCH_FLUSHES PMC_EV_PPC7450_SECOND_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLY PMC_EV_PPC7450_THIRD_SPECULATION_BUFFER_ACTIVE PMC_EV_PPC7450_BRANCH_UNIT_STALL_ON_CTR_DEPENDENCY PMC_EV_PPC7450_FAST_BTIC_HIT PMC_EV_PPC7450_BRANCH_LINK_STACK_MISPREDICTED PMC_EV_PPC7450_CYCLES_THREE_INSTR_COMPLETED PMC_EV_PPC7450_CYCLES_NO_INSTR_DISPATCHED PMC_EV_PPC7450_GPR_ISSUE_QUEUE_ENTRIES_OVER_THRESHOLD PMC_EV_PPC7450_GPR_ISSUE_QUEUE_STALLED PMC_EV_PPC7450_IU1_INSTR_COMPLETED PMC_EV_PPC7450_DSSALL_INSTR_COMPLETED PMC_EV_PPC7450_TLBSYNC_INSTR_COMPLETED PMC_EV_PPC7450_SYNC_INSTR_COMPLETED PMC_EV_PPC7450_SS_SM_INSTR_PIECES PMC_EV_PPC7450_DTLB_HW_SEARCH_CYCLES PMC_EV_PPC7450_SNOOP_RETRIES PMC_EV_PPC7450_SUCCESSFUL_STWCX PMC_EV_PPC7450_DST_STREAM_3_CACHE_LINE_FETCHES PMC_EV_PPC7450_THIRD_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLY PMC_EV_PPC7450_MISPREDICTED_BRANCHES PMC_EV_PPC7450_FOLDED_BRANCHES PMC_EV_PPC7450_FP_STORE_DOUBLE_COMPLETES_IN_LSU PMC_EV_PPC7450_L2_CACHE_HITS PMC_EV_PPC7450_L3_CACHE_HITS PMC_EV_PPC7450_L2_INSTR_CACHE_MISSES PMC_EV_PPC7450_L3_INSTR_CACHE_MISSES PMC_EV_PPC7450_L2_DATA_CACHE_MISSES PMC_EV_PPC7450_L3_DATA_CACHE_MISSES PMC_EV_PPC7450_L2_LOAD_HITS PMC_EV_PPC7450_L2_STORE_HITS PMC_EV_PPC7450_L3_LOAD_HITS PMC_EV_PPC7450_L3_STORE_HITS PMC_EV_PPC7450_L2_TOUCH_HITS PMC_EV_PPC7450_L3_TOUCH_HITS PMC_EV_PPC7450_SNOOP_MODIFIED PMC_EV_PPC7450_SNOOP_VALID PMC_EV_PPC7450_INTERVENTION PMC_EV_PPC7450_L2_CACHE_MISSES PMC_EV_PPC7450_L3_CACHE_MISSES PMC_EV_PPC7450_L2_CACHE_CASTOUTS PMC_EV_PPC7450_L3_CACHE_CASTOUTS PMC_EV_PPC7450_L2SQ_FULL_CYCLES PMC_EV_PPC7450_L3SQ_FULL_CYCLES PMC_EV_PPC7450_RAQ_FULL_CYCLES PMC_EV_PPC7450_WAQ_FULL_CYCLES PMC_EV_PPC7450_L1_EXTERNAL_INTERVENTIONS PMC_EV_PPC7450_L2_EXTERNAL_INTERVENTIONS PMC_EV_PPC7450_L3_EXTERNAL_INTERVENTIONS PMC_EV_PPC7450_EXTERNAL_INTERVENTIONS PMC_EV_PPC7450_EXTERNAL_PUSHES PMC_EV_PPC7450_EXTERNAL_SNOOP_RETRY PMC_EV_PPC7450_DTQ_FULL_CYCLES PMC_EV_PPC7450_BUS_RETRY PMC_EV_PPC7450_L2_VALID_REQUEST PMC_EV_PPC7450_BORDQ_FULL PMC_EV_PPC7450_BUS_TAS_FOR_READS PMC_EV_PPC7450_BUS_TAS_FOR_WRITES PMC_EV_PPC7450_BUS_READS_NOT_RETRIED PMC_EV_PPC7450_BUS_WRITES_NOT_RETRIED PMC_EV_PPC7450_BUS_READS_WRITES_NOT_RETRIED PMC_EV_PPC7450_BUS_RETRY_DUE_TO_L1_RETRY PMC_EV_PPC7450_BUS_RETRY_DUE_TO_PREVIOUS_ADJACENT PMC_EV_PPC7450_BUS_RETRY_DUE_TO_COLLISION PMC_EV_PPC7450_BUS_RETRY_DUE_TO_INTERVENTION_ORDERING PMC_EV_PPC7450_SNOOP_REQUESTS PMC_EV_PPC7450_PREFETCH_ENGINE_REQUEST PMC_EV_PPC7450_PREFETCH_ENGINE_COLLISION_VS_LOAD PMC_EV_PPC7450_PREFETCH_ENGINE_COLLISION_VS_STORE PMC_EV_PPC7450_PREFETCH_ENGINE_COLLISION_VS_INSTR_FETCH PMC_EV_PPC7450_PREFETCH_ENGINE_COLLISION_VS_LOAD_STORE_INSTR_FETCH PMC_EV_PPC7450_PREFETCH_ENGINE_FULL PMC_EV_PPC970__BLOCK_START PMC_EV_PPC970_INSTR_COMPLETED PMC_EV_PPC970_MARKED_GROUP_DISPATCH PMC_EV_PPC970_MARKED_STORE_COMPLETED PMC_EV_PPC970_GCT_EMPTY PMC_EV_PPC970_RUN_CYCLES PMC_EV_PPC970_OVERFLOW PMC_EV_PPC970_CYCLES PMC_EV_PPC970_THRESHOLD_TIMEOUT PMC_EV_PPC970_GROUP_DISPATCH PMC_EV_PPC970_BR_MARKED_INSTR_FINISH PMC_EV_PPC970_GCT_EMPTY_BY_SRQ_FULL PMC_EV_PPC970_STOP_COMPLETION PMC_EV_PPC970_LSU_EMPTY PMC_EV_PPC970_MARKED_STORE_WITH_INTR PMC_EV_PPC970_CYCLES_IN_SUPER PMC_EV_PPC970_VPU_MARKED_INSTR_COMPLETED PMC_EV_PPC970_FXU0_IDLE_FXU1_BUSY PMC_EV_PPC970_SRQ_EMPTY PMC_EV_PPC970_MARKED_GROUP_COMPLETED PMC_EV_PPC970_CR_MARKED_INSTR_FINISH PMC_EV_PPC970_DISPATCH_SUCCESS PMC_EV_PPC970_FXU0_IDLE_FXU1_IDLE PMC_EV_PPC970_ONE_PLUS_INSTR_COMPLETED PMC_EV_PPC970_GROUP_MARKED_IDU PMC_EV_PPC970_MARKED_GROUP_COMPLETE_TIMEOUT PMC_EV_PPC970_FXU0_BUSY_FXU1_BUSY PMC_EV_PPC970_MARKED_STORE_SENT_TO_STS PMC_EV_PPC970_FXU_MARKED_INSTR_FINISHED PMC_EV_PPC970_MARKED_GROUP_ISSUED PMC_EV_PPC970_FXU0_BUSY_FXU1_IDLE PMC_EV_PPC970_GROUP_COMPLETED PMC_EV_PPC970_FPU_MARKED_INSTR_COMPLETED PMC_EV_PPC970_MARKED_INSTR_FINISH_ANY_UNIT PMC_EV_PPC970_EXTERNAL_INTERRUPT PMC_EV_PPC970_GROUP_DISPATCH_REJECT PMC_EV_PPC970_LSU_MARKED_INSTR_FINISH PMC_EV_PPC970_TIMEBASE_EVENT PMC_EV_PPC970_LSU_COMPLETION_STALL PMC_EV_PPC970_FXU_COMPLETION_STALL PMC_EV_PPC970_DCACHE_MISS_COMPLETION_STALL PMC_EV_PPC970_FPU_COMPLETION_STALL PMC_EV_PPC970_FXU_LONG_INSTR_COMPLETION_STALL PMC_EV_PPC970_REJECT_COMPLETION_STALL PMC_EV_PPC970_FPU_LONG_INSTR_COMPLETION_STALL PMC_EV_PPC970_GCT_EMPTY_BY_ICACHE_MISS PMC_EV_PPC970_REJECT_COMPLETION_STALL_ERAT_MISS PMC_EV_PPC970_GCT_EMPTY_BY_BRANCH_MISS_PREDICT PMC_EV_PPC970_BUS_HIGH PMC_EV_PPC970_BUS_LOW PMC_EV_PPC970_ADDER PMC_EV_POWER8__BLOCK_START PMC_EV_POWER8_CYCLES PMC_EV_POWER8_CYCLES_WITH_INSTRS_COMPLETED PMC_EV_POWER8_FPU_INSTR_COMPLETED PMC_EV_POWER8_ERAT_INSTR_MISS PMC_EV_POWER8_CYCLES_IDLE PMC_EV_POWER8_CYCLES_WITH_ANY_THREAD_RUNNING PMC_EV_POWER8_STORE_COMPLETED PMC_EV_POWER8_INSTR_DISPATCHED PMC_EV_POWER8_CYCLES_RUNNING PMC_EV_POWER8_ERAT_DATA_MISS PMC_EV_POWER8_EXTERNAL_INTERRUPT PMC_EV_POWER8_BRANCH_TAKEN PMC_EV_POWER8_L1_INSTR_MISS PMC_EV_POWER8_L2_LOAD_MISS PMC_EV_POWER8_STORE_NO_REAL_ADDR PMC_EV_POWER8_INSTR_COMPLETED_WITH_ALL_THREADS_RUNNING PMC_EV_POWER8_L1_LOAD_MISS PMC_EV_POWER8_TIMEBASE_EVENT PMC_EV_POWER8_L3_INSTR_MISS PMC_EV_POWER8_TLB_DATA_MISS PMC_EV_POWER8_L3_LOAD_MISS PMC_EV_POWER8_LOAD_NO_REAL_ADDR PMC_EV_POWER8_CYCLES_WITH_INSTRS_DISPATCHED PMC_EV_POWER8_CYCLES_RUNNING_PURR_INC PMC_EV_POWER8_BRANCH_MISPREDICTED PMC_EV_POWER8_PREFETCHED_INSTRS_DISCARDED PMC_EV_POWER8_INSTR_COMPLETED_RUNNING PMC_EV_POWER8_TLB_INSTR_MISS PMC_EV_POWER8_CACHE_LOAD_MISS PMC_EV_POWER8_INSTR_COMPLETED PMC_EV_E500__BLOCK_START PMC_EV_E500_CYCLES PMC_EV_E500_INSTR_COMPLETED PMC_EV_E500_UOPS_COMPLETED PMC_EV_E500_INSTR_FETCHED PMC_EV_E500_UOPS_DECODED PMC_EV_E500_PM_EVENT_TRANSITIONS PMC_EV_E500_PM_EVENT_CYCLES PMC_EV_E500_BRANCH_INSTRS_COMPLETED PMC_EV_E500_LOAD_UOPS_COMPLETED PMC_EV_E500_STORE_UOPS_COMPLETED PMC_EV_E500_CQ_REDIRECTS PMC_EV_E500_BRANCHES_FINISHED PMC_EV_E500_TAKEN_BRANCHES_FINISHED PMC_EV_E500_FINISHED_UNCOND_BRANCHES_MISS_BTB PMC_EV_E500_BRANCH_MISPRED PMC_EV_E500_BTB_BRANCH_MISPRED_FROM_DIRECTION PMC_EV_E500_BTB_HITS_PSEUDO_HITS PMC_EV_E500_CYCLES_DECODE_STALLED PMC_EV_E500_CYCLES_ISSUE_STALLED PMC_EV_E500_CYCLES_BRANCH_ISSUE_STALLED PMC_EV_E500_CYCLES_SU1_SCHED_STALLED PMC_EV_E500_CYCLES_SU2_SCHED_STALLED PMC_EV_E500_CYCLES_MU_SCHED_STALLED PMC_EV_E500_CYCLES_LRU_SCHED_STALLED PMC_EV_E500_CYCLES_BU_SCHED_STALLED PMC_EV_E500_TOTAL_TRANSLATED PMC_EV_E500_LOADS_TRANSLATED PMC_EV_E500_STORES_TRANSLATED PMC_EV_E500_TOUCHES_TRANSLATED PMC_EV_E500_CACHEOPS_TRANSLATED PMC_EV_E500_CACHE_INHIBITED_ACCESS_TRANSLATED PMC_EV_E500_GUARDED_LOADS_TRANSLATED PMC_EV_E500_WRITE_THROUGH_STORES_TRANSLATED PMC_EV_E500_MISALIGNED_LOAD_STORE_ACCESS_TRANSLATED PMC_EV_E500_TOTAL_ALLOCATED_TO_DLFB PMC_EV_E500_LOADS_TRANSLATED_ALLOCATED_TO_DLFB PMC_EV_E500_STORES_COMPLETED_ALLOCATED_TO_DLFB PMC_EV_E500_TOUCHES_TRANSLATED_ALLOCATED_TO_DLFB PMC_EV_E500_STORES_COMPLETED PMC_EV_E500_DATA_L1_CACHE_LOCKS PMC_EV_E500_DATA_L1_CACHE_RELOADS PMC_EV_E500_DATA_L1_CACHE_CASTOUTS PMC_EV_E500_LOAD_MISS_DLFB_FULL PMC_EV_E500_LOAD_MISS_LDQ_FULL PMC_EV_E500_LOAD_GUARDED_MISS PMC_EV_E500_STORE_TRANSLATE_WHEN_QUEUE_FULL PMC_EV_E500_ADDRESS_COLLISION PMC_EV_E500_DATA_MMU_MISS PMC_EV_E500_DATA_MMU_BUSY PMC_EV_E500_PART2_MISALIGNED_CACHE_ACCESS PMC_EV_E500_LOAD_MISS_DLFB_FULL_CYCLES PMC_EV_E500_LOAD_MISS_LDQ_FULL_CYCLES PMC_EV_E500_LOAD_GUARDED_MISS_CYCLES PMC_EV_E500_STORE_TRANSLATE_WHEN_QUEUE_FULL_CYCLES PMC_EV_E500_ADDRESS_COLLISION_CYCLES PMC_EV_E500_DATA_MMU_MISS_CYCLES PMC_EV_E500_DATA_MMU_BUSY_CYCLES PMC_EV_E500_PART2_MISALIGNED_CACHE_ACCESS_CYCLES PMC_EV_E500_INSTR_L1_CACHE_LOCKS PMC_EV_E500_INSTR_L1_CACHE_RELOADS PMC_EV_E500_INSTR_L1_CACHE_FETCHES PMC_EV_E500_INSTR_MMU_TLB4K_RELOADS PMC_EV_E500_INSTR_MMU_VSP_RELOADS PMC_EV_E500_DATA_MMU_TLB4K_RELOADS PMC_EV_E500_DATA_MMU_VSP_RELOADS PMC_EV_E500_L2MMU_MISSES PMC_EV_E500_BIU_MASTER_REQUESTS PMC_EV_E500_BIU_MASTER_INSTR_SIDE_REQUESTS PMC_EV_E500_BIU_MASTER_DATA_SIDE_REQUESTS PMC_EV_E500_BIU_MASTER_DATA_SIDE_CASTOUT_REQUESTS PMC_EV_E500_BIU_MASTER_RETRIES PMC_EV_E500_SNOOP_REQUESTS PMC_EV_E500_SNOOP_HITS PMC_EV_E500_SNOOP_PUSHES PMC_EV_E500_SNOOP_RETRIES PMC_EV_E500_DLFB_LOAD_MISS_CYCLES PMC_EV_E500_ILFB_FETCH_MISS_CYCLES PMC_EV_E500_EXT_INPU_INTR_LATENCY_CYCLES PMC_EV_E500_CRIT_INPUT_INTR_LATENCY_CYCLES PMC_EV_E500_EXT_INPUT_INTR_PENDING_LATENCY_CYCLES PMC_EV_E500_CRIT_INPUT_INTR_PENDING_LATENCY_CYCLES PMC_EV_E500_PMC0_OVERFLOW PMC_EV_E500_PMC1_OVERFLOW PMC_EV_E500_PMC2_OVERFLOW PMC_EV_E500_PMC3_OVERFLOW PMC_EV_E500_INTERRUPTS_TAKEN PMC_EV_E500_EXT_INPUT_INTR_TAKEN PMC_EV_E500_CRIT_INPUT_INTR_TAKEN PMC_EV_E500_SYSCALL_TRAP_INTR PMC_EV_E500_TLB_BIT_TRANSITIONS PMC_EV_E500_L2_LINEFILL_BUFFER PMC_EV_E500_LV2_VS PMC_EV_E500_CASTOUTS_RELEASED PMC_EV_E500_INTV_ALLOCATIONS PMC_EV_E500_DLFB_RETRIES_TO_MBAR PMC_EV_E500_STORE_RETRIES PMC_EV_E500_STASH_L1_HITS PMC_EV_E500_STASH_L2_HITS PMC_EV_E500_STASH_BUSY_1 PMC_EV_E500_STASH_BUSY_2 PMC_EV_E500_STASH_BUSY_3 PMC_EV_E500_STASH_HITS PMC_EV_E500_STASH_HIT_DLFB PMC_EV_E500_STASH_REQUESTS PMC_EV_E500_STASH_REQUESTS_L1 PMC_EV_E500_STASH_REQUESTS_L2 PMC_EV_E500_STALLS_NO_CAQ_OR_COB PMC_EV_E500_L2_CACHE_ACCESSES PMC_EV_E500_L2_HIT_CACHE_ACCESSES PMC_EV_E500_L2_CACHE_DATA_ACCESSES PMC_EV_E500_L2_CACHE_DATA_HITS PMC_EV_E500_L2_CACHE_INSTR_ACCESSES PMC_EV_E500_L2_CACHE_INSTR_HITS PMC_EV_E500_L2_CACHE_ALLOCATIONS PMC_EV_E500_L2_CACHE_DATA_ALLOCATIONS PMC_EV_E500_L2_CACHE_DIRTY_DATA_ALLOCATIONS PMC_EV_E500_L2_CACHE_INSTR_ALLOCATIONS PMC_EV_E500_L2_CACHE_UPDATES PMC_EV_E500_L2_CACHE_CLEAN_UPDATES PMC_EV_E500_L2_CACHE_DIRTY_UPDATES PMC_EV_E500_L2_CACHE_CLEAN_REDUNDANT_UPDATES PMC_EV_E500_L2_CACHE_DIRTY_REDUNDANT_UPDATES PMC_EV_E500_L2_CACHE_LOCKS PMC_EV_E500_L2_CACHE_CASTOUTS PMC_EV_E500_L2_CACHE_DATA_DIRTY_HITS PMC_EV_E500_INSTR_LFB_WENT_HIGH_PRIORITY PMC_EV_E500_SNOOP_THROTTLING_TURNED_ON PMC_EV_E500_L2_CLEAN_LINE_INVALIDATIONS PMC_EV_E500_L2_INCOHERENT_LINE_INVALIDATIONS PMC_EV_E500_L2_COHERENT_LINE_INVALIDATIONS PMC_EV_E500_COHERENT_LOOKUP_MISS_DUE_TO_VALID_BUT_INCOHERENT_MATCHES PMC_EV_E500_IAC1S_DETECTED PMC_EV_E500_IAC2S_DETECTED PMC_EV_E500_DAC1S_DTECTED PMC_EV_E500_DAC2S_DTECTED PMC_EV_E500_DVT0_DETECTED PMC_EV_E500_DVT1_DETECTED PMC_EV_E500_DVT2_DETECTED PMC_EV_E500_DVT3_DETECTED PMC_EV_E500_DVT4_DETECTED PMC_EV_E500_DVT5_DETECTED PMC_EV_E500_DVT6_DETECTED PMC_EV_E500_DVT7_DETECTED PMC_EV_E500_CYCLES_COMPLETION_STALLED_NEXUS_FIFO_FULL PMC_EV_E500_FPU_DOUBLE_PUMP PMC_EV_E500_FPU_FINISH PMC_EV_E500_FPU_DIVIDE_CYCLES PMC_EV_E500_FPU_DENORM_INPUT_CYCLES PMC_EV_E500_FPU_RESULT_STALL_CYCLES PMC_EV_E500_FPU_FPSCR_FULL_STALL PMC_EV_E500_FPU_PIPE_SYNC_STALLS PMC_EV_E500_FPU_INPUT_DATA_STALLS PMC_EV_E500_DECORATED_LOADS PMC_EV_E500_DECORATED_STORES PMC_EV_E500_LOAD_RETRIES PMC_EV_E500_STWCX_SUCCESSES PMC_EV_E500_STWCX_FAILURES PMC_EV_ARMV7__BLOCK_START PMC_EV_ARMV7_EVENT_00H PMC_EV_ARMV7_EVENT_01H PMC_EV_ARMV7_EVENT_02H PMC_EV_ARMV7_EVENT_03H PMC_EV_ARMV7_EVENT_04H PMC_EV_ARMV7_EVENT_05H PMC_EV_ARMV7_EVENT_06H PMC_EV_ARMV7_EVENT_07H PMC_EV_ARMV7_EVENT_08H PMC_EV_ARMV7_EVENT_09H PMC_EV_ARMV7_EVENT_0AH PMC_EV_ARMV7_EVENT_0BH PMC_EV_ARMV7_EVENT_0CH PMC_EV_ARMV7_EVENT_0DH PMC_EV_ARMV7_EVENT_0EH PMC_EV_ARMV7_EVENT_0FH PMC_EV_ARMV7_EVENT_10H PMC_EV_ARMV7_EVENT_11H PMC_EV_ARMV7_EVENT_12H PMC_EV_ARMV7_EVENT_13H PMC_EV_ARMV7_EVENT_14H PMC_EV_ARMV7_EVENT_15H PMC_EV_ARMV7_EVENT_16H PMC_EV_ARMV7_EVENT_17H PMC_EV_ARMV7_EVENT_18H PMC_EV_ARMV7_EVENT_19H PMC_EV_ARMV7_EVENT_1AH PMC_EV_ARMV7_EVENT_1BH PMC_EV_ARMV7_EVENT_1CH PMC_EV_ARMV7_EVENT_1DH PMC_EV_ARMV7_EVENT_1EH PMC_EV_ARMV7_EVENT_1FH PMC_EV_ARMV7_EVENT_20H PMC_EV_ARMV7_EVENT_21H PMC_EV_ARMV7_EVENT_22H PMC_EV_ARMV7_EVENT_23H PMC_EV_ARMV7_EVENT_24H PMC_EV_ARMV7_EVENT_25H PMC_EV_ARMV7_EVENT_26H PMC_EV_ARMV7_EVENT_27H PMC_EV_ARMV7_EVENT_28H PMC_EV_ARMV7_EVENT_29H PMC_EV_ARMV7_EVENT_2AH PMC_EV_ARMV7_EVENT_2BH PMC_EV_ARMV7_EVENT_2CH PMC_EV_ARMV7_EVENT_2DH PMC_EV_ARMV7_EVENT_2EH PMC_EV_ARMV7_EVENT_2FH PMC_EV_ARMV7_EVENT_30H PMC_EV_ARMV7_EVENT_31H PMC_EV_ARMV7_EVENT_32H PMC_EV_ARMV7_EVENT_33H PMC_EV_ARMV7_EVENT_34H PMC_EV_ARMV7_EVENT_35H PMC_EV_ARMV7_EVENT_36H PMC_EV_ARMV7_EVENT_37H PMC_EV_ARMV7_EVENT_38H PMC_EV_ARMV7_EVENT_39H PMC_EV_ARMV7_EVENT_3AH PMC_EV_ARMV7_EVENT_3BH PMC_EV_ARMV7_EVENT_3CH PMC_EV_ARMV7_EVENT_3DH PMC_EV_ARMV7_EVENT_3EH PMC_EV_ARMV7_EVENT_3FH PMC_EV_ARMV7_EVENT_40H PMC_EV_ARMV7_EVENT_41H PMC_EV_ARMV7_EVENT_42H PMC_EV_ARMV7_EVENT_43H PMC_EV_ARMV7_EVENT_44H PMC_EV_ARMV7_EVENT_45H PMC_EV_ARMV7_EVENT_46H PMC_EV_ARMV7_EVENT_47H PMC_EV_ARMV7_EVENT_48H PMC_EV_ARMV7_EVENT_49H PMC_EV_ARMV7_EVENT_4AH PMC_EV_ARMV7_EVENT_4BH PMC_EV_ARMV7_EVENT_4CH PMC_EV_ARMV7_EVENT_4DH PMC_EV_ARMV7_EVENT_4EH PMC_EV_ARMV7_EVENT_4FH PMC_EV_ARMV7_EVENT_50H PMC_EV_ARMV7_EVENT_51H PMC_EV_ARMV7_EVENT_52H PMC_EV_ARMV7_EVENT_53H PMC_EV_ARMV7_EVENT_54H PMC_EV_ARMV7_EVENT_55H PMC_EV_ARMV7_EVENT_56H PMC_EV_ARMV7_EVENT_57H PMC_EV_ARMV7_EVENT_58H PMC_EV_ARMV7_EVENT_59H PMC_EV_ARMV7_EVENT_5AH PMC_EV_ARMV7_EVENT_5BH PMC_EV_ARMV7_EVENT_5CH PMC_EV_ARMV7_EVENT_5DH PMC_EV_ARMV7_EVENT_5EH PMC_EV_ARMV7_EVENT_5FH PMC_EV_ARMV7_EVENT_60H PMC_EV_ARMV7_EVENT_61H PMC_EV_ARMV7_EVENT_62H PMC_EV_ARMV7_EVENT_63H PMC_EV_ARMV7_EVENT_64H PMC_EV_ARMV7_EVENT_65H PMC_EV_ARMV7_EVENT_66H PMC_EV_ARMV7_EVENT_67H PMC_EV_ARMV7_EVENT_68H PMC_EV_ARMV7_EVENT_69H PMC_EV_ARMV7_EVENT_6AH PMC_EV_ARMV7_EVENT_6BH PMC_EV_ARMV7_EVENT_6CH PMC_EV_ARMV7_EVENT_6DH PMC_EV_ARMV7_EVENT_6EH PMC_EV_ARMV7_EVENT_6FH PMC_EV_ARMV7_EVENT_70H PMC_EV_ARMV7_EVENT_71H PMC_EV_ARMV7_EVENT_72H PMC_EV_ARMV7_EVENT_73H PMC_EV_ARMV7_EVENT_74H PMC_EV_ARMV7_EVENT_75H PMC_EV_ARMV7_EVENT_76H PMC_EV_ARMV7_EVENT_77H PMC_EV_ARMV7_EVENT_78H PMC_EV_ARMV7_EVENT_79H PMC_EV_ARMV7_EVENT_7AH PMC_EV_ARMV7_EVENT_7BH PMC_EV_ARMV7_EVENT_7CH PMC_EV_ARMV7_EVENT_7DH PMC_EV_ARMV7_EVENT_7EH PMC_EV_ARMV7_EVENT_7FH PMC_EV_ARMV7_EVENT_80H PMC_EV_ARMV7_EVENT_81H PMC_EV_ARMV7_EVENT_82H PMC_EV_ARMV7_EVENT_83H PMC_EV_ARMV7_EVENT_84H PMC_EV_ARMV7_EVENT_85H PMC_EV_ARMV7_EVENT_86H PMC_EV_ARMV7_EVENT_87H PMC_EV_ARMV7_EVENT_88H PMC_EV_ARMV7_EVENT_89H PMC_EV_ARMV7_EVENT_8AH PMC_EV_ARMV7_EVENT_8BH PMC_EV_ARMV7_EVENT_8CH PMC_EV_ARMV7_EVENT_8DH PMC_EV_ARMV7_EVENT_8EH PMC_EV_ARMV7_EVENT_8FH PMC_EV_ARMV7_EVENT_90H PMC_EV_ARMV7_EVENT_91H PMC_EV_ARMV7_EVENT_92H PMC_EV_ARMV7_EVENT_93H PMC_EV_ARMV7_EVENT_94H PMC_EV_ARMV7_EVENT_95H PMC_EV_ARMV7_EVENT_96H PMC_EV_ARMV7_EVENT_97H PMC_EV_ARMV7_EVENT_98H PMC_EV_ARMV7_EVENT_99H PMC_EV_ARMV7_EVENT_9AH PMC_EV_ARMV7_EVENT_9BH PMC_EV_ARMV7_EVENT_9CH PMC_EV_ARMV7_EVENT_9DH PMC_EV_ARMV7_EVENT_9EH PMC_EV_ARMV7_EVENT_9FH PMC_EV_ARMV7_EVENT_A0H PMC_EV_ARMV7_EVENT_A1H PMC_EV_ARMV7_EVENT_A2H PMC_EV_ARMV7_EVENT_A3H PMC_EV_ARMV7_EVENT_A4H PMC_EV_ARMV7_EVENT_A5H PMC_EV_ARMV7_EVENT_A6H PMC_EV_ARMV7_EVENT_A7H PMC_EV_ARMV7_EVENT_A8H PMC_EV_ARMV7_EVENT_A9H PMC_EV_ARMV7_EVENT_AAH PMC_EV_ARMV7_EVENT_ABH PMC_EV_ARMV7_EVENT_ACH PMC_EV_ARMV7_EVENT_ADH PMC_EV_ARMV7_EVENT_AEH PMC_EV_ARMV7_EVENT_AFH PMC_EV_ARMV7_EVENT_B0H PMC_EV_ARMV7_EVENT_B1H PMC_EV_ARMV7_EVENT_B2H PMC_EV_ARMV7_EVENT_B3H PMC_EV_ARMV7_EVENT_B4H PMC_EV_ARMV7_EVENT_B5H PMC_EV_ARMV7_EVENT_B6H PMC_EV_ARMV7_EVENT_B7H PMC_EV_ARMV7_EVENT_B8H PMC_EV_ARMV7_EVENT_B9H PMC_EV_ARMV7_EVENT_BAH PMC_EV_ARMV7_EVENT_BBH PMC_EV_ARMV7_EVENT_BCH PMC_EV_ARMV7_EVENT_BDH PMC_EV_ARMV7_EVENT_BEH PMC_EV_ARMV7_EVENT_BFH PMC_EV_ARMV7_EVENT_C0H PMC_EV_ARMV7_EVENT_C1H PMC_EV_ARMV7_EVENT_C2H PMC_EV_ARMV7_EVENT_C3H PMC_EV_ARMV7_EVENT_C4H PMC_EV_ARMV7_EVENT_C5H PMC_EV_ARMV7_EVENT_C6H PMC_EV_ARMV7_EVENT_C7H PMC_EV_ARMV7_EVENT_C8H PMC_EV_ARMV7_EVENT_C9H PMC_EV_ARMV7_EVENT_CAH PMC_EV_ARMV7_EVENT_CBH PMC_EV_ARMV7_EVENT_CCH PMC_EV_ARMV7_EVENT_CDH PMC_EV_ARMV7_EVENT_CEH PMC_EV_ARMV7_EVENT_CFH PMC_EV_ARMV7_EVENT_D0H PMC_EV_ARMV7_EVENT_D1H PMC_EV_ARMV7_EVENT_D2H PMC_EV_ARMV7_EVENT_D3H PMC_EV_ARMV7_EVENT_D4H PMC_EV_ARMV7_EVENT_D5H PMC_EV_ARMV7_EVENT_D6H PMC_EV_ARMV7_EVENT_D7H PMC_EV_ARMV7_EVENT_D8H PMC_EV_ARMV7_EVENT_D9H PMC_EV_ARMV7_EVENT_DAH PMC_EV_ARMV7_EVENT_DBH PMC_EV_ARMV7_EVENT_DCH PMC_EV_ARMV7_EVENT_DDH PMC_EV_ARMV7_EVENT_DEH PMC_EV_ARMV7_EVENT_DFH PMC_EV_ARMV7_EVENT_E0H PMC_EV_ARMV7_EVENT_E1H PMC_EV_ARMV7_EVENT_E2H PMC_EV_ARMV7_EVENT_E3H PMC_EV_ARMV7_EVENT_E4H PMC_EV_ARMV7_EVENT_E5H PMC_EV_ARMV7_EVENT_E6H PMC_EV_ARMV7_EVENT_E7H PMC_EV_ARMV7_EVENT_E8H PMC_EV_ARMV7_EVENT_E9H PMC_EV_ARMV7_EVENT_EAH PMC_EV_ARMV7_EVENT_EBH PMC_EV_ARMV7_EVENT_ECH PMC_EV_ARMV7_EVENT_EDH PMC_EV_ARMV7_EVENT_EEH PMC_EV_ARMV7_EVENT_EFH PMC_EV_ARMV7_EVENT_F0H PMC_EV_ARMV7_EVENT_F1H PMC_EV_ARMV7_EVENT_F2H PMC_EV_ARMV7_EVENT_F3H PMC_EV_ARMV7_EVENT_F4H PMC_EV_ARMV7_EVENT_F5H PMC_EV_ARMV7_EVENT_F6H PMC_EV_ARMV7_EVENT_F7H PMC_EV_ARMV7_EVENT_F8H PMC_EV_ARMV7_EVENT_F9H PMC_EV_ARMV7_EVENT_FAH PMC_EV_ARMV7_EVENT_FBH PMC_EV_ARMV7_EVENT_FCH PMC_EV_ARMV7_EVENT_FDH PMC_EV_ARMV7_EVENT_FEH PMC_EV_ARMV7_EVENT_FFH PMC_EV_ARMV8__BLOCK_START PMC_EV_ARMV8_EVENT_00H PMC_EV_ARMV8_EVENT_01H PMC_EV_ARMV8_EVENT_02H PMC_EV_ARMV8_EVENT_03H PMC_EV_ARMV8_EVENT_04H PMC_EV_ARMV8_EVENT_05H PMC_EV_ARMV8_EVENT_06H PMC_EV_ARMV8_EVENT_07H PMC_EV_ARMV8_EVENT_08H PMC_EV_ARMV8_EVENT_09H PMC_EV_ARMV8_EVENT_0AH PMC_EV_ARMV8_EVENT_0BH PMC_EV_ARMV8_EVENT_0CH PMC_EV_ARMV8_EVENT_0DH PMC_EV_ARMV8_EVENT_0EH PMC_EV_ARMV8_EVENT_0FH PMC_EV_ARMV8_EVENT_10H PMC_EV_ARMV8_EVENT_11H PMC_EV_ARMV8_EVENT_12H PMC_EV_ARMV8_EVENT_13H PMC_EV_ARMV8_EVENT_14H PMC_EV_ARMV8_EVENT_15H PMC_EV_ARMV8_EVENT_16H PMC_EV_ARMV8_EVENT_17H PMC_EV_ARMV8_EVENT_18H PMC_EV_ARMV8_EVENT_19H PMC_EV_ARMV8_EVENT_1AH PMC_EV_ARMV8_EVENT_1BH PMC_EV_ARMV8_EVENT_1CH PMC_EV_ARMV8_EVENT_1DH PMC_EV_ARMV8_EVENT_1EH PMC_EV_ARMV8_EVENT_1FH PMC_EV_ARMV8_EVENT_20H PMC_EV_ARMV8_EVENT_21H PMC_EV_ARMV8_EVENT_22H PMC_EV_ARMV8_EVENT_23H PMC_EV_ARMV8_EVENT_24H PMC_EV_ARMV8_EVENT_25H PMC_EV_ARMV8_EVENT_26H PMC_EV_ARMV8_EVENT_27H PMC_EV_ARMV8_EVENT_28H PMC_EV_ARMV8_EVENT_29H PMC_EV_ARMV8_EVENT_2AH PMC_EV_ARMV8_EVENT_2BH PMC_EV_ARMV8_EVENT_2CH PMC_EV_ARMV8_EVENT_2DH PMC_EV_ARMV8_EVENT_2EH PMC_EV_ARMV8_EVENT_2FH PMC_EV_ARMV8_EVENT_30H PMC_EV_ARMV8_EVENT_31H PMC_EV_ARMV8_EVENT_32H PMC_EV_ARMV8_EVENT_33H PMC_EV_ARMV8_EVENT_34H PMC_EV_ARMV8_EVENT_35H PMC_EV_ARMV8_EVENT_36H PMC_EV_ARMV8_EVENT_37H PMC_EV_ARMV8_EVENT_38H PMC_EV_ARMV8_EVENT_39H PMC_EV_ARMV8_EVENT_3AH PMC_EV_ARMV8_EVENT_3BH PMC_EV_ARMV8_EVENT_3CH PMC_EV_ARMV8_EVENT_3DH PMC_EV_ARMV8_EVENT_3EH PMC_EV_ARMV8_EVENT_3FH PMC_EV_ARMV8_EVENT_40H PMC_EV_ARMV8_EVENT_41H PMC_EV_ARMV8_EVENT_42H PMC_EV_ARMV8_EVENT_43H PMC_EV_ARMV8_EVENT_44H PMC_EV_ARMV8_EVENT_45H PMC_EV_ARMV8_EVENT_46H PMC_EV_ARMV8_EVENT_47H PMC_EV_ARMV8_EVENT_48H PMC_EV_ARMV8_EVENT_49H PMC_EV_ARMV8_EVENT_4AH PMC_EV_ARMV8_EVENT_4BH PMC_EV_ARMV8_EVENT_4CH PMC_EV_ARMV8_EVENT_4DH PMC_EV_ARMV8_EVENT_4EH PMC_EV_ARMV8_EVENT_4FH PMC_EV_ARMV8_EVENT_50H PMC_EV_ARMV8_EVENT_51H PMC_EV_ARMV8_EVENT_52H PMC_EV_ARMV8_EVENT_53H PMC_EV_ARMV8_EVENT_54H PMC_EV_ARMV8_EVENT_55H PMC_EV_ARMV8_EVENT_56H PMC_EV_ARMV8_EVENT_57H PMC_EV_ARMV8_EVENT_58H PMC_EV_ARMV8_EVENT_59H PMC_EV_ARMV8_EVENT_5AH PMC_EV_ARMV8_EVENT_5BH PMC_EV_ARMV8_EVENT_5CH PMC_EV_ARMV8_EVENT_5DH PMC_EV_ARMV8_EVENT_5EH PMC_EV_ARMV8_EVENT_5FH PMC_EV_ARMV8_EVENT_60H PMC_EV_ARMV8_EVENT_61H PMC_EV_ARMV8_EVENT_62H PMC_EV_ARMV8_EVENT_63H PMC_EV_ARMV8_EVENT_64H PMC_EV_ARMV8_EVENT_65H PMC_EV_ARMV8_EVENT_66H PMC_EV_ARMV8_EVENT_67H PMC_EV_ARMV8_EVENT_68H PMC_EV_ARMV8_EVENT_69H PMC_EV_ARMV8_EVENT_6AH PMC_EV_ARMV8_EVENT_6BH PMC_EV_ARMV8_EVENT_6CH PMC_EV_ARMV8_EVENT_6DH PMC_EV_ARMV8_EVENT_6EH PMC_EV_ARMV8_EVENT_6FH PMC_EV_ARMV8_EVENT_70H PMC_EV_ARMV8_EVENT_71H PMC_EV_ARMV8_EVENT_72H PMC_EV_ARMV8_EVENT_73H PMC_EV_ARMV8_EVENT_74H PMC_EV_ARMV8_EVENT_75H PMC_EV_ARMV8_EVENT_76H PMC_EV_ARMV8_EVENT_77H PMC_EV_ARMV8_EVENT_78H PMC_EV_ARMV8_EVENT_79H PMC_EV_ARMV8_EVENT_7AH PMC_EV_ARMV8_EVENT_7BH PMC_EV_ARMV8_EVENT_7CH PMC_EV_ARMV8_EVENT_7DH PMC_EV_ARMV8_EVENT_7EH PMC_EV_ARMV8_EVENT_7FH PMC_EV_ARMV8_EVENT_80H PMC_EV_ARMV8_EVENT_81H PMC_EV_ARMV8_EVENT_82H PMC_EV_ARMV8_EVENT_83H PMC_EV_ARMV8_EVENT_84H PMC_EV_ARMV8_EVENT_85H PMC_EV_ARMV8_EVENT_86H PMC_EV_ARMV8_EVENT_87H PMC_EV_ARMV8_EVENT_88H PMC_EV_ARMV8_EVENT_89H PMC_EV_ARMV8_EVENT_8AH PMC_EV_ARMV8_EVENT_8BH PMC_EV_ARMV8_EVENT_8CH PMC_EV_ARMV8_EVENT_8DH PMC_EV_ARMV8_EVENT_8EH PMC_EV_ARMV8_EVENT_8FH PMC_EV_ARMV8_EVENT_90H PMC_EV_ARMV8_EVENT_91H PMC_EV_ARMV8_EVENT_92H PMC_EV_ARMV8_EVENT_93H PMC_EV_ARMV8_EVENT_94H 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pmu_alias_table pa pmu_event_get alias event desc topic long_desc pmu unit perpkg metric_expr metric_name metric_group pmu_event cpuid event_name idx int pme version type table pmu_events_map i pe sysctlbyname strcasestr regcomp re_magic re_nsub re_endp re_g re_guts regexec rm_so long long int __int64_t __off_t regoff_t rm_eo regfree strsep getenv free pmc_pmu_intel_pmcallocate pm pm_caps uint32_t pm_cpu pm_class pm_ev pm_flags pm_mode pm_pmcid pmc_id_t pm_count pmc_value_t pm_md pm_amd pm_amd_config pm_amd_sub_class pmc_md_amd_op_pmcallocate pm_iap pm_iap_config pm_iap_rsp pmc_md_iap_op_pmcallocate pm_ucf pm_ucf_flags unsigned short __uint16_t uint16_t pmc_md_ucf_op_pmcallocate pm_ucp pm_ucp_config pmc_md_ucp_op_pmcallocate __pad pmc_md_op_pmcallocate pmc_op_pmcallocate ped ped_period ped_offcore_rsp ped_l3_thread ped_l3_slice ped_event ped_frontend ped_ldlat ped_config1 ped_umask short __int16_t int16_t ped_cmask unsigned char __uint8_t uint8_t ped_any ped_inv ped_edge ped_fc_mask ped_ch_mask pmu_event_desc isfixed iap pmc_pmu_amd_pmcallocate amd pmc_pmu_enabled pmc_pmu_idx_get_by_event pmc_pmu_event_get_by_idx pmu_events_map_get pmc_pmu_sample_rate_get pmu_parse_event pmc_pmu_print_counters pmc_pmu_print_counter_desc pmc_pmu_print_counter_desc_long pmc_pmu_print_counter_full pmc_pmu_pmcallocate pmc_pmu_stat_mode realname re regex_t pmatch regmatch_t match eventin r kvp value key debug do_debug ev cntrs FreeBSD clang version 11.0.1 (git@github.com:llvm/llvm-project.git llvmorg-11.0.1-0-g43ff75f2c3fe) zR | ( AB
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%s, "pmcid": "0x%08x", "pid": "%d", "pathname": "%s"}
%s, "pmcid": "0x%08x", "pid": "%d"}
%s, "pmcid": "0x%08x", "pid": "%d" "tid": "%d", "value": "0x%016jx"}
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" " " " '" " " " F" W" \" q" >" D" q" " :# # $ $ g# # $ $ p# # $ $ # # # # # # # # N$ $ $ % W$ $ $ % v$ $ $ $ n$ t$ $ $ j% & ' ' % & ' ' % & ' ' % % % % % % % & l& & ' $' u& & ' $' & & & & & & & & ' )( 7) @) ' )( 7) @) ' )( 7) @) ' ' ' ( ' ' ( %( ( ( @) I) ( ( @) I) ( ( ( ( ( ( ( ( FreeBSD clang version 11.0.1 (git@github.com:llvm/llvm-project.git llvmorg-11.0.1-0-g43ff75f2c3fe) /usr/src/lib/libpmc/libpmc_json.cc /usr/obj/usr/src/amd64.amd64/obj-lib32/lib/libpmc jsonconvert std __1 _ZNKSt3__121__basic_string_commonILb1EE20__throw_length_errorEv __throw_length_error _ZNKSt3__121__basic_string_commonILb1EE20__throw_out_of_rangeEv __throw_out_of_range bool __basic_string_common<true> __short_mask _ZNSt3__116allocator_traitsINS_9allocatorIcEEE8allocateERS2_j allocate allocator _ZNKSt3__19allocatorIcE7addressERc address char pointer reference _ZNKSt3__19allocatorIcE7addressERKc const_pointer const_reference _ZNSt3__19allocatorIcE8allocateEj unsigned int __uint32_t __size_t size_t _ZNSt3__19allocatorIcE8allocateEjPKv _ZNSt3__19allocatorIcE10deallocateEPcj deallocate _ZNKSt3__19allocatorIcE8max_sizeEv max_size size_type _ZNSt3__19allocatorIcE7destroyEPc destroy _Tp allocator<char> allocator_type _ZNSt3__116allocator_traitsINS_9allocatorIcEEE8allocateERS2_jPKv _ZNSt3__114pointer_traitsIPcE10pointer_toERc pointer_to _Bp __nat _If _Then conditional<false, std::__1::pointer_traits<char *>::__nat, char> type _Ptr pointer_traits<char *> rebind<const void> const_void_pointer _ZNSt3__116allocator_traitsINS_9allocatorIcEEE10deallocateERS2_Pcj _ZNSt3__116allocator_traitsINS_9allocatorIcEEE8max_sizeERKS2_ _ZNSt3__116allocator_traitsINS_9allocatorIcEEE37select_on_container_copy_constructionERKS2_ select_on_container_copy_construction _ZNSt3__116allocator_traitsINS_9allocatorIcEEE10__allocateERS2_jPKvNS_17integral_constantIbLb1EEE __allocate value _ZNKSt3__117integral_constantIbLb1EEcvbEv operator bool value_type _ZNKSt3__117integral_constantIbLb1EEclEv operator() __v integral_constant<bool, true> true_type _ZNSt3__116allocator_traitsINS_9allocatorIcEEE10__allocateERS2_jPKvNS_17integral_constantIbLb0EEE _ZNKSt3__117integral_constantIbLb0EEcvbEv _ZNKSt3__117integral_constantIbLb0EEclEv integral_constant<bool, false> false_type _ZNSt3__116allocator_traitsINS_9allocatorIcEEE10__max_sizeENS_17integral_constantIbLb1EEERKS2_ __max_size _ZNSt3__116allocator_traitsINS_9allocatorIcEEE10__max_sizeENS_17integral_constantIbLb0EEERKS2_ _ZNSt3__116allocator_traitsINS_9allocatorIcEEE39__select_on_container_copy_constructionENS_17integral_constantIbLb1EEERKS2_ __select_on_container_copy_construction _ZNSt3__116allocator_traitsINS_9allocatorIcEEE39__select_on_container_copy_constructionENS_17integral_constantIbLb0EEERKS2_ _Alloc allocator_traits<std::__1::allocator<char> > __long_mask __r_ __value_ __l __cap_ __size_ __data_ __long __s unsigned char __lx __ARRAY_SIZE_TYPE__ __short __r __words __raw __rep __compressed_pair_elem __default_init_tag __value_init_tag _ZNSt3__122__compressed_pair_elemINS_12basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE5__repELi0ELb0EE5__getEv __get _ZNKSt3__122__compressed_pair_elemINS_12basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE5__repELi0ELb0EE5__getEv int _Idx _CanBeEmptyBase __compressed_pair_elem<std::__1::basic_string<char, std::__1::char_traits<char>, std::__1::allocator<char> >::__rep, 0, false> _ZNSt3__122__compressed_pair_elemINS_9allocatorIcEELi1ELb1EE5__getEv _ZNKSt3__122__compressed_pair_elemINS_9allocatorIcEELi1ELb1EE5__getEv __compressed_pair_elem<std::__1::allocator<char>, 1, true> _ZNSt3__117__compressed_pairINS_12basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE5__repES5_E5firstEv first _ZNKSt3__117__compressed_pairINS_12basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE5__repES5_E5firstEv _ZNSt3__117__compressed_pairINS_12basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE5__repES5_E6secondEv second _ZNKSt3__117__compressed_pairINS_12basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE5__repES5_E6secondEv _ZNSt3__117__compressed_pairINS_12basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE5__repES5_E4swapERS8_ swap _T1 _T2 __compressed_pair<std::__1::basic_string<char, std::__1::char_traits<char>, std::__1::allocator<char> >::__rep, std::__1::allocator<char> > npos basic_string __begin_ initializer_list _ZNKSt16initializer_listIcE4sizeEv size _ZNKSt16initializer_listIcE5beginEv begin _ZNKSt16initializer_listIcE3endEv end _Ep initializer_list<char> ~basic_string _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEEcvNS_17basic_string_viewIcS2_EEEv operator basic_string_view __data __size basic_string_view _ZNSt3__117basic_string_viewIcNS_11char_traitsIcEEEaSERKS3_ operator= _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE5beginEv const_iterator _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE3endEv _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE6cbeginEv cbegin _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE4cendEv cend _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE6rbeginEv rbegin reverse_iterator<const char *> const_reverse_iterator _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE4rendEv rend _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE7crbeginEv crbegin _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE5crendEv crend _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE4sizeEv _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE6lengthEv length _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE8max_sizeEv _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE5emptyEv empty _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEEixEj operator[] _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE2atEj at _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE5frontEv front _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE4backEv back _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE4dataEv data _ZNSt3__117basic_string_viewIcNS_11char_traitsIcEEE13remove_prefixEj remove_prefix _ZNSt3__117basic_string_viewIcNS_11char_traitsIcEEE13remove_suffixEj remove_suffix _ZNSt3__117basic_string_viewIcNS_11char_traitsIcEEE4swapERS3_ _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE4copyEPcjj copy _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE6substrEjj substr _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE7compareES3_ compare _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE7compareEjjS3_ _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE7compareEjjS3_jj _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE7compareEPKc _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE7compareEjjPKc _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE7compareEjjPKcj _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE4findES3_j find _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE4findEcj _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE4findEPKcjj _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE4findEPKcj _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE5rfindES3_j rfind _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE5rfindEcj _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE5rfindEPKcjj _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE5rfindEPKcj _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE13find_first_ofES3_j find_first_of _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE13find_first_ofEcj _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE13find_first_ofEPKcjj _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE13find_first_ofEPKcj _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE12find_last_ofES3_j find_last_of _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE12find_last_ofEcj _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE12find_last_ofEPKcjj _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE12find_last_ofEPKcj _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE17find_first_not_ofES3_j find_first_not_of _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE17find_first_not_ofEcj _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE17find_first_not_ofEPKcjj _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE17find_first_not_ofEPKcj _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE16find_last_not_ofES3_j find_last_not_of _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE16find_last_not_ofEcj _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE16find_last_not_ofEPKcjj _ZNKSt3__117basic_string_viewIcNS_11char_traitsIcEEE16find_last_not_ofEPKcj _CharT _ZNSt3__111char_traitsIcE6assignERcRKc assign char_type _ZNSt3__111char_traitsIcE2eqEcc eq _ZNSt3__111char_traitsIcE2ltEcc lt _ZNSt3__111char_traitsIcE7compareEPKcS3_j _ZNSt3__111char_traitsIcE6lengthEPKc _ZNSt3__111char_traitsIcE4findEPKcjRS2_ _ZNSt3__111char_traitsIcE4moveEPcPKcj move _ZNSt3__111char_traitsIcE4copyEPcPKcj _ZNSt3__111char_traitsIcE6assignEPcjc _ZNSt3__111char_traitsIcE7not_eofEi not_eof int_type _ZNSt3__111char_traitsIcE12to_char_typeEi to_char_type _ZNSt3__111char_traitsIcE11to_int_typeEc to_int_type _ZNSt3__111char_traitsIcE11eq_int_typeEii eq_int_type _ZNSt3__111char_traitsIcE3eofEv eof char_traits<char> _Traits basic_string_view<char, std::__1::char_traits<char> > __self_view _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEEaSERKS5_ _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEEaSEOS5_ _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEEaSESt16initializer_listIcE _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEEaSEPKc _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEEaSEc _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE5beginEv __wrap_iter<char *> iterator _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE5beginEv __wrap_iter<const char *> _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE3endEv _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE3endEv _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6rbeginEv reverse_iterator<std::__1::__wrap_iter<char *> > reverse_iterator _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6rbeginEv reverse_iterator<std::__1::__wrap_iter<const char *> > _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE4rendEv _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE4rendEv _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6cbeginEv _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE4cendEv _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE7crbeginEv _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE5crendEv _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE4sizeEv _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6lengthEv _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE8max_sizeEv _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE8capacityEv capacity _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6resizeEjc resize _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6resizeEj _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE7reserveEj reserve _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE21__resize_default_initEj __resize_default_init _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE7reserveEv _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE13shrink_to_fitEv shrink_to_fit _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE5clearEv clear _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE5emptyEv _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEEixEj _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEEixEj _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE2atEj _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE2atEj _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEEpLERKS5_ operator+= _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEEpLEPKc _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEEpLEc _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEEpLESt16initializer_listIcE _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6appendERKS5_ append _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6appendERKS5_jj _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6appendEPKcj _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6appendEPKc _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6appendEjc _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE21__append_default_initEj __append_default_init _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6appendESt16initializer_listIcE _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE9push_backEc push_back _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE8pop_backEv pop_back _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE5frontEv _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE5frontEv _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE4backEv _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE4backEv _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6assignERKS5_ _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6assignEOS5_ _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6assignERKS5_jj _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6assignEPKcj _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6assignEPKc _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6assignEjc _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6assignESt16initializer_listIcE _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6insertEjRKS5_ insert _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6insertEjRKS5_jj _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6insertEjPKcj _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6insertEjPKc _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6insertEjjc _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6insertENS_11__wrap_iterIPKcEEc _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6insertENS_11__wrap_iterIPKcEEjc _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6insertENS_11__wrap_iterIPKcEESt16initializer_listIcE _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE5eraseEjj erase _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE5eraseENS_11__wrap_iterIPKcEE _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE5eraseENS_11__wrap_iterIPKcEES9_ _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE7replaceEjjRKS5_ replace _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE7replaceEjjRKS5_jj _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE7replaceEjjPKcj _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE7replaceEjjPKc _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE7replaceEjjjc _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE7replaceENS_11__wrap_iterIPKcEES9_RKS5_ _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE7replaceENS_11__wrap_iterIPKcEES9_S8_j _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE7replaceENS_11__wrap_iterIPKcEES9_S8_ _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE7replaceENS_11__wrap_iterIPKcEES9_jc _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE7replaceENS_11__wrap_iterIPKcEES9_St16initializer_listIcE _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE4copyEPcjj _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6substrEjj _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE4swapERS5_ _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE5c_strEv c_str _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE4dataEv _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE13get_allocatorEv get_allocator _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE4findERKS5_j _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE4findEPKcjj _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE4findEPKcj _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE4findEcj _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE5rfindERKS5_j _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE5rfindEPKcjj _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE5rfindEPKcj _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE5rfindEcj _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE13find_first_ofERKS5_j _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE13find_first_ofEPKcjj _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE13find_first_ofEPKcj _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE13find_first_ofEcj _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE12find_last_ofERKS5_j _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE12find_last_ofEPKcjj _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE12find_last_ofEPKcj _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE12find_last_ofEcj _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE17find_first_not_ofERKS5_j _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE17find_first_not_ofEPKcjj _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE17find_first_not_ofEPKcj _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE17find_first_not_ofEcj _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE16find_last_not_ofERKS5_j _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE16find_last_not_ofEPKcjj _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE16find_last_not_ofEPKcj _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE16find_last_not_ofEcj _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE7compareERKS5_ _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE7compareEjjRKS5_ _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE7compareEjjRKS5_jj _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE7compareEPKc _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE7compareEjjPKc _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE7compareEjjPKcj _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE12__invariantsEv __invariants _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE18__clear_and_shrinkEv __clear_and_shrink _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE9__is_longEv __is_long _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE7__allocEv __alloc _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE7__allocEv _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE16__set_short_sizeEj __set_short_size _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE16__get_short_sizeEv __get_short_size _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE15__set_long_sizeEj __set_long_size _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE15__get_long_sizeEv __get_long_size _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE10__set_sizeEj __set_size _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE14__set_long_capEj __set_long_cap _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE14__get_long_capEv __get_long_cap _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE18__set_long_pointerEPc __set_long_pointer _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE18__get_long_pointerEv __get_long_pointer _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE18__get_long_pointerEv _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE19__get_short_pointerEv __get_short_pointer _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE19__get_short_pointerEv _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE13__get_pointerEv __get_pointer _ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE13__get_pointerEv _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6__zeroEv __zero _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE11__recommendEj __recommend _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6__initEPKcjj __init _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6__initEPKcj _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6__initEjc _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE25__init_copy_ctor_externalEPKcj __init_copy_ctor_external _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE9__grow_byEjjjjjj __grow_by _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE21__grow_by_and_replaceEjjjjjjPKc __grow_by_and_replace _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE14__erase_to_endEj __erase_to_end _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE26__erase_external_with_moveEjj __erase_external_with_move _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE19__copy_assign_allocERKS5_ __copy_assign_alloc _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE19__copy_assign_allocERKS5_NS_17integral_constantIbLb1EEE _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE19__copy_assign_allocERKS5_NS_17integral_constantIbLb0EEE _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE13__move_assignERS5_NS_17integral_constantIbLb0EEE __move_assign _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE13__move_assignERS5_NS_17integral_constantIbLb1EEE _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE19__move_assign_allocERS5_ __move_assign_alloc _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE19__move_assign_allocERS5_NS_17integral_constantIbLb1EEE _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE19__move_assign_allocERS5_NS_17integral_constantIbLb0EEE _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE17__assign_externalEPKc __assign_external _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE17__assign_externalEPKcj _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE14__assign_shortEPKcj __assign_short _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE26__invalidate_all_iteratorsEv __invalidate_all_iterators _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE27__invalidate_iterators_pastEj __invalidate_iterators_past _Allocator basic_string<char, std::__1::char_traits<char>, std::__1::allocator<char> > string pl_state PMCLOG_OK PMCLOG_EOF PMCLOG_REQUIRE_DATA PMCLOG_ERROR pmclog_state pl_offset long long int __int64_t __off_t off_t pl_count pl_ts tv_sec __int32_t __time_t time_t tv_nsec long int timespec pl_type PMCLOG_TYPE_CLOSELOG PMCLOG_TYPE_DROPNOTIFY PMCLOG_TYPE_INITIALIZE PMCLOG_TYPE_PMCALLOCATE PMCLOG_TYPE_PMCATTACH PMCLOG_TYPE_PMCDETACH PMCLOG_TYPE_PROCCSW PMCLOG_TYPE_PROCEXEC PMCLOG_TYPE_PROCEXIT PMCLOG_TYPE_PROCFORK PMCLOG_TYPE_SYSEXIT PMCLOG_TYPE_USERDATA PMCLOG_TYPE_MAP_IN PMCLOG_TYPE_MAP_OUT PMCLOG_TYPE_CALLCHAIN PMCLOG_TYPE_PMCALLOCATEDYN PMCLOG_TYPE_THR_CREATE PMCLOG_TYPE_THR_EXIT PMCLOG_TYPE_PROC_CREATE pmclog_type pl_data pl_len pl_u pl_cc pl_pid uint32_t pl_tid pl_pmcid pl_cpuflags pl_cpuflags2 pl_npc pl_pc u_int uintfptr_t pmclog_ev_callchain pl_cl pmclog_ev_closelog pl_dn pmclog_ev_dropnotify pl_i pl_version pl_arch pl_tsc_freq long long unsigned int __uint64_t uint64_t pl_cpuid pmclog_ev_initialize pl_mi __pid_t pid_t pl_start pl_pathname pmclog_ev_map_in pl_mo pl_end pmclog_ev_map_out pl_a pl_evname pl_rate pl_event pl_flags pmc_id_t pmclog_ev_pmcallocate pl_ad pmclog_ev_pmcallocatedyn pl_t pmclog_ev_pmcattach pl_d pmclog_ev_pmcdetach pl_c pl_value pmc_value_t pmclog_ev_proccsw pl_pcomm pmclog_ev_proccreate pl_x pl_entryaddr pmclog_ev_procexec pl_e pmclog_ev_procexit pl_f pl_oldpid pl_newpid pmclog_ev_procfork pl_se pmclog_ev_sysexit pl_tc pl_tdname pmclog_ev_threadcreate pl_te pmclog_ev_threadexit pl_userdata pmclog_ev_userdata pmclog_ev jconv _ZL11jsonconvert typenames _ZL9typenames __n_words __min_cap __alignment __uintmax_t uintmax_t _vptr$exception __vtbl_ptr_type exception ~exception _ZNKSt9exception4whatEv what __imp_ _ZNKSt3__118__libcpp_refstring15__uses_refcountEv __uses_refcount __libcpp_refstring _ZNSt3__118__libcpp_refstringaSERKS0_ ~__libcpp_refstring _ZNKSt3__118__libcpp_refstring5c_strEv logic_error _ZNSt11logic_erroraSERKS_ ~logic_error _ZNKSt11logic_error4whatEv length_error ~length_error __intmax_t intmax_t decltype(nullptr) nullptr_t __ptrdiff_t ptrdiff_t __max_align1 __max_align2 long double __max_align_t max_align_t memcpy memmove strcpy strncpy strcat strncat memcmp strcmp strncmp strcoll strxfrm _Z6memchrUa9enable_ifIXLb1EEEPvij memchr _Z6strchrUa9enable_ifIXLb1EEEPci strchr strcspn _Z7strpbrkUa9enable_ifIXLb1EEEPcPKc strpbrk _Z7strrchrUa9enable_ifIXLb1EEEPci strrchr strspn _Z6strstrUa9enable_ifIXLb1EEEPcPKc strstr strtok memset strerror strlen signed char __int8_t int8_t short __int16_t int16_t int32_t int64_t __uint8_t uint8_t unsigned short __uint16_t uint16_t __int_least8_t int_least8_t __int_least16_t int_least16_t __int_least32_t int_least32_t __int_least64_t int_least64_t __uint_least8_t uint_least8_t __uint_least16_t uint_least16_t __uint_least32_t uint_least32_t __uint_least64_t uint_least64_t __int_fast8_t int_fast8_t __int_fast16_t int_fast16_t __int_fast32_t int_fast32_t __int_fast64_t int_fast64_t __uint_fast8_t uint_fast8_t __uint_fast16_t uint_fast16_t __uint_fast32_t uint_fast32_t __uint_fast64_t uint_fast64_t __intptr_t intptr_t __uintptr_t uintptr_t quot rem div_t ldiv_t lldiv_t atof double atoi atol atoll strtod strtof float strtold strtol strtoll strtoul long unsigned int strtoull rand srand calloc free malloc realloc abort atexit exit _Exit getenv system bsearch qsort _Z3abse abs labs llabs _Z3divxx div ldiv lldiv mblen mbtowc wchar_t wctomb mbstowcs wcstombs at_quick_exit quick_exit __clock_t clock_t tm_sec tm_min tm_hour tm_mday tm_mon tm_year tm_wday tm_yday tm_isdst tm_gmtoff tm_zone tm clock difftime mktime time asctime ctime gmtime localtime strftime chrono literals chrono_literals _p _r _w _flags _file _bf _base _size __sbuf _lbfsize _cookie _close _read _seek fpos_t _write _ub _up _ur _ubuf _nbuf _lb _blksize _offset _fl_mutex pthread_mutex _fl_owner pthread _fl_count _orientation _mbstate __mbstate8 _mbstateL __mbstate_t _flags2 __sFILE FILE fclose fflush setbuf setvbuf fprintf fscanf snprintf sprintf sscanf vfprintf __builtin_va_list __va_list vfscanf vsscanf vsnprintf vsprintf fgetc fgets fputc fputs getc putc ungetc fread fwrite fgetpos fseek fsetpos ftell rewind clearerr feof ferror perror fopen freopen remove rename tmpfile tmpnam getchar scanf vscanf printf putchar puts vprintf isalnum isalpha isblank iscntrl isdigit isgraph islower isprint ispunct isspace isupper isxdigit tolower toupper __ct_rune_t __wint_t wint_t wctrans_t wctype_t iswalnum iswalpha iswblank iswcntrl iswdigit iswgraph iswlower iswprint iswpunct iswspace iswupper iswxdigit iswctype wctype towlower towupper towctrans wctrans mbstate_t fwprintf fwscanf swprintf vfwprintf vswprintf swscanf vfwscanf vswscanf fgetwc fgetws fputwc fputws fwide getwc putwc ungetwc wcstod wcstof wcstold wcstol wcstoll wcstoul wcstoull wcscpy wcsncpy wcscat wcsncat wcscmp wcscoll wcsncmp wcsxfrm _Z6wcschrUa9enable_ifIXLb1EEEPww wcschr _Z7wcspbrkUa9enable_ifIXLb1EEEPwPKw wcspbrk _Z7wcsrchrUa9enable_ifIXLb1EEEPww wcsrchr _Z6wcsstrUa9enable_ifIXLb1EEEPwPKw wcsstr _Z7wmemchrUa9enable_ifIXLb1EEEPwwj wmemchr wcscspn wcslen wcsspn wcstok wmemcmp wmemcpy wmemmove wmemset wcsftime btowc wctob mbsinit mbrlen mbrtowc wcrtomb mbsrtowcs wcsrtombs getwchar vwscanf wscanf putwchar vwprintf wprintf errx this __a __i _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEEC2Ev _ZL10startentryP9pmclog_ev startentry ev eventbuf basic_string<nullptr_t> _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEEC2IDnEEPKc __sz __p __cap __s1 __s2 __n __guess _ZNSt3__117__libcpp_allocateEjj __libcpp_allocate __align __c1 __c2 __str _ZNSt3__117_DeallocateCaller33__do_deallocate_handle_size_alignEPvjj __do_deallocate_handle_size_align _ZNSt3__117_DeallocateCaller28__do_deallocate_handle_alignEPvj __do_deallocate_handle_align _ZNSt3__117_DeallocateCaller27__do_deallocate_handle_sizeEPvj __do_deallocate_handle_size _ZNSt3__117_DeallocateCaller9__do_callEPv __do_call _DeallocateCaller __ptr _ZNSt3__119__libcpp_deallocateEPvjj __libcpp_deallocate _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEED2Ev _Z13event_to_jsonP9pmclog_ev event_to_json _ZL12stub_to_jsonP9pmclog_ev stub_to_json _ZL18initialize_to_jsonP9pmclog_ev initialize_to_json _ZL19pmcallocate_to_jsonP9pmclog_ev pmcallocate_to_json _ZL17pmcattach_to_jsonP9pmclog_ev pmcattach_to_json _ZL17pmcdetach_to_jsonP9pmclog_ev pmcdetach_to_json _ZL15proccsw_to_jsonP9pmclog_ev proccsw_to_json _ZL16procexec_to_jsonP9pmclog_ev procexec_to_json _ZL16procexit_to_jsonP9pmclog_ev procexit_to_json _ZL16procfork_to_jsonP9pmclog_ev procfork_to_json _ZL15sysexit_to_jsonP9pmclog_ev sysexit_to_json _ZL16userdata_to_jsonP9pmclog_ev userdata_to_json _ZL14map_in_to_jsonP9pmclog_ev map_in_to_json _ZL15map_out_to_jsonP9pmclog_ev map_out_to_json _ZL17callchain_to_jsonP9pmclog_ev callchain_to_json _ZL22pmcallocatedyn_to_jsonP9pmclog_ev pmcallocatedyn_to_json _ZL20threadcreate_to_jsonP9pmclog_ev threadcreate_to_json _ZL18threadexit_to_jsonP9pmclog_ev threadexit_to_json _ZL18proccreate_to_jsonP9pmclog_ev proccreate_to_json startent result i FreeBSD clang version 11.0.1 (git@github.com:llvm/llvm-project.git llvmorg-11.0.1-0-g43ff75f2c3fe) zR | $ D AB
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Y * Y A \ N Y e \ r Y Y Y Ň Y Y Y ^ " \ + \ 8 Y E \ S ^ \ \ e \ n \ w \ Y Y ^ \ ˈ Y ؈ \ Y \ Y \ $ Y 1 \ : \ J Y W \ l Y y \ \ Y ^ \ É \ ̉ \ ډ Y Y \ Y - Y M Y m Y \ Y \ Y Њ Y Y Y # Y C Y c Y z \ Y \ Y Ƌ Y Y A B % 4 ) Y C Y d Y m \ } ^ \ ^ \ \ Y Ռ ^ ތ \ \ \ \ Y ) Y A ^ F \ S Y ` \ n Y \ Y \ Y \ \ ҍ Y Y \ Y > ^ G \ P \ Y \ g Y Y \ \ Y \ \ ˎ Y Y Y ' Y > \ K Y b \ o Y Y Y Y ݏ Y Y ^ \ ( \ 5 Y B \ P ^ Y \ b \ k \ t \ Y Y ^ \ Ȑ Y Ր \ Y \ Y \ ! Y . \ 7 \ G Y T \ i Y v \ \ Y ^ \ \ ɑ \ ב Y Y \ Y * Y J Y j Y \ Y \ Y ͒ Y Y Y Y @ Y ` Y w \ Y \ Y Ó Y ݓ Y C D % 4 & Y @ Y a Y j \ z ^ \ ^ \ \ Y Ҕ ^ ۔ \ \ \ \ Y & Y > ^ C \ P Y ] \ k Y } \ Y \ Y \ \ ϕ Y Y \ Y ; ^ D \ M \ V \ d Y Y \ \ Y \ \ Ȗ Y Y Y $ Y ; \ H Y _ \ l Y Y Y Y ڗ Y Y ^ ! \ . Y ; \ I ^ W \ ` \ i \ v Y \ Y ^ \ Y ̘ \ ژ Y \ Y \ Y % \ . \ > Y K \ ` Y m \ v \ Y ^ \ \ \ Ι Y Y \ Y ! Y A Y a Y x \ Y \ Y Ě Y Y Y Y 7 Y W Y n \ { Y \ Y Y ԛ Y ޛ E F % 4 Y 7 Y X Y a \ q ^ y \ ^ \ \ Y ɜ ^ Ҝ \ ۜ \ \ \ Y Y 5 ^ : \ G Y T \ b Y t \ Y \ Y \ \ Ɲ Y Y \ Y 2 ^ ; \ D \ M \ [ Y z Y \ \ Y \ \ Y ۞ Y Y Y 2 \ ? Y V \ c Y ~ Y Y Y џ Y Y ^ \ % Y 2 \ @ ^ N \ W \ ` \ m Y z \ Y ^ \ Y à \ Ѡ Y \ Y \ Y \ % \ 5 Y B \ W Y d \ m \ { Y ^ \ \ \ š Y Y \ Y Y 8 Y X Y o \ | Y \ Y Y آ Y Y Y . Y N Y e \ r Y \ Y Y ˣ Y գ G ٣ H % 4 Y . Y O Y X \ h ^ p \ ^ \ \ Y ^ ɤ \ Ҥ \ ۤ \ \ Y Y , ^ 1 \ > Y K \ Y Y k \ x Y \ Y \ \ Y Y \ Y ) ^ 2 \ ; \ D \ R Y q Y } \ \ Y \ \ Y Ҧ Y Y Y ) \ 6 Y M \ Z Y u Y Y Y ȧ Y Y ^ \ Y ) \ 7 ^ E \ N \ W \ d Y q \ Y ^ \ Y \ Ȩ Y ڨ \ Y \ Y \ \ , Y 9 \ N Y [ \ d \ r Y ^ \ \ \ Y ک Y \ Y Y / Y O Y f \ s Y \ Y Y Ϫ Y Y Y % Y E Y \ \ i Y \ Y Y « Y ̫ I Ы J ޫ % 4 Y % Y F Y O \ _ ^ g \ } ^ \ \ Y ^ \ ɬ \ Ҭ \ ۬ \ Y Y # ^ ( \ 5 Y B \ P Y b \ o Y \ Y \ \ Y Y \ Y ^ ) \ 2 \ ; \ I Y h Y t \ } \ Y \ \ Y ɮ Y Y Y \ - Y D \ Q Y l Y Y Y Y گ Y ^ \
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\ \ \ ) Y 6 \ K Y ` ^ e \ r Y \ Y \ Y \ Y \ \ Y \ Y \ ) \ 7 Y X ^ a \ j \ s \ Y Y \ Y Y Y Y , \ 9 Y P \ ] Y x Y Y Y Y Y Y # \ 0 Y G \ T Y o Y Y W X % 4 Y Y Y \ + ^ 4 \ J ^ R \ [ \ h Y ^ \ \ \ \ Y Y ^ \ Y \ Y / \ < Y N \ [ Y h \ q \ Y Y \ Y ^ \ \ \ Y 5 Y B \ K \ X Y e \ n \ { Y Y Y Y \ Y \ Y : Y X Y s Y Y Y ^ \ \ Y \ ^ \ \ \ & \ 3 Y S Y h ^ m \ z Y \ Y \ Y \ Y \ \ Y \ Y ( \ 1 \ ? Y ` ^ i \ r \ { \ Y Y \ Y Y Y Y 4 \ A Y X \ e Y Y Y Y Y Y Y + \ 8 Y O \ \ Y w Y Y S g h Y q Z Y Z Y % Z x Y Z Y Z 0 Y 9 Z Y Z Y Z D Y M Z Y Z Y Z X Y a Z Y Z Y Z Y Z Y Z \ Y e Z Y Z Y memcpy errx .debug_abbrev _ZL15proccsw_to_jsonP9pmclog_ev _ZL15map_out_to_jsonP9pmclog_ev _Z13event_to_jsonP9pmclog_ev _ZL15sysexit_to_jsonP9pmclog_ev _ZL18threadexit_to_jsonP9pmclog_ev _ZL16procexit_to_jsonP9pmclog_ev _ZL22pmcallocatedyn_to_jsonP9pmclog_ev _ZL17callchain_to_jsonP9pmclog_ev _ZL14map_in_to_jsonP9pmclog_ev _ZL16procfork_to_jsonP9pmclog_ev _ZL17pmcattach_to_jsonP9pmclog_ev _ZL17pmcdetach_to_jsonP9pmclog_ev _ZL18initialize_to_jsonP9pmclog_ev _ZL20threadcreate_to_jsonP9pmclog_ev _ZL18proccreate_to_jsonP9pmclog_ev _ZL19pmcallocate_to_jsonP9pmclog_ev _ZL16procexec_to_jsonP9pmclog_ev _ZL12stub_to_jsonP9pmclog_ev _ZL16userdata_to_jsonP9pmclog_ev _ZdlPv _ZNKSt3__121__basic_string_commonILb1EE20__throw_length_errorEv .rel.text _ZL11jsonconvert .mcount .comment _ZL9typenames .debug_ranges .debug_str .L.str .rel.debug_info strlen __stack_chk_fail .note.GNU-stack _Znwj _ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6appendEPKcj .llvm_addrsig snprintf .rel.debug_line _Unwind_Resume .rel.eh_frame .gcc_except_table __stack_chk_guard .debug_loc libpmc_json.cc .strtab .symtab .rel.rodata GCC_except_table9 .L.str.39 .L.str.29 .L.str.19 .L.str.9 GCC_except_table8 .L.str.38 .L.str.28 GCC_except_table18 .L.str.18 .L.str.8 GCC_except_table7 .L.str.37 .L.str.27 GCC_except_table17 .L.str.17 .L.str.7 GCC_except_table6 .L.str.36 .L.str.26 GCC_except_table16 .L.str.16 .L.str.6 GCC_except_table5 .L.str.35 .L.str.25 GCC_except_table15 .L.str.15 .L.str.5 GCC_except_table4 .L.str.34 .L.str.24 GCC_except_table14 .L.str.14 .L.str.4 GCC_except_table3 .L.str.33 GCC_except_table13 .L.str.13 .L.str.3 GCC_except_table2 .L.str.42 .L.str.32 .L.str.22 GCC_except_table12 .L.str.12 .L.str.2 GCC_except_table1 .L.str.41 .L.str.31 .L.str.21 GCC_except_table11 .L.str.11 .rodata.str1.1 __gxx_personality_v0 .L.str.40 .L.str.30 .L.str.20 GCC_except_table10 .L.str.10 D Y @ j) 4 p ) X - T @ 2 (. * 3 ^
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ELF 8/ 4 ( GenuineIntel-6-56 v5 core GenuineIntel-6-3D v17 GenuineIntel-6-47 GenuineIntel-6-4F v10 GenuineIntel-6-1C v4 GenuineIntel-6-26 GenuineIntel-6-27 GenuineIntel-6-36 GenuineIntel-6-35 GenuineIntel-6-5C v8 GenuineIntel-6-5F GenuineIntel-6-7A v1 GenuineIntel-6-3C v24 GenuineIntel-6-45 GenuineIntel-6-46 GenuineIntel-6-3F GenuineIntel-6-3A v18 GenuineIntel-6-3E v19 GenuineIntel-6-2D v20 GenuineIntel-6-57 v9 GenuineIntel-6-85 GenuineIntel-6-1E v2 GenuineIntel-6-1F GenuineIntel-6-1A GenuineIntel-6-2E GenuineIntel-6-[4589]E GenuineIntel-6-37 v13 GenuineIntel-6-4D GenuineIntel-6-4C GenuineIntel-6-2A v15 GenuineIntel-6-2C GenuineIntel-6-25 GenuineIntel-6-2F GenuineIntel-6-55-[01234] GenuineIntel-6-55-[56789ABCDEF] GenuineIntel-6-7D GenuineIntel-6-7E GenuineIntel-6-86 AuthenticAMD-23-[012][0-9A-F] AuthenticAMD-23-[[:xdigit:]]+ HygonGenuine-24-00 Instructions Per Cycle (per logical thread) bdwde metrics inst_retired.any / cpu_clk_unhalted.thread IPC TopDownL1 Uops Per Instruction uops_retired.retire_slots / inst_retired.any UPI Pipeline Rough Estimation of fraction of fetched lines bytes that were likely consumed by program instructions min( 1 , idq.mite_uops / ( uops_retired.retire_slots / inst_retired.any * 16 * ( icache.hit + icache.misses ) / 4.0 ) ) IFetch_Line_Utilization Frontend Fraction of Uops delivered by the DSB (aka Decoded Icache; or Uop Cache) idq.dsb_uops / ( idq.dsb_uops + lsd.uops + idq.mite_uops + idq.ms_uops ) DSB_Coverage DSB; Frontend_Bandwidth Cycles Per Instruction (threaded) 1 / inst_retired.any / cycles CPI Pipeline;Summary Per-thread actual clocks when the logical processor is active. This is called 'Clockticks' in VTune cpu_clk_unhalted.thread CLKS Summary Total issue-pipeline slots 4*( cpu_clk_unhalted.thread_any / 2 ) if #smt_on else cycles SLOTS Total number of retired Instructions inst_retired.any Instructions Instructions Per Cycle (per physical core) inst_retired.any / ( cpu_clk_unhalted.thread_any / 2 ) if #smt_on else cycles CoreIPC SMT Instruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed) uops_executed.thread / ( cpu@uops_executed.core\,cmask\=1@ / 2) if #smt_on else uops_executed.cycles_ge_1_uop_exec ILP Pipeline;Ports_Utilization Average Branch Address Clear Cost (fraction of cycles) 2* ( rs_events.empty_cycles - icache.ifdata_stall - ( 14 * itlb_misses.stlb_hit + cpu@itlb_misses.walk_duration\,cmask\=1@ + 7* itlb_misses.walk_completed ) ) / rs_events.empty_end BAClear_Cost Unknown_Branches Core actual clocks when any thread is active on the physical core ( cpu_clk_unhalted.thread_any / 2 ) if #smt_on else cpu_clk_unhalted.thread CORE_CLKS Actual Average Latency for L1 data-cache miss demand loads l1d_pend_miss.pending / ( mem_load_uops_retired.l1_miss + mem_load_uops_retired.hit_lfb ) Load_Miss_Real_Latency Memory_Bound;Memory_Lat Memory-Level-Parallelism (average number of L1 miss demand load when there is at least 1 such miss) l1d_pend_miss.pending / ( cpu@l1d_pend_miss.pending_cycles\,any\=1@ / 2) if #smt_on else l1d_pend_miss.pending_cycles MLP Memory_Bound;Memory_BW Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses ( cpu@itlb_misses.walk_duration\,cmask\=1@ + cpu@dtlb_load_misses.walk_duration\,cmask\=1@ + cpu@dtlb_store_misses.walk_duration\,cmask\=1@ + 7*(dtlb_store_misses.walk_completed+dtlb_load_misses.walk_completed+itlb_misses.walk_completed)) / ( cpu_clk_unhalted.thread_any / 2 ) if #smt_on else cycles Page_Walks_Utilization TLB Average CPU Utilization cpu_clk_unhalted.ref_tsc / msr@tsc@ CPU_Utilization Giga Floating Point Operations Per Second ( 1*( fp_arith_inst_retired.scalar_single + fp_arith_inst_retired.scalar_double ) + 2* fp_arith_inst_retired.128b_packed_double + 4*( fp_arith_inst_retired.128b_packed_single + fp_arith_inst_retired.256b_packed_double ) + 8* fp_arith_inst_retired.256b_packed_single ) / 1000000000 / duration_time GFLOPs FLOPS;Summary Average Frequency Utilization relative nominal frequency cpu_clk_unhalted.thread / cpu_clk_unhalted.ref_tsc Turbo_Utilization Power Fraction of cycles where both hardware threads were active 1 - cpu_clk_thread_unhalted.one_thread_active / ( cpu_clk_thread_unhalted.ref_xclk_any / 2 ) if #smt_on else 0 SMT_2T_Utilization SMT;Summary Fraction of cycles spent in Kernel mode cpu_clk_unhalted.ref_tsc:k / cpu_clk_unhalted.ref_tsc Kernel_Utilization C3 residency percent per core (cstate_core@c3\-residency@ / msr@tsc@) * 100 C3_Core_Residency C6 residency percent per core (cstate_core@c6\-residency@ / msr@tsc@) * 100 C6_Core_Residency C7 residency percent per core (cstate_core@c7\-residency@ / msr@tsc@) * 100 C7_Core_Residency C2 residency percent per package (cstate_pkg@c2\-residency@ / msr@tsc@) * 100 C2_Pkg_Residency C3 residency percent per package (cstate_pkg@c3\-residency@ / msr@tsc@) * 100 C3_Pkg_Residency C6 residency percent per package (cstate_pkg@c6\-residency@ / msr@tsc@) * 100 C6_Pkg_Residency C7 residency percent per package (cstate_pkg@c7\-residency@ / msr@tsc@) * 100 C7_Pkg_Residency l2_rqsts.demand_data_rd_miss umask=0x21,period=200003,event=0x24 Demand Data Read miss L2, no rejects cache This event counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted l2_rqsts.rfo_miss umask=0x22,period=200003,event=0x24 RFO requests that miss L2 cache l2_rqsts.code_rd_miss umask=0x24,period=200003,event=0x24 L2 cache misses when fetching instructions l2_rqsts.all_demand_miss umask=0x27,period=200003,event=0x24 Demand requests that miss L2 cache l2_rqsts.l2_pf_miss umask=0x30,period=200003,event=0x24 L2 prefetch requests that miss L2 cache This event counts the number of requests from the L2 hardware prefetchers that miss L2 cache l2_rqsts.miss umask=0x3f,period=200003,event=0x24 All requests that miss L2 cache l2_rqsts.demand_data_rd_hit umask=0x41,period=200003,event=0x24 Demand Data Read requests that hit L2 cache This event counts the number of demand Data Read requests that hit L2 cache. Only not rejected loads are counted l2_rqsts.rfo_hit umask=0x42,period=200003,event=0x24 RFO requests that hit L2 cache l2_rqsts.code_rd_hit umask=0x44,period=200003,event=0x24 L2 cache hits when fetching instructions, code reads l2_rqsts.l2_pf_hit umask=0x50,period=200003,event=0x24 L2 prefetch requests that hit L2 cache This event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types l2_rqsts.all_demand_data_rd umask=0xe1,period=200003,event=0x24 Demand Data Read requests This event counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted l2_rqsts.all_rfo umask=0xe2,period=200003,event=0x24 RFO requests to L2 cache This event counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches l2_rqsts.all_code_rd umask=0xe4,period=200003,event=0x24 L2 code requests This event counts the total number of L2 code requests l2_rqsts.all_demand_references umask=0xe7,period=200003,event=0x24 Demand requests to L2 cache l2_rqsts.all_pf umask=0xf8,period=200003,event=0x24 Requests from L2 hardware prefetchers This event counts the total number of requests from the L2 hardware prefetchers l2_rqsts.references umask=0xff,period=200003,event=0x24 All L2 requests l2_demand_rqsts.wb_hit umask=0x50,period=200003,event=0x27 Not rejected writebacks that hit L2 cache This event counts the number of WB requests that hit L2 cache longest_lat_cache.miss umask=0x41,period=100003,event=0x2e Core-originated cacheable demand requests missed L3 This event counts core-originated cacheable demand requests that miss the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU longest_lat_cache.reference umask=0x4f,period=100003,event=0x2e Core-originated cacheable demand requests that refer to L3 This event counts core-originated cacheable demand requests that refer to the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU l1d_pend_miss.pending umask=0x1,period=2000003,event=0x48 L1D miss oustandings duration in cycles This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch.
Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type l1d_pend_miss.pending_cycles umask=0x1,cmask=1,period=2000003,event=0x48 Cycles with L1D load Misses outstanding This event counts duration of L1D miss outstanding in cycles l1d_pend_miss.pending_cycles_any umask=0x1,any=1,cmask=1,period=2000003,event=0x48 Cycles with L1D load Misses outstanding from any thread on physical core l1d_pend_miss.fb_full umask=0x2,cmask=1,period=2000003,event=0x48 Cycles a demand request was blocked due to Fill Buffers inavailability l1d.replacement umask=0x1,period=2000003,event=0x51 L1D data line replacements This event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace offcore_requests_outstanding.demand_data_rd umask=0x1,period=2000003,event=0x60 Offcore outstanding Demand Data Read transactions in uncore queue Spec update: BDM76 This event counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.
Note: A prefetch promoted to Demand is counted from the promotion point Spec update: BDM76 offcore_requests_outstanding.cycles_with_demand_data_rd umask=0x1,cmask=1,period=2000003,event=0x60 Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore Spec update: BDM76 This event counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation) Spec update: BDM76 offcore_requests_outstanding.demand_data_rd_ge_6 umask=0x1,cmask=6,period=2000003,event=0x60 Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue Spec update: BDM76 offcore_requests_outstanding.demand_code_rd umask=0x2,period=2000003,event=0x60 Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle Spec update: BDM76 This event counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS Spec update: BDM76 offcore_requests_outstanding.demand_rfo umask=0x4,period=2000003,event=0x60 Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore Spec update: BDM76 This event counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS Spec update: BDM76 offcore_requests_outstanding.cycles_with_demand_rfo umask=0x4,cmask=1,period=2000003,event=0x60 Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle Spec update: BDM76 This event counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS Spec update: BDM76 offcore_requests_outstanding.all_data_rd umask=0x8,period=2000003,event=0x60 Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore Spec update: BDM76 This event counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS Spec update: BDM76 offcore_requests_outstanding.cycles_with_data_rd umask=0x8,cmask=1,period=2000003,event=0x60 Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore Spec update: BDM76 This event counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS Spec update: BDM76 lock_cycles.cache_lock_duration umask=0x2,period=2000003,event=0x63 Cycles when L1D is locked This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION) offcore_requests.demand_data_rd umask=0x1,period=100003,event=0xb0 Demand Data Read requests sent to uncore This event counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore offcore_requests.demand_code_rd umask=0x2,period=100003,event=0xb0 Cacheable and noncachaeble code read requests This event counts both cacheable and noncachaeble code read requests offcore_requests.demand_rfo umask=0x4,period=100003,event=0xb0 Demand RFO requests including regular RFOs, locks, ItoM This event counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM offcore_requests.all_data_rd umask=0x8,period=100003,event=0xb0 Demand and prefetch data reads This event counts the demand and prefetch data reads. All Core Data Reads include cacheable Demands and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type offcore_requests_buffer.sq_full umask=0x1,period=2000003,event=0xb2 Offcore requests buffer cannot take more entries for this thread core This event counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.
Note: Writeback pending FIFO has six entries offcore_response umask=0x1,period=100003,event=0xb7 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction mem_uops_retired.stlb_miss_loads umask=0x11,period=100003,event=0xd0 Retired load uops that miss the STLB. (Precise Event - PEBS) Supports address when precise (Precise event) This is a precise version (that is, uses PEBS) of the event that counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault Supports address when precise (Precise event) mem_uops_retired.stlb_miss_stores umask=0x12,period=100003,event=0xd0 Retired store uops that miss the STLB. (Precise Event - PEBS) Supports address when precise (Precise event) This is a precise version (that is, uses PEBS) of the event that counts store uops true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault Supports address when precise (Precise event) mem_uops_retired.lock_loads umask=0x21,period=100007,event=0xd0 Retired load uops with locked access. (Precise Event - PEBS) Supports address when precise. Spec update: BDM35 (Precise event) This is a precise version (that is, uses PEBS) of the event that counts load uops with locked access retired to the architected path Supports address when precise. Spec update: BDM35 (Precise event) mem_uops_retired.split_loads umask=0x41,period=100003,event=0xd0 Retired load uops that split across a cacheline boundary.(Precise Event - PEBS) Supports address when precise (Precise event) This is a precise version (that is, uses PEBS) of the event that counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K) Supports address when precise (Precise event) mem_uops_retired.split_stores umask=0x42,period=100003,event=0xd0 Retired store uops that split across a cacheline boundary. (Precise Event - PEBS) Supports address when precise (Precise event) This is a precise version (that is, uses PEBS) of the event that counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K) Supports address when precise (Precise event) mem_uops_retired.all_loads umask=0x81,period=2000003,event=0xd0 All retired load uops. (Precise Event - PEBS) Supports address when precise (Precise event) This is a precise version (that is, uses PEBS) of the event that counts load uops retired to the architected path with a filter on bits 0 and 1 applied.
Note: This event ?ounts AVX-256bit load/store double-pump memory uops as a single uop at retirement. This event also counts SW prefetches Supports address when precise (Precise event) mem_uops_retired.all_stores umask=0x82,period=2000003,event=0xd0 This is a precise version (that is, uses PEBS) of the event that counts store uops retired to the architected path with a filter on bits 0 and 1 applied.
Note: This event ?ounts AVX-256bit load/store double-pump memory uops as a single uop at retirement Supports address when precise (Precise event) mem_load_uops_retired.l1_hit umask=0x1,period=2000003,event=0xd1 Retired load uops with L1 cache hits as data sources. (Precise Event - PEBS) Supports address when precise (Precise event) This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data source were hits in the nearest-level (L1) cache.
Note: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. This event also counts SW prefetches independent of the actual data source Supports address when precise (Precise event) mem_load_uops_retired.l2_hit umask=0x2,period=100003,event=0xd1 Retired load uops with L2 cache hits as data sources. (Precise Event - PEBS) Supports address when precise. Spec update: BDM35 (Precise event) This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were hits in the mid-level (L2) cache Supports address when precise. Spec update: BDM35 (Precise event) mem_load_uops_retired.l3_hit umask=0x4,period=50021,event=0xd1 Hit in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS) Supports address when precise. Spec update: BDM100 (Precise event) This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required Supports address when precise. Spec update: BDM100 (Precise event) mem_load_uops_retired.l1_miss umask=0x8,period=100003,event=0xd1 Retired load uops misses in L1 cache as data sources. Uses PEBS Supports address when precise (Precise event) This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting excludes unknown and UC data source Supports address when precise (Precise event) mem_load_uops_retired.l2_miss umask=0x10,period=50021,event=0xd1 Retired load uops with L2 cache misses as data sources. Uses PEBS Supports address when precise (Precise event) This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting excludes unknown and UC data source Supports address when precise (Precise event) mem_load_uops_retired.l3_miss umask=0x20,period=100007,event=0xd1 Miss in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS) Supports address when precise. Spec update: BDM100, BDE70 (Precise event) mem_load_uops_retired.hit_lfb umask=0x40,period=100003,event=0xd1 Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. (Precise Event - PEBS) Supports address when precise (Precise event) This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were load uops missed L1 but hit a fill buffer due to a preceding miss to the same cache line with the data not ready.
Note: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load Supports address when precise (Precise event) mem_load_uops_l3_hit_retired.xsnp_miss umask=0x1,period=20011,event=0xd2 Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS) Supports address when precise. Spec update: BDM100 (Precise event) This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache Supports address when precise. Spec update: BDM100 (Precise event) mem_load_uops_l3_hit_retired.xsnp_hit umask=0x2,period=20011,event=0xd2 Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS) Supports address when precise. Spec update: BDM100 (Precise event) This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache Supports address when precise. Spec update: BDM100 (Precise event) mem_load_uops_l3_hit_retired.xsnp_hitm umask=0x4,period=20011,event=0xd2 Retired load uops which data sources were HitM responses from shared L3. (Precise Event - PEBS) Supports address when precise. Spec update: BDM100 (Precise event) This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were HitM responses from a core on same socket (shared L3) Supports address when precise. Spec update: BDM100 (Precise event) mem_load_uops_l3_hit_retired.xsnp_none umask=0x8,period=100003,event=0xd2 Retired load uops which data sources were hits in L3 without snoops required. (Precise Event - PEBS) Supports address when precise. Spec update: BDM100 (Precise event) This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required Supports address when precise. Spec update: BDM100 (Precise event) mem_load_uops_l3_miss_retired.local_dram umask=0x1,period=100007,event=0xd3 (null) This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches. This is a precise event Supports address when precise. Spec update: BDE70, BDM100 mem_load_uops_l3_miss_retired.remote_dram umask=0x4,period=100007,event=0xd3 Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI) (Precise Event) Supports address when precise. Spec update: BDE70 mem_load_uops_l3_miss_retired.remote_hitm umask=0x10,period=100007,event=0xd3 Retired load uop whose Data Source was: Remote cache HITM (Precise Event) Supports address when precise. Spec update: BDE70 mem_load_uops_l3_miss_retired.remote_fwd umask=0x20,period=100007,event=0xd3 Retired load uop whose Data Source was: forwarded from remote cache (Precise Event) Supports address when precise. Spec update: BDE70 l2_trans.demand_data_rd umask=0x1,period=200003,event=0xf0 Demand Data Read requests that access L2 cache This event counts Demand Data Read requests that access L2 cache, including rejects l2_trans.rfo umask=0x2,period=200003,event=0xf0 RFO requests that access L2 cache This event counts Read for Ownership (RFO) requests that access L2 cache l2_trans.code_rd umask=0x4,period=200003,event=0xf0 L2 cache accesses when fetching instructions This event counts the number of L2 cache accesses when fetching instructions l2_trans.all_pf umask=0x8,period=200003,event=0xf0 L2 or L3 HW prefetches that access L2 cache This event counts L2 or L3 HW prefetches that access L2 cache including rejects l2_trans.l1d_wb umask=0x10,period=200003,event=0xf0 L1D writebacks that access L2 cache This event counts L1D writebacks that access L2 cache l2_trans.l2_fill umask=0x20,period=200003,event=0xf0 L2 fill requests that access L2 cache This event counts L2 fill requests that access L2 cache l2_trans.l2_wb umask=0x40,period=200003,event=0xf0 L2 writebacks that access L2 cache This event counts L2 writebacks that access L2 cache l2_trans.all_requests umask=0x80,period=200003,event=0xf0 Transactions accessing L2 pipe This event counts transactions that access the L2 pipe including snoops, pagewalks, and so on l2_lines_in.i umask=0x1,period=100003,event=0xf1 L2 cache lines in I state filling L2 This event counts the number of L2 cache lines in the Invalidate state filling the L2. Counting does not cover rejects l2_lines_in.s umask=0x2,period=100003,event=0xf1 L2 cache lines in S state filling L2 This event counts the number of L2 cache lines in the Shared state filling the L2. Counting does not cover rejects l2_lines_in.e umask=0x4,period=100003,event=0xf1 L2 cache lines in E state filling L2 This event counts the number of L2 cache lines in the Exclusive state filling the L2. Counting does not cover rejects l2_lines_in.all umask=0x7,period=100003,event=0xf1 L2 cache lines filling L2 This event counts the number of L2 cache lines filling the L2. Counting does not cover rejects l2_lines_out.demand_clean umask=0x5,period=100003,event=0xf2 Clean L2 cache lines evicted by demand sq_misc.split_lock umask=0x10,period=100003,event=0xf4 Split locks in SQ This event counts the number of split locks in the super queue other_assists.avx_to_sse umask=0x8,period=100003,event=0xc1 Number of transitions from AVX-256 to legacy SSE when penalty applicable Spec update: BDM30 floating point This event counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable Spec update: BDM30 other_assists.sse_to_avx umask=0x10,period=100003,event=0xc1 Number of transitions from SSE to AVX-256 when penalty applicable Spec update: BDM30 This event counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable Spec update: BDM30 fp_arith_inst_retired.scalar_double umask=0x1,period=2000003,event=0xc7 Number of SSE/AVX computational scalar double precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element fp_arith_inst_retired.scalar_single umask=0x2,period=2000003,event=0xc7 Number of SSE/AVX computational scalar single precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element fp_arith_inst_retired.scalar umask=0x3,period=2000003,event=0xc7 Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element fp_arith_inst_retired.128b_packed_double umask=0x4,period=2000003,event=0xc7 Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired. Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element fp_arith_inst_retired.128b_packed_single umask=0x8,period=2000003,event=0xc7 Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element fp_arith_inst_retired.256b_packed_double umask=0x10,period=2000003,event=0xc7 Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element fp_arith_inst_retired.double umask=0x15,period=2000006,event=0xc7 Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ? fp_arith_inst_retired.256b_packed_single umask=0x20,period=2000003,event=0xc7 Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element fp_arith_inst_retired.single umask=0x2a,period=2000005,event=0xc7 Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ? fp_arith_inst_retired.packed umask=0x3c,period=2000004,event=0xc7 Number of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element fp_assist.x87_output umask=0x2,period=100003,event=0xca Number of X87 assists due to output value This event counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid fp_assist.x87_input umask=0x4,period=100003,event=0xca Number of X87 assists due to input value This event counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid fp_assist.simd_output umask=0x8,period=100003,event=0xca Number of SIMD FP assists due to Output values This event counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention fp_assist.simd_input umask=0x10,period=100003,event=0xca Number of SIMD FP assists due to input values This event counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention fp_assist.any umask=0x1e,cmask=1,period=100003,event=0xca Cycles with any input/output SSE or FP assist This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1 idq.empty umask=0x2,period=2000003,event=0x79 Instruction Decode Queue (IDQ) empty cycles frontend This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end. It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty idq.mite_uops umask=0x4,period=2000003,event=0x79 Uops delivered to Instruction Decode Queue (IDQ) from MITE path This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB) idq.mite_cycles umask=0x4,cmask=1,period=2000003,event=0x79 Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ idq.dsb_uops umask=0x8,period=2000003,event=0x79 Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ idq.dsb_cycles umask=0x8,cmask=1,period=2000003,event=0x79 Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ idq.ms_dsb_uops umask=0x10,period=2000003,event=0x79 Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ idq.ms_dsb_cycles umask=0x10,cmask=1,period=2000003,event=0x79 Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy This event counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ idq.ms_dsb_occur edge=1,umask=0x10,cmask=1,period=2000003,event=0x79 Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy This event counts the number of deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ idq.all_dsb_cycles_4_uops umask=0x18,cmask=4,period=2000003,event=0x79 Cycles Decode Stream Buffer (DSB) is delivering 4 Uops This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ idq.all_dsb_cycles_any_uops umask=0x18,cmask=1,period=2000003,event=0x79 Cycles Decode Stream Buffer (DSB) is delivering any Uop This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ idq.ms_mite_uops umask=0x20,period=2000003,event=0x79 Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ idq.all_mite_cycles_4_uops umask=0x24,cmask=4,period=2000003,event=0x79 Cycles MITE is delivering 4 Uops This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB) idq.all_mite_cycles_any_uops umask=0x24,cmask=1,period=2000003,event=0x79 Cycles MITE is delivering any Uop This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB) idq.ms_uops umask=0x30,period=2000003,event=0x79 Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE idq.ms_cycles umask=0x30,cmask=1,period=2000003,event=0x79 Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE idq.ms_switches edge=1,umask=0x30,cmask=1,period=2000003,event=0x79 Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer idq.mite_all_uops umask=0x3c,period=2000003,event=0x79 icache.hit umask=0x1,period=2000003,event=0x80 Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches This event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetches icache.misses umask=0x2,period=200003,event=0x80 Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses icache.ifdata_stall umask=0x4,period=2000003,event=0x80 Cycles where a code fetch is stalled due to L1 instruction-cache miss This event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit) idq_uops_not_delivered.core umask=0x1,period=2000003,event=0x9c Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:
a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;
b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions);
c. Instruction Decode Queue (IDQ) delivers four uops idq_uops_not_delivered.cycles_0_uops_deliv.core umask=0x1,cmask=4,period=2000003,event=0x9c Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled This event counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4 idq_uops_not_delivered.cycles_le_1_uop_deliv.core umask=0x1,cmask=3,period=2000003,event=0x9c Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled This event counts, on the per-thread basis, cycles when less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >=3 idq_uops_not_delivered.cycles_le_2_uop_deliv.core umask=0x1,cmask=2,period=2000003,event=0x9c Cycles with less than 2 uops delivered by the front end idq_uops_not_delivered.cycles_le_3_uop_deliv.core umask=0x1,cmask=1,period=2000003,event=0x9c Cycles with less than 3 uops delivered by the front end idq_uops_not_delivered.cycles_fe_was_ok inv=1,umask=0x1,cmask=1,period=2000003,event=0x9c Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE dsb2mite_switches.penalty_cycles umask=0x2,period=2000003,event=0xab Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop.
MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.
Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles misalign_mem_ref.loads umask=0x1,period=2000003,event=0x5 Speculative cache line split load uops dispatched to L1 cache memory This event counts speculative cache-line split load uops dispatched to the L1 cache misalign_mem_ref.stores umask=0x2,period=2000003,event=0x5 Speculative cache line split STA uops dispatched to L1 cache This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache tx_mem.abort_conflict umask=0x1,period=2000003,event=0x54 Number of times a TSX line had a cache conflict tx_mem.abort_capacity_write umask=0x2,period=2000003,event=0x54 Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow tx_mem.abort_hle_store_to_elided_lock umask=0x4,period=2000003,event=0x54 Number of times a TSX Abort was triggered due to a non-release/commit store to lock tx_mem.abort_hle_elision_buffer_not_empty umask=0x8,period=2000003,event=0x54 Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty tx_mem.abort_hle_elision_buffer_mismatch umask=0x10,period=2000003,event=0x54 Number of times a TSX Abort was triggered due to release/commit but data and address mismatch tx_mem.abort_hle_elision_buffer_unsupported_alignment umask=0x20,period=2000003,event=0x54 Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer tx_mem.hle_elision_buffer_full umask=0x40,period=2000003,event=0x54 Number of times we could not allocate Lock Buffer tx_exec.misc1 umask=0x1,period=2000003,event=0x5d Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort tx_exec.misc2 umask=0x2,period=2000003,event=0x5d Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region Unfriendly TSX abort triggered by a vzeroupper instruction tx_exec.misc3 umask=0x4,period=2000003,event=0x5d Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded Unfriendly TSX abort triggered by a nest count that is too deep tx_exec.misc4 umask=0x8,period=2000003,event=0x5d Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region RTM region detected inside HLE tx_exec.misc5 umask=0x10,period=2000003,event=0x5d Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region machine_clears.memory_ordering umask=0x2,period=100003,event=0xc3 Counts the number of machine clears due to memory order conflicts This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:
1. memory disambiguation,
2. external snoop, or
3. cross SMT-HW-thread snoop (stores) hitting load buffer hle_retired.start umask=0x1,period=2000003,event=0xc8 Number of times we entered an HLE region; does not count nested transactions Number of times we entered an HLE region
does not count nested transactions hle_retired.commit umask=0x2,period=2000003,event=0xc8 Number of times HLE commit succeeded hle_retired.aborted umask=0x4,period=2000003,event=0xc8 Number of times HLE abort was triggered (PEBS) (Precise event) hle_retired.aborted_misc1 umask=0x8,period=2000003,event=0xc8 Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts) Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details) hle_retired.aborted_misc2 umask=0x10,period=2000003,event=0xc8 Number of times an HLE execution aborted due to uncommon conditions Number of times the TSX watchdog signaled an HLE abort hle_retired.aborted_misc3 umask=0x20,period=2000003,event=0xc8 Number of times an HLE execution aborted due to HLE-unfriendly instructions Number of times a disallowed operation caused an HLE abort hle_retired.aborted_misc4 umask=0x40,period=2000003,event=0xc8 Number of times an HLE execution aborted due to incompatible memory type Number of times HLE caused a fault hle_retired.aborted_misc5 umask=0x80,period=2000003,event=0xc8 Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts) Number of times HLE aborted and was not due to the abort conditions in subevents 3-6 rtm_retired.start umask=0x1,period=2000003,event=0xc9 Number of times we entered an RTM region; does not count nested transactions Number of times we entered an RTM region
does not count nested transactions rtm_retired.commit umask=0x2,period=2000003,event=0xc9 Number of times RTM commit succeeded rtm_retired.aborted umask=0x4,period=2000003,event=0xc9 Number of times RTM abort was triggered (PEBS) (Precise event) rtm_retired.aborted_misc1 umask=0x8,period=2000003,event=0xc9 Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts) Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details) rtm_retired.aborted_misc2 umask=0x10,period=2000003,event=0xc9 Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts) Number of times the TSX watchdog signaled an RTM abort rtm_retired.aborted_misc3 umask=0x20,period=2000003,event=0xc9 Number of times an RTM execution aborted due to HLE-unfriendly instructions Number of times a disallowed operation caused an RTM abort rtm_retired.aborted_misc4 umask=0x40,period=2000003,event=0xc9 Number of times an RTM execution aborted due to incompatible memory type Number of times a RTM caused a fault rtm_retired.aborted_misc5 umask=0x80,period=2000003,event=0xc9 Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt) Number of times RTM aborted and was not due to the abort conditions in subevents 3-6 mem_trans_retired.load_latency_gt_4 umask=0x1,period=100003,event=0xcd,ldlat=0x4 Loads with latency value being above 4 Spec update: BDM100, BDM35 (Must be precise) This event counts loads with latency value being above four Spec update: BDM100, BDM35 (Must be precise) mem_trans_retired.load_latency_gt_8 umask=0x1,period=50021,event=0xcd,ldlat=0x8 Loads with latency value being above 8 Spec update: BDM100, BDM35 (Must be precise) This event counts loads with latency value being above eight Spec update: BDM100, BDM35 (Must be precise) mem_trans_retired.load_latency_gt_16 umask=0x1,period=20011,event=0xcd,ldlat=0x10 Loads with latency value being above 16 Spec update: BDM100, BDM35 (Must be precise) This event counts loads with latency value being above 16 Spec update: BDM100, BDM35 (Must be precise) mem_trans_retired.load_latency_gt_32 umask=0x1,period=100007,event=0xcd,ldlat=0x20 Loads with latency value being above 32 Spec update: BDM100, BDM35 (Must be precise) This event counts loads with latency value being above 32 Spec update: BDM100, BDM35 (Must be precise) mem_trans_retired.load_latency_gt_64 umask=0x1,period=2003,event=0xcd,ldlat=0x40 Loads with latency value being above 64 Spec update: BDM100, BDM35 (Must be precise) This event counts loads with latency value being above 64 Spec update: BDM100, BDM35 (Must be precise) mem_trans_retired.load_latency_gt_128 umask=0x1,period=1009,event=0xcd,ldlat=0x80 Loads with latency value being above 128 Spec update: BDM100, BDM35 (Must be precise) This event counts loads with latency value being above 128 Spec update: BDM100, BDM35 (Must be precise) mem_trans_retired.load_latency_gt_256 umask=0x1,period=503,event=0xcd,ldlat=0x100 Loads with latency value being above 256 Spec update: BDM100, BDM35 (Must be precise) This event counts loads with latency value being above 256 Spec update: BDM100, BDM35 (Must be precise) mem_trans_retired.load_latency_gt_512 umask=0x1,period=101,event=0xcd,ldlat=0x200 Loads with latency value being above 512 Spec update: BDM100, BDM35 (Must be precise) This event counts loads with latency value being above 512 Spec update: BDM100, BDM35 (Must be precise) cpl_cycles.ring0 umask=0x1,period=2000003,event=0x5c Unhalted core cycles when the thread is in ring 0 other This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode cpl_cycles.ring0_trans edge=1,umask=0x1,cmask=1,period=100007,event=0x5c Number of intervals between processor halts while thread is in ring 0 This event counts when there is a transition from ring 1,2 or 3 to ring0 cpl_cycles.ring123 umask=0x2,period=2000003,event=0x5c Unhalted core cycles when thread is in rings 1, 2, or 3 This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3 lock_cycles.split_lock_uc_lock_duration umask=0x1,period=2000003,event=0x63 Cycles when L1 and L2 are locked due to UC or split lock This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access event=0xc0 Instructions retired from execution pipeline This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers.
Notes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event.
Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions event=0x3c Core cycles when the thread is not in halt state This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events cpu_clk_unhalted.thread_any event=0x3c,any=1 Core cycles when at least one thread on the physical core is not in halt state cpu_clk_unhalted.ref_tsc umask=0x3,period=2000003,event=0 Reference cycles when the core is not in halt state This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.
Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. This event is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case ld_blocks.store_forward umask=0x2,period=100003,event=0x3 Cases when loads get true Block-on-Store blocking code preventing store forwarding This event counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when:
- preceding store conflicts with the load (incomplete overlap);
- store forwarding is impossible due to u-arch limitations;
- preceding lock RMW operations are not forwarded;
- store has the no-forward bit set (uncacheable/page-split/masked stores);
- all-blocking stores are used (mostly, fences and port I/O);
and others.
The most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events.
See the table of not supported store forwards in the Optimization Guide ld_blocks.no_sr umask=0x8,period=100003,event=0x3 This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use ld_blocks_partial.address_alias umask=0x1,period=100003,event=0x7 False dependencies in MOB due to partial compare This event counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased int_misc.recovery_cycles umask=0x3,cmask=1,period=2000003,event=0xd Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke) Cycles checkpoints in Resource Allocation Table (RAT) are recovering from JEClear or machine clear int_misc.recovery_cycles_any umask=0x3,any=1,cmask=1,period=2000003,event=0xd Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke) int_misc.rat_stall_cycles umask=0x8,period=2000003,event=0xd Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread This event counts the number of cycles during which Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the current thread. This also includes the cycles during which the Allocator is serving another thread uops_issued.any umask=0x1,period=2000003,event=0xe Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS) This event counts the number of Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) uops_issued.stall_cycles inv=1,umask=0x1,cmask=1,period=2000003,event=0xe Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread This event counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread uops_issued.flags_merge umask=0x10,period=2000003,event=0xe Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch Number of flags-merge uops being allocated. Such uops considered perf sensitive
added by GSR u-arch uops_issued.slow_lea umask=0x20,period=2000003,event=0xe Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not uops_issued.single_mul umask=0x40,period=2000003,event=0xe Number of Multiply packed/scalar single precision uops allocated arith.fpu_div_active umask=0x1,period=2000003,event=0x14 Cycles when divider is busy executing divide operations This event counts the number of the divide operations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DIV_ACTIVE to get the number of the divide operations executed cpu_clk_unhalted.thread_p umask=0x0,period=2000003,event=0x3c Thread cycles when thread is not in halt state This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time cpu_clk_unhalted.thread_p_any umask=0x0,any=1,period=2000003,event=0x3c cpu_clk_thread_unhalted.ref_xclk umask=0x1,period=2000003,event=0x3c Reference cycles when the thread is unhalted (counts at 100 MHz rate) This is a fixed-frequency event programmed to general counters. It counts when the core is unhalted at 100 Mhz cpu_clk_thread_unhalted.ref_xclk_any umask=0x1,any=1,period=2000003,event=0x3c Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate) cpu_clk_unhalted.ref_xclk cpu_clk_unhalted.ref_xclk_any cpu_clk_thread_unhalted.one_thread_active umask=0x2,period=2000003,event=0x3c Count XClk pulses when this thread is unhalted and the other thread is halted cpu_clk_unhalted.one_thread_active load_hit_pre.sw_pf umask=0x1,period=100003,event=0x4c Not software-prefetch load dispatches that hit FB allocated for software prefetch This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by asm inspection of the nearby instructions load_hit_pre.hw_pf umask=0x2,period=100003,event=0x4c Not software-prefetch load dispatches that hit FB allocated for hardware prefetch This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the hardware prefetch move_elimination.int_eliminated umask=0x1,period=1000003,event=0x58 Number of integer Move Elimination candidate uops that were eliminated move_elimination.simd_eliminated umask=0x2,period=1000003,event=0x58 Number of SIMD Move Elimination candidate uops that were eliminated move_elimination.int_not_eliminated umask=0x4,period=1000003,event=0x58 Number of integer Move Elimination candidate uops that were not eliminated move_elimination.simd_not_eliminated umask=0x8,period=1000003,event=0x58 Number of SIMD Move Elimination candidate uops that were not eliminated rs_events.empty_cycles umask=0x1,period=2000003,event=0x5e Cycles when Reservation Station (RS) is empty for the thread This event counts cycles during which the reservation station (RS) is empty for the thread.
Note: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues rs_events.empty_end edge=1,inv=1,umask=0x1,cmask=1,period=200003,event=0x5e Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues ild_stall.lcp umask=0x1,period=2000003,event=0x87 Stalls caused by changing prefix length of the instruction This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk br_inst_exec.nontaken_conditional umask=0x41,period=200003,event=0x88 Not taken macro-conditional branches This event counts not taken macro-conditional branch instructions br_inst_exec.taken_conditional umask=0x81,period=200003,event=0x88 Taken speculative and retired macro-conditional branches This event counts taken speculative and retired macro-conditional branch instructions br_inst_exec.taken_direct_jump umask=0x82,period=200003,event=0x88 Taken speculative and retired macro-conditional branch instructions excluding calls and indirects This event counts taken speculative and retired macro-conditional branch instructions excluding calls and indirect branches br_inst_exec.taken_indirect_jump_non_call_ret umask=0x84,period=200003,event=0x88 Taken speculative and retired indirect branches excluding calls and returns This event counts taken speculative and retired indirect branches excluding calls and return branches br_inst_exec.taken_indirect_near_return umask=0x88,period=200003,event=0x88 Taken speculative and retired indirect branches with return mnemonic This event counts taken speculative and retired indirect branches that have a return mnemonic br_inst_exec.taken_direct_near_call umask=0x90,period=200003,event=0x88 Taken speculative and retired direct near calls This event counts taken speculative and retired direct near calls br_inst_exec.taken_indirect_near_call umask=0xa0,period=200003,event=0x88 Taken speculative and retired indirect calls This event counts taken speculative and retired indirect calls including both register and memory indirect br_inst_exec.all_conditional umask=0xc1,period=200003,event=0x88 Speculative and retired macro-conditional branches This event counts both taken and not taken speculative and retired macro-conditional branch instructions br_inst_exec.all_direct_jmp umask=0xc2,period=200003,event=0x88 Speculative and retired macro-unconditional branches excluding calls and indirects This event counts both taken and not taken speculative and retired macro-unconditional branch instructions, excluding calls and indirects br_inst_exec.all_indirect_jump_non_call_ret umask=0xc4,period=200003,event=0x88 Speculative and retired indirect branches excluding calls and returns This event counts both taken and not taken speculative and retired indirect branches excluding calls and return branches br_inst_exec.all_indirect_near_return umask=0xc8,period=200003,event=0x88 Speculative and retired indirect return branches This event counts both taken and not taken speculative and retired indirect branches that have a return mnemonic br_inst_exec.all_direct_near_call umask=0xd0,period=200003,event=0x88 Speculative and retired direct near calls This event counts both taken and not taken speculative and retired direct near calls br_inst_exec.all_branches umask=0xff,period=200003,event=0x88 Speculative and retired branches This event counts both taken and not taken speculative and retired branch instructions br_misp_exec.nontaken_conditional umask=0x41,period=200003,event=0x89 Not taken speculative and retired mispredicted macro conditional branches This event counts not taken speculative and retired mispredicted macro conditional branch instructions br_misp_exec.taken_conditional umask=0x81,period=200003,event=0x89 Taken speculative and retired mispredicted macro conditional branches This event counts taken speculative and retired mispredicted macro conditional branch instructions br_misp_exec.taken_indirect_jump_non_call_ret umask=0x84,period=200003,event=0x89 Taken speculative and retired mispredicted indirect branches excluding calls and returns This event counts taken speculative and retired mispredicted indirect branches excluding calls and returns br_misp_exec.taken_return_near umask=0x88,period=200003,event=0x89 Taken speculative and retired mispredicted indirect branches with return mnemonic This event counts taken speculative and retired mispredicted indirect branches that have a return mnemonic br_misp_exec.taken_indirect_near_call umask=0xa0,period=200003,event=0x89 Taken speculative and retired mispredicted indirect calls br_misp_exec.all_conditional umask=0xc1,period=200003,event=0x89 Speculative and retired mispredicted macro conditional branches This event counts both taken and not taken speculative and retired mispredicted macro conditional branch instructions br_misp_exec.all_indirect_jump_non_call_ret umask=0xc4,period=200003,event=0x89 Mispredicted indirect branches excluding calls and returns This event counts both taken and not taken mispredicted indirect branches excluding calls and returns br_misp_exec.all_branches umask=0xff,period=200003,event=0x89 This event counts both taken and not taken speculative and retired mispredicted branch instructions uop_dispatches_cancelled.simd_prf umask=0x3,period=2000003,event=0xa0 Micro-op dispatches cancelled due to insufficient SIMD physical register file read ports This event counts the number of micro-operations cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports across all dispatch ports exceeds the read bandwidth of the physical register file. The SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*. See the Broadwell Optimization Guide for more information uops_dispatched_port.port_0 umask=0x1,period=2000003,event=0xa1 Cycles per thread when uops are executed in port 0 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0 uops_executed_port.port_0_core umask=0x1,any=1,period=2000003,event=0xa1 Cycles per core when uops are exectuted in port 0 uops_executed_port.port_0 uops_dispatched_port.port_1 umask=0x2,period=2000003,event=0xa1 Cycles per thread when uops are executed in port 1 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1 uops_executed_port.port_1_core umask=0x2,any=1,period=2000003,event=0xa1 Cycles per core when uops are exectuted in port 1 uops_executed_port.port_1 uops_dispatched_port.port_2 umask=0x4,period=2000003,event=0xa1 Cycles per thread when uops are executed in port 2 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2 uops_executed_port.port_2_core umask=0x4,any=1,period=2000003,event=0xa1 Cycles per core when uops are dispatched to port 2 uops_executed_port.port_2 uops_dispatched_port.port_3 umask=0x8,period=2000003,event=0xa1 Cycles per thread when uops are executed in port 3 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3 uops_executed_port.port_3_core umask=0x8,any=1,period=2000003,event=0xa1 Cycles per core when uops are dispatched to port 3 uops_executed_port.port_3 uops_dispatched_port.port_4 umask=0x10,period=2000003,event=0xa1 Cycles per thread when uops are executed in port 4 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4 uops_executed_port.port_4_core umask=0x10,any=1,period=2000003,event=0xa1 Cycles per core when uops are exectuted in port 4 uops_executed_port.port_4 uops_dispatched_port.port_5 umask=0x20,period=2000003,event=0xa1 Cycles per thread when uops are executed in port 5 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5 uops_executed_port.port_5_core umask=0x20,any=1,period=2000003,event=0xa1 Cycles per core when uops are exectuted in port 5 uops_executed_port.port_5 uops_dispatched_port.port_6 umask=0x40,period=2000003,event=0xa1 Cycles per thread when uops are executed in port 6 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6 uops_executed_port.port_6_core umask=0x40,any=1,period=2000003,event=0xa1 Cycles per core when uops are exectuted in port 6 uops_executed_port.port_6 uops_dispatched_port.port_7 umask=0x80,period=2000003,event=0xa1 Cycles per thread when uops are executed in port 7 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7 uops_executed_port.port_7_core umask=0x80,any=1,period=2000003,event=0xa1 Cycles per core when uops are dispatched to port 7 uops_executed_port.port_7 resource_stalls.any umask=0x1,period=2000003,event=0xa2 Resource-related stall cycles This event counts resource-related stall cycles. Reasons for stalls can be as follows:
- *any* u-arch structure got full (LB, SB, RS, ROB, BOB, LM, Physical Register Reclaim Table (PRRT), or Physical History Table (PHT) slots)
- *any* u-arch structure got empty (like INT/SIMD FreeLists)
- FPU control word (FPCW), MXCSR
and others. This counts cycles that the pipeline backend blocked uop delivery from the front end resource_stalls.rs umask=0x4,period=2000003,event=0xa2 Cycles stalled due to no eligible RS entry available This event counts stall cycles caused by absence of eligible entries in the reservation station (RS). This may result from RS overflow, or from RS deallocation because of the RS array Write Port allocation scheme (each RS entry has two write ports instead of four. As a result, empty entries could not be used, although RS is not really full). This counts cycles that the pipeline backend blocked uop delivery from the front end resource_stalls.sb umask=0x8,period=2000003,event=0xa2 Cycles stalled due to no store buffers available. (not including draining form sync) This event counts stall cycles caused by the store buffer (SB) overflow (excluding draining from synch). This counts cycles that the pipeline backend blocked uop delivery from the front end resource_stalls.rob umask=0x10,period=2000003,event=0xa2 Cycles stalled due to re-order buffer full This event counts ROB full stall cycles. This counts cycles that the pipeline backend blocked uop delivery from the front end cycle_activity.cycles_l2_pending umask=0x1,cmask=1,period=2000003,event=0xa3 Cycles while L2 cache miss demand load is outstanding Counts number of cycles the CPU has at least one pending demand* load request missing the L2 cache cycle_activity.cycles_l2_miss cycle_activity.cycles_ldm_pending umask=0x2,cmask=2,period=2000003,event=0xa3 Cycles while memory subsystem has an outstanding load Counts number of cycles the CPU has at least one pending demand load request (that is cycles with non-completed load waiting for its data from memory subsystem) cycle_activity.cycles_mem_any cycle_activity.cycles_no_execute umask=0x4,cmask=4,period=2000003,event=0xa3 This event increments by 1 for every cycle where there was no execute for this thread Counts number of cycles nothing is executed on any execution port cycle_activity.stalls_total Total execution stalls cycle_activity.stalls_l2_pending umask=0x5,cmask=5,period=2000003,event=0xa3 Execution stalls while L2 cache miss demand load is outstanding Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand* load request missing the L2 cache.(as a footprint) * includes also L1 HW prefetch requests that may or may not be required by demands cycle_activity.stalls_l2_miss cycle_activity.stalls_ldm_pending umask=0x6,cmask=6,period=2000003,event=0xa3 Execution stalls while memory subsystem has an outstanding load Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request cycle_activity.stalls_mem_any cycle_activity.cycles_l1d_pending umask=0x8,cmask=8,period=2000003,event=0xa3 Cycles while L1 cache miss demand load is outstanding Counts number of cycles the CPU has at least one pending demand load request missing the L1 data cache cycle_activity.cycles_l1d_miss cycle_activity.stalls_l1d_pending umask=0xc,cmask=12,period=2000003,event=0xa3 Execution stalls while L1 cache miss demand load is outstanding Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request missing the L1 data cache cycle_activity.stalls_l1d_miss lsd.uops umask=0x1,period=2000003,event=0xa8 Number of Uops delivered by the LSD lsd.cycles_4_uops umask=0x1,cmask=4,period=2000003,event=0xa8 Cycles 4 Uops delivered by the LSD, but didn't come from the decoder lsd.cycles_active umask=0x1,cmask=1,period=2000003,event=0xa8 Cycles Uops delivered by the LSD, but didn't come from the decoder uops_executed.thread umask=0x1,period=2000003,event=0xb1 Counts the number of uops to be executed per-thread each cycle Number of uops to be executed per-thread each cycle uops_executed.stall_cycles inv=1,umask=0x1,cmask=1,period=2000003,event=0xb1 Counts number of cycles no uops were dispatched to be executed on this thread This event counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread uops_executed.cycles_ge_1_uop_exec umask=0x1,cmask=1,period=2000003,event=0xb1 Cycles where at least 1 uop was executed per-thread uops_executed.cycles_ge_2_uops_exec umask=0x1,cmask=2,period=2000003,event=0xb1 Cycles where at least 2 uops were executed per-thread uops_executed.cycles_ge_3_uops_exec umask=0x1,cmask=3,period=2000003,event=0xb1 Cycles where at least 3 uops were executed per-thread uops_executed.cycles_ge_4_uops_exec umask=0x1,cmask=4,period=2000003,event=0xb1 Cycles where at least 4 uops were executed per-thread uops_executed.core umask=0x2,period=2000003,event=0xb1 Number of uops executed on the core Number of uops executed from any thread uops_executed.core_cycles_ge_1 umask=0x2,cmask=1,period=2000003,event=0xb1 Cycles at least 1 micro-op is executed from any thread on physical core uops_executed.core_cycles_ge_2 umask=0x2,cmask=2,period=2000003,event=0xb1 Cycles at least 2 micro-op is executed from any thread on physical core uops_executed.core_cycles_ge_3 umask=0x2,cmask=3,period=2000003,event=0xb1 Cycles at least 3 micro-op is executed from any thread on physical core uops_executed.core_cycles_ge_4 umask=0x2,cmask=4,period=2000003,event=0xb1 Cycles at least 4 micro-op is executed from any thread on physical core uops_executed.core_cycles_none inv=1,umask=0x2,period=2000003,event=0xb1 Cycles with no micro-ops executed from any thread on physical core inst_retired.any_p Number of instructions retired. General Counter - architectural event Spec update: BDM61 This event counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two) Spec update: BDM61 inst_retired.prec_dist umask=0x1,period=2000003,event=0xc0 Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution Spec update: BDM11, BDM55 (Must be precise) This is a precise version (that is, uses PEBS) of the event that counts instructions retired Spec update: BDM11, BDM55 (Must be precise) inst_retired.x87 umask=0x2,period=2000003,event=0xc0 FP operations retired. X87 FP operations that have no exceptions: This event counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling other_assists.any_wb_assist umask=0x40,period=100003,event=0xc1 Number of times any microcode assist is invoked by HW upon uop writeback uops_retired.all umask=0x1,period=2000003,event=0xc2 Actually retired uops. (Precise Event - PEBS) Supports address when precise (Precise event) This is a precise version (that is, uses PEBS) of the event that counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight Supports address when precise (Precise event) uops_retired.stall_cycles inv=1,umask=0x1,cmask=1,period=2000003,event=0xc2 Cycles without actually retired uops This event counts cycles without actually retired uops uops_retired.total_cycles inv=1,umask=0x1,cmask=10,period=2000003,event=0xc2 Cycles with less than 10 actually retired uops Number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event uops_retired.retire_slots umask=0x2,period=2000003,event=0xc2 Retirement slots used. (Precise Event - PEBS) (Precise event) This is a precise version (that is, uses PEBS) of the event that counts the number of retirement slots used (Precise event) machine_clears.cycles umask=0x1,period=2000003,event=0xc3 Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes This event counts both thread-specific (TS) and all-thread (AT) nukes machine_clears.count edge=1,umask=0x1,cmask=1,period=100003,event=0xc3 Number of machine clears (nukes) of any type machine_clears.smc umask=0x4,period=100003,event=0xc3 Self-modifying code (SMC) detected This event counts self-modifying code (SMC) detected, which causes a machine clear machine_clears.maskmov umask=0x20,period=100003,event=0xc3 This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0 Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault br_inst_retired.all_branches umask=0x0,period=400009,event=0xc4 All (macro) branch instructions retired This event counts all (macro) branch instructions retired br_inst_retired.conditional umask=0x1,period=400009,event=0xc4 Conditional branch instructions retired. (Precise Event - PEBS) (Precise event) This is a precise version (that is, uses PEBS) of the event that counts conditional branch instructions retired (Precise event) br_inst_retired.near_call umask=0x2,period=100007,event=0xc4 Direct and indirect near call instructions retired. (Precise Event - PEBS) (Precise event) This is a precise version (that is, uses PEBS) of the event that counts both direct and indirect near call instructions retired (Precise event) br_inst_retired.near_call_r3 Direct and indirect macro near call instructions retired (captured in ring 3). (Precise Event - PEBS) (Precise event) This is a precise version (that is, uses PEBS) of the event that counts both direct and indirect macro near call instructions retired (captured in ring 3) (Precise event) br_inst_retired.all_branches_pebs umask=0x4,period=400009,event=0xc4 All (macro) branch instructions retired. (Precise Event - PEBS) Spec update: BDW98 (Must be precise) This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired Spec update: BDW98 (Must be precise) br_inst_retired.near_return umask=0x8,period=100007,event=0xc4 Return instructions retired. (Precise Event - PEBS) (Precise event) This is a precise version (that is, uses PEBS) of the event that counts return instructions retired (Precise event) br_inst_retired.not_taken umask=0x10,period=400009,event=0xc4 Not taken branch instructions retired This event counts not taken branch instructions retired br_inst_retired.near_taken umask=0x20,period=400009,event=0xc4 Taken branch instructions retired. (Precise Event - PEBS) (Precise event) This is a precise version (that is, uses PEBS) of the event that counts taken branch instructions retired (Precise event) br_inst_retired.far_branch umask=0x40,period=100007,event=0xc4 Far branch instructions retired Spec update: BDW98 This event counts far branch instructions retired Spec update: BDW98 br_misp_retired.all_branches umask=0x0,period=400009,event=0xc5 All mispredicted macro branch instructions retired This event counts all mispredicted macro branch instructions retired br_misp_retired.conditional umask=0x1,period=400009,event=0xc5 Mispredicted conditional branch instructions retired. (Precise Event - PEBS) (Precise event) This is a precise version (that is, uses PEBS) of the event that counts mispredicted conditional branch instructions retired (Precise event) br_misp_retired.all_branches_pebs umask=0x4,period=400009,event=0xc5 Mispredicted macro branch instructions retired. (Precise Event - PEBS) (Must be precise) This is a precise version of BR_MISP_RETIRED.ALL_BRANCHES that counts all mispredicted macro branch instructions retired (Must be precise) br_misp_retired.ret umask=0x8,period=100007,event=0xc5 This event counts the number of mispredicted ret instructions retired.(Precise Event) This is a precise version (that is, uses PEBS) of the event that counts mispredicted return instructions retired br_misp_retired.near_taken umask=0x20,period=400009,event=0xc5 number of near branch instructions retired that were mispredicted and taken. (Precise Event - PEBS) (Precise event) Number of near branch instructions retired that were mispredicted and taken. (Precise Event - PEBS) (Precise event) rob_misc_events.lbr_inserts umask=0x20,period=2000003,event=0xcc Count cases of saving new LBR This event counts cases of saving new LBR records by hardware. This assumes proper enabling of LBRs and takes into account LBR filtering done by the LBR_SELECT register baclears.any umask=0x1f,period=100003,event=0xe6 Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end unc_c_clockticks event=0 Uncore cache clock ticks. Unit: uncore_cbox uncore cache uncore_cbox 1 unc_c_llc_lookup.any umask=0x11,event=0x34,filter_state=0x1 All LLC Misses (code+ data rd + data wr - including demand and prefetch). Unit: uncore_cbox 64Bytes unc_c_llc_victims.m_state umask=0x1,event=0x37 M line evictions from LLC (writebacks to memory). Unit: uncore_cbox llc_misses.data_read umask=0x3,event=0x35,filter_opc=0x182 LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox llc_misses.uncacheable umask=0x3,event=0x35,filter_opc=0x187 LLC misses - Uncacheable reads (from cpu) . Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox llc_misses.mmio_read umask=0x3,event=0x35,filter_opc=0x187,filter_nc=1 MMIO reads. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox llc_misses.mmio_write umask=0x3,event=0x35,filter_opc=0x18f,filter_nc=1 MMIO writes. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox llc_misses.rfo_llc_prefetch umask=0x3,event=0x35,filter_opc=0x190 LLC prefetch misses for RFO. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox llc_misses.code_llc_prefetch umask=0x3,event=0x35,filter_opc=0x191 LLC prefetch misses for code reads. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox llc_misses.data_llc_prefetch umask=0x3,event=0x35,filter_opc=0x192 LLC prefetch misses for data reads. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox llc_misses.pcie_read umask=0x3,event=0x35,filter_opc=0x19e LLC misses for PCIe read current. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox llc_misses.pcie_write umask=0x3,event=0x35,filter_opc=0x1c8 ItoM write misses (as part of fast string memcpy stores) + PCIe full line writes. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox llc_misses.pcie_non_snoop_write umask=0x3,event=0x35,filter_opc=0x1c8,filter_tid=0x3e PCIe write misses (full cache line). Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox llc_references.pcie_ns_partial_write umask=0x1,event=0x35,filter_opc=0x180,filter_tid=0x3e PCIe writes (partial cache line). Derived from unc_c_tor_inserts.opcode. Unit: uncore_cbox llc_references.code_llc_prefetch umask=0x1,event=0x35,filter_opc=0x181 L2 demand and L2 prefetch code references to LLC. Derived from unc_c_tor_inserts.opcode. Unit: uncore_cbox llc_references.streaming_full umask=0x1,event=0x35,filter_opc=0x18c Streaming stores (full cache line). Derived from unc_c_tor_inserts.opcode. Unit: uncore_cbox llc_references.streaming_partial umask=0x1,event=0x35,filter_opc=0x18d Streaming stores (partial cache line). Derived from unc_c_tor_inserts.opcode. Unit: uncore_cbox llc_references.pcie_read umask=0x1,event=0x35,filter_opc=0x19e PCIe read current. Derived from unc_c_tor_inserts.opcode. Unit: uncore_cbox llc_references.pcie_write umask=0x1,event=0x35,filter_opc=0x1c8,filter_tid=0x3e PCIe write references (full cache line). Derived from unc_c_tor_inserts.opcode. Unit: uncore_cbox unc_c_tor_occupancy.llc_data_read umask=0x3,event=0x36,filter_opc=0x182 Occupancy counter for LLC data reads (demand and L2 prefetch). Derived from unc_c_tor_occupancy.miss_opcode. Unit: uncore_cbox unc_h_requests.reads umask=0x3,event=0x1 read requests to home agent. Unit: uncore_ha uncore_ha unc_h_requests.reads_local umask=0x1,event=0x1 read requests to local home agent. Unit: uncore_ha unc_h_requests.reads_remote umask=0x2,event=0x1 read requests to remote home agent. Unit: uncore_ha unc_h_requests.writes umask=0xC,event=0x1 write requests to home agent. Unit: uncore_ha unc_h_requests.writes_local umask=0x4,event=0x1 write requests to local home agent. Unit: uncore_ha unc_h_requests.writes_remote umask=0x8,event=0x1 write requests to remote home agent. Unit: uncore_ha unc_h_snoop_resp.rspcnflct umask=0x40,event=0x21 Conflict requests (requests for same address from multiple agents simultaneously). Unit: uncore_ha unc_h_snoop_resp.rsp_fwd_wb umask=0x20,event=0x21 M line forwarded from remote cache along with writeback to memory. Unit: uncore_ha unc_h_snoop_resp.rspifwd umask=0x4,event=0x21 M line forwarded from remote cache with no writeback to memory. Unit: uncore_ha unc_h_snoop_resp.rsps umask=0x2,event=0x21 Shared line response from remote cache. Unit: uncore_ha unc_h_snoop_resp.rspsfwd umask=0x8,event=0x21 Shared line forwarded from remote cache. Unit: uncore_ha llc_misses.mem_read umask=0x3,event=0x4 read requests to memory controller. Derived from unc_m_cas_count.rd. Unit: uncore_imc uncore memory uncore_imc llc_misses.mem_write umask=0xC,event=0x4 write requests to memory controller. Derived from unc_m_cas_count.wr. Unit: uncore_imc unc_m_dclockticks Memory controller clock ticks. Unit: uncore_imc unc_m_power_channel_ppd event=0x85 Cycles where DRAM ranks are in power down (CKE) mode. Unit: uncore_imc (unc_m_power_channel_ppd / unc_m_dclockticks) * 100. power_channel_ppd % unc_m_power_critical_throttle_cycles event=0x86 Cycles all ranks are in critical thermal throttle. Unit: uncore_imc (unc_m_power_critical_throttle_cycles / unc_m_dclockticks) * 100. power_critical_throttle_cycles % unc_m_power_self_refresh event=0x43 Cycles Memory is in self refresh power mode. Unit: uncore_imc (unc_m_power_self_refresh / unc_m_dclockticks) * 100. power_self_refresh % unc_m_pre_count.page_miss umask=0x1,event=0x2 Pre-charges due to page misses. Unit: uncore_imc unc_m_pre_count.rd umask=0x4,event=0x2 Pre-charge for reads. Unit: uncore_imc unc_m_pre_count.wr umask=0x8,event=0x2 Pre-charge for writes. Unit: uncore_imc unc_p_clockticks PCU clock ticks. Use to get percentages of PCU cycles events. Unit: uncore_pcu uncore power uncore_pcu unc_p_power_state_occupancy.cores_c0 event=0x80,occ_sel=1 This is an occupancy event that tracks the number of cores that are in C0. It can be used by itself to get the average number of cores in C0, with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details. Unit: uncore_pcu (unc_p_power_state_occupancy.cores_c0 / unc_p_clockticks) * 100. power_state_occupancy.cores_c0 % unc_p_power_state_occupancy.cores_c3 event=0x80,occ_sel=2 This is an occupancy event that tracks the number of cores that are in C3. It can be used by itself to get the average number of cores in C0, with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details. Unit: uncore_pcu (unc_p_power_state_occupancy.cores_c3 / unc_p_clockticks) * 100. power_state_occupancy.cores_c3 % unc_p_power_state_occupancy.cores_c6 event=0x80,occ_sel=3 This is an occupancy event that tracks the number of cores that are in C6. It can be used by itself to get the average number of cores in C0, with threshholding to generate histograms, or with other PCU events . Unit: uncore_pcu (unc_p_power_state_occupancy.cores_c6 / unc_p_clockticks) * 100. power_state_occupancy.cores_c6 % unc_p_prochot_external_cycles event=0xa Counts the number of cycles that we are in external PROCHOT mode. This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip. Unit: uncore_pcu (unc_p_prochot_external_cycles / unc_p_clockticks) * 100. prochot_external_cycles % unc_p_freq_max_limit_thermal_cycles event=0x4 Counts the number of cycles when temperature is the upper limit on frequency. Unit: uncore_pcu (unc_p_freq_max_limit_thermal_cycles / unc_p_clockticks) * 100. freq_max_limit_thermal_cycles % unc_p_freq_max_os_cycles event=0x6 Counts the number of cycles when the OS is the upper limit on frequency. Unit: uncore_pcu (unc_p_freq_max_os_cycles / unc_p_clockticks) * 100. freq_max_os_cycles % unc_p_freq_max_power_cycles event=0x5 Counts the number of cycles when power is the upper limit on frequency. Unit: uncore_pcu (unc_p_freq_max_power_cycles / unc_p_clockticks) * 100. freq_max_power_cycles % unc_p_freq_trans_cycles event=0x74 Counts the number of cycles when current is the upper limit on frequency. Unit: uncore_pcu (unc_p_freq_trans_cycles / unc_p_clockticks) * 100. freq_trans_cycles % dtlb_load_misses.miss_causes_a_walk umask=0x1,period=100003,event=0x8 Load misses in all DTLB levels that cause page walks Spec update: BDM69 virtual memory This event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G) Spec update: BDM69 dtlb_load_misses.walk_completed_4k umask=0x2,period=2000003,event=0x8 Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K) Spec update: BDM69 This event counts load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault Spec update: BDM69 dtlb_load_misses.walk_completed_2m_4m umask=0x4,period=2000003,event=0x8 Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M) Spec update: BDM69 This event counts load misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault Spec update: BDM69 dtlb_load_misses.walk_completed_1g umask=0x8,period=2000003,event=0x8 Load miss in all TLB levels causes a page walk that completes. (1G) Spec update: BDM69 This event counts load misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault Spec update: BDM69 dtlb_load_misses.walk_completed umask=0xe,period=100003,event=0x8 Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size Spec update: BDM69 dtlb_load_misses.walk_duration umask=0x10,period=2000003,event=0x8 Cycles when PMH is busy with page walks Spec update: BDM69 This event counts the number of cycles while PMH is busy with the page walk Spec update: BDM69 dtlb_load_misses.stlb_hit_4k umask=0x20,period=2000003,event=0x8 Load misses that miss the DTLB and hit the STLB (4K) dtlb_load_misses.stlb_hit_2m umask=0x40,period=2000003,event=0x8 Load misses that miss the DTLB and hit the STLB (2M) dtlb_load_misses.stlb_hit umask=0x60,period=2000003,event=0x8 Load operations that miss the first DTLB level but hit the second and do not cause page walks dtlb_store_misses.miss_causes_a_walk umask=0x1,period=100003,event=0x49 Store misses in all DTLB levels that cause page walks Spec update: BDM69 This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G) Spec update: BDM69 dtlb_store_misses.walk_completed_4k umask=0x2,period=100003,event=0x49 Store miss in all TLB levels causes a page walk that completes. (4K) Spec update: BDM69 This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault Spec update: BDM69 dtlb_store_misses.walk_completed_2m_4m umask=0x4,period=100003,event=0x49 Store misses in all DTLB levels that cause completed page walks (2M/4M) Spec update: BDM69 This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault Spec update: BDM69 dtlb_store_misses.walk_completed_1g umask=0x8,period=100003,event=0x49 Store misses in all DTLB levels that cause completed page walks (1G) Spec update: BDM69 This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault Spec update: BDM69 dtlb_store_misses.walk_completed umask=0xe,period=100003,event=0x49 Store misses in all DTLB levels that cause completed page walks Spec update: BDM69 dtlb_store_misses.walk_duration umask=0x10,period=100003,event=0x49 dtlb_store_misses.stlb_hit_4k umask=0x20,period=100003,event=0x49 Store misses that miss the DTLB and hit the STLB (4K) dtlb_store_misses.stlb_hit_2m umask=0x40,period=100003,event=0x49 Store misses that miss the DTLB and hit the STLB (2M) dtlb_store_misses.stlb_hit umask=0x60,period=100003,event=0x49 Store operations that miss the first TLB level but hit the second and do not cause page walks ept.walk_cycles umask=0x10,period=2000003,event=0x4f Cycle count for an Extended Page table walk This event counts cycles for an extended page table walk. The Extended Page directory cache differs from standard TLB caches by the operating system that use it. Virtual machine operating systems use the extended page directory cache, while guest operating systems use the standard TLB caches itlb_misses.miss_causes_a_walk umask=0x1,period=100003,event=0x85 Misses at all ITLB levels that cause page walks Spec update: BDM69 itlb_misses.walk_completed_4k umask=0x2,period=100003,event=0x85 Code miss in all TLB levels causes a page walk that completes. (4K) Spec update: BDM69 itlb_misses.walk_completed_2m_4m umask=0x4,period=100003,event=0x85 Code miss in all TLB levels causes a page walk that completes. (2M/4M) Spec update: BDM69 itlb_misses.walk_completed_1g umask=0x8,period=100003,event=0x85 Store miss in all TLB levels causes a page walk that completes. (1G) Spec update: BDM69 itlb_misses.walk_completed umask=0xe,period=100003,event=0x85 Misses in all ITLB levels that cause completed page walks Spec update: BDM69 itlb_misses.walk_duration umask=0x10,period=100003,event=0x85 itlb_misses.stlb_hit_4k umask=0x20,period=100003,event=0x85 Core misses that miss the DTLB and hit the STLB (4K) itlb_misses.stlb_hit_2m umask=0x40,period=100003,event=0x85 Code misses that miss the DTLB and hit the STLB (2M) itlb_misses.stlb_hit umask=0x60,period=100003,event=0x85 Operations that miss the first ITLB level but hit the second and do not cause any page walks itlb.itlb_flush umask=0x1,period=100007,event=0xae Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific) page_walker_loads.dtlb_l1 umask=0x11,period=2000003,event=0xbc Number of DTLB page walker hits in the L1+FB Spec update: BDM69, BDM98 page_walker_loads.dtlb_l2 umask=0x12,period=2000003,event=0xbc Number of DTLB page walker hits in the L2 Spec update: BDM69, BDM98 page_walker_loads.dtlb_l3 umask=0x14,period=2000003,event=0xbc Number of DTLB page walker hits in the L3 + XSNP Spec update: BDM69, BDM98 page_walker_loads.dtlb_memory umask=0x18,period=2000003,event=0xbc Number of DTLB page walker hits in Memory Spec update: BDM69, BDM98 page_walker_loads.itlb_l1 umask=0x21,period=2000003,event=0xbc Number of ITLB page walker hits in the L1+FB Spec update: BDM69, BDM98 page_walker_loads.itlb_l2 umask=0x22,period=2000003,event=0xbc Number of ITLB page walker hits in the L2 Spec update: BDM69, BDM98 page_walker_loads.itlb_l3 umask=0x24,period=2000003,event=0xbc Number of ITLB page walker hits in the L3 + XSNP Spec update: BDM69, BDM98 tlb_flush.dtlb_thread umask=0x1,period=100007,event=0xbd DTLB flush attempts of the thread-specific entries This event counts the number of DTLB flush attempts of the thread-specific entries tlb_flush.stlb_any umask=0x20,period=100007,event=0xbd STLB flush attempts This event counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on) This category represents fraction of slots where the processor's Frontend undersupplies its Backend bdw metrics This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-ops (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound idq_uops_not_delivered.core / (4 * cycles) Frontend_Bound TopdownL1 This category represents fraction of slots where the processor's Frontend undersupplies its Backend. SMT version; use when SMT is enabled and measuring per logical CPU This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-ops (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPU idq_uops_not_delivered.core / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) ))) Frontend_Bound_SMT TopdownL1_SMT This category represents fraction of slots wasted due to incorrect speculations This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example ( uops_issued.any - uops_retired.retire_slots + 4 * int_misc.recovery_cycles ) / (4 * cycles) Bad_Speculation This category represents fraction of slots wasted due to incorrect speculations. SMT version; use when SMT is enabled and measuring per logical CPU This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example. SMT version; use when SMT is enabled and measuring per logical CPU ( uops_issued.any - uops_retired.retire_slots + 4 * (( int_misc.recovery_cycles_any / 2 )) ) / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) ))) Bad_Speculation_SMT This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound 1 - ( (idq_uops_not_delivered.core / (4 * cycles)) + (( uops_issued.any - uops_retired.retire_slots + 4 * int_misc.recovery_cycles ) / (4 * cycles)) + (uops_retired.retire_slots / (4 * cycles)) ) Backend_Bound This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. SMT version; use when SMT is enabled and measuring per logical CPU This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. SMT version; use when SMT is enabled and measuring per logical CPU 1 - ( (idq_uops_not_delivered.core / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )))) + (( uops_issued.any - uops_retired.retire_slots + 4 * (( int_misc.recovery_cycles_any / 2 )) ) / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )))) + (uops_retired.retire_slots / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )))) ) Backend_Bound_SMT This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum 4 uops retired per cycle has been achieved. Maximizing Retiring typically increases the Instruction-Per-Cycle metric. Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Microcode assists are categorized under Retiring. They hurt performance and can often be avoided uops_retired.retire_slots / (4 * cycles) Retiring This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. SMT version; use when SMT is enabled and measuring per logical CPU This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum 4 uops retired per cycle has been achieved. Maximizing Retiring typically increases the Instruction-Per-Cycle metric. Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Microcode assists are categorized under Retiring. They hurt performance and can often be avoided. SMT version; use when SMT is enabled and measuring per logical CPU uops_retired.retire_slots / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) ))) Retiring_SMT Instructions Per Cycle (per Logical Processor) Pipeline;Retire Instruction per taken branch inst_retired.any / br_inst_retired.near_taken IpTB Branches;Fetch_BW;PGO Branch instructions per taken branch br_inst_retired.all_branches / br_inst_retired.near_taken BpTB Branches;PGO Rough Estimation of fraction of fetched lines bytes that were likely (includes speculatively fetches) consumed by program instructions min( 1 , idq.mite_uops / ( (uops_retired.retire_slots / inst_retired.any) * 16 * ( icache.hit + icache.misses ) / 4.0 ) ) PGO;IcMiss Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache) idq.dsb_uops / (( idq.dsb_uops + lsd.uops + idq.mite_uops + idq.ms_uops ) ) DSB;Fetch_BW Cycles Per Instruction (per Logical Processor) 1 / (inst_retired.any / cycles) Per-Logical Processor actual clocks when the Logical Processor is active Total issue-pipeline slots (per-Physical Core) 4 * cycles 4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )) SLOTS_SMT TopDownL1_SMT Instructions per Load (lower number means higher occurance rate) inst_retired.any / mem_uops_retired.all_loads IpL Instruction_Type Instructions per Store (lower number means higher occurance rate) inst_retired.any / mem_uops_retired.all_stores IpS Instructions per Branch (lower number means higher occurance rate) inst_retired.any / br_inst_retired.all_branches IpB Branches;Instruction_Type Instruction per (near) call (lower number means higher occurance rate) inst_retired.any / br_inst_retired.near_call IpCall Branches inst_retired.any / cycles inst_retired.any / (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )) CoreIPC_SMT Floating Point Operations Per Cycle (( 1 * ( fp_arith_inst_retired.scalar_single + fp_arith_inst_retired.scalar_double ) + 2 * fp_arith_inst_retired.128b_packed_double + 4 * ( fp_arith_inst_retired.128b_packed_single + fp_arith_inst_retired.256b_packed_double ) + 8 * fp_arith_inst_retired.256b_packed_single )) / cycles FLOPc FLOPS (( 1 * ( fp_arith_inst_retired.scalar_single + fp_arith_inst_retired.scalar_double ) + 2 * fp_arith_inst_retired.128b_packed_double + 4 * ( fp_arith_inst_retired.128b_packed_single + fp_arith_inst_retired.256b_packed_double ) + 8 * fp_arith_inst_retired.256b_packed_single )) / (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )) FLOPc_SMT FLOPS_SMT uops_executed.thread / (( cpu@uops_executed.core\,cmask\=1@ / 2 ) if #smt_on else uops_executed.cycles_ge_1_uop_exec) Branch Misprediction Cost: Fraction of TopDown slots wasted per non-speculative branch misprediction (jeclear) ( ((br_misp_retired.all_branches / ( br_misp_retired.all_branches + machine_clears.count )) * (( uops_issued.any - uops_retired.retire_slots + 4 * int_misc.recovery_cycles ) / (4 * cycles))) + (4 * idq_uops_not_delivered.cycles_0_uops_deliv.core / (4 * cycles)) * (12 * ( br_misp_retired.all_branches + machine_clears.count + baclears.any ) / cycles) / (4 * idq_uops_not_delivered.cycles_0_uops_deliv.core / (4 * cycles)) ) * (4 * cycles) / br_misp_retired.all_branches Branch_Misprediction_Cost BrMispredicts ( ((br_misp_retired.all_branches / ( br_misp_retired.all_branches + machine_clears.count )) * (( uops_issued.any - uops_retired.retire_slots + 4 * (( int_misc.recovery_cycles_any / 2 )) ) / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) ))))) + (4 * idq_uops_not_delivered.cycles_0_uops_deliv.core / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )))) * (12 * ( br_misp_retired.all_branches + machine_clears.count + baclears.any ) / cycles) / (4 * idq_uops_not_delivered.cycles_0_uops_deliv.core / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )))) ) * (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) ))) / br_misp_retired.all_branches Branch_Misprediction_Cost_SMT BrMispredicts_SMT Number of Instructions per non-speculative Branch Misprediction (JEClear) inst_retired.any / br_misp_retired.all_branches IpMispredict Core actual clocks when any Logical Processor is active on the Physical Core ( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) ) Actual Average Latency for L1 data-cache miss demand loads (in core cycles) Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor) l1d_pend_miss.pending / l1d_pend_miss.pending_cycles ( cpu@itlb_misses.walk_duration\,cmask\=1@ + cpu@dtlb_load_misses.walk_duration\,cmask\=1@ + cpu@dtlb_store_misses.walk_duration\,cmask\=1@ + 7 * ( dtlb_store_misses.walk_completed + dtlb_load_misses.walk_completed + itlb_misses.walk_completed ) ) / cycles ( cpu@itlb_misses.walk_duration\,cmask\=1@ + cpu@dtlb_load_misses.walk_duration\,cmask\=1@ + cpu@dtlb_store_misses.walk_duration\,cmask\=1@ + 7 * ( dtlb_store_misses.walk_completed + dtlb_load_misses.walk_completed + itlb_misses.walk_completed ) ) / (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )) Page_Walks_Utilization_SMT TLB_SMT Average data fill bandwidth to the L1 data cache [GB / sec] 64 * l1d.replacement / 1000000000 / duration_time L1D_Cache_Fill_BW Memory_BW Average data fill bandwidth to the L2 cache [GB / sec] 64 * l2_lines_in.all / 1000000000 / duration_time L2_Cache_Fill_BW Average per-core data fill bandwidth to the L3 cache [GB / sec] 64 * longest_lat_cache.miss / 1000000000 / duration_time L3_Cache_Fill_BW L1 cache true misses per kilo instruction for retired demand loads 1000 * mem_load_uops_retired.l1_miss / inst_retired.any L1MPKI Cache_Misses L2 cache true misses per kilo instruction for retired demand loads 1000 * mem_load_uops_retired.l2_miss / inst_retired.any L2MPKI L2 cache misses per kilo instruction for all request types (including speculative) 1000 * l2_rqsts.miss / inst_retired.any L2MPKI_All L2 cache hits per kilo instruction for all request types (including speculative) 1000 * ( l2_rqsts.references - l2_rqsts.miss ) / inst_retired.any L2HPKI_All L3 cache true misses per kilo instruction for retired demand loads 1000 * mem_load_uops_retired.l3_miss / inst_retired.any L3MPKI ( (( 1 * ( fp_arith_inst_retired.scalar_single + fp_arith_inst_retired.scalar_double ) + 2 * fp_arith_inst_retired.128b_packed_double + 4 * ( fp_arith_inst_retired.128b_packed_single + fp_arith_inst_retired.256b_packed_double ) + 8 * fp_arith_inst_retired.256b_packed_single )) / 1000000000 ) / duration_time Fraction of cycles where both hardware Logical Processors were active Average external Memory Bandwidth Use for reads and writes [GB / sec] 64 * ( arb@event\=0x81\,umask\=0x1@ + arb@event\=0x84\,umask\=0x1@ ) / 1000000 / duration_time / 1000 DRAM_BW_Use umask=0xc1,period=200003,event=0x24 Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache umask=0xc2,period=200003,event=0x24 umask=0xc4,period=200003,event=0x24 umask=0xd0,period=200003,event=0x24 umask=0x1,period=2000003,cmask=1,event=0x48 umask=0x1,any=1,period=2000003,cmask=1,event=0x48 umask=0x2,period=2000003,cmask=1,event=0x48 umask=0x1,period=2000003,cmask=1,event=0x60 umask=0x1,period=2000003,cmask=6,event=0x60 umask=0x4,period=2000003,cmask=1,event=0x60 umask=0x8,period=2000003,cmask=1,event=0x60 Retired load uops with locked access. (Precise Event - PEBS) Spec update: BDM35. Supports address when precise (Precise event) This is a precise version (that is, uses PEBS) of the event that counts load uops with locked access retired to the architected path Spec update: BDM35. Supports address when precise (Precise event) Retired load uops with L2 cache hits as data sources. (Precise Event - PEBS) Spec update: BDM35. Supports address when precise (Precise event) This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were hits in the mid-level (L2) cache Spec update: BDM35. Supports address when precise (Precise event) Hit in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS) Spec update: BDM100. Supports address when precise (Precise event) This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required Spec update: BDM100. Supports address when precise (Precise event) Miss in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS) Spec update: BDM100, BDE70. Supports address when precise (Precise event) Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS) Spec update: BDM100. Supports address when precise (Precise event) This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache Spec update: BDM100. Supports address when precise (Precise event) Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS) Spec update: BDM100. Supports address when precise (Precise event) This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache Spec update: BDM100. Supports address when precise (Precise event) Retired load uops which data sources were HitM responses from shared L3. (Precise Event - PEBS) Spec update: BDM100. Supports address when precise (Precise event) This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were HitM responses from a core on same socket (shared L3) Spec update: BDM100. Supports address when precise (Precise event) Retired load uops which data sources were hits in L3 without snoops required. (Precise Event - PEBS) Spec update: BDM100. Supports address when precise (Precise event) This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required Spec update: BDM100. Supports address when precise (Precise event) This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches. This is a precise event Spec update: BDE70, BDM100. Supports address when precise offcore_response.demand_data_rd.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010001 Counts demand data reads have any response type offcore_response.demand_data_rd.supplier_none.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020001 Counts demand data reads offcore_response.demand_data_rd.supplier_none.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020001 offcore_response.demand_data_rd.supplier_none.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020001 offcore_response.demand_data_rd.supplier_none.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020001 offcore_response.demand_data_rd.supplier_none.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020001 offcore_response.demand_data_rd.supplier_none.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020001 offcore_response.demand_data_rd.l3_hit.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0001 offcore_response.demand_data_rd.l3_hit.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0001 offcore_response.demand_data_rd.l3_hit.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0001 offcore_response.demand_data_rd.l3_hit.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0001 offcore_response.demand_data_rd.l3_hit.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0001 offcore_response.demand_data_rd.l3_hit.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0001 offcore_response.demand_rfo.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010002 Counts all demand data writes (RFOs) have any response type offcore_response.demand_rfo.l3_hit.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0002 Counts all demand data writes (RFOs) offcore_response.demand_rfo.l3_hit.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0002 offcore_response.demand_rfo.l3_hit.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0002 offcore_response.demand_rfo.l3_hit.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0002 offcore_response.demand_rfo.l3_hit.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0002 offcore_response.demand_rfo.l3_hit.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0002 offcore_response.demand_code_rd.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010004 Counts all demand code reads have any response type offcore_response.demand_code_rd.supplier_none.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020004 Counts all demand code reads offcore_response.demand_code_rd.supplier_none.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020004 offcore_response.demand_code_rd.supplier_none.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020004 offcore_response.demand_code_rd.supplier_none.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020004 offcore_response.demand_code_rd.supplier_none.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020004 offcore_response.demand_code_rd.supplier_none.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020004 offcore_response.demand_code_rd.l3_hit.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0004 offcore_response.demand_code_rd.l3_hit.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0004 offcore_response.demand_code_rd.l3_hit.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0004 offcore_response.demand_code_rd.l3_hit.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0004 offcore_response.demand_code_rd.l3_hit.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0004 offcore_response.demand_code_rd.l3_hit.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0004 offcore_response.corewb.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010008 Counts writebacks (modified to exclusive) have any response type offcore_response.corewb.supplier_none.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020008 Counts writebacks (modified to exclusive) offcore_response.corewb.supplier_none.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020008 offcore_response.corewb.supplier_none.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020008 offcore_response.corewb.supplier_none.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020008 offcore_response.corewb.supplier_none.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020008 offcore_response.corewb.supplier_none.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020008 offcore_response.corewb.l3_hit.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0008 offcore_response.corewb.l3_hit.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0008 offcore_response.corewb.l3_hit.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0008 offcore_response.corewb.l3_hit.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0008 offcore_response.corewb.l3_hit.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0008 offcore_response.corewb.l3_hit.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0008 offcore_response.pf_l2_data_rd.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010010 Counts prefetch (that bring data to L2) data reads have any response type offcore_response.pf_l2_data_rd.supplier_none.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020010 Counts prefetch (that bring data to L2) data reads offcore_response.pf_l2_data_rd.supplier_none.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020010 offcore_response.pf_l2_data_rd.supplier_none.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020010 offcore_response.pf_l2_data_rd.supplier_none.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020010 offcore_response.pf_l2_data_rd.supplier_none.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020010 offcore_response.pf_l2_data_rd.supplier_none.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020010 offcore_response.pf_l2_data_rd.l3_hit.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0010 offcore_response.pf_l2_data_rd.l3_hit.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0010 offcore_response.pf_l2_data_rd.l3_hit.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0010 offcore_response.pf_l2_data_rd.l3_hit.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0010 offcore_response.pf_l2_data_rd.l3_hit.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0010 offcore_response.pf_l2_data_rd.l3_hit.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0010 offcore_response.pf_l2_rfo.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010020 Counts all prefetch (that bring data to L2) RFOs have any response type offcore_response.pf_l2_rfo.supplier_none.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020020 Counts all prefetch (that bring data to L2) RFOs offcore_response.pf_l2_rfo.supplier_none.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020020 offcore_response.pf_l2_rfo.supplier_none.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020020 offcore_response.pf_l2_rfo.supplier_none.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020020 offcore_response.pf_l2_rfo.supplier_none.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020020 offcore_response.pf_l2_rfo.supplier_none.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020020 offcore_response.pf_l2_rfo.l3_hit.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0020 offcore_response.pf_l2_rfo.l3_hit.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0020 offcore_response.pf_l2_rfo.l3_hit.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0020 offcore_response.pf_l2_rfo.l3_hit.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0020 offcore_response.pf_l2_rfo.l3_hit.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0020 offcore_response.pf_l2_rfo.l3_hit.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0020 offcore_response.pf_l2_code_rd.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010040 Counts all prefetch (that bring data to LLC only) code reads have any response type offcore_response.pf_l2_code_rd.supplier_none.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020040 Counts all prefetch (that bring data to LLC only) code reads offcore_response.pf_l2_code_rd.supplier_none.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020040 offcore_response.pf_l2_code_rd.supplier_none.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020040 offcore_response.pf_l2_code_rd.supplier_none.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020040 offcore_response.pf_l2_code_rd.supplier_none.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020040 offcore_response.pf_l2_code_rd.supplier_none.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020040 offcore_response.pf_l2_code_rd.l3_hit.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0040 offcore_response.pf_l2_code_rd.l3_hit.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0040 offcore_response.pf_l2_code_rd.l3_hit.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0040 offcore_response.pf_l2_code_rd.l3_hit.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0040 offcore_response.pf_l2_code_rd.l3_hit.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0040 offcore_response.pf_l2_code_rd.l3_hit.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0040 offcore_response.pf_l3_data_rd.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010080 Counts all prefetch (that bring data to LLC only) data reads have any response type offcore_response.pf_l3_data_rd.supplier_none.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020080 Counts all prefetch (that bring data to LLC only) data reads offcore_response.pf_l3_data_rd.supplier_none.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020080 offcore_response.pf_l3_data_rd.supplier_none.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020080 offcore_response.pf_l3_data_rd.supplier_none.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020080 offcore_response.pf_l3_data_rd.supplier_none.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020080 offcore_response.pf_l3_data_rd.supplier_none.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020080 offcore_response.pf_l3_data_rd.l3_hit.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0080 offcore_response.pf_l3_data_rd.l3_hit.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0080 offcore_response.pf_l3_data_rd.l3_hit.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0080 offcore_response.pf_l3_data_rd.l3_hit.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0080 offcore_response.pf_l3_data_rd.l3_hit.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0080 offcore_response.pf_l3_data_rd.l3_hit.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0080 offcore_response.pf_l3_rfo.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010100 Counts all prefetch (that bring data to LLC only) RFOs have any response type offcore_response.pf_l3_rfo.supplier_none.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020100 Counts all prefetch (that bring data to LLC only) RFOs offcore_response.pf_l3_rfo.supplier_none.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020100 offcore_response.pf_l3_rfo.supplier_none.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020100 offcore_response.pf_l3_rfo.supplier_none.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020100 offcore_response.pf_l3_rfo.supplier_none.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020100 offcore_response.pf_l3_rfo.supplier_none.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020100 offcore_response.pf_l3_rfo.l3_hit.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0100 offcore_response.pf_l3_rfo.l3_hit.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0100 offcore_response.pf_l3_rfo.l3_hit.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0100 offcore_response.pf_l3_rfo.l3_hit.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0100 offcore_response.pf_l3_rfo.l3_hit.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0100 offcore_response.pf_l3_rfo.l3_hit.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0100 offcore_response.pf_l3_code_rd.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010200 Counts prefetch (that bring data to LLC only) code reads have any response type offcore_response.pf_l3_code_rd.supplier_none.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020200 Counts prefetch (that bring data to LLC only) code reads offcore_response.pf_l3_code_rd.supplier_none.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020200 offcore_response.pf_l3_code_rd.supplier_none.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020200 offcore_response.pf_l3_code_rd.supplier_none.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020200 offcore_response.pf_l3_code_rd.supplier_none.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020200 offcore_response.pf_l3_code_rd.supplier_none.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020200 offcore_response.pf_l3_code_rd.l3_hit.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0200 offcore_response.pf_l3_code_rd.l3_hit.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0200 offcore_response.pf_l3_code_rd.l3_hit.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0200 offcore_response.pf_l3_code_rd.l3_hit.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0200 offcore_response.pf_l3_code_rd.l3_hit.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0200 offcore_response.pf_l3_code_rd.l3_hit.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0200 offcore_response.other.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000018000 Counts any other requests have any response type offcore_response.other.supplier_none.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080028000 Counts any other requests offcore_response.other.supplier_none.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100028000 offcore_response.other.supplier_none.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200028000 offcore_response.other.supplier_none.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400028000 offcore_response.other.supplier_none.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000028000 offcore_response.other.supplier_none.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80028000 offcore_response.other.l3_hit.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C8000 offcore_response.other.l3_hit.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C8000 offcore_response.other.l3_hit.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C8000 offcore_response.other.l3_hit.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C8000 offcore_response.other.l3_hit.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C8000 offcore_response.other.l3_hit.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C8000 offcore_response.all_pf_data_rd.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010090 Counts all prefetch data reads have any response type offcore_response.all_pf_data_rd.supplier_none.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020090 Counts all prefetch data reads offcore_response.all_pf_data_rd.supplier_none.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020090 offcore_response.all_pf_data_rd.supplier_none.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020090 offcore_response.all_pf_data_rd.supplier_none.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020090 offcore_response.all_pf_data_rd.supplier_none.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020090 offcore_response.all_pf_data_rd.supplier_none.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020090 offcore_response.all_pf_data_rd.l3_hit.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0090 offcore_response.all_pf_data_rd.l3_hit.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0090 offcore_response.all_pf_data_rd.l3_hit.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0090 offcore_response.all_pf_data_rd.l3_hit.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0090 offcore_response.all_pf_data_rd.l3_hit.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0090 offcore_response.all_pf_data_rd.l3_hit.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0090 offcore_response.all_pf_rfo.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010120 Counts prefetch RFOs have any response type offcore_response.all_pf_rfo.supplier_none.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020120 Counts prefetch RFOs offcore_response.all_pf_rfo.supplier_none.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020120 offcore_response.all_pf_rfo.supplier_none.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020120 offcore_response.all_pf_rfo.supplier_none.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020120 offcore_response.all_pf_rfo.supplier_none.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020120 offcore_response.all_pf_rfo.supplier_none.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020120 offcore_response.all_pf_rfo.l3_hit.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0120 offcore_response.all_pf_rfo.l3_hit.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0120 offcore_response.all_pf_rfo.l3_hit.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0120 offcore_response.all_pf_rfo.l3_hit.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0120 offcore_response.all_pf_rfo.l3_hit.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0120 offcore_response.all_pf_rfo.l3_hit.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0120 offcore_response.all_pf_code_rd.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010240 Counts all prefetch code reads have any response type offcore_response.all_pf_code_rd.supplier_none.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020240 Counts all prefetch code reads offcore_response.all_pf_code_rd.supplier_none.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020240 offcore_response.all_pf_code_rd.supplier_none.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020240 offcore_response.all_pf_code_rd.supplier_none.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020240 offcore_response.all_pf_code_rd.supplier_none.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020240 offcore_response.all_pf_code_rd.supplier_none.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020240 offcore_response.all_pf_code_rd.l3_hit.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0240 offcore_response.all_pf_code_rd.l3_hit.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0240 offcore_response.all_pf_code_rd.l3_hit.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0240 offcore_response.all_pf_code_rd.l3_hit.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0240 offcore_response.all_pf_code_rd.l3_hit.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0240 offcore_response.all_pf_code_rd.l3_hit.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0240 offcore_response.all_data_rd.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010091 Counts all demand & prefetch data reads have any response type offcore_response.all_data_rd.supplier_none.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020091 Counts all demand & prefetch data reads offcore_response.all_data_rd.supplier_none.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020091 offcore_response.all_data_rd.supplier_none.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020091 offcore_response.all_data_rd.supplier_none.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020091 offcore_response.all_data_rd.supplier_none.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020091 offcore_response.all_data_rd.supplier_none.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020091 offcore_response.all_data_rd.l3_hit.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0091 offcore_response.all_data_rd.l3_hit.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0091 offcore_response.all_data_rd.l3_hit.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0091 offcore_response.all_data_rd.l3_hit.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0091 offcore_response.all_data_rd.l3_hit.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0091 offcore_response.all_data_rd.l3_hit.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0091 offcore_response.all_rfo.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010122 Counts all demand & prefetch RFOs have any response type offcore_response.all_rfo.supplier_none.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020122 Counts all demand & prefetch RFOs offcore_response.all_rfo.supplier_none.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020122 offcore_response.all_rfo.supplier_none.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020122 offcore_response.all_rfo.supplier_none.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020122 offcore_response.all_rfo.supplier_none.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020122 offcore_response.all_rfo.supplier_none.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020122 offcore_response.all_rfo.l3_hit.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0122 offcore_response.all_rfo.l3_hit.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0122 offcore_response.all_rfo.l3_hit.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0122 offcore_response.all_rfo.l3_hit.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0122 offcore_response.all_rfo.l3_hit.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0122 offcore_response.all_rfo.l3_hit.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0122 Number of transitions from AVX-256 to legacy SSE when penalty applicable (Precise Event) Spec update: BDM30 This is a precise version (that is, uses PEBS) of the event that counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable Spec update: BDM30 Number of transitions from legacy SSE to AVX-256 when penalty applicable (Precise Event) Spec update: BDM30 This is a precise version (that is, uses PEBS) of the event that counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable Spec update: BDM30 Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. (RSQRT for single precision?) Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired. Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element Number of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. (RSQRT for single-precision?) output - Numeric Overflow, Numeric Underflow, Inexact Result (Precise Event) This is a precise version (that is, uses PEBS) of the event that counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid input - Invalid Operation, Denormal Operand, SNaN Operand (Precise Event) This is a precise version (that is, uses PEBS) of the event that counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid SSE* FP micro-code assist when output value is invalid. (Precise Event) This is a precise version (that is, uses PEBS) of the event that counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention Any input SSE* FP Assist - (Precise Event) This is a precise version (that is, uses PEBS) of the event that counts any input SSE* floating-point (FP) assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention umask=0x1e,period=100003,cmask=1,event=0xca Counts any FP_ASSIST umask was incrementing (Precise Event) This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1. Uses PEBS umask=0x4,period=2000003,cmask=1,event=0x79 umask=0x8,period=2000003,cmask=1,event=0x79 umask=0x10,period=2000003,cmask=1,event=0x79 umask=0x10,edge=1,period=2000003,cmask=1,event=0x79 umask=0x18,period=2000003,cmask=4,event=0x79 umask=0x18,period=2000003,cmask=1,event=0x79 umask=0x24,period=2000003,cmask=4,event=0x79 umask=0x24,period=2000003,cmask=1,event=0x79 umask=0x30,period=2000003,cmask=1,event=0x79 umask=0x30,edge=1,period=2000003,cmask=1,event=0x79 This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding “4 – x” when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:
a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;
b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions);
c. Instruction Decode Queue (IDQ) delivers four uops umask=0x1,period=2000003,cmask=4,event=0x9c umask=0x1,period=2000003,cmask=3,event=0x9c umask=0x1,period=2000003,cmask=2,event=0x9c umask=0x1,period=2000003,cmask=1,event=0x9c inv=1,umask=0x1,period=2000003,cmask=1,event=0x9c This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop.
MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.
Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 0–2 cycles Randomly selected loads with latency value being above 4 Spec update: BDM100, BDM35 (Must be precise) Counts randomly selected loads with latency value being above four Spec update: BDM100, BDM35 (Must be precise) Randomly selected loads with latency value being above 8 Spec update: BDM100, BDM35 (Must be precise) Counts randomly selected loads with latency value being above eight Spec update: BDM100, BDM35 (Must be precise) Randomly selected loads with latency value being above 16 Spec update: BDM100, BDM35 (Must be precise) Counts randomly selected loads with latency value being above 16 Spec update: BDM100, BDM35 (Must be precise) Randomly selected loads with latency value being above 32 Spec update: BDM100, BDM35 (Must be precise) Counts randomly selected loads with latency value being above 32 Spec update: BDM100, BDM35 (Must be precise) Randomly selected loads with latency value being above 64 Spec update: BDM100, BDM35 (Must be precise) Counts randomly selected loads with latency value being above 64 Spec update: BDM100, BDM35 (Must be precise) Randomly selected loads with latency value being above 128 Spec update: BDM100, BDM35 (Must be precise) Counts randomly selected loads with latency value being above 128 Spec update: BDM100, BDM35 (Must be precise) Randomly selected loads with latency value being above 256 Spec update: BDM100, BDM35 (Must be precise) Counts randomly selected loads with latency value being above 256 Spec update: BDM100, BDM35 (Must be precise) Randomly selected loads with latency value being above 512 Spec update: BDM100, BDM35 (Must be precise) Counts randomly selected loads with latency value being above 512 Spec update: BDM100, BDM35 (Must be precise) offcore_response.demand_data_rd.supplier_none.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020001 offcore_response.demand_data_rd.l3_hit.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0001 offcore_response.demand_data_rd.l3_miss_local_dram.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000001 offcore_response.demand_data_rd.l3_miss_local_dram.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000001 offcore_response.demand_data_rd.l3_miss_local_dram.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000001 offcore_response.demand_data_rd.l3_miss_local_dram.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000001 offcore_response.demand_data_rd.l3_miss_local_dram.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000001 offcore_response.demand_data_rd.l3_miss_local_dram.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000001 offcore_response.demand_data_rd.l3_miss_local_dram.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000001 offcore_response.demand_data_rd.l3_miss.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000001 offcore_response.demand_data_rd.l3_miss.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000001 offcore_response.demand_data_rd.l3_miss.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000001 offcore_response.demand_data_rd.l3_miss.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000001 offcore_response.demand_rfo.l3_hit.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0002 offcore_response.demand_rfo.l3_miss_local_dram.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000002 offcore_response.demand_rfo.l3_miss.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000002 offcore_response.demand_rfo.l3_miss.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000002 offcore_response.demand_rfo.l3_miss.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000002 offcore_response.demand_rfo.l3_miss.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000002 offcore_response.demand_code_rd.supplier_none.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020004 offcore_response.demand_code_rd.l3_hit.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0004 offcore_response.demand_code_rd.l3_miss_local_dram.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000004 offcore_response.demand_code_rd.l3_miss_local_dram.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000004 offcore_response.demand_code_rd.l3_miss_local_dram.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000004 offcore_response.demand_code_rd.l3_miss_local_dram.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000004 offcore_response.demand_code_rd.l3_miss_local_dram.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000004 offcore_response.demand_code_rd.l3_miss_local_dram.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000004 offcore_response.demand_code_rd.l3_miss_local_dram.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000004 offcore_response.demand_code_rd.l3_miss.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000004 offcore_response.demand_code_rd.l3_miss.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000004 offcore_response.demand_code_rd.l3_miss.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000004 offcore_response.demand_code_rd.l3_miss.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000004 offcore_response.corewb.supplier_none.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020008 offcore_response.corewb.l3_hit.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0008 offcore_response.corewb.l3_miss_local_dram.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000008 offcore_response.corewb.l3_miss_local_dram.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000008 offcore_response.corewb.l3_miss_local_dram.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000008 offcore_response.corewb.l3_miss_local_dram.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000008 offcore_response.corewb.l3_miss_local_dram.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000008 offcore_response.corewb.l3_miss_local_dram.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000008 offcore_response.corewb.l3_miss_local_dram.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000008 offcore_response.corewb.l3_miss.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000008 offcore_response.corewb.l3_miss.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000008 offcore_response.corewb.l3_miss.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000008 offcore_response.corewb.l3_miss.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000008 offcore_response.pf_l2_data_rd.supplier_none.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020010 offcore_response.pf_l2_data_rd.l3_hit.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0010 offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000010 offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000010 offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000010 offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000010 offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000010 offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000010 offcore_response.pf_l2_data_rd.l3_miss_local_dram.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000010 offcore_response.pf_l2_data_rd.l3_miss.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000010 offcore_response.pf_l2_data_rd.l3_miss.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000010 offcore_response.pf_l2_data_rd.l3_miss.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000010 offcore_response.pf_l2_data_rd.l3_miss.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000010 offcore_response.pf_l2_rfo.supplier_none.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020020 offcore_response.pf_l2_rfo.l3_hit.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0020 offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000020 offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000020 offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000020 offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000020 offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000020 offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000020 offcore_response.pf_l2_rfo.l3_miss_local_dram.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000020 offcore_response.pf_l2_rfo.l3_miss.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000020 offcore_response.pf_l2_rfo.l3_miss.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000020 offcore_response.pf_l2_rfo.l3_miss.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000020 offcore_response.pf_l2_rfo.l3_miss.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000020 offcore_response.pf_l2_code_rd.supplier_none.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020040 offcore_response.pf_l2_code_rd.l3_hit.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0040 offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000040 offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000040 offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000040 offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000040 offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000040 offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000040 offcore_response.pf_l2_code_rd.l3_miss_local_dram.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000040 offcore_response.pf_l2_code_rd.l3_miss.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000040 offcore_response.pf_l2_code_rd.l3_miss.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000040 offcore_response.pf_l2_code_rd.l3_miss.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000040 offcore_response.pf_l2_code_rd.l3_miss.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000040 offcore_response.pf_l3_data_rd.supplier_none.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020080 offcore_response.pf_l3_data_rd.l3_hit.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0080 offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000080 offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000080 offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000080 offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000080 offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000080 offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000080 offcore_response.pf_l3_data_rd.l3_miss_local_dram.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000080 offcore_response.pf_l3_data_rd.l3_miss.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000080 offcore_response.pf_l3_data_rd.l3_miss.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000080 offcore_response.pf_l3_data_rd.l3_miss.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000080 offcore_response.pf_l3_data_rd.l3_miss.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000080 offcore_response.pf_l3_rfo.supplier_none.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020100 offcore_response.pf_l3_rfo.l3_hit.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0100 offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000100 offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000100 offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000100 offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000100 offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000100 offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000100 offcore_response.pf_l3_rfo.l3_miss_local_dram.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000100 offcore_response.pf_l3_rfo.l3_miss.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000100 offcore_response.pf_l3_rfo.l3_miss.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000100 offcore_response.pf_l3_rfo.l3_miss.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000100 offcore_response.pf_l3_rfo.l3_miss.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000100 offcore_response.pf_l3_code_rd.supplier_none.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020200 offcore_response.pf_l3_code_rd.l3_hit.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0200 offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000200 offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000200 offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000200 offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000200 offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000200 offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000200 offcore_response.pf_l3_code_rd.l3_miss_local_dram.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000200 offcore_response.pf_l3_code_rd.l3_miss.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000200 offcore_response.pf_l3_code_rd.l3_miss.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000200 offcore_response.pf_l3_code_rd.l3_miss.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000200 offcore_response.pf_l3_code_rd.l3_miss.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000200 offcore_response.other.supplier_none.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000028000 offcore_response.other.l3_hit.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C8000 offcore_response.other.l3_miss_local_dram.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084008000 offcore_response.other.l3_miss_local_dram.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104008000 offcore_response.other.l3_miss_local_dram.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204008000 offcore_response.other.l3_miss_local_dram.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404008000 offcore_response.other.l3_miss_local_dram.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004008000 offcore_response.other.l3_miss_local_dram.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004008000 offcore_response.other.l3_miss_local_dram.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84008000 offcore_response.other.l3_miss.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC008000 offcore_response.other.l3_miss.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C008000 offcore_response.other.l3_miss.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C008000 offcore_response.other.l3_miss.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C008000 offcore_response.all_pf_data_rd.supplier_none.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020090 offcore_response.all_pf_data_rd.l3_hit.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0090 offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000090 offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000090 offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000090 offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000090 offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000090 offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000090 offcore_response.all_pf_data_rd.l3_miss_local_dram.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000090 offcore_response.all_pf_data_rd.l3_miss.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000090 offcore_response.all_pf_data_rd.l3_miss.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000090 offcore_response.all_pf_data_rd.l3_miss.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000090 offcore_response.all_pf_data_rd.l3_miss.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000090 offcore_response.all_pf_rfo.supplier_none.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020120 offcore_response.all_pf_rfo.l3_hit.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0120 offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000120 offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000120 offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000120 offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000120 offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000120 offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000120 offcore_response.all_pf_rfo.l3_miss_local_dram.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000120 offcore_response.all_pf_rfo.l3_miss.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000120 offcore_response.all_pf_rfo.l3_miss.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000120 offcore_response.all_pf_rfo.l3_miss.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000120 offcore_response.all_pf_rfo.l3_miss.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000120 offcore_response.all_pf_code_rd.supplier_none.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020240 offcore_response.all_pf_code_rd.l3_hit.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0240 offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000240 offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000240 offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000240 offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000240 offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000240 offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000240 offcore_response.all_pf_code_rd.l3_miss_local_dram.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000240 offcore_response.all_pf_code_rd.l3_miss.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000240 offcore_response.all_pf_code_rd.l3_miss.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000240 offcore_response.all_pf_code_rd.l3_miss.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000240 offcore_response.all_pf_code_rd.l3_miss.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000240 offcore_response.all_data_rd.supplier_none.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020091 offcore_response.all_data_rd.l3_hit.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0091 offcore_response.all_data_rd.l3_miss_local_dram.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000091 offcore_response.all_data_rd.l3_miss_local_dram.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000091 offcore_response.all_data_rd.l3_miss_local_dram.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000091 offcore_response.all_data_rd.l3_miss_local_dram.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000091 offcore_response.all_data_rd.l3_miss_local_dram.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000091 offcore_response.all_data_rd.l3_miss_local_dram.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000091 offcore_response.all_data_rd.l3_miss_local_dram.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000091 offcore_response.all_data_rd.l3_miss.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000091 offcore_response.all_data_rd.l3_miss.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000091 offcore_response.all_data_rd.l3_miss.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000091 offcore_response.all_data_rd.l3_miss.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000091 offcore_response.all_rfo.supplier_none.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020122 offcore_response.all_rfo.l3_hit.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0122 offcore_response.all_rfo.l3_miss_local_dram.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000122 offcore_response.all_rfo.l3_miss_local_dram.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000122 offcore_response.all_rfo.l3_miss_local_dram.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000122 offcore_response.all_rfo.l3_miss_local_dram.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000122 offcore_response.all_rfo.l3_miss_local_dram.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000122 offcore_response.all_rfo.l3_miss_local_dram.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000122 offcore_response.all_rfo.l3_miss_local_dram.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000122 offcore_response.all_rfo.l3_miss.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000122 offcore_response.all_rfo.l3_miss.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000122 offcore_response.all_rfo.l3_miss.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000122 offcore_response.all_rfo.l3_miss.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000122 umask=0x1,edge=1,period=100007,cmask=1,event=0x5c umask=0x3,period=2000003,cmask=1,event=0xd umask=0x3,any=1,period=2000003,cmask=1,event=0xd inv=1,umask=0x1,period=2000003,cmask=1,event=0xe inv=1,umask=0x1,edge=1,period=200003,cmask=1,event=0x5e This event counts resource-related stall cycles umask=0x1,period=2000003,cmask=1,event=0xa3 umask=0x2,period=2000003,cmask=2,event=0xa3 umask=0x4,period=2000003,cmask=4,event=0xa3 umask=0x5,period=2000003,cmask=5,event=0xa3 umask=0x6,period=2000003,cmask=6,event=0xa3 umask=0x8,period=2000003,cmask=8,event=0xa3 umask=0xc,period=2000003,cmask=12,event=0xa3 umask=0x1,period=2000003,cmask=4,event=0xa8 umask=0x1,period=2000003,cmask=1,event=0xa8 inv=1,umask=0x1,period=2000003,cmask=1,event=0xb1 umask=0x1,period=2000003,cmask=1,event=0xb1 umask=0x1,period=2000003,cmask=2,event=0xb1 umask=0x1,period=2000003,cmask=3,event=0xb1 umask=0x1,period=2000003,cmask=4,event=0xb1 umask=0x2,period=2000003,cmask=1,event=0xb1 umask=0x2,period=2000003,cmask=2,event=0xb1 umask=0x2,period=2000003,cmask=3,event=0xb1 umask=0x2,period=2000003,cmask=4,event=0xb1 FP operations retired. X87 FP operations that have no exceptions: (Precise event) This is a precise version (that is, uses PEBS) of the event that counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling (Precise event) inv=1,umask=0x1,period=2000003,cmask=1,event=0xc2 Cycles no executable uops retired (Precise Event) This is a precise version (that is, uses PEBS) of the event that counts cycles without actually retired uops inv=1,umask=0x1,period=2000003,cmask=10,event=0xc2 Number of cycles using always true condition applied to PEBS uops retired event (Precise event) Number of cycles using always true condition (uops_ret < 16) applied to PEBS uops retired event (Precise event) umask=0x1,edge=1,period=100003,cmask=1,event=0xc3 Counts all not taken macro branch instructions retired. (Precise Event) This is a precise version (that is, uses PEBS) of the event that counts not taken branch instructions retired Counts the number of far branch instructions retired.(Precise Event) Spec update: BDW98 This is a precise version (that is, uses PEBS) of the event that counts far branch instructions retired Spec update: BDW98 unc_cbo_xsnp_response.miss_xcore umask=0x41,event=0x22 Unit: uncore_cbox A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core uncore A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core unc_cbo_xsnp_response.miss_eviction umask=0x81,event=0x22 Unit: uncore_cbox A cross-core snoop resulted from L3 Eviction which misses in some processor core A cross-core snoop resulted from L3 Eviction which misses in some processor core unc_cbo_xsnp_response.hit_xcore umask=0x44,event=0x22 Unit: uncore_cbox A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core unc_cbo_xsnp_response.hitm_xcore umask=0x48,event=0x22 Unit: uncore_cbox A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core unc_cbo_cache_lookup.read_m umask=0x11,event=0x34 Unit: uncore_cbox L3 Lookup read request that access cache and found line in M-state L3 Lookup read request that access cache and found line in M-state unc_cbo_cache_lookup.write_m umask=0x21,event=0x34 Unit: uncore_cbox L3 Lookup write request that access cache and found line in M-state L3 Lookup write request that access cache and found line in M-state unc_cbo_cache_lookup.any_m umask=0x81,event=0x34 Unit: uncore_cbox L3 Lookup any request that access cache and found line in M-state L3 Lookup any request that access cache and found line in M-state unc_cbo_cache_lookup.read_i umask=0x18,event=0x34 Unit: uncore_cbox L3 Lookup read request that access cache and found line in I-state L3 Lookup read request that access cache and found line in I-state unc_cbo_cache_lookup.any_i umask=0x88,event=0x34 Unit: uncore_cbox L3 Lookup any request that access cache and found line in I-state L3 Lookup any request that access cache and found line in I-state unc_cbo_cache_lookup.read_mesi umask=0x1f,event=0x34 Unit: uncore_cbox L3 Lookup read request that access cache and found line in any MESI-state L3 Lookup read request that access cache and found line in any MESI-state unc_cbo_cache_lookup.write_mesi umask=0x2f,event=0x34 Unit: uncore_cbox L3 Lookup write request that access cache and found line in MESI-state L3 Lookup write request that access cache and found line in MESI-state unc_cbo_cache_lookup.any_mesi umask=0x8f,event=0x34 Unit: uncore_cbox L3 Lookup any request that access cache and found line in MESI-state L3 Lookup any request that access cache and found line in MESI-state unc_cbo_cache_lookup.any_es umask=0x86,event=0x34 Unit: uncore_cbox L3 Lookup any request that access cache and found line in E or S-state L3 Lookup any request that access cache and found line in E or S-state unc_cbo_cache_lookup.read_es umask=0x16,event=0x34 Unit: uncore_cbox L3 Lookup read request that access cache and found line in E or S-state L3 Lookup read request that access cache and found line in E or S-state unc_cbo_cache_lookup.write_es umask=0x26,event=0x34 Unit: uncore_cbox L3 Lookup write request that access cache and found line in E or S-state L3 Lookup write request that access cache and found line in E or S-state unc_arb_trk_occupancy.all umask=0x01,event=0x80 Unit: uncore_arb Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic uncore_arb unc_arb_trk_occupancy.drd_direct umask=0x02,event=0x80 Unit: uncore_arb Each cycle count number of 'valid' coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case Each cycle count number of 'valid' coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case unc_arb_trk_requests.all umask=0x01,event=0x81 Unit: uncore_arb Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic unc_arb_trk_requests.drd_direct umask=0x02,event=0x81 Unit: uncore_arb Number of Core coherent Data Read entries allocated in DirectData mode Number of Core coherent Data Read entries allocated in DirectData mode unc_arb_trk_requests.writes umask=0x20,event=0x81 Unit: uncore_arb Number of Writes allocated - any write transactions: full/partials writes and evictions Number of Writes allocated - any write transactions: full/partials writes and evictions unc_arb_coh_trk_requests.all umask=0x01,event=0x84 Unit: uncore_arb Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc unc_arb_trk_occupancy.cycles_with_any_request umask=0x01,cmask=1,event=0x80 Unit: uncore_arb Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.; Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC unc_clock.socket umask=0x01,event=0 Unit: uncore_ncu This 48-bit fixed counter counts the UCLK cycles This 48-bit fixed counter counts the UCLK cycles uncore_ncu bdx metrics ( itlb_misses.walk_duration + dtlb_load_misses.walk_duration + dtlb_store_misses.walk_duration + 7 * ( dtlb_store_misses.walk_completed + dtlb_load_misses.walk_completed + itlb_misses.walk_completed ) ) / ( 2 * cycles ) ( itlb_misses.walk_duration + dtlb_load_misses.walk_duration + dtlb_store_misses.walk_duration + 7 * ( dtlb_store_misses.walk_completed + dtlb_load_misses.walk_completed + itlb_misses.walk_completed ) ) / ( 2 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )) ) ( 64 * ( uncore_imc@cas_count_read@ + uncore_imc@cas_count_write@ ) / 1000000000 ) / duration_time Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches 1000000000 * ( cbox@event\=0x36\,umask\=0x3\,filter_opc\=0x182@ / cbox@event\=0x35\,umask\=0x3\,filter_opc\=0x182@ ) / ( cbox_0@event\=0x0@ / duration_time ) DRAM_Read_Latency Memory_Lat Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches cbox@event\=0x36\,umask\=0x3\,filter_opc\=0x182@ / cbox@event\=0x36\,umask\=0x3\,filter_opc\=0x182\,thresh\=1@ DRAM_Parallel_Reads Socket actual clocks when any core is active on that socket cbox_0@event\=0x0@ Socket_CLKS Retired load uops that miss the STLB Supports address when precise (Precise event) This event counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault Supports address when precise (Precise event) Retired store uops that miss the STLB Supports address when precise (Precise event) This event counts store uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault Supports address when precise (Precise event) Retired load uops with locked access Supports address when precise. Spec update: BDM35 (Precise event) This event counts load uops with locked access retired to the architected path Supports address when precise. Spec update: BDM35 (Precise event) Retired load uops that split across a cacheline boundary Supports address when precise (Precise event) This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K) Supports address when precise (Precise event) Retired store uops that split across a cacheline boundary Supports address when precise (Precise event) This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K) Supports address when precise (Precise event) All retired load uops Supports address when precise (Precise event) This event counts load uops retired to the architected path with a filter on bits 0 and 1 applied.
Note: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement. This event also counts SW prefetches Supports address when precise (Precise event) All retired store uops Supports address when precise (Precise event) This event counts store uops retired to the architected path with a filter on bits 0 and 1 applied.
Note: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement Supports address when precise (Precise event) Retired load uops with L1 cache hits as data sources Supports address when precise (Precise event) This event counts retired load uops which data sources were hits in the nearest-level (L1) cache.
Note: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. This event also counts SW prefetches independent of the actual data source Supports address when precise (Precise event) Retired load uops with L2 cache hits as data sources Supports address when precise. Spec update: BDM35 (Precise event) This event counts retired load uops which data sources were hits in the mid-level (L2) cache Supports address when precise. Spec update: BDM35 (Precise event) Retired load uops which data sources were data hits in L3 without snoops required Supports address when precise. Spec update: BDM100 (Precise event) This event counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required Supports address when precise. Spec update: BDM100 (Precise event) Retired load uops misses in L1 cache as data sources Supports address when precise (Precise event) This event counts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting excludes unknown and UC data source Supports address when precise (Precise event) Miss in mid-level (L2) cache. Excludes Unknown data-source Supports address when precise (Precise event) This event counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting excludes unknown and UC data source Supports address when precise (Precise event) Miss in last-level (L3) cache. Excludes Unknown data-source Supports address when precise. Spec update: BDM100, BDE70 (Precise event) Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready Supports address when precise (Precise event) This event counts retired load uops which data sources were load uops missed L1 but hit a fill buffer due to a preceding miss to the same cache line with the data not ready.
Note: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load Supports address when precise (Precise event) Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache Supports address when precise. Spec update: BDM100 (Precise event) This event counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache Supports address when precise. Spec update: BDM100 (Precise event) Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache Supports address when precise. Spec update: BDM100 (Precise event) This event counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache Supports address when precise. Spec update: BDM100 (Precise event) Retired load uops which data sources were HitM responses from shared L3 Supports address when precise. Spec update: BDM100 (Precise event) This event counts retired load uops which data sources were HitM responses from a core on same socket (shared L3) Supports address when precise. Spec update: BDM100 (Precise event) Retired load uops which data sources were hits in L3 without snoops required Supports address when precise. Spec update: BDM100 (Precise event) This event counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required Supports address when precise. Spec update: BDM100 (Precise event) Data from local DRAM either Snoop not needed or Snoop Miss (RspI) Supports address when precise. Spec update: BDE70, BDM100 (Precise event) Retired load uop whose Data Source was: local DRAM either Snoop not needed or Snoop Miss (RspI) Supports address when precise. Spec update: BDE70, BDM100 (Precise event) Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI) Supports address when precise. Spec update: BDE70 (Precise event) Retired load uop whose Data Source was: Remote cache HITM Supports address when precise. Spec update: BDE70 (Precise event) Retired load uop whose Data Source was: forwarded from remote cache Supports address when precise. Spec update: BDE70 (Precise event) offcore_response.all_requests.llc_hit.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C8FFF Counts all requests hit in the L3 offcore_response.all_reads.llc_hit.hitm_other_core umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C07F7 Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded offcore_response.all_reads.llc_hit.hit_other_core_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C07F7 Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded offcore_response.all_code_rd.llc_hit.hit_other_core_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0244 Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded offcore_response.all_rfo.llc_hit.hitm_other_core Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded offcore_response.all_rfo.llc_hit.hit_other_core_no_fwd Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded offcore_response.all_data_rd.llc_hit.hitm_other_core Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded offcore_response.all_data_rd.llc_hit.hit_other_core_no_fwd Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded offcore_response.pf_llc_code_rd.llc_hit.any_response Counts prefetch (that bring data to LLC only) code reads hit in the L3 offcore_response.pf_llc_rfo.llc_hit.any_response Counts all prefetch (that bring data to LLC only) RFOs hit in the L3 offcore_response.demand_rfo.llc_hit.hitm_other_core Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded offcore_response.demand_rfo.llc_hit.any_response Counts all demand data writes (RFOs) hit in the L3 Number of times HLE abort was triggered (Precise event) Number of times RTM abort was triggered (Precise event) Number of times RTM abort was triggered (Precise event) offcore_response.all_requests.llc_miss.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC08FFF Counts all requests miss in the L3 offcore_response.all_reads.llc_miss.remote_hit_forward umask=0x1,period=100003,event=0xb7,offcore_rsp=0x087FC007F7 Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache offcore_response.all_reads.llc_miss.remote_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x103FC007F7 Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache offcore_response.all_reads.llc_miss.remote_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063BC007F7 Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram offcore_response.all_reads.llc_miss.local_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x06040007F7 Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram offcore_response.all_reads.llc_miss.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC007F7 Counts all data/code/rfo reads (demand & prefetch) miss in the L3 offcore_response.all_code_rd.llc_miss.local_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0604000244 Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram offcore_response.all_code_rd.llc_miss.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00244 Counts all demand & prefetch code reads miss in the L3 offcore_response.all_rfo.llc_miss.local_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0604000122 Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram offcore_response.all_rfo.llc_miss.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00122 Counts all demand & prefetch RFOs miss in the L3 offcore_response.all_data_rd.llc_miss.remote_hit_forward umask=0x1,period=100003,event=0xb7,offcore_rsp=0x087FC00091 Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache offcore_response.all_data_rd.llc_miss.remote_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x103FC00091 Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache offcore_response.all_data_rd.llc_miss.remote_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063BC00091 Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram offcore_response.all_data_rd.llc_miss.local_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0604000091 Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram offcore_response.all_data_rd.llc_miss.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00091 Counts all demand & prefetch data reads miss in the L3 offcore_response.pf_llc_code_rd.llc_miss.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00200 Counts prefetch (that bring data to LLC only) code reads miss in the L3 offcore_response.pf_llc_rfo.llc_miss.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00100 Counts all prefetch (that bring data to LLC only) RFOs miss in the L3 offcore_response.demand_rfo.llc_miss.remote_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x103FC00002 Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache offcore_response.demand_rfo.llc_miss.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00002 Counts all demand data writes (RFOs) miss in the L3 Actually retired uops Supports address when precise (Precise event) This event counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight Supports address when precise (Precise event) Retirement slots used (Precise event) This event counts the number of retirement slots used (Precise event) Conditional branch instructions retired (Precise event) This event counts conditional branch instructions retired (Precise event) Direct and indirect near call instructions retired (Precise event) This event counts both direct and indirect near call instructions retired (Precise event) Direct and indirect macro near call instructions retired (captured in ring 3) (Precise event) This event counts both direct and indirect macro near call instructions retired (captured in ring 3) (Precise event) Return instructions retired (Precise event) This event counts return instructions retired (Precise event) Taken branch instructions retired (Precise event) This event counts taken branch instructions retired (Precise event) Mispredicted conditional branch instructions retired (Precise event) This event counts mispredicted conditional branch instructions retired (Precise event) This event counts the number of mispredicted ret instructions retired. Non PEBS (Precise event) This event counts mispredicted return instructions retired (Precise event) number of near branch instructions retired that were mispredicted and taken (Precise event) Number of near branch instructions retired that were mispredicted and taken (Precise event) unc_q_clockticks event=0x14 QPI clock ticks. Unit: uncore_qpi uncore interconnect uncore_qpi qpi_data_bandwidth_tx umask=0x2,event=0 Number of data flits transmitted . Derived from unc_q_txl_flits_g0.data. Unit: uncore_qpi 8Bytes qpi_ctl_bandwidth_tx umask=0x4,event=0 Number of non data (control) flits transmitted . Derived from unc_q_txl_flits_g0.non_data. Unit: uncore_qpi unc_m_clockticks (unc_m_power_channel_ppd / unc_m_clockticks) * 100. (unc_m_power_critical_throttle_cycles / unc_m_clockticks) * 100. (unc_m_power_self_refresh / unc_m_clockticks) * 100. l2_ads.self umask=0x40,period=200000,event=0x21 Cycles L2 address bus is in use l2_dbus_busy.self umask=0x40,period=200000,event=0x22 Cycles the L2 cache data bus is busy l2_dbus_busy_rd.self umask=0x40,period=200000,event=0x23 Cycles the L2 transfers data to the core l2_lines_in.self.any umask=0x70,period=200000,event=0x24 L2 cache misses l2_lines_in.self.demand umask=0x40,period=200000,event=0x24 l2_lines_in.self.prefetch umask=0x50,period=200000,event=0x24 l2_m_lines_in.self umask=0x40,period=200000,event=0x25 L2 cache line modifications l2_lines_out.self.any umask=0x70,period=200000,event=0x26 L2 cache lines evicted l2_lines_out.self.demand umask=0x40,period=200000,event=0x26 l2_lines_out.self.prefetch umask=0x50,period=200000,event=0x26 l2_m_lines_out.self.any umask=0x70,period=200000,event=0x27 Modified lines evicted from the L2 cache l2_m_lines_out.self.demand umask=0x40,period=200000,event=0x27 l2_m_lines_out.self.prefetch umask=0x50,period=200000,event=0x27 l2_ifetch.self.e_state umask=0x44,period=200000,event=0x28 L2 cacheable instruction fetch requests l2_ifetch.self.i_state umask=0x41,period=200000,event=0x28 l2_ifetch.self.m_state umask=0x48,period=200000,event=0x28 l2_ifetch.self.s_state umask=0x42,period=200000,event=0x28 l2_ifetch.self.mesi umask=0x4f,period=200000,event=0x28 l2_ld.self.any.e_state umask=0x74,period=200000,event=0x29 L2 cache reads l2_ld.self.any.i_state umask=0x71,period=200000,event=0x29 l2_ld.self.any.m_state umask=0x78,period=200000,event=0x29 l2_ld.self.any.s_state umask=0x72,period=200000,event=0x29 l2_ld.self.any.mesi umask=0x7f,period=200000,event=0x29 l2_ld.self.demand.e_state umask=0x44,period=200000,event=0x29 l2_ld.self.demand.i_state umask=0x41,period=200000,event=0x29 l2_ld.self.demand.m_state umask=0x48,period=200000,event=0x29 l2_ld.self.demand.s_state umask=0x42,period=200000,event=0x29 l2_ld.self.demand.mesi umask=0x4f,period=200000,event=0x29 l2_ld.self.prefetch.e_state umask=0x54,period=200000,event=0x29 l2_ld.self.prefetch.i_state umask=0x51,period=200000,event=0x29 l2_ld.self.prefetch.m_state umask=0x58,period=200000,event=0x29 l2_ld.self.prefetch.s_state umask=0x52,period=200000,event=0x29 l2_ld.self.prefetch.mesi umask=0x5f,period=200000,event=0x29 l2_st.self.e_state umask=0x44,period=200000,event=0x2a L2 store requests l2_st.self.i_state umask=0x41,period=200000,event=0x2a l2_st.self.m_state umask=0x48,period=200000,event=0x2a l2_st.self.s_state umask=0x42,period=200000,event=0x2a l2_st.self.mesi umask=0x4f,period=200000,event=0x2a l2_lock.self.e_state umask=0x44,period=200000,event=0x2b L2 locked accesses l2_lock.self.i_state umask=0x41,period=200000,event=0x2b l2_lock.self.m_state umask=0x48,period=200000,event=0x2b l2_lock.self.s_state umask=0x42,period=200000,event=0x2b l2_lock.self.mesi umask=0x4f,period=200000,event=0x2b l2_data_rqsts.self.e_state umask=0x44,period=200000,event=0x2c All data requests from the L1 data cache l2_data_rqsts.self.i_state umask=0x41,period=200000,event=0x2c l2_data_rqsts.self.m_state umask=0x48,period=200000,event=0x2c l2_data_rqsts.self.s_state umask=0x42,period=200000,event=0x2c l2_data_rqsts.self.mesi umask=0x4f,period=200000,event=0x2c l2_ld_ifetch.self.e_state umask=0x44,period=200000,event=0x2d All read requests from L1 instruction and data caches l2_ld_ifetch.self.i_state umask=0x41,period=200000,event=0x2d l2_ld_ifetch.self.m_state umask=0x48,period=200000,event=0x2d l2_ld_ifetch.self.s_state umask=0x42,period=200000,event=0x2d l2_ld_ifetch.self.mesi umask=0x4f,period=200000,event=0x2d l2_rqsts.self.any.e_state umask=0x74,period=200000,event=0x2e L2 cache requests l2_rqsts.self.any.i_state umask=0x71,period=200000,event=0x2e l2_rqsts.self.any.m_state umask=0x78,period=200000,event=0x2e l2_rqsts.self.any.s_state umask=0x72,period=200000,event=0x2e l2_rqsts.self.any.mesi umask=0x7f,period=200000,event=0x2e l2_rqsts.self.demand.e_state umask=0x44,period=200000,event=0x2e l2_rqsts.self.demand.m_state umask=0x48,period=200000,event=0x2e l2_rqsts.self.demand.s_state umask=0x42,period=200000,event=0x2e l2_rqsts.self.prefetch.e_state umask=0x54,period=200000,event=0x2e l2_rqsts.self.prefetch.i_state umask=0x51,period=200000,event=0x2e l2_rqsts.self.prefetch.m_state umask=0x58,period=200000,event=0x2e l2_rqsts.self.prefetch.s_state umask=0x52,period=200000,event=0x2e l2_rqsts.self.prefetch.mesi umask=0x5f,period=200000,event=0x2e l2_rqsts.self.demand.i_state umask=0x41,period=200000,event=0x2e L2 cache demand requests from this core that missed the L2 l2_rqsts.self.demand.mesi umask=0x4f,period=200000,event=0x2e L2 cache demand requests from this core l2_reject_busq.self.any.e_state umask=0x74,period=200000,event=0x30 Rejected L2 cache requests l2_reject_busq.self.any.i_state umask=0x71,period=200000,event=0x30 l2_reject_busq.self.any.m_state umask=0x78,period=200000,event=0x30 l2_reject_busq.self.any.s_state umask=0x72,period=200000,event=0x30 l2_reject_busq.self.any.mesi umask=0x7f,period=200000,event=0x30 l2_reject_busq.self.demand.e_state umask=0x44,period=200000,event=0x30 l2_reject_busq.self.demand.i_state umask=0x41,period=200000,event=0x30 l2_reject_busq.self.demand.m_state umask=0x48,period=200000,event=0x30 l2_reject_busq.self.demand.s_state umask=0x42,period=200000,event=0x30 l2_reject_busq.self.demand.mesi umask=0x4f,period=200000,event=0x30 l2_reject_busq.self.prefetch.e_state umask=0x54,period=200000,event=0x30 l2_reject_busq.self.prefetch.i_state umask=0x51,period=200000,event=0x30 l2_reject_busq.self.prefetch.m_state umask=0x58,period=200000,event=0x30 l2_reject_busq.self.prefetch.s_state umask=0x52,period=200000,event=0x30 l2_reject_busq.self.prefetch.mesi umask=0x5f,period=200000,event=0x30 l2_no_req.self umask=0x40,period=200000,event=0x32 Cycles no L2 cache requests are pending l1d_cache.ld umask=0xa1,period=2000000,event=0x40 L1 Cacheable Data Reads l1d_cache.st umask=0xa2,period=2000000,event=0x40 L1 Cacheable Data Writes l1d_cache.all_ref umask=0x83,period=2000000,event=0x40 L1 Data reads and writes l1d_cache.all_cache_ref umask=0xa3,period=2000000,event=0x40 L1 Data Cacheable reads and writes l1d_cache.repl umask=0x8,period=200000,event=0x40 L1 Data line replacements l1d_cache.replm umask=0x48,period=200000,event=0x40 Modified cache lines allocated in the L1 data cache l1d_cache.evict umask=0x10,period=200000,event=0x40 Modified cache lines evicted from the L1 data cache mem_load_retired.l2_hit umask=0x1,period=200000,event=0xcb Retired loads that hit the L2 cache (precise event) mem_load_retired.l2_miss umask=0x2,period=10000,event=0xcb Retired loads that miss the L2 cache x87_comp_ops_exe.any.s umask=0x1,period=2000000,event=0x10 Floating point computational micro-ops executed x87_comp_ops_exe.any.ar umask=0x81,period=2000000,event=0x10 Floating point computational micro-ops retired (Must be precise) x87_comp_ops_exe.fxch.s umask=0x2,period=2000000,event=0x10 FXCH uops executed x87_comp_ops_exe.fxch.ar umask=0x82,period=2000000,event=0x10 FXCH uops retired (Must be precise) fp_assist.s umask=0x1,period=10000,event=0x11 Floating point assists fp_assist.ar umask=0x81,period=10000,event=0x11 Floating point assists for retired operations simd_uops_exec.s umask=0x0,period=2000000,event=0xb0 SIMD micro-ops executed (excluding stores) simd_uops_exec.ar umask=0x80,period=2000000,event=0xb0 SIMD micro-ops retired (excluding stores) (Must be precise) simd_sat_uop_exec.s umask=0x0,period=2000000,event=0xb1 SIMD saturated arithmetic micro-ops executed simd_sat_uop_exec.ar umask=0x80,period=2000000,event=0xb1 SIMD saturated arithmetic micro-ops retired simd_uop_type_exec.mul.s umask=0x1,period=2000000,event=0xb3 SIMD packed multiply micro-ops executed simd_uop_type_exec.mul.ar umask=0x81,period=2000000,event=0xb3 SIMD packed multiply micro-ops retired simd_uop_type_exec.shift.s umask=0x2,period=2000000,event=0xb3 SIMD packed shift micro-ops executed simd_uop_type_exec.shift.ar umask=0x82,period=2000000,event=0xb3 SIMD packed shift micro-ops retired simd_uop_type_exec.pack.s umask=0x4,period=2000000,event=0xb3 SIMD packed micro-ops executed simd_uop_type_exec.pack.ar umask=0x84,period=2000000,event=0xb3 SIMD packed micro-ops retired simd_uop_type_exec.unpack.s umask=0x8,period=2000000,event=0xb3 SIMD unpacked micro-ops executed simd_uop_type_exec.unpack.ar umask=0x88,period=2000000,event=0xb3 SIMD unpacked micro-ops retired simd_uop_type_exec.logical.s umask=0x10,period=2000000,event=0xb3 SIMD packed logical micro-ops executed simd_uop_type_exec.logical.ar umask=0x90,period=2000000,event=0xb3 SIMD packed logical micro-ops retired simd_uop_type_exec.arithmetic.s umask=0x20,period=2000000,event=0xb3 SIMD packed arithmetic micro-ops executed simd_uop_type_exec.arithmetic.ar umask=0xa0,period=2000000,event=0xb3 SIMD packed arithmetic micro-ops retired simd_inst_retired.packed_single umask=0x1,period=2000000,event=0xc7 Retired Streaming SIMD Extensions (SSE) packed-single instructions simd_inst_retired.scalar_single umask=0x2,period=2000000,event=0xc7 Retired Streaming SIMD Extensions (SSE) scalar-single instructions simd_inst_retired.scalar_double umask=0x8,period=2000000,event=0xc7 Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions simd_inst_retired.vector umask=0x10,period=2000000,event=0xc7 Retired Streaming SIMD Extensions 2 (SSE2) vector instructions simd_comp_inst_retired.packed_single umask=0x1,period=2000000,event=0xca Retired computational Streaming SIMD Extensions (SSE) packed-single instructions simd_comp_inst_retired.scalar_single umask=0x2,period=2000000,event=0xca Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions simd_comp_inst_retired.scalar_double umask=0x8,period=2000000,event=0xca Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions simd_assist umask=0x0,period=100000,event=0xcd SIMD assists invoked simd_instr_retired umask=0x0,period=2000000,event=0xce SIMD Instructions retired simd_sat_instr_retired umask=0x0,period=2000000,event=0xcf Saturated arithmetic instructions retired icache.accesses umask=0x3,period=200000,event=0x80 Instruction fetches umask=0x1,period=200000,event=0x80 Icache hit umask=0x2,period=200000,event=0x80 Icache miss cycles_icache_mem_stalled.icache_mem_stalled umask=0x1,period=2000000,event=0x86 Cycles during which instruction fetches are stalled decode_stall.pfb_empty umask=0x1,period=2000000,event=0x87 Decode stall due to PFB empty decode_stall.iq_full umask=0x2,period=2000000,event=0x87 Decode stall due to IQ full macro_insts.non_cisc_decoded umask=0x1,period=2000000,event=0xaa Non-CISC nacro instructions decoded macro_insts.cisc_decoded umask=0x2,period=2000000,event=0xaa CISC macro instructions decoded macro_insts.all_decoded umask=0x3,period=2000000,event=0xaa All Instructions decoded uops.ms_cycles umask=0x1,period=2000000,cmask=1,event=0xa9 This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ misalign_mem_ref.split umask=0xf,period=200000,event=0x5 Memory references that cross an 8-byte boundary misalign_mem_ref.ld_split umask=0x9,period=200000,event=0x5 Load splits misalign_mem_ref.st_split umask=0xa,period=200000,event=0x5 Store splits misalign_mem_ref.split.ar umask=0x8f,period=200000,event=0x5 Memory references that cross an 8-byte boundary (At Retirement) misalign_mem_ref.ld_split.ar umask=0x89,period=200000,event=0x5 Load splits (At Retirement) misalign_mem_ref.st_split.ar umask=0x8a,period=200000,event=0x5 Store splits (Ar Retirement) misalign_mem_ref.rmw_split umask=0x8c,period=200000,event=0x5 ld-op-st splits misalign_mem_ref.bubble umask=0x97,period=200000,event=0x5 Nonzero segbase 1 bubble misalign_mem_ref.ld_bubble umask=0x91,period=200000,event=0x5 Nonzero segbase load 1 bubble misalign_mem_ref.st_bubble umask=0x92,period=200000,event=0x5 Nonzero segbase store 1 bubble misalign_mem_ref.rmw_bubble umask=0x94,period=200000,event=0x5 Nonzero segbase ld-op-st 1 bubble prefetch.prefetcht0 umask=0x81,period=200000,event=0x7 Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed prefetch.prefetcht1 umask=0x82,period=200000,event=0x7 Streaming SIMD Extensions (SSE) PrefetchT1 instructions executed prefetch.prefetcht2 umask=0x84,period=200000,event=0x7 Streaming SIMD Extensions (SSE) PrefetchT2 instructions executed prefetch.sw_l2 umask=0x86,period=200000,event=0x7 Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed prefetch.prefetchnta umask=0x88,period=200000,event=0x7 Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed prefetch.hw_prefetch umask=0x10,period=2000000,event=0x7 L1 hardware prefetch request prefetch.software_prefetch umask=0xf,period=200000,event=0x7 Any Software prefetch prefetch.software_prefetch.ar umask=0x8f,period=200000,event=0x7 segment_reg_loads.any umask=0x80,period=200000,event=0x6 Number of segment register loads dispatch_blocked.any umask=0x20,period=200000,event=0x9 Memory cluster signals to block micro-op dispatch for any reason eist_trans umask=0x0,period=200000,event=0x3a Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions thermal_trip umask=0xc0,period=200000,event=0x3b Number of thermal trips bus_request_outstanding.all_agents umask=0xe0,period=200000,event=0x60 Outstanding cacheable data read bus requests duration bus_request_outstanding.self umask=0x40,period=200000,event=0x60 bus_bnr_drv.all_agents umask=0x20,period=200000,event=0x61 Number of Bus Not Ready signals asserted bus_bnr_drv.this_agent umask=0x0,period=200000,event=0x61 bus_drdy_clocks.all_agents umask=0x20,period=200000,event=0x62 Bus cycles when data is sent on the bus bus_drdy_clocks.this_agent umask=0x0,period=200000,event=0x62 bus_lock_clocks.all_agents umask=0xe0,period=200000,event=0x63 Bus cycles when a LOCK signal is asserted bus_lock_clocks.self umask=0x40,period=200000,event=0x63 bus_data_rcv.self umask=0x40,period=200000,event=0x64 Bus cycles while processor receives data bus_trans_brd.all_agents umask=0xe0,period=200000,event=0x65 Burst read bus transactions bus_trans_brd.self umask=0x40,period=200000,event=0x65 bus_trans_rfo.all_agents umask=0xe0,period=200000,event=0x66 RFO bus transactions bus_trans_rfo.self umask=0x40,period=200000,event=0x66 bus_trans_wb.all_agents umask=0xe0,period=200000,event=0x67 Explicit writeback bus transactions bus_trans_wb.self umask=0x40,period=200000,event=0x67 bus_trans_ifetch.all_agents umask=0xe0,period=200000,event=0x68 Instruction-fetch bus transactions bus_trans_ifetch.self umask=0x40,period=200000,event=0x68 bus_trans_inval.all_agents umask=0xe0,period=200000,event=0x69 Invalidate bus transactions bus_trans_inval.self umask=0x40,period=200000,event=0x69 bus_trans_pwr.all_agents umask=0xe0,period=200000,event=0x6a Partial write bus transaction bus_trans_pwr.self umask=0x40,period=200000,event=0x6a bus_trans_p.all_agents umask=0xe0,period=200000,event=0x6b Partial bus transactions bus_trans_p.self umask=0x40,period=200000,event=0x6b bus_trans_io.all_agents umask=0xe0,period=200000,event=0x6c IO bus transactions bus_trans_io.self umask=0x40,period=200000,event=0x6c bus_trans_def.all_agents umask=0xe0,period=200000,event=0x6d Deferred bus transactions bus_trans_def.self umask=0x40,period=200000,event=0x6d bus_trans_burst.all_agents umask=0xe0,period=200000,event=0x6e Burst (full cache-line) bus transactions bus_trans_burst.self umask=0x40,period=200000,event=0x6e bus_trans_mem.all_agents umask=0xe0,period=200000,event=0x6f Memory bus transactions bus_trans_mem.self umask=0x40,period=200000,event=0x6f bus_trans_any.all_agents umask=0xe0,period=200000,event=0x70 All bus transactions bus_trans_any.self umask=0x40,period=200000,event=0x70 ext_snoop.this_agent.any umask=0xb,period=200000,event=0x77 External snoops ext_snoop.this_agent.clean umask=0x1,period=200000,event=0x77 ext_snoop.this_agent.hit umask=0x2,period=200000,event=0x77 ext_snoop.this_agent.hitm umask=0x8,period=200000,event=0x77 ext_snoop.all_agents.any umask=0x2b,period=200000,event=0x77 ext_snoop.all_agents.clean umask=0x21,period=200000,event=0x77 ext_snoop.all_agents.hit umask=0x22,period=200000,event=0x77 ext_snoop.all_agents.hitm umask=0x28,period=200000,event=0x77 bus_hit_drv.all_agents umask=0x20,period=200000,event=0x7a HIT signal asserted bus_hit_drv.this_agent umask=0x0,period=200000,event=0x7a bus_hitm_drv.all_agents umask=0x20,period=200000,event=0x7b HITM signal asserted bus_hitm_drv.this_agent umask=0x0,period=200000,event=0x7b busq_empty.self umask=0x40,period=200000,event=0x7d Bus queue is empty snoop_stall_drv.all_agents umask=0xe0,period=200000,event=0x7e Bus stalled for snoops snoop_stall_drv.self umask=0x40,period=200000,event=0x7e bus_io_wait.self umask=0x40,period=200000,event=0x7f IO requests waiting in the bus queue cycles_int_masked.cycles_int_masked umask=0x1,period=2000000,event=0xc6 Cycles during which interrupts are disabled cycles_int_masked.cycles_int_pending_and_masked umask=0x2,period=2000000,event=0xc6 Cycles during which interrupts are pending and disabled hw_int_rcv umask=0x0,period=200000,event=0xc8 Hardware interrupts received store_forwards.any umask=0x83,period=200000,event=0x2 All store forwards store_forwards.good umask=0x81,period=200000,event=0x2 Good store forwards reissue.any umask=0x7f,period=200000,event=0x3 Micro-op reissues for any cause reissue.any.ar umask=0xff,period=200000,event=0x3 Micro-op reissues for any cause (At Retirement) mul.s umask=0x1,period=2000000,event=0x12 Multiply operations executed mul.ar umask=0x81,period=2000000,event=0x12 Multiply operations retired div.s umask=0x1,period=2000000,event=0x13 Divide operations executed div.ar umask=0x81,period=2000000,event=0x13 Divide operations retired cycles_div_busy umask=0x1,period=2000000,event=0x14 Cycles the divider is busy cpu_clk_unhalted.core_p umask=0x0,period=2000000,event=0x3c Core cycles when core is not halted cpu_clk_unhalted.bus umask=0x1,period=200000,event=0x3c Bus cycles when core is not halted cpu_clk_unhalted.core umask=0x0,period=2000000,event=0xa cpu_clk_unhalted.ref event=0x0,umask=0x03 Reference cycles when core is not halted br_inst_type_retired.cond umask=0x1,period=2000000,event=0x88 All macro conditional branch instructions br_inst_type_retired.uncond umask=0x2,period=2000000,event=0x88 All macro unconditional branch instructions, excluding calls and indirects br_inst_type_retired.ind umask=0x4,period=2000000,event=0x88 All indirect branches that are not calls br_inst_type_retired.ret umask=0x8,period=2000000,event=0x88 All indirect branches that have a return mnemonic br_inst_type_retired.dir_call umask=0x10,period=2000000,event=0x88 All non-indirect calls br_inst_type_retired.ind_call umask=0x20,period=2000000,event=0x88 All indirect calls, including both register and memory indirect br_inst_type_retired.cond_taken umask=0x41,period=2000000,event=0x88 Only taken macro conditional branch instructions br_missp_type_retired.cond umask=0x1,period=200000,event=0x89 Mispredicted cond branch instructions retired br_missp_type_retired.ind umask=0x2,period=200000,event=0x89 Mispredicted ind branches that are not calls br_missp_type_retired.return umask=0x4,period=200000,event=0x89 Mispredicted return branches br_missp_type_retired.ind_call umask=0x8,period=200000,event=0x89 Mispredicted indirect calls, including both register and memory indirect br_missp_type_retired.cond_taken umask=0x11,period=200000,event=0x89 Mispredicted and taken cond branch instructions retired Instructions retired (precise event) (Must be precise) Instructions retired uops_retired.any umask=0x10,period=2000000,event=0xc2 Micro-ops retired uops_retired.stalled_cycles Cycles no micro-ops retired uops_retired.stalls Periods no micro-ops retired umask=0x1,period=200000,event=0xc3 Self-Modifying Code detected br_inst_retired.any umask=0x0,period=2000000,event=0xc4 Retired branch instructions br_inst_retired.pred_not_taken umask=0x1,period=2000000,event=0xc4 Retired branch instructions that were predicted not-taken br_inst_retired.mispred_not_taken umask=0x2,period=200000,event=0xc4 Retired branch instructions that were mispredicted not-taken br_inst_retired.pred_taken umask=0x4,period=2000000,event=0xc4 Retired branch instructions that were predicted taken br_inst_retired.mispred_taken umask=0x8,period=200000,event=0xc4 Retired branch instructions that were mispredicted taken br_inst_retired.taken umask=0xc,period=2000000,event=0xc4 Retired taken branch instructions br_inst_retired.any1 umask=0xf,period=2000000,event=0xc4 br_inst_retired.mispred umask=0x0,period=200000,event=0xc5 Retired mispredicted branch instructions (precise event) (Precise event) resource_stalls.div_busy umask=0x2,period=2000000,event=0xdc Cycles issue is stalled due to div busy br_inst_decoded umask=0x1,period=2000000,event=0xe0 Branch instructions decoded bogus_br umask=0x1,period=2000000,event=0xe4 Bogus branches umask=0x1,period=2000000,event=0xe6 BACLEARS asserted reissue.overlap_store umask=0x1,period=200000,event=0x3 Micro-op reissues on a store-load collision reissue.overlap_store.ar umask=0x81,period=200000,event=0x3 Micro-op reissues on a store-load collision (At Retirement) data_tlb_misses.dtlb_miss umask=0x7,period=200000,event=0x8 Memory accesses that missed the DTLB data_tlb_misses.dtlb_miss_ld umask=0x5,period=200000,event=0x8 DTLB misses due to load operations data_tlb_misses.l0_dtlb_miss_ld umask=0x9,period=200000,event=0x8 L0 DTLB misses due to load operations data_tlb_misses.dtlb_miss_st umask=0x6,period=200000,event=0x8 DTLB misses due to store operations data_tlb_misses.l0_dtlb_miss_st umask=0xa,period=200000,event=0x8 L0 DTLB misses due to store operations page_walks.walks umask=0x3,period=200000,event=0xc Number of page-walks executed page_walks.cycles umask=0x3,period=2000000,event=0xc Duration of page-walks in core cycles page_walks.d_side_walks umask=0x1,period=200000,event=0xc Number of D-side only page walks page_walks.d_side_cycles umask=0x1,period=2000000,event=0xc Duration of D-side only page walks page_walks.i_side_walks umask=0x2,period=200000,event=0xc Number of I-Side page walks page_walks.i_side_cycles umask=0x2,period=2000000,event=0xc Duration of I-Side page walks itlb.hit umask=0x1,period=200000,event=0x82 ITLB hits itlb.flush umask=0x4,period=200000,event=0x82 ITLB flushes itlb.misses umask=0x2,period=200000,event=0x82 ITLB misses (Must be precise) mem_load_retired.dtlb_miss umask=0x4,period=200000,event=0xcb Retired loads that miss the DTLB (precise event) (Precise event) umask=0x41,period=200003,event=0x2e L2 cache request misses Counts memory requests originating from the core that miss in the L2 cache umask=0x4f,period=200003,event=0x2e Counts memory requests originating from the core that reference a cache line in the L2 cache l2_reject_xq.all umask=0x0,period=200003,event=0x30 Requests rejected by the XQ Counts the number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the intra-die interconnect (IDI) fabric. The XQ may reject transactions from the L2Q (non-cacheable requests), L2 misses and L2 write-back victims core_reject_l2q.all umask=0x0,period=200003,event=0x31 Requests rejected by the L2Q Counts the number of demand and L1 prefetcher requests rejected by the L2Q due to a full or nearly full condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to ensure fairness between cores, or to delay a core's dirty eviction when the address conflicts with incoming external snoops dl1.dirty_eviction umask=0x1,period=200003,event=0x51 L1 Cache evictions for dirty data Counts when a modified (dirty) cache line is evicted from the data L1 cache and needs to be written back to memory. No count will occur if the evicted line is clean, and hence does not require a writeback fetch_stall.icache_fill_pending_cycles umask=0x2,period=200003,event=0x86 Cycles code-fetch stalled due to an outstanding ICache miss Counts cycles that fetch is stalled due to an outstanding ICache miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ICache miss. Note: this event is not the same as the total number of cycles spent retrieving instruction cache lines from the memory hierarchy umask=0x1,period=100007,event=0xb7 Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) umask=0x21,period=200003,event=0xd0 Locked load uops retired (Precise event capable) Supports address when precise (Must be precise) Counts locked memory uops retired. This includes regular locks and bus locks. (To specifically count bus locks only, see the Offcore response event.) A locked access is one with a lock prefix, or an exchange to memory. See the SDM for a complete description of which memory load accesses are locks Supports address when precise (Must be precise) umask=0x41,period=200003,event=0xd0 Load uops retired that split a cache-line (Precise event capable) Supports address when precise (Must be precise) Counts load uops retired where the data requested spans a 64 byte cache line boundary Supports address when precise (Must be precise) umask=0x42,period=200003,event=0xd0 Stores uops retired that split a cache-line (Precise event capable) Supports address when precise (Must be precise) Counts store uops retired where the data requested spans a 64 byte cache line boundary Supports address when precise (Must be precise) mem_uops_retired.split umask=0x43,period=200003,event=0xd0 Memory uops retired that split a cache-line (Precise event capable) Supports address when precise (Must be precise) Counts memory uops retired where the data requested spans a 64 byte cache line boundary Supports address when precise (Must be precise) umask=0x81,period=200003,event=0xd0 Load uops retired (Precise event capable) Supports address when precise (Must be precise) Counts the number of load uops retired Supports address when precise (Must be precise) umask=0x82,period=200003,event=0xd0 Store uops retired (Precise event capable) Supports address when precise (Must be precise) Counts the number of store uops retired Supports address when precise (Must be precise) mem_uops_retired.all umask=0x83,period=200003,event=0xd0 Memory uops retired (Precise event capable) Supports address when precise (Must be precise) Counts the number of memory uops retired that is either a loads or a store or both Supports address when precise (Must be precise) umask=0x1,period=200003,event=0xd1 Load uops retired that hit L1 data cache (Precise event capable) Supports address when precise (Must be precise) Counts load uops retired that hit the L1 data cache Supports address when precise (Must be precise) umask=0x2,period=200003,event=0xd1 Load uops retired that hit L2 (Precise event capable) Supports address when precise (Must be precise) Counts load uops retired that hit in the L2 cache Supports address when precise (Must be precise) umask=0x8,period=200003,event=0xd1 Load uops retired that missed L1 data cache (Precise event capable) Supports address when precise (Must be precise) Counts load uops retired that miss the L1 data cache Supports address when precise (Must be precise) umask=0x10,period=200003,event=0xd1 Load uops retired that missed L2 (Precise event capable) Supports address when precise (Must be precise) Counts load uops retired that miss in the L2 cache Supports address when precise (Must be precise) mem_load_uops_retired.hitm umask=0x20,period=200003,event=0xd1 Memory uop retired where cross core or cross module HITM occurred (Precise event capable) Supports address when precise (Must be precise) Counts load uops retired where the cache line containing the data was in the modified state of another core or modules cache (HITM). More specifically, this means that when the load address was checked by other caching agents (typically another processor) in the system, one of those caching agents indicated that they had a dirty copy of the data. Loads that obtain a HITM response incur greater latency than most is typical for a load. In addition, since HITM indicates that some other processor had this data in its cache, it implies that the data was shared between processors, or potentially was a lock or semaphore value. This event is useful for locating sharing, false sharing, and contended locks Supports address when precise (Must be precise) mem_load_uops_retired.wcb_hit umask=0x40,period=200003,event=0xd1 Loads retired that hit WCB (Precise event capable) Supports address when precise (Must be precise) Counts memory load uops retired where the data is retrieved from the WCB (or fill buffer), indicating that the load found its data while that data was in the process of being brought into the L1 cache. Typically a load will receive this indication when some other load or prefetch missed the L1 cache and was in the process of retrieving the cache line containing the data, but that process had not yet finished (and written the data back to the cache). For example, consider load X and Y, both referencing the same cache line that is not in the L1 cache. If load X misses cache first, it obtains and WCB (or fill buffer) and begins the process of requesting the data. When load Y requests the data, it will either hit the WCB, or the L1 cache, depending on exactly what time the request to Y occurs Supports address when precise (Must be precise) mem_load_uops_retired.dram_hit umask=0x80,period=200003,event=0xd1 Loads retired that came from DRAM (Precise event capable) Supports address when precise (Must be precise) Counts memory load uops retired where the data is retrieved from DRAM. Event is counted at retirement, so the speculative loads are ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit DRAM, hit in the WCB or receive a HITM response Supports address when precise (Must be precise) offcore_response.any_read.l2_miss.any umask=0x1,period=100007,event=0xb7,offcore_rsp=0x36000032b7 Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_read.l2_miss.hitm_other_core umask=0x1,period=100007,event=0xb7,offcore_rsp=0x10000032b7 Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_read.l2_miss.hit_other_core_no_fwd umask=0x1,period=100007,event=0xb7,offcore_rsp=0x04000032b7 Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_read.l2_miss.snoop_miss_or_no_snoop_needed umask=0x1,period=100007,event=0xb7,offcore_rsp=0x02000032b7 Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_read.l2_hit umask=0x1,period=100007,event=0xb7,offcore_rsp=0x00000432b7 Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that hit the L2 cache Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_rfo.l2_miss.any umask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600000022 Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_rfo.l2_miss.hitm_other_core umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000000022 Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_rfo.l2_miss.hit_other_core_no_fwd umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400000022 Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_rfo.l2_miss.snoop_miss_or_no_snoop_needed umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200000022 Counts reads for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module Counts reads for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_rfo.l2_hit umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000040022 Counts reads for ownership (RFO) requests (demand & prefetch) that hit the L2 cache Counts reads for ownership (RFO) requests (demand & prefetch) that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_data_rd.l2_miss.any umask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600003091 Counts data reads (demand & prefetch) that miss the L2 cache Counts data reads (demand & prefetch) that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_data_rd.l2_miss.hitm_other_core umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000003091 Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_data_rd.l2_miss.hit_other_core_no_fwd umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400003091 Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_data_rd.l2_miss.snoop_miss_or_no_snoop_needed umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200003091 Counts data reads (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module Counts data reads (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_data_rd.l2_hit umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000043091 Counts data reads (demand & prefetch) that hit the L2 cache Counts data reads (demand & prefetch) that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_pf_data_rd.l2_miss.any umask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600003010 Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_pf_data_rd.l2_miss.hitm_other_core umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000003010 Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_pf_data_rd.l2_miss.hit_other_core_no_fwd umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400003010 Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_pf_data_rd.l2_miss.snoop_miss_or_no_snoop_needed umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200003010 Counts data reads generated by L1 or L2 prefetchers that true miss for the L2 cache with a snoop miss in the other processor module Counts data reads generated by L1 or L2 prefetchers that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_pf_data_rd.l2_hit umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000043010 Counts data reads generated by L1 or L2 prefetchers that hit the L2 cache Counts data reads generated by L1 or L2 prefetchers that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_request.l2_miss.hitm_other_core umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000008000 Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_request.l2_miss.hit_other_core_no_fwd umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400008000 Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_request.l2_miss.snoop_miss_or_no_snoop_needed umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200008000 Counts requests to the uncore subsystem that true miss for the L2 cache with a snoop miss in the other processor module Counts requests to the uncore subsystem that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_request.l2_hit umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000048000 Counts requests to the uncore subsystem that hit the L2 cache Counts requests to the uncore subsystem that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_request.any_response umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000018000 Counts requests to the uncore subsystem that have any transaction responses from the uncore subsystem Counts requests to the uncore subsystem that have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.streaming_stores.l2_miss.any umask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600004800 Counts any data writes to uncacheable write combining (USWC) memory region that miss the L2 cache Counts any data writes to uncacheable write combining (USWC) memory region that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.streaming_stores.l2_hit umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000044800 Counts any data writes to uncacheable write combining (USWC) memory region that hit the L2 cache Counts any data writes to uncacheable write combining (USWC) memory region that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.partial_streaming_stores.l2_miss.any umask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600004000 Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.partial_streaming_stores.l2_miss.hitm_other_core umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000004000 Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.partial_streaming_stores.l2_miss.hit_other_core_no_fwd umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400004000 Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.partial_streaming_stores.l2_miss.snoop_miss_or_no_snoop_needed umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200004000 Counts partial cache line data writes to uncacheable write combining (USWC) memory region that true miss for the L2 cache with a snoop miss in the other processor module Counts partial cache line data writes to uncacheable write combining (USWC) memory region that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.partial_streaming_stores.l2_hit umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000044000 Counts partial cache line data writes to uncacheable write combining (USWC) memory region that hit the L2 cache Counts partial cache line data writes to uncacheable write combining (USWC) memory region that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l1_data_rd.l2_miss.any umask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600002000 Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l1_data_rd.l2_miss.hitm_other_core umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000002000 Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l1_data_rd.l2_miss.hit_other_core_no_fwd umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400002000 Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l1_data_rd.l2_miss.snoop_miss_or_no_snoop_needed umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200002000 Counts data cache line reads generated by hardware L1 data cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module Counts data cache line reads generated by hardware L1 data cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l1_data_rd.l2_hit umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000042000 Counts data cache line reads generated by hardware L1 data cache prefetcher that hit the L2 cache Counts data cache line reads generated by hardware L1 data cache prefetcher that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.sw_prefetch.l2_miss.any umask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600001000 Counts data cache lines requests by software prefetch instructions that miss the L2 cache Counts data cache lines requests by software prefetch instructions that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.sw_prefetch.l2_miss.hitm_other_core umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000001000 Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.sw_prefetch.l2_miss.hit_other_core_no_fwd umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400001000 Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.sw_prefetch.l2_miss.snoop_miss_or_no_snoop_needed umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200001000 Counts data cache lines requests by software prefetch instructions that true miss for the L2 cache with a snoop miss in the other processor module Counts data cache lines requests by software prefetch instructions that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.sw_prefetch.l2_hit umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000041000 Counts data cache lines requests by software prefetch instructions that hit the L2 cache Counts data cache lines requests by software prefetch instructions that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.full_streaming_stores.l2_miss.any umask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600000800 Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.full_streaming_stores.l2_miss.hitm_other_core umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000000800 Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.full_streaming_stores.l2_miss.hit_other_core_no_fwd umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400000800 Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.full_streaming_stores.l2_miss.snoop_miss_or_no_snoop_needed umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200000800 Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that true miss for the L2 cache with a snoop miss in the other processor module Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.full_streaming_stores.l2_hit umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000040800 Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that hit the L2 cache Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.bus_locks.any_response umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010400 Counts bus lock and split lock requests that have any transaction responses from the uncore subsystem Counts bus lock and split lock requests that have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.partial_writes.l2_miss.any umask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600000100 Counts the number of demand write requests (RFO) generated by a write to partial data cache line, including the writes to uncacheable (UC) and write through (WT), and write protected (WP) types of memory that miss the L2 cache Counts the number of demand write requests (RFO) generated by a write to partial data cache line, including the writes to uncacheable (UC) and write through (WT), and write protected (WP) types of memory that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.partial_reads.l2_miss.any umask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600000080 Counts demand data partial reads, including data in uncacheable (UC) or uncacheable write combining (USWC) memory types that miss the L2 cache Counts demand data partial reads, including data in uncacheable (UC) or uncacheable write combining (USWC) memory types that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_rfo.l2_miss.any umask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600000020 Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_rfo.l2_miss.hitm_other_core umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000000020 Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_rfo.l2_miss.hit_other_core_no_fwd umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400000020 Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_rfo.l2_miss.snoop_miss_or_no_snoop_needed umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200000020 Counts reads for ownership (RFO) requests generated by L2 prefetcher that true miss for the L2 cache with a snoop miss in the other processor module Counts reads for ownership (RFO) requests generated by L2 prefetcher that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_rfo.l2_hit umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000040020 Counts reads for ownership (RFO) requests generated by L2 prefetcher that hit the L2 cache Counts reads for ownership (RFO) requests generated by L2 prefetcher that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_data_rd.l2_miss.any umask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600000010 Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_data_rd.l2_miss.hitm_other_core umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000000010 Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_data_rd.l2_miss.hit_other_core_no_fwd umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400000010 Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_data_rd.l2_miss.snoop_miss_or_no_snoop_needed umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200000010 Counts data cacheline reads generated by hardware L2 cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module Counts data cacheline reads generated by hardware L2 cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_data_rd.l2_hit umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000040010 Counts data cacheline reads generated by hardware L2 cache prefetcher that hit the L2 cache Counts data cacheline reads generated by hardware L2 cache prefetcher that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.corewb.l2_miss.any umask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600000008 Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.corewb.l2_miss.hitm_other_core umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000000008 Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.corewb.l2_miss.hit_other_core_no_fwd umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400000008 Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.corewb.l2_miss.snoop_miss_or_no_snoop_needed umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200000008 Counts the number of writeback transactions caused by L1 or L2 cache evictions that true miss for the L2 cache with a snoop miss in the other processor module Counts the number of writeback transactions caused by L1 or L2 cache evictions that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.corewb.l2_hit umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000040008 Counts the number of writeback transactions caused by L1 or L2 cache evictions that hit the L2 cache Counts the number of writeback transactions caused by L1 or L2 cache evictions that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_code_rd.outstanding umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000004 Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that are outstanding, per cycle, from the time of the L2 miss to when any response is received Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that are outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_code_rd.l2_miss.any umask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600000004 Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_code_rd.l2_miss.hit_other_core_no_fwd umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400000004 Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_code_rd.l2_miss.snoop_miss_or_no_snoop_needed umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200000004 Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that true miss for the L2 cache with a snoop miss in the other processor module Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_code_rd.l2_hit umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000040004 Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that hit the L2 cache Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_rfo.outstanding umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000002 Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that are outstanding, per cycle, from the time of the L2 miss to when any response is received Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that are outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_rfo.l2_miss.any umask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600000002 Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_rfo.l2_miss.hitm_other_core umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000000002 Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_rfo.l2_miss.hit_other_core_no_fwd umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400000002 Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_rfo.l2_miss.snoop_miss_or_no_snoop_needed umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200000002 Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that true miss for the L2 cache with a snoop miss in the other processor module Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_rfo.l2_hit umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000040002 Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that hit the L2 cache Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_data_rd.outstanding umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000001 Counts demand cacheable data reads of full cache lines that are outstanding, per cycle, from the time of the L2 miss to when any response is received Counts demand cacheable data reads of full cache lines that are outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_data_rd.l2_miss.any umask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600000001 Counts demand cacheable data reads of full cache lines that miss the L2 cache Counts demand cacheable data reads of full cache lines that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_data_rd.l2_miss.hitm_other_core umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000000001 Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_data_rd.l2_miss.hit_other_core_no_fwd umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400000001 Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_data_rd.l2_miss.snoop_miss_or_no_snoop_needed umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200000001 Counts demand cacheable data reads of full cache lines that true miss for the L2 cache with a snoop miss in the other processor module Counts demand cacheable data reads of full cache lines that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_data_rd.l2_hit umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000040001 Counts demand cacheable data reads of full cache lines that hit the L2 cache Counts demand cacheable data reads of full cache lines that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) umask=0x1,period=200003,event=0x80 References per ICache line that are available in the ICache (hit). This event counts differently than Intel processors based on Silvermont microarchitecture Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is in the ICache (hit). The event strives to count on a cache line basis, so that multiple accesses which hit in a single cache line count as one ICACHE.HIT. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture References per ICache line that are not available in the ICache (miss). This event counts differently than Intel processors based on Silvermont microarchitecture Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is not in the ICache (miss). The event strives to count on a cache line basis, so that multiple accesses which miss in a single cache line count as one ICACHE.MISS. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is not in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture umask=0x3,period=200003,event=0x80 References per ICache line. This event counts differently than Intel processors based on Silvermont microarchitecture Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line. The event strives to count on a cache line basis, so that multiple fetches to a single cache line count as one ICACHE.ACCESS. Specifically, the event counts when accesses from straight line code crosses the cache line boundary, or when a branch target is to a new line.
This event counts differently than Intel processors based on Silvermont microarchitecture ms_decoded.ms_entry umask=0x1,period=200003,event=0xe7 MS decode starts Counts the number of times the Microcode Sequencer (MS) starts a flow of uops from the MSROM. It does not count every time a uop is read from the MSROM. The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine. Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort that initiates a flow of uops. The event will count MS startups for uops that are speculative, and subsequently cleared by branch mispredict or a machine clear decode_restriction.predecode_wrong umask=0x1,period=200003,event=0xe9 Decode restrictions due to predicting wrong instruction length Counts the number of times the prediction (from the predecode cache) for instruction length is incorrect misalign_mem_ref.load_page_split umask=0x2,period=200003,event=0x13 Load uops that split a page (Precise event capable) (Must be precise) Counts when a memory load of a uop spans a page boundary (a split) is retired (Must be precise) misalign_mem_ref.store_page_split umask=0x4,period=200003,event=0x13 Store uops that split a page (Precise event capable) (Must be precise) Counts when a memory store of a uop spans a page boundary (a split) is retired (Must be precise) umask=0x2,period=200003,event=0xc3 Machine clears due to memory ordering issue Counts machine clears due to memory ordering issues. This occurs when a snoop request happens and the machine is uncertain if memory ordering will be preserved as another core is in the process of modifying the data fetch_stall.all umask=0x0,period=200003,event=0x86 Cycles code-fetch stalled due to any reason Counts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes. This will include cycles due to an ITLB miss, ICache miss and other events fetch_stall.itlb_fill_pending_cycles umask=0x1,period=200003,event=0x86 Cycles code-fetch stalled due to an outstanding ITLB miss Counts cycles that fetch is stalled due to an outstanding ITLB miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ITLB miss. Note: this event is not the same as page walk cycles to retrieve an instruction translation issue_slots_not_consumed.any umask=0x0,period=200003,event=0xca Unfilled issue slots per cycle Counts the number of issue slots per core cycle that were not consumed by the backend due to either a full resource in the backend (RESOURCE_FULL) or due to the processor recovering from some event (RECOVERY) issue_slots_not_consumed.resource_full umask=0x1,period=200003,event=0xca Unfilled issue slots per cycle because of a full resource in the backend Counts the number of issue slots per core cycle that were not consumed because of a full resource in the backend. Including but not limited to resources such as the Re-order Buffer (ROB), reservation stations (RS), load/store buffers, physical registers, or any other needed machine resource that is currently unavailable. Note that uops must be available for consumption in order for this event to fire. If a uop is not available (Instruction Queue is empty), this event will not count issue_slots_not_consumed.recovery umask=0x2,period=200003,event=0xca Unfilled issue slots per cycle to recover Counts the number of issue slots per core cycle that were not consumed by the backend because allocation is stalled waiting for a mispredicted jump to retire or other branch-like conditions (e.g. the event is relevant during certain microcode flows). Counts all issue slots blocked while within this window including slots where uops were not available in the Instruction Queue hw_interrupts.received umask=0x1,period=203,event=0xcb Counts hardware interrupts received by the processor hw_interrupts.masked umask=0x2,period=200003,event=0xcb Cycles hardware interrupts are masked Counts the number of core cycles during which interrupts are masked (disabled). Increments by 1 each core cycle that EFLAGS.IF is 0, regardless of whether interrupts are pending or not hw_interrupts.pending_and_masked umask=0x4,period=200003,event=0xcb Cycles pending interrupts are masked Counts core cycles during which there are pending interrupts, but interrupts are masked (EFLAGS.IF = 0) Instructions retired (Fixed event) Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0. You cannot collect a PEBs record for this event umask=0x2,period=2000003,event=0 Core cycles when core is not halted (Fixed event) Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1. You cannot collect a PEBs record for this event Reference cycles when core is not halted (Fixed event) Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. This event uses fixed counter 2. You cannot collect a PEBs record for this event ld_blocks.data_unknown umask=0x1,period=200003,event=0x3 Loads blocked due to store data not ready (Precise event capable) (Must be precise) Counts a load blocked from using a store forward, but did not occur because the store data was not available at the right time. The forward might occur subsequently when the data is available (Must be precise) umask=0x2,period=200003,event=0x3 Loads blocked due to store forward restriction (Precise event capable) (Must be precise) Counts a load blocked from using a store forward because of an address/size mismatch, only one of the loads blocked from each store will be counted (Must be precise) ld_blocks.4k_alias umask=0x4,period=200003,event=0x3 Loads blocked because address has 4k partial address false dependence (Precise event capable) (Must be precise) Counts loads that block because their address modulo 4K matches a pending store (Must be precise) ld_blocks.utlb_miss umask=0x8,period=200003,event=0x3 Loads blocked because address in not in the UTLB (Precise event capable) (Must be precise) Counts loads blocked because they are unable to find their physical address in the micro TLB (UTLB) (Must be precise) ld_blocks.all_block umask=0x10,period=200003,event=0x3 Loads blocked (Precise event capable) (Must be precise) Counts anytime a load that retires is blocked for any reason (Must be precise) umask=0x0,period=200003,event=0xe Uops issued to the back end per cycle Counts uops issued by the front end and allocated into the back end of the machine. This event counts uops that retire as well as uops that were speculatively executed but didn't retire. The sort of speculative uops that might be counted includes, but is not limited to those uops issued in the shadow of a miss-predicted branch, those uops that are inserted during an assist (such as for a denormal floating point result), and (previously allocated) uops that might be canceled during a machine clear Core cycles when core is not halted. This event uses a (_P)rogrammable general purpose performance counter Reference cycles when core is not halted. This event uses a programmable general purpose performance counter uops_not_delivered.any umask=0x0,period=200003,event=0x9c Uops requested but not-delivered to the back-end per cycle This event used to measure front-end inefficiencies. I.e. when front-end of the machine is not delivering uops to the back-end and the back-end has is not stalled. This event can be used to identify if the machine is truly front-end bound. When this event occurs, it is an indication that the front-end of the machine is operating at less than its theoretical peak performance. Background: We can think of the processor pipeline as being divided into 2 broader parts: Front-end and Back-end. Front-end is responsible for fetching the instruction, decoding into uops in machine understandable format and putting them into a uop queue to be consumed by back end. The back-end then takes these uops, allocates the required resources. When all resources are ready, uops are executed. If the back-end is not ready to accept uops from the front-end, then we do not want to count these as front-end bottlenecks. However, whenever we have bottlenecks in the back-end, we will have allocation unit stalls and eventually forcing the front-end to wait until the back-end is ready to receive more uops. This event counts only when back-end is requesting more uops and front-end is not able to provide them. When 3 uops are requested and no uops are delivered, the event counts 3. When 3 are requested, and only 1 is delivered, the event counts 2. When only 2 are delivered, the event counts 1. Alternatively stated, the event will not count if 3 uops are delivered, or if the back end is stalled and not requesting any uops at all. Counts indicate missed opportunities for the front-end to deliver a uop to the back end. Some examples of conditions that cause front-end efficiencies are: ICache misses, ITLB misses, and decoder restrictions that limit the front-end bandwidth. Known Issues: Some uops require multiple allocation slots. These uops will not be charged as a front end 'not delivered' opportunity, and will be regarded as a back end problem. For example, the INC instruction has one uop that requires 2 issue slots. A stream of INC instructions will not count as UOPS_NOT_DELIVERED, even though only one instruction can be issued per clock. The low uop issue rate for a stream of INC instructions is considered to be a back end issue Instructions retired (Precise event capable) (Must be precise) Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The event continues counting during hardware interrupts, traps, and inside interrupt handlers. This is an architectural performance event. This event uses a (_P)rogrammable general purpose performance counter. *This event is Precise Event capable: The EventingRIP field in the PEBS record is precise to the address of the instruction which caused the event. Note: Because PEBS records can be collected only on IA32_PMC0, only one event can use the PEBS facility at a time (Must be precise) umask=0x0,period=2000003,event=0xc2 Uops retired (Precise event capable) (Must be precise) Counts uops which retired (Must be precise) uops_retired.ms MS uops retired (Precise event capable) (Must be precise) Counts uops retired that are from the complex flows issued by the micro-sequencer (MS). Counts both the uops from a micro-coded instruction, and the uops that might be generated from a micro-coded assist (Must be precise) uops_retired.fpdiv umask=0x8,period=2000003,event=0xc2 Floating point divide uops retired. (Precise Event Capable) (Must be precise) Counts the number of floating point divide uops retired (Must be precise) uops_retired.idiv umask=0x10,period=2000003,event=0xc2 Integer divide uops retired. (Precise Event Capable) (Must be precise) Counts the number of integer divide uops retired (Must be precise) machine_clears.all umask=0x0,period=200003,event=0xc3 All machine clears Counts machine clears for any reason umask=0x1,period=200003,event=0xc3 Counts the number of times that the processor detects that a program is writing to a code section and has to perform a machine clear because of that modification. Self-modifying code (SMC) causes a severe penalty in all Intel® architecture processors machine_clears.fp_assist umask=0x4,period=200003,event=0xc3 Machine clears due to FP assists Counts machine clears due to floating point (FP) operations needing assists. For instance, if the result was a floating point denormal, the hardware clears the pipeline and reissues uops to produce the correct IEEE compliant denormal result machine_clears.disambiguation umask=0x8,period=200003,event=0xc3 Machine clears due to memory disambiguation Counts machine clears due to memory disambiguation. Memory disambiguation happens when a load which has been issued conflicts with a previous unretired store in the pipeline whose address was not known at issue time, but is later resolved to be the same as the load address umask=0x0,period=200003,event=0xc4 Retired branch instructions (Precise event capable) (Must be precise) Counts branch instructions retired for all branch types. This is an architectural performance event (Must be precise) br_inst_retired.jcc umask=0x7e,period=200003,event=0xc4 Retired conditional branch instructions (Precise event capable) (Must be precise) Counts retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired, including both when the branch was taken and when it was not taken (Must be precise) br_inst_retired.all_taken_branches umask=0x80,period=200003,event=0xc4 Retired taken branch instructions (Precise event capable) (Must be precise) Counts the number of taken branch instructions retired (Must be precise) umask=0xbf,period=200003,event=0xc4 Retired far branch instructions (Precise event capable) (Must be precise) Counts far branch instructions retired. This includes far jump, far call and return, and Interrupt call and return (Must be precise) br_inst_retired.non_return_ind umask=0xeb,period=200003,event=0xc4 Retired instructions of near indirect Jmp or call (Precise event capable) (Must be precise) Counts near indirect call or near indirect jmp branch instructions retired (Must be precise) br_inst_retired.return umask=0xf7,period=200003,event=0xc4 Retired near return instructions (Precise event capable) (Must be precise) Counts near return branch instructions retired (Must be precise) br_inst_retired.call umask=0xf9,period=200003,event=0xc4 Retired near call instructions (Precise event capable) (Must be precise) Counts near CALL branch instructions retired (Must be precise) br_inst_retired.ind_call umask=0xfb,period=200003,event=0xc4 Retired near indirect call instructions (Precise event capable) (Must be precise) Counts near indirect CALL branch instructions retired (Must be precise) br_inst_retired.rel_call umask=0xfd,period=200003,event=0xc4 Retired near relative call instructions (Precise event capable) (Must be precise) Counts near relative CALL branch instructions retired (Must be precise) br_inst_retired.taken_jcc umask=0xfe,period=200003,event=0xc4 Retired conditional branch instructions that were taken (Precise event capable) (Must be precise) Counts Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired that were taken and does not count when the Jcc branch instruction were not taken (Must be precise) umask=0x0,period=200003,event=0xc5 Retired mispredicted branch instructions (Precise event capable) (Must be precise) Counts mispredicted branch instructions retired including all branch types (Must be precise) br_misp_retired.jcc umask=0x7e,period=200003,event=0xc5 Retired mispredicted conditional branch instructions (Precise event capable) (Must be precise) Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired, including both when the branch was supposed to be taken and when it was not supposed to be taken (but the processor predicted the opposite condition) (Must be precise) br_misp_retired.non_return_ind umask=0xeb,period=200003,event=0xc5 Retired mispredicted instructions of near indirect Jmp or near indirect call. (Precise event capable) (Must be precise) Counts mispredicted branch instructions retired that were near indirect call or near indirect jmp, where the target address taken was not what the processor predicted (Must be precise) br_misp_retired.return umask=0xf7,period=200003,event=0xc5 Retired mispredicted near return instructions (Precise event capable) (Must be precise) Counts mispredicted near RET branch instructions retired, where the return address taken was not what the processor predicted (Must be precise) br_misp_retired.ind_call umask=0xfb,period=200003,event=0xc5 Retired mispredicted near indirect call instructions (Precise event capable) (Must be precise) Counts mispredicted near indirect CALL branch instructions retired, where the target address taken was not what the processor predicted (Must be precise) br_misp_retired.taken_jcc umask=0xfe,period=200003,event=0xc5 Retired mispredicted conditional branch instructions that were taken (Precise event capable) (Must be precise) Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired that were supposed to be taken but the processor predicted that it would not be taken (Must be precise) cycles_div_busy.all umask=0x0,period=2000003,event=0xcd Cycles a divider is busy Counts core cycles if either divide unit is busy cycles_div_busy.idiv umask=0x1,period=200003,event=0xcd Cycles the integer divide unit is busy Counts core cycles the integer divide unit is busy cycles_div_busy.fpdiv umask=0x2,period=200003,event=0xcd Cycles the FP divide unit is busy Counts core cycles the floating point divide unit is busy baclears.all umask=0x1,period=200003,event=0xe6 BACLEARs asserted for any branch type Counts the number of times a BACLEAR is signaled for any reason, including, but not limited to indirect branch/call, Jcc (Jump on Conditional Code/Jump if Condition is Met) branch, unconditional branch/call, and returns baclears.return umask=0x8,period=200003,event=0xe6 BACLEARs asserted for return branch Counts BACLEARS on return instructions baclears.cond umask=0x10,period=200003,event=0xe6 BACLEARs asserted for conditional branch Counts BACLEARS on Jcc (Jump on Conditional Code/Jump if Condition is Met) branches umask=0x1,period=200003,event=0x5 Duration of D-side page-walks in cycles Counts every core cycle when a Data-side (walks due to a data operation) page walk is in progress umask=0x2,period=200003,event=0x5 Duration of I-side pagewalks in cycles Counts every core cycle when a Instruction-side (walks due to an instruction fetch) page walk is in progress umask=0x3,period=200003,event=0x5 Duration of page-walks in cycles Counts every core cycle a page-walk is in progress due to either a data memory operation or an instruction fetch itlb.miss umask=0x4,period=200003,event=0x81 ITLB misses Counts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) for a linear address of an instruction fetch. It counts when new translation are filled into the ITLB. The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLB mem_uops_retired.dtlb_miss_loads umask=0x11,period=200003,event=0xd0 Load uops retired that missed the DTLB (Precise event capable) Supports address when precise (Must be precise) Counts load uops retired that caused a DTLB miss Supports address when precise (Must be precise) mem_uops_retired.dtlb_miss_stores umask=0x12,period=200003,event=0xd0 Store uops retired that missed the DTLB (Precise event capable) Supports address when precise (Must be precise) Counts store uops retired that caused a DTLB miss Supports address when precise (Must be precise) mem_uops_retired.dtlb_miss umask=0x13,period=200003,event=0xd0 Memory uops retired that missed the DTLB (Precise event capable) Supports address when precise (Must be precise) Counts uops retired that had a DTLB miss on load, store or either. Note that when two distinct memory operations to the same page miss the DTLB, only one of them will be recorded as a DTLB miss Supports address when precise (Must be precise) Counts the number of demand and L1 prefetcher requests rejected by the L2Q due to a full or nearly full condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to insure fairness between cores, or to delay a core's dirty eviction when the address conflicts with incoming external snoops dl1.replacement umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010001 Counts demand cacheable data reads of full cache lines have any transaction responses from the uncore subsystem Counts demand cacheable data reads of full cache lines have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand cacheable data reads of full cache lines hit the L2 cache Counts demand cacheable data reads of full cache lines hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand cacheable data reads of full cache lines true miss for the L2 cache with a snoop miss in the other processor module Counts demand cacheable data reads of full cache lines true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand cacheable data reads of full cache lines miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts demand cacheable data reads of full cache lines miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand cacheable data reads of full cache lines outstanding, per cycle, from the time of the L2 miss to when any response is received Counts demand cacheable data reads of full cache lines outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010002 Counts demand reads for ownership (RFO) requests generated by a write to full data cache line have any transaction responses from the uncore subsystem Counts demand reads for ownership (RFO) requests generated by a write to full data cache line have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand reads for ownership (RFO) requests generated by a write to full data cache line hit the L2 cache Counts demand reads for ownership (RFO) requests generated by a write to full data cache line hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand reads for ownership (RFO) requests generated by a write to full data cache line true miss for the L2 cache with a snoop miss in the other processor module Counts demand reads for ownership (RFO) requests generated by a write to full data cache line true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand reads for ownership (RFO) requests generated by a write to full data cache line miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts demand reads for ownership (RFO) requests generated by a write to full data cache line miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand reads for ownership (RFO) requests generated by a write to full data cache line outstanding, per cycle, from the time of the L2 miss to when any response is received Counts demand reads for ownership (RFO) requests generated by a write to full data cache line outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010004 Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache have any transaction responses from the uncore subsystem Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache hit the L2 cache Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache true miss for the L2 cache with a snoop miss in the other processor module Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_code_rd.l2_miss.hitm_other_core umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000000004 Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache outstanding, per cycle, from the time of the L2 miss to when any response is received Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010008 Counts the number of writeback transactions caused by L1 or L2 cache evictions have any transaction responses from the uncore subsystem Counts the number of writeback transactions caused by L1 or L2 cache evictions have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts the number of writeback transactions caused by L1 or L2 cache evictions hit the L2 cache Counts the number of writeback transactions caused by L1 or L2 cache evictions hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts the number of writeback transactions caused by L1 or L2 cache evictions true miss for the L2 cache with a snoop miss in the other processor module Counts the number of writeback transactions caused by L1 or L2 cache evictions true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts the number of writeback transactions caused by L1 or L2 cache evictions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts the number of writeback transactions caused by L1 or L2 cache evictions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.corewb.outstanding umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000008 Counts the number of writeback transactions caused by L1 or L2 cache evictions outstanding, per cycle, from the time of the L2 miss to when any response is received Counts the number of writeback transactions caused by L1 or L2 cache evictions outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010010 Counts data cacheline reads generated by hardware L2 cache prefetcher have any transaction responses from the uncore subsystem Counts data cacheline reads generated by hardware L2 cache prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cacheline reads generated by hardware L2 cache prefetcher hit the L2 cache Counts data cacheline reads generated by hardware L2 cache prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cacheline reads generated by hardware L2 cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module Counts data cacheline reads generated by hardware L2 cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cacheline reads generated by hardware L2 cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts data cacheline reads generated by hardware L2 cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_data_rd.outstanding umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000010 Counts data cacheline reads generated by hardware L2 cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received Counts data cacheline reads generated by hardware L2 cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010020 Counts reads for ownership (RFO) requests generated by L2 prefetcher have any transaction responses from the uncore subsystem Counts reads for ownership (RFO) requests generated by L2 prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts reads for ownership (RFO) requests generated by L2 prefetcher hit the L2 cache Counts reads for ownership (RFO) requests generated by L2 prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts reads for ownership (RFO) requests generated by L2 prefetcher true miss for the L2 cache with a snoop miss in the other processor module Counts reads for ownership (RFO) requests generated by L2 prefetcher true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts reads for ownership (RFO) requests generated by L2 prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts reads for ownership (RFO) requests generated by L2 prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_rfo.outstanding umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000020 Counts reads for ownership (RFO) requests generated by L2 prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received Counts reads for ownership (RFO) requests generated by L2 prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts bus lock and split lock requests have any transaction responses from the uncore subsystem Counts bus lock and split lock requests have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.bus_locks.l2_hit umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000040400 Counts bus lock and split lock requests hit the L2 cache Counts bus lock and split lock requests hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.bus_locks.l2_miss.snoop_miss_or_no_snoop_needed umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200000400 Counts bus lock and split lock requests true miss for the L2 cache with a snoop miss in the other processor module Counts bus lock and split lock requests true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.bus_locks.l2_miss.hitm_other_core umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000000400 Counts bus lock and split lock requests miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts bus lock and split lock requests miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.bus_locks.outstanding umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000400 Counts bus lock and split lock requests outstanding, per cycle, from the time of the L2 miss to when any response is received Counts bus lock and split lock requests outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.full_streaming_stores.any_response umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010800 Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes have any transaction responses from the uncore subsystem Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes hit the L2 cache Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes true miss for the L2 cache with a snoop miss in the other processor module Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.full_streaming_stores.outstanding umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000800 Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes outstanding, per cycle, from the time of the L2 miss to when any response is received Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.sw_prefetch.any_response umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000011000 Counts data cache lines requests by software prefetch instructions have any transaction responses from the uncore subsystem Counts data cache lines requests by software prefetch instructions have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cache lines requests by software prefetch instructions hit the L2 cache Counts data cache lines requests by software prefetch instructions hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cache lines requests by software prefetch instructions true miss for the L2 cache with a snoop miss in the other processor module Counts data cache lines requests by software prefetch instructions true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cache lines requests by software prefetch instructions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts data cache lines requests by software prefetch instructions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.sw_prefetch.outstanding umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000001000 Counts data cache lines requests by software prefetch instructions outstanding, per cycle, from the time of the L2 miss to when any response is received Counts data cache lines requests by software prefetch instructions outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l1_data_rd.any_response umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000012000 Counts data cache line reads generated by hardware L1 data cache prefetcher have any transaction responses from the uncore subsystem Counts data cache line reads generated by hardware L1 data cache prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cache line reads generated by hardware L1 data cache prefetcher hit the L2 cache Counts data cache line reads generated by hardware L1 data cache prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cache line reads generated by hardware L1 data cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module Counts data cache line reads generated by hardware L1 data cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cache line reads generated by hardware L1 data cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts data cache line reads generated by hardware L1 data cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l1_data_rd.outstanding umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000002000 Counts data cache line reads generated by hardware L1 data cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received Counts data cache line reads generated by hardware L1 data cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.streaming_stores.any_response umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000014800 Counts any data writes to uncacheable write combining (USWC) memory region have any transaction responses from the uncore subsystem Counts any data writes to uncacheable write combining (USWC) memory region have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts any data writes to uncacheable write combining (USWC) memory region hit the L2 cache Counts any data writes to uncacheable write combining (USWC) memory region hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.streaming_stores.l2_miss.snoop_miss_or_no_snoop_needed umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200004800 Counts any data writes to uncacheable write combining (USWC) memory region true miss for the L2 cache with a snoop miss in the other processor module Counts any data writes to uncacheable write combining (USWC) memory region true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.streaming_stores.l2_miss.hitm_other_core umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000004800 Counts any data writes to uncacheable write combining (USWC) memory region miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts any data writes to uncacheable write combining (USWC) memory region miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.streaming_stores.outstanding umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000004800 Counts any data writes to uncacheable write combining (USWC) memory region outstanding, per cycle, from the time of the L2 miss to when any response is received Counts any data writes to uncacheable write combining (USWC) memory region outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts requests to the uncore subsystem have any transaction responses from the uncore subsystem Counts requests to the uncore subsystem have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts requests to the uncore subsystem hit the L2 cache Counts requests to the uncore subsystem hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts requests to the uncore subsystem true miss for the L2 cache with a snoop miss in the other processor module Counts requests to the uncore subsystem true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts requests to the uncore subsystem miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts requests to the uncore subsystem miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_request.outstanding umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000008000 Counts requests to the uncore subsystem outstanding, per cycle, from the time of the L2 miss to when any response is received Counts requests to the uncore subsystem outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_pf_data_rd.any_response umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000013010 Counts data reads generated by L1 or L2 prefetchers have any transaction responses from the uncore subsystem Counts data reads generated by L1 or L2 prefetchers have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data reads generated by L1 or L2 prefetchers hit the L2 cache Counts data reads generated by L1 or L2 prefetchers hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data reads generated by L1 or L2 prefetchers true miss for the L2 cache with a snoop miss in the other processor module Counts data reads generated by L1 or L2 prefetchers true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data reads generated by L1 or L2 prefetchers miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts data reads generated by L1 or L2 prefetchers miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_pf_data_rd.outstanding umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000003010 Counts data reads generated by L1 or L2 prefetchers outstanding, per cycle, from the time of the L2 miss to when any response is received Counts data reads generated by L1 or L2 prefetchers outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_data_rd.any_response umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000013091 Counts data reads (demand & prefetch) have any transaction responses from the uncore subsystem Counts data reads (demand & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data reads (demand & prefetch) hit the L2 cache Counts data reads (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data reads (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module Counts data reads (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data reads (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts data reads (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_data_rd.outstanding umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000003091 Counts data reads (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received Counts data reads (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_rfo.any_response umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010022 Counts reads for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem Counts reads for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts reads for ownership (RFO) requests (demand & prefetch) hit the L2 cache Counts reads for ownership (RFO) requests (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts reads for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module Counts reads for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts reads for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts reads for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_rfo.outstanding umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000022 Counts reads for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received Counts reads for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_read.any_response umask=0x1,period=100007,event=0xb7,offcore_rsp=0x00000132b7 Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) hit the L2 cache Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_read.outstanding umask=0x1,period=100007,event=0xb7,offcore_rsp=0x40000032b7 Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) umask=0x2,period=20003,event=0xc3 Counts machine clears due to memory ordering issues. This occurs when a snoop request happens and the machine is uncertain if memory ordering will be preserved - as another core is in the process of modifying the data Cycles the code-fetch stalls and an ITLB miss is outstanding Instructions retired (Fixed event) (Must be precise) Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0. You cannot collect a PEBs record for this event (Must be precise) Reference cycles when core is not halted. This event uses a (_P)rogrammable general purpose performance counter umask=0x0,period=2000003,event=0xc0 Instructions retired - using Reduced Skid PEBS feature (Must be precise) Counts INST_RETIRED.ANY using the Reduced Skid PEBS feature that reduces the shadow in which events aren't counted allowing for a more unbiased distribution of samples across instructions retired (Must be precise) Floating point divide uops retired (Precise Event Capable) (Must be precise) Integer divide uops retired (Precise Event Capable) (Must be precise) umask=0x0,period=20003,event=0xc3 umask=0x1,period=20003,event=0xc3 umask=0x4,period=20003,event=0xc3 umask=0x8,period=20003,event=0xc3 machine_clears.page_fault umask=0x20,period=20003,event=0xc3 Machines clear due to a page fault Counts the number of times that the machines clears due to a page fault. Covers both I-side and D-side(Loads/Stores) page faults. A page fault occurs when either page is not present, or an access violation Retired mispredicted instructions of near indirect Jmp or near indirect call (Precise event capable) (Must be precise) umask=0x2,period=200003,event=0x8 Page walk completed due to a demand load to a 4K page Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 4K pages. The page walks can end with or without a page fault umask=0x4,period=200003,event=0x8 Page walk completed due to a demand load to a 2M or 4M page Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 2M or 4M pages. The page walks can end with or without a page fault dtlb_load_misses.walk_completed_1gb umask=0x8,period=200003,event=0x8 Page walk completed due to a demand load to a 1GB page Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 1GB pages. The page walks can end with or without a page fault dtlb_load_misses.walk_pending umask=0x10,period=200003,event=0x8 Page walks outstanding due to a demand load every cycle Counts once per cycle for each page walk occurring due to a load (demand data loads or SW prefetches). Includes cycles spent traversing the Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of walks umask=0x2,period=2000003,event=0x49 Page walk completed due to a demand data store to a 4K page Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault umask=0x4,period=2000003,event=0x49 Page walk completed due to a demand data store to a 2M or 4M page Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 2M or 4M pages. The page walks can end with or without a page fault dtlb_store_misses.walk_completed_1gb umask=0x8,period=2000003,event=0x49 Page walk completed due to a demand data store to a 1GB page Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 1GB pages. The page walks can end with or without a page fault dtlb_store_misses.walk_pending umask=0x10,period=200003,event=0x49 Page walks outstanding due to a demand data store every cycle Counts once per cycle for each page walk occurring due to a demand data store. Includes cycles spent traversing the Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of walks ept.walk_pending umask=0x10,period=200003,event=0x4f Page walks outstanding due to walking the EPT every cycle Counts once per cycle for each page walk only while traversing the Extended Page Table (EPT), and does not count during the rest of the translation. The EPT is used for translating Guest-Physical Addresses to Physical Addresses for Virtual Machine Monitors (VMMs). Average cycles per walk can be calculated by dividing the count by number of walks umask=0x2,period=2000003,event=0x85 Page walk completed due to an instruction fetch in a 4K page Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault umask=0x4,period=2000003,event=0x85 Page walk completed due to an instruction fetch in a 2M or 4M page Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 2M or 4M pages. The page walks can end with or without a page fault itlb_misses.walk_completed_1gb umask=0x8,period=2000003,event=0x85 Page walk completed due to an instruction fetch in a 1GB page Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 1GB pages. The page walks can end with or without a page fault itlb_misses.walk_pending umask=0x10,period=200003,event=0x85 Page walks outstanding due to an instruction fetch every cycle Counts once per cycle for each page walk occurring due to an instruction fetch. Includes cycles spent traversing the Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of walks tlb_flushes.stlb_any umask=0x20,period=20003,event=0xbd STLB flushes Counts STLB flushes. The TLBs are flushed on instructions like INVLPG and MOV to CR3 Demand Data Read miss L2, no rejects Spec update: HSD78 Demand data read requests that missed L2, no rejects Spec update: HSD78 Counts the number of store RFO requests that miss the L2 cache Number of instruction fetches that missed the L2 cache Demand requests that miss L2 cache Spec update: HSD78 Counts all L2 HW prefetcher requests that missed L2 All requests that miss L2 cache Spec update: HSD78 All requests that missed L2 Spec update: HSD78 Demand Data Read requests that hit L2 cache Spec update: HSD78 Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache Spec update: HSD78 Counts the number of store RFO requests that hit the L2 cache Number of instruction fetches that hit the L2 cache Counts all L2 HW prefetcher requests that hit L2 Demand Data Read requests Spec update: HSD78 Counts any demand and L1 HW prefetch data load requests to L2 Spec update: HSD78 Counts all L2 store RFO requests Counts all L2 code requests Demand requests to L2 cache Spec update: HSD78 Counts all L2 HW prefetcher requests All L2 requests Spec update: HSD78 All requests to L2 cache Spec update: HSD78 This event counts each cache miss condition for references to the last level cache This event counts requests originating from the core that reference a cache line in the last level cache Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences l1d_pend_miss.request_fb_full umask=0x2,period=2000003,event=0x48 Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e This event counts when new data lines are brought into the L1 Data cache, which cause other lines to be evicted from the cache Offcore outstanding Demand Data Read transactions in uncore queue Spec update: HSD78, HSD62, HSD61 Offcore outstanding demand data read transactions in SQ to uncore. Set Cmask=1 to count cycles Spec update: HSD78, HSD62, HSD61 Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore Spec update: HSD78, HSD62, HSD61 Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue Spec update: HSD78, HSD62, HSD61 Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle Spec update: HSD62, HSD61 Offcore outstanding Demand code Read transactions in SQ to uncore. Set Cmask=1 to count cycles Spec update: HSD62, HSD61 Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore Spec update: HSD62, HSD61 Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles Spec update: HSD62, HSD61 Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle Spec update: HSD62, HSD61 Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore Spec update: HSD62, HSD61 Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles Spec update: HSD62, HSD61 Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore Spec update: HSD62, HSD61 Cycles in which the L1D is locked Demand Data Read requests sent to uncore Spec update: HSD78 Demand data read requests sent to uncore Spec update: HSD78 Demand code read requests sent to uncore Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM Data read requests sent to uncore (demand and prefetch) Retired load uops that miss the STLB. (precise Event) Spec update: HSD29, HSM30. Supports address when precise (Precise event) Retired store uops that miss the STLB. (precise Event) Spec update: HSD29, HSM30. Supports address when precise (Precise event) umask=0x21,period=100003,event=0xd0 Retired load uops with locked access. (precise Event) Spec update: HSD76, HSD29, HSM30. Supports address when precise (Precise event) Retired load uops that split across a cacheline boundary. (precise Event) Spec update: HSD29, HSM30. Supports address when precise (Precise event) This event counts load uops retired which had memory addresses spilt across 2 cache lines. A line split is across 64B cache-lines which may include a page split (4K). This is a precise event Spec update: HSD29, HSM30. Supports address when precise (Precise event) Retired store uops that split across a cacheline boundary. (precise Event) Spec update: HSD29, HSM30. Supports address when precise (Precise event) This event counts store uops retired which had memory addresses spilt across 2 cache lines. A line split is across 64B cache-lines which may include a page split (4K). This is a precise event Spec update: HSD29, HSM30. Supports address when precise (Precise event) All retired load uops. (precise Event) Spec update: HSD29, HSM30. Supports address when precise (Precise event) All retired store uops. (precise Event) Spec update: HSD29, HSM30. Supports address when precise (Precise event) This event counts all store uops retired. This is a precise event Spec update: HSD29, HSM30. Supports address when precise (Precise event) Retired load uops with L1 cache hits as data sources Spec update: HSD29, HSM30. Supports address when precise (Precise event) Retired load uops with L2 cache hits as data sources Spec update: HSD76, HSD29, HSM30. Supports address when precise (Precise event) Miss in last-level (L3) cache. Excludes Unknown data-source Spec update: HSD74, HSD29, HSD25, HSM26, HSM30. Supports address when precise (Precise event) This event counts retired load uops in which data sources were data hits in the L3 cache without snoops required. This does not include hardware prefetches. This is a precise event Spec update: HSD74, HSD29, HSD25, HSM26, HSM30. Supports address when precise (Precise event) Retired load uops misses in L1 cache as data sources Spec update: HSM30. Supports address when precise (Precise event) This event counts retired load uops in which data sources missed in the L1 cache. This does not include hardware prefetches. This is a precise event Spec update: HSM30. Supports address when precise (Precise event) Retired load uops with L2 cache misses as data sources Spec update: HSD29, HSM30. Supports address when precise (Precise event) umask=0x20,period=100003,event=0xd1 Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready Spec update: HSM30. Supports address when precise (Precise event) Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache Spec update: HSD29, HSD25, HSM26, HSM30. Supports address when precise (Precise event) Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache Spec update: HSD29, HSD25, HSM26, HSM30. Supports address when precise (Precise event) This event counts retired load uops that hit in the L3 cache, but required a cross-core snoop which resulted in a HIT in an on-pkg core cache. This does not include hardware prefetches. This is a precise event Spec update: HSD29, HSD25, HSM26, HSM30. Supports address when precise (Precise event) Retired load uops which data sources were HitM responses from shared L3 Spec update: HSD29, HSD25, HSM26, HSM30. Supports address when precise (Precise event) This event counts retired load uops that hit in the L3 cache, but required a cross-core snoop which resulted in a HITM (hit modified) in an on-pkg core cache. This does not include hardware prefetches. This is a precise event Spec update: HSD29, HSD25, HSM26, HSM30. Supports address when precise (Precise event) Retired load uops which data sources were hits in L3 without snoops required Spec update: HSD74, HSD29, HSD25, HSM26, HSM30. Supports address when precise (Precise event) umask=0x1,period=100003,event=0xd3 This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches. This is a precise event Spec update: HSD74, HSD29, HSD25, HSM30. Supports address when precise Demand data read requests that access L2 cache Any MLC or L3 HW prefetch accessing L2, including rejects This event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2 cache when there was an L2 miss l2_lines_out.demand_dirty umask=0x6,period=100003,event=0xf2 Dirty L2 cache lines evicted by demand offcore_response.all_requests.l3_hit.any_response offcore_response.all_reads.l3_hit.hitm_other_core hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded offcore_response.all_reads.l3_hit.hit_other_core_no_fwd hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded offcore_response.all_code_rd.l3_hit.hit_other_core_no_fwd offcore_response.all_rfo.l3_hit.hitm_other_core offcore_response.all_rfo.l3_hit.hit_other_core_no_fwd offcore_response.all_data_rd.l3_hit.hitm_other_core offcore_response.all_data_rd.l3_hit.hit_other_core_no_fwd offcore_response.pf_l3_code_rd.l3_hit.any_response offcore_response.pf_l3_rfo.l3_hit.any_response offcore_response.pf_l3_data_rd.l3_hit.any_response Counts all prefetch (that bring data to LLC only) data reads hit in the L3 offcore_response.pf_l2_code_rd.l3_hit.any_response Counts all prefetch (that bring data to LLC only) code reads hit in the L3 offcore_response.pf_l2_rfo.l3_hit.any_response Counts all prefetch (that bring data to L2) RFOs hit in the L3 offcore_response.pf_l2_data_rd.l3_hit.any_response Counts prefetch (that bring data to L2) data reads hit in the L3 offcore_response.demand_code_rd.l3_hit.hitm_other_core Counts all demand code reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded offcore_response.demand_code_rd.l3_hit.hit_other_core_no_fwd Counts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded offcore_response.demand_rfo.l3_hit.hitm_other_core offcore_response.demand_rfo.l3_hit.hit_other_core_no_fwd Counts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded offcore_response.demand_data_rd.l3_hit.hitm_other_core Counts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded offcore_response.demand_data_rd.l3_hit.hit_other_core_no_fwd Counts demand data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Number of transitions from AVX-256 to legacy SSE when penalty applicable Spec update: HSD56, HSM57 (Precise event) Spec update: HSD56, HSM57 (Precise event) Number of transitions from legacy SSE to AVX-256 when penalty applicable Spec update: HSD56, HSM57 (Precise event) avx_insts.all umask=0x7,period=2000003,event=0xc6 Approximate counts of AVX & AVX2 256-bit instructions, including non-arithmetic instructions, loads, and stores. May count non-AVX instructions that employ 256-bit operations, including (but not necessarily limited to) rep string instructions that use 256-bit loads and stores for optimized performance, XSAVE* and XRSTOR*, and operations that transition the x87 FPU data registers between x87 and MMX Note that a whole rep string only counts AVX_INST.ALL once output - Numeric Overflow, Numeric Underflow, Inexact Result (Precise event) (Precise event) input - Invalid Operation, Denormal Operand, SNaN Operand (Precise event) SSE* FP micro-code assist when output value is invalid (Precise event) Any input SSE* FP Assist (Precise event) Counts any FP_ASSIST umask was incrementing (Precise event) Instruction Decode Queue (IDQ) empty cycles Spec update: HSD135 Counts cycles the IDQ is empty Spec update: HSD135 Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery Counts cycles DSB is delivered four uops. Set Cmask = 4 Counts cycles DSB is delivered at least one uops. Set Cmask = 1 Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles Counts cycles MITE is delivered four uops. Set Cmask = 4 Counts cycles MITE is delivered at least one uop. Set Cmask = 1 This event counts uops delivered by the Front-end with the assistance of the microcode sequencer. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance This event counts cycles during which the microcode sequencer assisted the Front-end in delivering uops. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance Number of uops delivered to IDQ from any path This event counts Instruction Cache (ICACHE) misses icache.ifetch_stall Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled Spec update: HSD135 This event count the number of undelivered (unallocated) uops from the Front-end to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalled. The Front-end can allocate up to 4 uops per cycle so this event can increment 0-4 times per cycle depending on the number of unallocated uops. This event is counted on a per-core basis Spec update: HSD135 Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled Spec update: HSD135 This event counts the number cycles during which the Front-end allocated exactly zero uops to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalled. This event is counted on a per-core basis Spec update: HSD135 Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled Spec update: HSD135 Cycles with less than 2 uops delivered by the front end Spec update: HSD135 Cycles with less than 3 uops delivered by the front end Spec update: HSD135 Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE Spec update: HSD135 hsw metrics ( uops_executed.core / 2 / (( cpu@uops_executed.core\,cmask\=1@ / 2 ) if #smt_on else cpu@uops_executed.core\,cmask\=1@) ) if #smt_on else uops_executed.core / (( cpu@uops_executed.core\,cmask\=1@ / 2 ) if #smt_on else cpu@uops_executed.core\,cmask\=1@) ( itlb_misses.walk_duration + dtlb_load_misses.walk_duration + dtlb_store_misses.walk_duration ) / cycles ( itlb_misses.walk_duration + dtlb_load_misses.walk_duration + dtlb_store_misses.walk_duration ) / (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )) Speculative cache-line split load uops dispatched to L1D Speculative cache-line split store-address uops dispatched to L1D Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address Number of times a transactional abort was signaled due to a data capacity limitation for transactional writes Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero This event counts the number of memory ordering machine clears detected. Memory ordering machine clears can result from memory address aliasing or snoops from another hardware thread or core to data inflight in the pipeline. Machine clears can have a significant performance impact if they are happening frequently Number of times an HLE execution started Number of times an HLE execution successfully committed Number of times an HLE execution aborted due to any reasons (multiple categories may count as one) (Precise event) Number of times an HLE execution aborted due to incompatible memory type Spec update: HSD65 Number of times an RTM execution started Number of times an RTM execution successfully committed Number of times an RTM execution aborted due to any reasons (multiple categories may count as one) (Precise event) Number of times an RTM execution aborted due to incompatible memory type Spec update: HSD65 Randomly selected loads with latency value being above 4 Spec update: HSD76, HSD25, HSM26 (Must be precise) Randomly selected loads with latency value being above 8 Spec update: HSD76, HSD25, HSM26 (Must be precise) Randomly selected loads with latency value being above 16 Spec update: HSD76, HSD25, HSM26 (Must be precise) umask=0x1,period=100003,event=0xcd,ldlat=0x20 Randomly selected loads with latency value being above 32 Spec update: HSD76, HSD25, HSM26 (Must be precise) Randomly selected loads with latency value being above 64 Spec update: HSD76, HSD25, HSM26 (Must be precise) Randomly selected loads with latency value being above 128 Spec update: HSD76, HSD25, HSM26 (Must be precise) Randomly selected loads with latency value being above 256 Spec update: HSD76, HSD25, HSM26 (Must be precise) Randomly selected loads with latency value being above 512 Spec update: HSD76, HSD25, HSM26 (Must be precise) offcore_response.all_requests.l3_miss.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC08FFF offcore_response.all_reads.l3_miss.local_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01004007F7 miss the L3 and the data is returned from local dram offcore_response.all_reads.l3_miss.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC007F7 miss in the L3 offcore_response.all_code_rd.l3_miss.local_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100400244 offcore_response.all_code_rd.l3_miss.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00244 offcore_response.all_rfo.l3_miss.local_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100400122 offcore_response.all_rfo.l3_miss.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00122 offcore_response.all_data_rd.l3_miss.local_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100400091 offcore_response.all_data_rd.l3_miss.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00091 offcore_response.pf_l3_code_rd.l3_miss.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00200 offcore_response.pf_l3_rfo.l3_miss.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00100 offcore_response.pf_l3_data_rd.l3_miss.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00080 Counts all prefetch (that bring data to LLC only) data reads miss in the L3 offcore_response.pf_l2_code_rd.l3_miss.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00040 Counts all prefetch (that bring data to LLC only) code reads miss in the L3 offcore_response.pf_l2_rfo.l3_miss.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00020 Counts all prefetch (that bring data to L2) RFOs miss in the L3 offcore_response.pf_l2_data_rd.l3_miss.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00010 Counts prefetch (that bring data to L2) data reads miss in the L3 offcore_response.demand_code_rd.l3_miss.local_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100400004 Counts all demand code reads miss the L3 and the data is returned from local dram offcore_response.demand_code_rd.l3_miss.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00004 Counts all demand code reads miss in the L3 offcore_response.demand_rfo.l3_miss.local_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100400002 Counts all demand data writes (RFOs) miss the L3 and the data is returned from local dram offcore_response.demand_rfo.l3_miss.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00002 offcore_response.demand_data_rd.l3_miss.local_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100400001 Counts demand data reads miss the L3 and the data is returned from local dram offcore_response.demand_data_rd.l3_miss.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00001 Counts demand data reads miss in the L3 umask=0x1,edge=1,period=100003,cmask=1,event=0x5c Unhalted core cycles when the thread is not in ring 0 Cycles in which the L1D and L2 are locked, due to a UC lock or split lock Instructions retired from execution Spec update: HSD140, HSD143 This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. INST_RETIRED.ANY is counted by a designated fixed counter, leaving the programmable counters available for other events. Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions Spec update: HSD140, HSD143 This event counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state loads blocked by overlapping with store buffer that cannot be forwarded This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store. The penalty for blocked store forwarding is that the load must wait for the store to write its value to the cache before it can be issued The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use False dependencies in MOB due to partial compare on address Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K. This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline which can have a performance impact This event counts the number of cycles spent waiting for a recovery after an event such as a processor nuke, JEClear, assist, hle/rtm abort etc This event counts the number of uops issued by the Front-end of the pipeline to the Back-end. This event is counted at the allocation stage and will count both retired and non-retired uops uops_issued.core_stall_cycles inv=1,umask=0x1,any=1,period=2000003,cmask=1,event=0xe Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads Number of flags-merge uops allocated. Such uops add delay Number of slow LEA or similar uops allocated. Such uop has 3 sources (for example, 2 sources + immediate) regardless of whether it is a result of LEA instruction or not Number of multiply packed/scalar single precision uops allocated arith.divider_uops umask=0x2,period=2000003,event=0x14 Any uop executed by the Divider. (This includes all divide uops, sqrt, ...) Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling Increments at the frequency of XCLK (100 MHz) when not halted Reference cycles when the thread is unhalted. (counts at 100 MHz rate) Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch Number of integer move elimination candidate uops that were eliminated Number of SIMD move elimination candidate uops that were eliminated Number of integer move elimination candidate uops that were not eliminated Number of SIMD move elimination candidate uops that were not eliminated This event counts cycles when the Reservation Station ( RS ) is empty for the thread. The RS is a structure that buffers allocated micro-ops from the Front-end. If there are many cycles when the RS is empty, it may represent an underflow of instructions delivered from the Front-end This event counts cycles where the decoder is stalled on an instruction with a length changing prefix (LCP) ild_stall.iq_full umask=0x4,period=2000003,event=0x87 Stall cycles because IQ is full Stall cycles due to IQ is full Counts all near executed branches (not necessarily retired) Cycles which a uop is dispatched on port 0 in this thread Cycles per core when uops are executed in port 0 Cycles which a uop is dispatched on port 1 in this thread Cycles per core when uops are executed in port 1 Cycles which a uop is dispatched on port 2 in this thread Cycles which a uop is dispatched on port 3 in this thread Cycles which a uop is dispatched on port 4 in this thread Cycles per core when uops are executed in port 4 Cycles which a uop is dispatched on port 5 in this thread Cycles per core when uops are executed in port 5 Cycles which a uop is dispatched on port 6 in this thread Cycles per core when uops are executed in port 6 Cycles which a uop is dispatched on port 7 in this thread Resource-related stall cycles Spec update: HSD135 Cycles allocation is stalled due to resource related reason Spec update: HSD135 This event counts cycles during which no instructions were allocated because no Store Buffers (SB) were available Cycles with pending L2 cache miss loads Spec update: HSD78 Cycles with pending L2 miss loads. Set Cmask=2 to count cycle Spec update: HSD78 Cycles with pending memory loads Cycles with pending memory loads. Set Cmask=2 to count cycle This event counts cycles during which no instructions were executed in the execution stage of the pipeline Execution stalls due to L2 cache misses Number of loads missed L2 Execution stalls due to memory subsystem This event counts cycles during which no instructions were executed in the execution stage of the pipeline and there were memory instructions pending (waiting for data) Cycles with pending L1 cache miss loads Cycles with pending L1 data cache miss loads. Set Cmask=8 to count cycle Execution stalls due to L1 data cache misses Execution stalls due to L1 data cache miss loads. Set Cmask=0CH Number of uops delivered by the LSD Counts number of cycles no uops were dispatched to be executed on this thread Spec update: HSD144, HSD30, HSM31 Cycles where at least 1 uop was executed per-thread Spec update: HSD144, HSD30, HSM31 This events counts the cycles where at least one uop was executed. It is counted per thread Spec update: HSD144, HSD30, HSM31 Cycles where at least 2 uops were executed per-thread Spec update: HSD144, HSD30, HSM31 This events counts the cycles where at least two uop were executed. It is counted per thread Spec update: HSD144, HSD30, HSM31 Cycles where at least 3 uops were executed per-thread Spec update: HSD144, HSD30, HSM31 This events counts the cycles where at least three uop were executed. It is counted per thread Spec update: HSD144, HSD30, HSM31 Cycles where at least 4 uops were executed per-thread Spec update: HSD144, HSD30, HSM31 Number of uops executed on the core Spec update: HSD30, HSM31 Counts total number of uops to be executed per-core each cycle Spec update: HSD30, HSM31 Cycles at least 1 micro-op is executed from any thread on physical core Spec update: HSD30, HSM31 Cycles at least 2 micro-op is executed from any thread on physical core Spec update: HSD30, HSM31 Cycles at least 3 micro-op is executed from any thread on physical core Spec update: HSD30, HSM31 Cycles at least 4 micro-op is executed from any thread on physical core Spec update: HSD30, HSM31 Cycles with no micro-ops executed from any thread on physical core Spec update: HSD30, HSM31 Number of instructions retired. General Counter - architectural event Spec update: HSD11, HSD140 Number of instructions at retirement Spec update: HSD11, HSD140 Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution Spec update: HSD140 (Must be precise) FP operations retired. X87 FP operations that have no exceptions: Counts also flows that have several X87 or flows that use X87 uops in the exception handling (Precise event) Cycles no executable uops retired (Precise event) uops_retired.core_stall_cycles inv=1,umask=0x1,any=1,period=2000003,cmask=1,event=0xc2 Cycles no executable uops retired on core (Precise event) This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear. Machine clears can have a significant performance impact if they are happening frequently Branch instructions at retirement umask=0x2,period=100003,event=0xc4 All (macro) branch instructions retired (Must be precise) umask=0x8,period=100003,event=0xc4 Counts all not taken macro branch instructions retired (Precise event) umask=0x40,period=100003,event=0xc4 Counts the number of far branch instructions retired (Precise event) Mispredicted branch instructions at retirement Mispredicted macro branch instructions retired (Must be precise) This event counts all mispredicted branch instructions retired. This is a precise event (Must be precise) Count cases of saving new LBR records by hardware Number of front end re-steers due to BPU misprediction unc_cbo_xsnp_response.miss_external umask=0x21,event=0x22 Unit: uncore_cbox An external snoop misses in some processor core An external snoop misses in some processor core unc_cbo_xsnp_response.hit_external umask=0x24,event=0x22 Unit: uncore_cbox An external snoop hits a non-modified line in some processor core An external snoop hits a non-modified line in some processor core unc_cbo_xsnp_response.hit_eviction umask=0x84,event=0x22 Unit: uncore_cbox A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core unc_cbo_xsnp_response.hitm_external umask=0x28,event=0x22 Unit: uncore_cbox An external snoop hits a modified line in some processor core An external snoop hits a modified line in some processor core unc_cbo_xsnp_response.hitm_eviction umask=0x88,event=0x22 Unit: uncore_cbox A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core unc_cbo_cache_lookup.extsnp_m umask=0x41,event=0x34 Unit: uncore_cbox L3 Lookup external snoop request that access cache and found line in M-state L3 Lookup external snoop request that access cache and found line in M-state unc_cbo_cache_lookup.write_i umask=0x28,event=0x34 Unit: uncore_cbox L3 Lookup write request that access cache and found line in I-state L3 Lookup write request that access cache and found line in I-state unc_cbo_cache_lookup.extsnp_i umask=0x48,event=0x34 Unit: uncore_cbox L3 Lookup external snoop request that access cache and found line in I-state L3 Lookup external snoop request that access cache and found line in I-state unc_cbo_cache_lookup.extsnp_mesi umask=0x4f,event=0x34 Unit: uncore_cbox L3 Lookup external snoop request that access cache and found line in MESI-state L3 Lookup external snoop request that access cache and found line in MESI-state unc_cbo_cache_lookup.extsnp_es umask=0x46,event=0x34 Unit: uncore_cbox L3 Lookup external snoop request that access cache and found line in E or S-state L3 Lookup external snoop request that access cache and found line in E or S-state unc_arb_coh_trk_occupancy.all umask=0x01,event=0x83 Unit: uncore_arb Each cycle count number of valid entries in Coherency Tracker queue from allocation till deallocation. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access memory) Each cycle count number of valid entries in Coherency Tracker queue from allocation till deallocation. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access memory) Load misses in all DTLB levels that cause page walks Misses in all TLB levels that cause a page walk of any page size Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K) Completed page walks due to demand load misses that caused 4K page walks in any TLB levels Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M) Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levels Load miss in all TLB levels causes a page walk that completes. (1G) Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size Completed page walks in any TLB of any page size due to demand load misses Cycles when PMH is busy with page walks This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses This event counts load operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks This event counts load operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks Number of cache load STLB hits. No page walk dtlb_load_misses.pde_cache_miss umask=0x80,period=100003,event=0x8 DTLB demand load misses with low part of linear-to-physical address translation missed Store misses in all DTLB levels that cause page walks Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G) Store miss in all TLB levels causes a page walk that completes. (4K) Completed page walks due to store misses in one or more TLB levels of 4K page structure Store misses in all DTLB levels that cause completed page walks (2M/4M) Completed page walks due to store misses in one or more TLB levels of 2M/4M page structure Store misses in all DTLB levels that cause completed page walks. (1G) Store misses in all DTLB levels that cause completed page walks Completed page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G) This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB store misses This event counts store operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks This event counts store operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks dtlb_store_misses.pde_cache_miss umask=0x80,period=100003,event=0x49 DTLB store misses with low part of linear-to-physical address translation missed Misses at all ITLB levels that cause page walks Misses in ITLB that causes a page walk of any page size Code miss in all TLB levels causes a page walk that completes. (4K) Completed page walks due to misses in ITLB 4K page entries Code miss in all TLB levels causes a page walk that completes. (2M/4M) Completed page walks due to misses in ITLB 2M/4M page entries Store miss in all TLB levels causes a page walk that completes. (1G) Misses in all ITLB levels that cause completed page walks Completed page walks in ITLB of any page size This event counts cycles when the page miss handler (PMH) is servicing page walks caused by ITLB misses ITLB misses that hit STLB (4K) ITLB misses that hit STLB (2M) ITLB misses that hit STLB. No page walk umask=0x1,period=100003,event=0xae Counts the number of ITLB flushes, includes 4k/2M/4M pages Number of DTLB page walker hits in the L1+FB Number of DTLB page walker loads that hit in the L1+FB Number of DTLB page walker hits in the L2 Number of DTLB page walker loads that hit in the L2 Number of DTLB page walker hits in the L3 + XSNP Spec update: HSD25 Number of DTLB page walker loads that hit in the L3 Spec update: HSD25 Number of DTLB page walker hits in Memory Spec update: HSD25 Number of DTLB page walker loads from memory Spec update: HSD25 Number of ITLB page walker hits in the L1+FB Number of ITLB page walker loads that hit in the L1+FB Number of ITLB page walker hits in the L2 Number of ITLB page walker loads that hit in the L2 Number of ITLB page walker hits in the L3 + XSNP Spec update: HSD25 Number of ITLB page walker loads that hit in the L3 Spec update: HSD25 page_walker_loads.itlb_memory umask=0x28,period=2000003,event=0xbc Number of ITLB page walker hits in Memory Spec update: HSD25 Number of ITLB page walker loads from memory Spec update: HSD25 page_walker_loads.ept_dtlb_l1 umask=0x41,period=2000003,event=0xbc Counts the number of Extended Page Table walks from the DTLB that hit in the L1 and FB page_walker_loads.ept_dtlb_l2 umask=0x42,period=2000003,event=0xbc Counts the number of Extended Page Table walks from the DTLB that hit in the L2 page_walker_loads.ept_dtlb_l3 umask=0x44,period=2000003,event=0xbc Counts the number of Extended Page Table walks from the DTLB that hit in the L3 page_walker_loads.ept_dtlb_memory umask=0x48,period=2000003,event=0xbc Counts the number of Extended Page Table walks from the DTLB that hit in memory page_walker_loads.ept_itlb_l1 umask=0x81,period=2000003,event=0xbc Counts the number of Extended Page Table walks from the ITLB that hit in the L1 and FB page_walker_loads.ept_itlb_l2 umask=0x82,period=2000003,event=0xbc Counts the number of Extended Page Table walks from the ITLB that hit in the L2 page_walker_loads.ept_itlb_l3 umask=0x84,period=2000003,event=0xbc page_walker_loads.ept_itlb_memory umask=0x88,period=2000003,event=0xbc Counts the number of Extended Page Table walks from the ITLB that hit in memory umask=0x1,period=100003,event=0xbd umask=0x20,period=100003,event=0xbd Count number of STLB flush attempts Retired load uops that miss the STLB Supports address when precise. Spec update: HSD29, HSM30 (Precise event) Retired store uops that miss the STLB Supports address when precise. Spec update: HSD29, HSM30 (Precise event) Retired load uops with locked access Supports address when precise. Spec update: HSD76, HSD29, HSM30 (Precise event) Retired load uops that split across a cacheline boundary Supports address when precise. Spec update: HSD29, HSM30 (Precise event) Retired store uops that split across a cacheline boundary Supports address when precise. Spec update: HSD29, HSM30 (Precise event) All retired load uops Supports address when precise. Spec update: HSD29, HSM30 (Precise event) All retired store uops Supports address when precise. Spec update: HSD29, HSM30 (Precise event) Retired load uops with L1 cache hits as data sources Supports address when precise. Spec update: HSD29, HSM30 (Precise event) Retired load uops with L2 cache hits as data sources Supports address when precise. Spec update: HSD76, HSD29, HSM30 (Precise event) Retired load uops which data sources were data hits in L3 without snoops required Supports address when precise. Spec update: HSD74, HSD29, HSD25, HSM26, HSM30 (Precise event) Retired load uops with L3 cache hits as data sources Supports address when precise. Spec update: HSD74, HSD29, HSD25, HSM26, HSM30 (Precise event) Retired load uops misses in L1 cache as data sources Supports address when precise. Spec update: HSM30 (Precise event) Retired load uops missed L1 cache as data sources Supports address when precise. Spec update: HSM30 (Precise event) Miss in mid-level (L2) cache. Excludes Unknown data-source Supports address when precise. Spec update: HSD29, HSM30 (Precise event) Retired load uops missed L2. Unknown data source excluded Supports address when precise. Spec update: HSD29, HSM30 (Precise event) Miss in last-level (L3) cache. Excludes Unknown data-source Supports address when precise. Spec update: HSD74, HSD29, HSD25, HSM26, HSM30 (Precise event) Retired load uops missed L3. Excludes unknown data source Supports address when precise. Spec update: HSD74, HSD29, HSD25, HSM26, HSM30 (Precise event) Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready Supports address when precise. Spec update: HSM30 (Precise event) Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache Supports address when precise. Spec update: HSD29, HSD25, HSM26, HSM30 (Precise event) Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache Supports address when precise. Spec update: HSD29, HSD25, HSM26, HSM30 (Precise event) Retired load uops which data sources were HitM responses from shared L3 Supports address when precise. Spec update: HSD29, HSD25, HSM26, HSM30 (Precise event) Retired load uops which data sources were hits in L3 without snoops required Supports address when precise. Spec update: HSD74, HSD29, HSD25, HSM26, HSM30 (Precise event) Data from local DRAM either Snoop not needed or Snoop Miss (RspI) Supports address when precise. Spec update: HSD74, HSD29, HSD25, HSM30 (Precise event) This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches Supports address when precise. Spec update: HSD74, HSD29, HSD25, HSM30 (Precise event) umask=0x4,period=100003,event=0xd3 Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI) Supports address when precise. Spec update: HSD29, HSM30 (Precise event) umask=0x10,period=100003,event=0xd3 Retired load uop whose Data Source was: Remote cache HITM Supports address when precise. Spec update: HSM30 (Precise event) umask=0x20,period=100003,event=0xd3 Retired load uop whose Data Source was: forwarded from remote cache Supports address when precise. Spec update: HSM30 (Precise event) offcore_response.demand_data_rd.llc_hit.hit_other_core_no_fwd offcore_response.demand_data_rd.llc_hit.hitm_other_core offcore_response.demand_rfo.llc_hit.hit_other_core_no_fwd offcore_response.demand_code_rd.llc_hit.hit_other_core_no_fwd offcore_response.demand_code_rd.llc_hit.hitm_other_core offcore_response.pf_l2_data_rd.llc_hit.any_response offcore_response.pf_l2_rfo.llc_hit.any_response offcore_response.pf_l2_code_rd.llc_hit.any_response offcore_response.pf_llc_data_rd.llc_hit.any_response Number of transitions from AVX-256 to legacy SSE when penalty applicable Spec update: HSD56, HSM57 Number of transitions from SSE to AVX-256 when penalty applicable Spec update: HSD56, HSM57 Number of X87 FP assists due to output values Number of X87 FP assists due to input values Number of SIMD FP assists due to output values Cycles with any input/output SSE* or FP assists hsx metrics offcore_response.demand_data_rd.llc_miss.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00001 offcore_response.demand_data_rd.llc_miss.local_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0600400001 offcore_response.demand_rfo.llc_miss.local_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0600400002 offcore_response.demand_code_rd.llc_miss.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00004 offcore_response.demand_code_rd.llc_miss.local_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0600400004 offcore_response.pf_l2_data_rd.llc_miss.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00010 offcore_response.pf_l2_rfo.llc_miss.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00020 offcore_response.pf_l2_code_rd.llc_miss.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00040 offcore_response.pf_llc_data_rd.llc_miss.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00080 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0600400091 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063F800091 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x083FC00091 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0600400122 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0600400244 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x06004007F7 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063F8007F7 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x083FC007F7 edge=1,umask=0x1,cmask=1,period=100003,event=0x5c inv=1,umask=0x1,any=1,cmask=1,period=2000003,event=0xe FP operations retired. X87 FP operations that have no exceptions: Counts also flows that have several X87 or flows that use X87 uops in the exception handling This is a non-precise version (that is, does not use PEBS) of the event that counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling Number of microcode assists invoked by HW upon uop writeback Counts the number of micro-ops retired. Use Cmask=1 and invert to count active cycles or stalled cycles Supports address when precise (Precise event) inv=1,umask=0x1,any=1,cmask=1,period=2000003,event=0xc2 This event counts the number of retirement slots used each cycle. There are potentially 4 slots that can be used each cycle - meaning, 4 uops or 4 instructions could retire each cycle (Precise event) Counts the number of conditional branch instructions retired (Precise event) Counts the number of near return instructions retired (Precise event) Counts the number of not taken branch instructions retired Number of near taken branches retired (Precise event) Far branch instructions retired Number of far branches retired Number of near branch instructions retired that were taken but mispredicted (Precise event) umask=0x1,period=200003,event=0x24 umask=0x3,period=200003,event=0x24 Counts any demand and L1 HW prefetch data load requests to L2 umask=0x4,period=200003,event=0x24 umask=0x8,period=200003,event=0x24 umask=0xc,period=200003,event=0x24 umask=0x10,period=200003,event=0x24 umask=0x20,period=200003,event=0x24 l2_rqsts.pf_hit umask=0x40,period=200003,event=0x24 Requests from the L2 hardware prefetchers that hit L2 cache l2_rqsts.pf_miss umask=0x80,period=200003,event=0x24 Requests from the L2 hardware prefetchers that miss L2 cache umask=0xc0,period=200003,event=0x24 l2_store_lock_rqsts.miss umask=0x1,period=200003,event=0x27 RFOs that miss cache lines l2_store_lock_rqsts.hit_m umask=0x8,period=200003,event=0x27 RFOs that hit cache lines in M state l2_store_lock_rqsts.all umask=0xf,period=200003,event=0x27 RFOs that access cache lines in any state l2_l1d_wb_rqsts.miss umask=0x1,period=200003,event=0x28 Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.) Not rejected writebacks that missed LLC l2_l1d_wb_rqsts.hit_e umask=0x4,period=200003,event=0x28 Not rejected writebacks from L1D to L2 cache lines in E state l2_l1d_wb_rqsts.hit_m umask=0x8,period=200003,event=0x28 Not rejected writebacks from L1D to L2 cache lines in M state l2_l1d_wb_rqsts.all umask=0xf,period=200003,event=0x28 Not rejected writebacks from L1D to L2 cache lines in any state Core-originated cacheable demand requests missed LLC Core-originated cacheable demand requests that refer to LLC Counts the number of lines brought into the L1 data cache Offcore outstanding Demand Data Read transactions in uncore queue Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle Offcore outstanding Demand Code Read transactions in SQ to uncore. Set Cmask=1 to count cycles offcore_requests_outstanding.cycles_with_demand_code_rd umask=0x2,period=2000003,cmask=1,event=0x60 Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore Demand data read requests sent to uncore Cases when offcore requests buffer cannot take more entries for core Retired load uops that miss the STLB. (Precise Event) Retired store uops that miss the STLB. (Precise Event) Retired load uops with locked access. (Precise Event) Retired load uops that split across a cacheline boundary. (Precise Event) Retired store uops that split across a cacheline boundary. (Precise Event) All retired load uops. (Precise Event) All retired store uops. (Precise Event) Retired load uops with L1 cache hits as data sources (Precise event) Retired load uops with L2 cache hits as data sources (Precise event) mem_load_uops_retired.llc_hit Retired load uops which data sources were data hits in LLC without snoops required (Precise event) Retired load uops which data sources following L1 data-cache miss (Precise event) Retired load uops with L2 cache misses as data sources (Precise event) mem_load_uops_retired.llc_miss Miss in last-level (L3) cache. Excludes Unknown data-source (Precise event) Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready (Precise event) mem_load_uops_llc_hit_retired.xsnp_miss Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache (Precise event) mem_load_uops_llc_hit_retired.xsnp_hit Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache (Precise event) mem_load_uops_llc_hit_retired.xsnp_hitm Retired load uops which data sources were HitM responses from shared LLC (Precise event) mem_load_uops_llc_hit_retired.xsnp_none Retired load uops which data sources were hits in LLC without snoops required (Precise event) mem_load_uops_llc_miss_retired.local_dram Retired load uops which data sources missed LLC but serviced from local dram Retired load uops whose data source was local memory (cross-socket snoop not needed or missed) L2 or LLC HW prefetches that access L2 cache Any MLC or LLC HW prefetch accessing L2, including rejects umask=0x1,period=100003,event=0xf2 umask=0x2,period=100003,event=0xf2 l2_lines_out.pf_clean umask=0x4,period=100003,event=0xf2 Clean L2 cache lines evicted by L2 prefetch Clean L2 cache lines evicted by the MLC prefetcher l2_lines_out.pf_dirty umask=0x8,period=100003,event=0xf2 Dirty L2 cache lines evicted by L2 prefetch Dirty L2 cache lines evicted by the MLC prefetcher l2_lines_out.dirty_all umask=0xa,period=100003,event=0xf2 Dirty L2 cache lines filling the L2 offcore_response.all_code_rd.llc_hit.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0244 Counts all demand & prefetch code reads that hit in the LLC offcore_response.all_code_rd.llc_hit.no_snoop_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0244 Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores offcore_response.all_data_rd.llc_hit.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0091 Counts all demand & prefetch data reads that hit in the LLC umask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0091 Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0091 Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded offcore_response.all_data_rd.llc_hit.no_snoop_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0091 Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores offcore_response.all_rfo.llc_hit.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0122 Counts all demand & prefetch RFOs that hit in the LLC offcore_response.all_rfo.llc_hit.no_snoop_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0122 Counts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10008 Counts all writebacks from the core to the LLC offcore_response.demand_code_rd.llc_hit.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0004 Counts all demand code reads that hit in the LLC offcore_response.demand_code_rd.llc_hit.no_snoop_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0004 Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores offcore_response.demand_data_rd.llc_hit.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0001 Counts all demand data reads that hit in the LLC umask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0001 Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0001 Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded offcore_response.demand_data_rd.llc_hit.no_snoop_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0001 Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0002 Counts all demand data writes (RFOs) that hit in the LLC umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0002 Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded offcore_response.demand_rfo.llc_hit.no_snoop_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0002 Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores umask=0x1,period=100003,event=0xb7,offcore_rsp=0x18000 Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core caches offcore_response.split_lock_uc_lock.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10400 Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10800 Counts non-temporal stores umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00010001 Counts all demand data reads umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00010002 Counts all demand rfo's umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00010004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x000105B3 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00010122 Counts all demand & prefetch prefetch RFOs offcore_response.all_reads.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x000107F7 Counts all data/code/rfo references (demand & prefetch) fp_comp_ops_exe.x87 umask=0x1,period=2000003,event=0x10 Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s Counts number of X87 uops executed fp_comp_ops_exe.sse_packed_double umask=0x10,period=2000003,event=0x10 Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle fp_comp_ops_exe.sse_scalar_single umask=0x20,period=2000003,event=0x10 Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle fp_comp_ops_exe.sse_packed_single umask=0x40,period=2000003,event=0x10 Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle fp_comp_ops_exe.sse_scalar_double umask=0x80,period=2000003,event=0x10 Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle Counts number of SSE* or AVX-128 double precision FP scalar uops executed simd_fp_256.packed_single umask=0x1,period=2000003,event=0x11 number of GSSE-256 Computational FP single precision uops issued this cycle Counts 256-bit packed single-precision floating-point instructions simd_fp_256.packed_double umask=0x2,period=2000003,event=0x11 number of AVX-256 Computational FP double precision uops issued this cycle Counts 256-bit packed double-precision floating-point instructions other_assists.avx_store Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations Number of assists associated with 256-bit AVX store operations Number of transitions from AVX-256 to legacy SSE when penalty applicable umask=0x20,period=100003,event=0xc1 Number of transitions from SSE to AVX-256 when penalty applicable Counts cycles the IDQ is empty Counts cycles MITE is delivered at least one uops. Set Cmask = 1 Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles Instruction cache, streaming buffer and victim cache misses Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss Count issue pipeline slots where no uop was delivered from the front end to the back end when there is no back-end stall dsb2mite_switches.count umask=0x1,period=2000003,event=0xab Decode Stream Buffer (DSB)-to-MITE switches Number of DSB to MITE switches Cycles DSB to MITE switches caused delay dsb_fill.exceed_dsb_lines umask=0x8,period=2000003,event=0xac Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines DSB Fill encountered > 3 DSB lines ivb metrics min( 1 , uops_issued.any / ( (uops_retired.retire_slots / inst_retired.any) * 32 * ( icache.hit + icache.misses ) / 4 ) ) (( 1 * ( fp_comp_ops_exe.sse_scalar_single + fp_comp_ops_exe.sse_scalar_double ) + 2 * fp_comp_ops_exe.sse_packed_double + 4 * ( fp_comp_ops_exe.sse_packed_single + simd_fp_256.packed_double ) + 8 * simd_fp_256.packed_single )) / cycles (( 1 * ( fp_comp_ops_exe.sse_scalar_single + fp_comp_ops_exe.sse_scalar_double ) + 2 * fp_comp_ops_exe.sse_packed_double + 4 * ( fp_comp_ops_exe.sse_packed_single + simd_fp_256.packed_double ) + 8 * simd_fp_256.packed_single )) / (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )) 1000 * mem_load_uops_retired.llc_miss / inst_retired.any ( (( 1 * ( fp_comp_ops_exe.sse_scalar_single + fp_comp_ops_exe.sse_scalar_double ) + 2 * fp_comp_ops_exe.sse_packed_double + 4 * ( fp_comp_ops_exe.sse_packed_single + simd_fp_256.packed_double ) + 8 * simd_fp_256.packed_single )) / 1000000000 ) / duration_time Speculative cache-line split Store-address uops dispatched to L1D page_walks.llc_miss umask=0x1,period=100003,event=0xbe Number of any page walk that had a miss in LLC Loads with latency value being above 4 (Must be precise) Loads with latency value being above 8 (Must be precise) Loads with latency value being above 16 (Must be precise) Loads with latency value being above 32 (Must be precise) Loads with latency value being above 64 (Must be precise) Loads with latency value being above 128 (Must be precise) Loads with latency value being above 256 (Must be precise) Loads with latency value being above 512 (Must be precise) mem_trans_retired.precise_store umask=0x2,period=2000003,event=0xcd Sample stores and collect precise store operation via PEBS record. PMC3 only (Must be precise) offcore_response.all_code_rd.llc_miss.dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400244 Counts all demand & prefetch code reads that miss the LLC and the data returned from dram offcore_response.all_data_rd.llc_miss.dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400091 Counts all demand & prefetch data reads that miss the LLC and the data returned from dram offcore_response.all_reads.llc_miss.dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3004003f7 Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from dram offcore_response.demand_code_rd.llc_miss.dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400004 Counts demand code reads that miss the LLC and the data returned from dram offcore_response.demand_data_rd.llc_miss.dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400001 Counts demand data reads that miss the LLC and the data returned from dram offcore_response.data_in_socket.llc_miss.local_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x6004001b3 Counts LLC replacements Loads blocked by overlapping with store buffer that cannot be forwarded Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.) int_misc.recovery_stalls_count umask=0x3,edge=1,period=2000003,cmask=1,event=0xd Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.) Increments each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core Number of flags-merge uops being allocated Number of flags-merge uops allocated. Such uops adds delay Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not Cycles that the divider is active, includes INT and FP. Set 'edge =1, cmask=1' to count the number of divides arith.fpu_div umask=0x4,edge=1,period=100003,cmask=1,event=0x14 Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate) Count XClk pulses when this thread is unhalted and the other is halted Cycles the RS is empty for the thread Cycles per thread when uops are dispatched to port 0 Cycles which a Uop is dispatched on port 0 uops_dispatched_port.port_0_core Cycles per core when uops are dispatched to port 0 Cycles per thread when uops are dispatched to port 1 Cycles which a Uop is dispatched on port 1 uops_dispatched_port.port_1_core Cycles per core when uops are dispatched to port 1 umask=0xc,period=2000003,event=0xa1 Cycles per thread when load or STA uops are dispatched to port 2 Cycles which a Uop is dispatched on port 2 uops_dispatched_port.port_2_core umask=0xc,any=1,period=2000003,event=0xa1 Uops dispatched to port 2, loads and stores per core (speculative and retired) umask=0x30,period=2000003,event=0xa1 Cycles per thread when load or STA uops are dispatched to port 3 Cycles which a Uop is dispatched on port 3 uops_dispatched_port.port_3_core umask=0x30,any=1,period=2000003,event=0xa1 Cycles per core when load or STA uops are dispatched to port 3 Cycles per thread when uops are dispatched to port 4 Cycles which a Uop is dispatched on port 4 uops_dispatched_port.port_4_core Cycles per core when uops are dispatched to port 4 Cycles per thread when uops are dispatched to port 5 Cycles which a Uop is dispatched on port 5 uops_dispatched_port.port_5_core Cycles per core when uops are dispatched to port 5 Cycles Allocation is stalled due to Resource Related reason Cycles stalled due to no store buffers available (not including draining form sync) Cycles with pending L2 cache miss loads Cycles with pending L2 miss loads. Set AnyThread to count per core Cycles while L2 cache miss load* is outstanding Cycles with pending memory loads. Set AnyThread to count per core Execution stalls while L2 cache miss load* is outstanding Cycles with pending L1 cache miss loads. Set AnyThread to count per core Counts total number of uops to be executed per-thread each cycle. Set Cmask = 1, INV =1 to count stall cycles Counts total number of uops to be executed per-core each cycle Number of instructions retired. General Counter - architectural event Number of instructions at retirement Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution (Must be precise) umask=0x80,period=100003,event=0xc1 Retired uops (Precise event) Number of self-modifying-code machine clears detected Counts the number of executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0 unc_cbo_xsnp_response.miss umask=0x01,event=0x22 Unit: uncore_cbox A snoop misses in some processor core A snoop misses in some processor core unc_cbo_xsnp_response.inval umask=0x02,event=0x22 Unit: uncore_cbox A snoop invalidates a non-modified line in some processor core A snoop invalidates a non-modified line in some processor core unc_cbo_xsnp_response.hit umask=0x04,event=0x22 Unit: uncore_cbox A snoop hits a non-modified line in some processor core A snoop hits a non-modified line in some processor core unc_cbo_xsnp_response.hitm umask=0x08,event=0x22 Unit: uncore_cbox A snoop hits a modified line in some processor core A snoop hits a modified line in some processor core unc_cbo_xsnp_response.inval_m umask=0x10,event=0x22 Unit: uncore_cbox A snoop invalidates a modified line in some processor core A snoop invalidates a modified line in some processor core unc_cbo_xsnp_response.external_filter umask=0x20,event=0x22 Unit: uncore_cbox Filter on cross-core snoops initiated by this Cbox due to external snoop request Filter on cross-core snoops initiated by this Cbox due to external snoop request unc_cbo_xsnp_response.xcore_filter umask=0x40,event=0x22 Unit: uncore_cbox Filter on cross-core snoops initiated by this Cbox due to processor core memory request Filter on cross-core snoops initiated by this Cbox due to processor core memory request unc_cbo_xsnp_response.eviction_filter umask=0x80,event=0x22 Unit: uncore_cbox Filter on cross-core snoops initiated by this Cbox due to LLC eviction Filter on cross-core snoops initiated by this Cbox due to LLC eviction unc_cbo_cache_lookup.m umask=0x01,event=0x34 Unit: uncore_cbox LLC lookup request that access cache and found line in M-state LLC lookup request that access cache and found line in M-state unc_cbo_cache_lookup.e umask=0x02,event=0x34 Unit: uncore_cbox LLC lookup request that access cache and found line in E-state LLC lookup request that access cache and found line in E-state unc_cbo_cache_lookup.s umask=0x04,event=0x34 Unit: uncore_cbox LLC lookup request that access cache and found line in S-state LLC lookup request that access cache and found line in S-state unc_cbo_cache_lookup.i umask=0x08,event=0x34 Unit: uncore_cbox LLC lookup request that access cache and found line in I-state LLC lookup request that access cache and found line in I-state unc_cbo_cache_lookup.read_filter umask=0x10,event=0x34 Unit: uncore_cbox Filter on processor core initiated cacheable read requests Filter on processor core initiated cacheable read requests unc_cbo_cache_lookup.write_filter umask=0x20,event=0x34 Unit: uncore_cbox Filter on processor core initiated cacheable write requests Filter on processor core initiated cacheable write requests unc_cbo_cache_lookup.extsnp_filter umask=0x40,event=0x34 Unit: uncore_cbox Filter on external snoop requests Filter on external snoop requests unc_cbo_cache_lookup.any_request_filter umask=0x80,event=0x34 Unit: uncore_cbox Filter on any IRQ or IPQ initiated requests including uncacheable, non-coherent requests Filter on any IRQ or IPQ initiated requests including uncacheable, non-coherent requests Unit: uncore_arb Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC Unit: uncore_arb Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC Unit: uncore_arb Counts the number of allocated write entries, include full, partial, and LLC evictions Counts the number of allocated write entries, include full, partial, and LLC evictions unc_arb_trk_requests.evictions umask=0x80,event=0x81 Unit: uncore_arb Counts the number of LLC evictions allocated Counts the number of LLC evictions allocated Unit: uncore_arb Cycles weighted by number of requests pending in Coherency Tracker Cycles weighted by number of requests pending in Coherency Tracker Unit: uncore_arb Number of requests allocated in Coherency Tracker Number of requests allocated in Coherency Tracker Unit: uncore_arb Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC unc_arb_trk_occupancy.cycles_over_half_full umask=0x01,cmask=10,event=0x80 Unit: uncore_arb Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC Unit: uncore_arb This 48-bit fixed counter counts the UCLK cycles unc_cbo_cache_lookup.es umask=0x06,event=0x34 Unit: uncore_cbox LLC lookup request that access cache and found line in E-state or S-state LLC lookup request that access cache and found line in E-state or S-state umask=0x81,period=100003,event=0x8 Demand load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page size Misses in all TLB levels that cause a page walk of any page size from demand loads umask=0x82,period=100003,event=0x8 Misses in all TLB levels that caused page walk completed of any size by demand loads umask=0x84,period=2000003,event=0x8 Demand load cycles page miss handler (PMH) is busy with this walk Cycle PMH is busy with a walk due to demand loads dtlb_load_misses.large_page_walk_completed umask=0x88,period=100003,event=0x8 Page walk for a large page completed for Demand load Miss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M/1G) Cycles PMH is busy with this walk Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches umask=0x4,period=100003,event=0x5f Counts load operations that missed 1st level DTLB but hit the 2nd level Misses in all ITLB levels that cause page walks Cycle PMH is busy with a walk itlb_misses.large_page_walk_completed umask=0x80,period=100003,event=0x85 Completed page walks in ITLB due to STLB load misses for large pages umask=0x3,period=100007,event=0xd3 Retired load uops whose data source was local DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded) mem_load_uops_llc_miss_retired.remote_dram umask=0xc,period=100007,event=0xd3 Retired load uops whose data source was remote DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded) mem_load_uops_llc_miss_retired.remote_hitm Remote cache HITM mem_load_uops_llc_miss_retired.remote_fwd Data forwarded from remote cache offcore_response.all_data_rd.llc_hit.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0091 Counts demand & prefetch data reads that hit in the LLC and sibling core snoop returned a clean response offcore_response.all_pf_data_rd.llc_hit.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0090 Counts all prefetch data reads that hit the LLC offcore_response.all_pf_data_rd.llc_hit.hit_other_core_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0090 Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded offcore_response.all_pf_data_rd.llc_hit.hitm_other_core umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0090 Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded offcore_response.all_pf_data_rd.llc_hit.no_snoop_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0090 Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores offcore_response.all_pf_data_rd.llc_hit.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0090 Counts prefetch data reads that hit in the LLC and sibling core snoop returned a clean response offcore_response.all_reads.llc_hit.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c03f7 Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC umask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c03f7 Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c03f7 Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded offcore_response.all_reads.llc_hit.no_snoop_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c03f7 Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores offcore_response.all_reads.llc_hit.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c03f7 Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoop returned a clean response offcore_response.demand_data_rd.llc_hit.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0001 Counts demand data reads that hit in the LLC and sibling core snoop returned a clean response offcore_response.other.lru_hints umask=0x1,period=100003,event=0xb7,offcore_rsp=0x803c8000 Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches offcore_response.other.portio_mmio_uc umask=0x1,period=100003,event=0xb7,offcore_rsp=0x23ffc08000 Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0040 Counts all prefetch (that bring data to L2) code reads that hit in the LLC umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0010 Counts prefetch (that bring data to L2) data reads that hit in the LLC offcore_response.pf_l2_data_rd.llc_hit.hit_other_core_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0010 Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded offcore_response.pf_l2_data_rd.llc_hit.hitm_other_core umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0010 Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded offcore_response.pf_l2_data_rd.llc_hit.no_snoop_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0010 Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores offcore_response.pf_l2_data_rd.llc_hit.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0010 Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0200 Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0080 Counts prefetch (that bring data to LLC only) data reads that hit in the LLC offcore_response.pf_llc_data_rd.llc_hit.hit_other_core_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0080 Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded offcore_response.pf_llc_data_rd.llc_hit.hitm_other_core umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0080 Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded offcore_response.pf_llc_data_rd.llc_hit.no_snoop_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0080 Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores offcore_response.pf_llc_data_rd.llc_hit.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0080 Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response ivt metrics umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3fffc00244 Counts all demand & prefetch code reads that miss the LLC offcore_response.all_code_rd.llc_miss.remote_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x67f800244 Counts all demand & prefetch code reads that miss the LLC and the data returned from remote dram offcore_response.all_code_rd.llc_miss.remote_hit_forward umask=0x1,period=100003,event=0xb7,offcore_rsp=0x87f800244 Counts all demand & prefetch code reads that miss the LLC and the data forwarded from remote cache umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3fffc20091 Counts all demand & prefetch data reads that hits the LLC umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3fffc203f7 Counts all data/code/rfo reads (demand & prefetch) that hit the LLC umask=0x1,period=100003,event=0xb7,offcore_rsp=0x6004003f7 Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from local dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x87f8203f7 Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data forwarded from remote cache umask=0x1,period=100003,event=0xb7,offcore_rsp=0x107fc003f7 Counts all data/code/rfo reads (demand & prefetch) that miss the LLC the data is found in M state in remote cache and forwarded from there umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3fffc20004 Counts all demand code reads that miss the LLC umask=0x1,period=100003,event=0xb7,offcore_rsp=0x600400004 Counts all demand code reads that miss the LLC and the data returned from local dram offcore_response.demand_code_rd.llc_miss.remote_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x67f800004 Counts all demand code reads that miss the LLC and the data returned from remote dram offcore_response.demand_code_rd.llc_miss.remote_hit_forward umask=0x1,period=100003,event=0xb7,offcore_rsp=0x87f820004 Counts all demand code reads that miss the LLC and the data forwarded from remote cache offcore_response.demand_code_rd.llc_miss.remote_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x107fc00004 Counts all demand code reads that miss the LLC the data is found in M state in remote cache and forwarded from there offcore_response.demand_data_rd.llc_miss.any_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x67fc00001 Counts demand data reads that miss the LLC and the data returned from remote & local dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3fffc20001 Counts demand data reads that miss in the LLC umask=0x1,period=100003,event=0xb7,offcore_rsp=0x600400001 Counts demand data reads that miss the LLC and the data returned from local dram offcore_response.demand_data_rd.llc_miss.remote_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x67f800001 Counts demand data reads that miss the LLC and the data returned from remote dram offcore_response.demand_data_rd.llc_miss.remote_hit_forward umask=0x1,period=100003,event=0xb7,offcore_rsp=0x87f820001 Counts demand data reads that miss the LLC and the data forwarded from remote cache offcore_response.demand_data_rd.llc_miss.remote_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x107fc00001 Counts demand data reads that miss the LLC the data is found in M state in remote cache and forwarded from there umask=0x1,period=100003,event=0xb7,offcore_rsp=0x107fc20002 Counts all demand data writes (RFOs) that miss the LLC and the data is found in M state in remote cache and forwarded from there umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3fffc20040 Counts all prefetch (that bring data to L2) code reads that miss the LLC and the data returned from remote & local dram offcore_response.pf_l2_data_rd.llc_miss.any_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x67fc00010 Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote & local dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3fffc20010 Counts prefetch (that bring data to L2) data reads that miss in the LLC offcore_response.pf_l2_data_rd.llc_miss.local_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x600400010 Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from local dram offcore_response.pf_l2_data_rd.llc_miss.remote_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x67f800010 Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote dram offcore_response.pf_l2_data_rd.llc_miss.remote_hit_forward umask=0x1,period=100003,event=0xb7,offcore_rsp=0x87f820010 Counts prefetch (that bring data to L2) data reads that miss the LLC and the data forwarded from remote cache offcore_response.pf_l2_data_rd.llc_miss.remote_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x107fc00010 Counts prefetch (that bring data to L2) data reads that miss the LLC the data is found in M state in remote cache and forwarded from there umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3fffc20200 Counts all prefetch (that bring data to LLC only) code reads that miss in the LLC umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3fffc20080 Counts prefetch (that bring data to LLC only) data reads that miss in the LLC LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derived from unc_c_tor_inserts.miss_opcode.demand. Unit: uncore_cbox LLC misses - Uncacheable reads. Derived from unc_c_tor_inserts.miss_opcode.uncacheable. Unit: uncore_cbox LLC prefetch misses for RFO. Derived from unc_c_tor_inserts.miss_opcode.rfo_prefetch. Unit: uncore_cbox LLC prefetch misses for code reads. Derived from unc_c_tor_inserts.miss_opcode.code. Unit: uncore_cbox LLC prefetch misses for data reads. Derived from unc_c_tor_inserts.miss_opcode.data_read. Unit: uncore_cbox umask=0x3,event=0x35,filter_opc=0x19c PCIe allocating writes that miss LLC - DDIO misses. Derived from unc_c_tor_inserts.miss_opcode.ddio_miss. Unit: uncore_cbox LLC misses for PCIe read current. Derived from unc_c_tor_inserts.miss_opcode.pcie_read. Unit: uncore_cbox llc_misses.itom_write LLC misses for ItoM writes (as part of fast string memcpy stores). Derived from unc_c_tor_inserts.miss_opcode.itom_write. Unit: uncore_cbox llc_misses.pcie_non_snoop_read umask=0x3,event=0x35,filter_opc=0x1e4 LLC misses for PCIe non-snoop reads. Derived from unc_c_tor_inserts.miss_opcode.pcie_read. Unit: uncore_cbox umask=0x3,event=0x35,filter_opc=0x1e6 LLC misses for PCIe non-snoop writes (full line). Derived from unc_c_tor_inserts.miss_opcode.pcie_write. Unit: uncore_cbox Streaming stores (full cache line). Derived from unc_c_tor_inserts.opcode.streaming_full. Unit: uncore_cbox Streaming stores (partial cache line). Derived from unc_c_tor_inserts.opcode.streaming_partial. Unit: uncore_cbox llc_references.pcie_partial_read umask=0x1,event=0x35,filter_opc=0x195 Partial PCIe reads. Derived from unc_c_tor_inserts.opcode.pcie_partial. Unit: uncore_cbox umask=0x1,event=0x35,filter_opc=0x19c PCIe allocating writes that hit in LLC (DDIO hits). Derived from unc_c_tor_inserts.opcode.ddio_hit. Unit: uncore_cbox PCIe read current. Derived from unc_c_tor_inserts.opcode.pcie_read_current. Unit: uncore_cbox llc_references.itom_write umask=0x1,event=0x35,filter_opc=0x1c8 ItoM write hits (as part of fast string memcpy stores). Derived from unc_c_tor_inserts.opcode.itom_write_hit. Unit: uncore_cbox llc_references.pcie_ns_read umask=0x1,event=0x35,filter_opc=0x1e4 PCIe non-snoop reads. Derived from unc_c_tor_inserts.opcode.pcie_read. Unit: uncore_cbox umask=0x1,event=0x35,filter_opc=0x1e5 PCIe non-snoop writes (partial). Derived from unc_c_tor_inserts.opcode.pcie_partial_write. Unit: uncore_cbox llc_references.pcie_ns_write umask=0x1,event=0x35,filter_opc=0x1e6 PCIe non-snoop writes (full line). Derived from unc_c_tor_inserts.opcode.pcie_full_write. Unit: uncore_cbox unc_c_tor_occupancy.miss_local umask=0x2A,event=0x36 Occupancy for all LLC misses that are addressed to local memory. Unit: uncore_cbox Occupancy counter for LLC data reads (demand and L2 prefetch). Derived from unc_c_tor_occupancy.miss_opcode.llc_data_read. Unit: uncore_cbox unc_c_tor_occupancy.miss_remote umask=0x8A,event=0x36 Occupancy for all LLC misses that are addressed to remote memory. Unit: uncore_cbox Read requests to home agent. Unit: uncore_ha Write requests to home agent. Unit: uncore_ha QPI clock ticks. Use to get percentages for QPI cycles events. Unit: uncore_qpi unc_q_rxl0p_power_cycles event=0x10 Cycles where receiving QPI link is in half-width mode. Unit: uncore_qpi (unc_q_rxl0p_power_cycles / unc_q_clockticks) * 100. rxl0p_power_cycles % unc_q_txl0p_power_cycles event=0xd Cycles where transmitting QPI link is in half-width mode. Unit: uncore_qpi (unc_q_txl0p_power_cycles / unc_q_clockticks) * 100. txl0p_power_cycles % unc_q_txl_flits_g0.data Number of data flits transmitted . Unit: uncore_qpi unc_q_txl_flits_g0.non_data Number of non data (control) flits transmitted . Unit: uncore_qpi unc_m_act_count.rd umask=0x1,umask=0x3,event=0x1 Memory page activates for reads and writes. Unit: uncore_imc Read requests to memory controller. Derived from unc_m_cas_count.rd. Unit: uncore_imc Write requests to memory controller. Derived from unc_m_cas_count.wr. Unit: uncore_imc Memory controller clock ticks. Use to generate percentages for memory controller CYCLES events. Unit: uncore_imc Memory page conflicts. Unit: uncore_imc unc_p_freq_band0_cycles event=0xb Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. (filter_band0=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Unit: uncore_pcu (unc_p_freq_band0_cycles / unc_p_clockticks) * 100. freq_band0_cycles % unc_p_freq_band1_cycles event=0xc Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. (filter_band1=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Unit: uncore_pcu (unc_p_freq_band1_cycles / unc_p_clockticks) * 100. freq_band1_cycles % unc_p_freq_band2_cycles Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. (filter_band2=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Unit: uncore_pcu (unc_p_freq_band2_cycles / unc_p_clockticks) * 100. freq_band2_cycles % unc_p_freq_band3_cycles event=0xe Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. (filter_band3=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Unit: uncore_pcu (unc_p_freq_band3_cycles / unc_p_clockticks) * 100. freq_band3_cycles % unc_p_freq_band0_transitions event=0xb,edge=1 Counts the number of times that the uncore transitioned a frequency greater than or equal to the frequency that is configured in the filter. (filter_band0=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Derived from unc_p_freq_band0_cycles. Unit: uncore_pcu unc_p_freq_band1_transitions event=0xc,edge=1 Counts the number of times that the uncore transitioned to a frequency greater than or equal to the frequency that is configured in the filter. (filter_band1=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Derived from unc_p_freq_band1_cycles. Unit: uncore_pcu unc_p_freq_band2_transitions event=0xd,edge=1 Counts the number of cycles that the uncore transitioned to a frequency greater than or equal to the frequency that is configured in the filter. (filter_band2=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Derived from unc_p_freq_band2_cycles. Unit: uncore_pcu unc_p_freq_band3_transitions event=0xe,edge=1 Counts the number of cycles that the uncore transitioned to a frequency greater than or equal to the frequency that is configured in the filter. (filter_band3=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Derived from unc_p_freq_band3_cycles. Unit: uncore_pcu unc_p_freq_max_current_cycles event=0x7 (unc_p_freq_max_current_cycles / unc_p_clockticks) * 100. freq_max_current_cycles % event=0x60 Cycles spent changing Frequency. Unit: uncore_pcu unc_p_freq_ge_1200mhz_cycles event=0xb,filter_band0=12 Counts the number of cycles that the uncore was running at a frequency greater than or equal to 1.2Ghz. Derived from unc_p_freq_band0_cycles. Unit: uncore_pcu (unc_p_freq_ge_1200mhz_cycles / unc_p_clockticks) * 100. freq_ge_1200mhz_cycles % unc_p_freq_ge_2000mhz_cycles event=0xc,filter_band1=20 Counts the number of cycles that the uncore was running at a frequency greater than or equal to 2Ghz. Derived from unc_p_freq_band1_cycles. Unit: uncore_pcu (unc_p_freq_ge_2000mhz_cycles / unc_p_clockticks) * 100. freq_ge_2000mhz_cycles % unc_p_freq_ge_3000mhz_cycles event=0xd,filter_band2=30 Counts the number of cycles that the uncore was running at a frequency greater than or equal to 3Ghz. Derived from unc_p_freq_band2_cycles. Unit: uncore_pcu (unc_p_freq_ge_3000mhz_cycles / unc_p_clockticks) * 100. freq_ge_3000mhz_cycles % unc_p_freq_ge_4000mhz_cycles event=0xe,filter_band3=40 Counts the number of cycles that the uncore was running at a frequency greater than or equal to 4Ghz. Derived from unc_p_freq_band3_cycles. Unit: uncore_pcu (unc_p_freq_ge_4000mhz_cycles / unc_p_clockticks) * 100. freq_ge_4000mhz_cycles % unc_p_freq_ge_1200mhz_transitions event=0xb,edge=1,filter_band0=12 Counts the number of times that the uncore transitioned to a frequency greater than or equal to 1.2Ghz. Derived from unc_p_freq_band0_cycles. Unit: uncore_pcu unc_p_freq_ge_2000mhz_transitions event=0xc,edge=1,filter_band1=20 Counts the number of times that the uncore transitioned to a frequency greater than or equal to 2Ghz. Derived from unc_p_freq_band1_cycles. Unit: uncore_pcu unc_p_freq_ge_3000mhz_transitions event=0xd,edge=1,filter_band2=30 Counts the number of cycles that the uncore transitioned to a frequency greater than or equal to 3Ghz. Derived from unc_p_freq_band2_cycles. Unit: uncore_pcu unc_p_freq_ge_4000mhz_transitions event=0xe,edge=1,filter_band3=40 Counts the number of cycles that the uncore transitioned to a frequency greater than or equal to 4Ghz. Derived from unc_p_freq_band3_cycles. Unit: uncore_pcu dtlb_load_misses.demand_ld_walk_completed dtlb_load_misses.demand_ld_walk_duration Retired load uops that miss the STLB (Precise event) Retired store uops that miss the STLB (Precise event) Retired load uops with locked access (Precise event) Retired load uops that split across a cacheline boundary (Precise event) This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K) (Precise event) Retired store uops that split across a cacheline boundary (Precise event) This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K) (Precise event) All retired load uops (Precise event) This event counts the number of load uops retired (Precise event) All retired store uops (Precise event) This event counts the number of store uops retired (Precise event) Retired load uops which data sources were data hits in LLC without snoops required This event counts retired load uops that hit in the last-level (L3) cache without snoops required Miss in last-level (L3) cache. Excludes Unknown data-source Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a non-modified state Retired load uops which data sources were HitM responses from shared LLC This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a modified state, so the line had to be invalidated in that L2 cache and transferred to the requesting L2 Retired load uops which data sources were hits in LLC without snoops required Data from local DRAM either Snoop not needed or Snoop Miss (RspI) Data from remote DRAM either Snoop not needed or Snoop Miss (RspI) This event counts L1D data line replacements. Replacements occur when a new line is brought into the cache, causing eviction of a line loaded earlier l1d.allocated_in_m umask=0x2,period=2000003,event=0x51 Allocated L1D data cache lines in M state l1d.eviction umask=0x4,period=2000003,event=0x51 L1D data cache lines in M state evicted due to replacement l1d.all_m_replacement umask=0x8,period=2000003,event=0x51 Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacement l2_store_lock_rqsts.hit_e umask=0x4,period=200003,event=0x27 RFOs that hit cache lines in E state l2_l1d_wb_rqsts.hit_s umask=0x2,period=200003,event=0x28 Not rejected writebacks from L1D to L2 cache lines in S state l1d_blocks.bank_conflict_cycles umask=0x5,period=100003,cmask=1,event=0xbf Cycles when dispatched loads are cancelled due to L1D bank conflicts with other load ports offcore_requests_outstanding.demand_data_rd_c6 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00010008 Number of GSSE-256 Computational FP single precision uops issued this cycle Number of AVX-256 Computational FP double precision uops issued this cycle This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes unchacheable accesses This event counts cycles during which the microcode sequencer assisted the front-end in delivering uops. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance. See the Intel? 64 and IA-32 Architectures Optimization Reference Manual for more information Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled This event counts the number of uops not delivered to the back-end per cycle, per thread, when the back-end was not stalled. In the ideal case 4 uops can be delivered each cycle. The event counts the undelivered uops - so if 3 were delivered in one cycle, the counter would be incremented by 1 for that cycle (4 - 3). If the back-end is stalled, the count for this event is not incremented even when uops were not delivered, because the back-end would not have been able to accept them. This event is used in determining the front-end bound category of the top-down pipeline slots characterization This event counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decoded instructions, to the legacy decode pipeline. It excludes cycles when the back-end cannot accept new micro-ops. The penalty for these switches is potentially several cycles of instruction starvation, where no micro-ops are delivered to the back-end dsb_fill.other_cancel umask=0x2,period=2000003,event=0xac Cases of cancelling valid DSB fill not because of exceeding way limit idq_uops_not_delivered.cycles_ge_1_uop_deliv.core inv=1,umask=0x1,period=2000003,cmask=4,event=0x9c Cycles when 1 or more uops were delivered to the by the front end dsb_fill.all_cancel umask=0xa,period=2000003,event=0xac Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limit jkt metrics uops_dispatched.thread / (( cpu@uops_dispatched.core\,cmask\=1@ / 2 ) if #smt_on else cpu@uops_dispatched.core\,cmask\=1@) This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers. Machine clears can have a significant performance impact if they are happening frequently Loads with latency value being above 4 (Must be precise) Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS) (Must be precise) offcore_response.all_demand_mlc_pref_reads.llc_miss.local_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x600400077 Counts all local dram accesses for all demand and L2 prefetches. LLC prefetches are excluded offcore_response.all_demand_mlc_pref_reads.llc_miss.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC20077 This event counts all LLC misses for all demand and L2 prefetches. LLC prefetches are excluded offcore_response.all_demand_mlc_pref_reads.llc_miss.remote_hitm_hit_forward umask=0x1,period=100003,event=0xb7,offcore_rsp=0x187FC20077 This event counts all remote cache-to-cache transfers (includes HITM and HIT-Forward) for all demand and L2 prefetches. LLC prefetches are excluded insts_written_to_iq.insts umask=0x1,period=2000003,event=0x17 Valid instructions written to IQ per cycle hw_pre_req.dl1_miss umask=0x2,period=2000003,event=0x4e Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events br_misp_exec.taken_direct_near_call umask=0x90,period=200003,event=0x89 Taken speculative and retired mispredicted direct near calls br_misp_exec.all_direct_near_call umask=0xd0,period=200003,event=0x89 Speculative and retired mispredicted direct near calls umask=0x40,period=2000003,event=0xd partial_rat_stalls.flags_merge_uop umask=0x20,period=2000003,event=0x59 Increments the number of flags-merge uops in flight each cycle partial_rat_stalls.slow_lea_window umask=0x40,period=2000003,event=0x59 Cycles with at least one slow LEA uop being allocated This event counts the number of cycles with at least one slow LEA uop being allocated. A uop is generally considered as slow LEA if it has three sources (for example, two sources and immediate) regardless of whether it is a result of LEA instruction or not. Examples of the slow LEA uop are or uops with base, index, and offset source operands using base and index reqisters, where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel? 64 and IA-32 Architectures Optimization Reference Manual for more details about slow LEA instructions partial_rat_stalls.mul_single_uop umask=0x80,period=2000003,event=0x59 Multiply packed/scalar single precision uops allocated resource_stalls.lb umask=0x2,period=2000003,event=0xa2 Counts the cycles of stall due to lack of load buffers resource_stalls2.bob_full umask=0x40,period=2000003,event=0x5b Cycles when Allocator is stalled if BOB is full and new branch needs it This event counts the number of Uops issued by the front-end of the pipeilne to the back-end Actually retired uops (Precise event) This event counts the number of micro-ops retired (Precise event) This event counts the number of retirement slots used each cycle. There are potentially 4 slots that can be used each cycle - meaning, 4 micro-ops or 4 instructions could retire each cycle. This event is used in determining the 'Retiring' category of the Top-Down pipeline slots characterization (Precise event) All (macro) branch instructions retired. (Precise Event - PEBS) (Must be precise) br_misp_retired.near_call umask=0x2,period=100007,event=0xc5 Direct and indirect mispredicted near call instructions retired (Precise event) br_misp_retired.not_taken umask=0x10,period=400009,event=0xc5 Mispredicted not taken branch instructions retired (Precise event) br_misp_retired.taken Mispredicted taken branch instructions retired (Precise event) other_assists.itlb_miss_retired umask=0x2,period=100003,event=0xc1 Retired instructions experiencing ITLB misses umask=0x1,edge=1,period=100003,cmask=1,event=0x14 This event counts the number of the divide operations executed uops_dispatched.thread Uops dispatched per thread uops_dispatched.core Uops dispatched from any thread cycle_activity.cycles_no_dispatch Each cycle there was no dispatch for this thread, increment by 1. Note this is connect to Umask 2. No dispatch can be deduced from the UOPS_EXECUTED event Each cycle there was a miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING Each cycle there was a MLC-miss pending demand load this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0 Each cycle there was a miss-pending demand load this thread and no uops dispatched, increment by 1. Note this is in DCU and connected to Umask 1 and 2. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING Each cycle there was a MLC-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0 and 2 umask=0x1,period=100003,event=0x3 Loads delayed due to SB blocks, preceding store operations with known addresses but unknown data This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceeding smaller uncompleted store. See the table of not supported store forwards in the Intel? 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued umask=0x10,period=100003,event=0x3 Number of cases where any load ends up with a valid block-code written to the load buffer (including blocks due to Memory Order Buffer (MOB), Data Cache Unit (DCU), TLB, but load has no DCU miss) Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K. This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline. The enhanced address check typically has a performance penalty of 5 cycles ld_blocks_partial.all_sta_block umask=0x8,period=100003,event=0x7 This event counts the number of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this type agu_bypass_cancel.count umask=0x1,period=100003,event=0xb6 This event counts executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in an Cycles per core when load or STA uops are dispatched to port 2 Instructions retired. (Precise Event - PEBS) (Must be precise) resource_stalls2.all_prf_control umask=0xf,period=2000003,event=0x5b Resource stalls2 control structures full for physical registers resource_stalls2.all_fl_empty umask=0xc,period=2000003,event=0x5b Cycles with either free list is empty resource_stalls.mem_rs umask=0xe,period=2000003,event=0xa2 Resource stalls due to memory buffers or Reservation Station (RS) being fully utilized resource_stalls.ooo_rsrc umask=0xf0,period=2000003,event=0xa2 Resource stalls due to Rob being full, FCSW, MXCSR and OTHER resource_stalls2.ooo_rsrc umask=0x4f,period=2000003,event=0x5b Resource stalls out of order resources full resource_stalls.lb_sb umask=0xa,period=2000003,event=0xa2 Resource stalls due to load or store buffers all being in use Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...) partial_rat_stalls.flags_merge_uop_cycles umask=0x20,period=2000003,cmask=1,event=0x59 Performance sensitive flags-merging uops added by Sandy Bridge u-arch This event counts the number of cycles spent executing performance-sensitive flags-merging uops. For example, shift CL (merge_arith_flags). For more details, See the Intel? 64 and IA-32 Architectures Optimization Reference Manual Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...) inv=1,umask=0x1,edge=1,period=2000003,cmask=1,event=0x5e unc_c_tor_occupancy.miss_all umask=0xa,event=0x36,filter_opc=0x182 Occupancy counter for all LLC misses; we divide this by UNC_C_CLOCKTICKS to get average Q depth. Unit: uncore_cbox (unc_c_tor_occupancy.miss_all / unc_c_clockticks) * 100. tor_occupancy.miss_all % umask=0x3,event=0x36 umask=0xc,event=0x1 QPI clock ticks. Used to get percentages of QPI cycles events. Unit: uncore_qpi unc_m_act_count event=0x1 Memory page activates. Unit: uncore_imc umask=0xc,event=0x4 Memory controller clock ticks. Used to get percentages of memory controller cycles events. Unit: uncore_imc unc_m_rpq_occupancy event=0x80 Occupancy counter for memory read queue. Unit: uncore_imc Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. (filter_band0=XXX with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Unit: uncore_pcu Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. (filter_band1=XXX with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Unit: uncore_pcu Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. (filter_band2=XXX with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Unit: uncore_pcu Counts the number of times that the uncore transitioned a frequency greater than or equal to the frequency that is configured in the filter. (filter_band0=XXX with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Derived from unc_p_freq_band0_cycles. Unit: uncore_pcu Counts the number of times that the uncore transistioned to a frequency greater than or equal to the frequency that is configured in the filter. (filter_band1=XXX with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Derived from unc_p_freq_band1_cycles. Unit: uncore_pcu Counts the number of cycles that the uncore transitioned to a frequency greater than or equal to the frequency that is configured in the filter. (filter_band2=XXX with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Derived from unc_p_freq_band2_cycles. Unit: uncore_pcu This event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses umask=0x2,period=100003,event=0x8 Load misses at all DTLB levels that cause completed page walks umask=0x10,period=100003,event=0x8 This event counts load operations that miss the first DTLB level but hit the second and do not cause any page walks. The penalty in this case is approximately 7 cycles l2_requests_reject.all Counts the number of MEC requests from the L2Q that reference a cache line (cacheable requests) exlcuding SW prefetches filling only to L2 cache and L1 evictions (automatically exlcudes L2HWP, UC, WC) that were rejected - Multiple repeated rejects should be counted multiple times Counts the number of MEC requests that were not accepted into the L2Q because of any L2 queue reject condition. There is no concept of at-ret here. It might include requests due to instructions in the speculative path l2_requests.reference Counts the total number of L2 cache references l2_requests.miss Counts the number of L2 cache misses umask=0x4,period=200003,event=0x86 Counts the number of core cycles the fetch stalls because of an icache miss. This is a cummulative count of core cycles the fetch stalled for all icache misses This event counts the number of core cycles the fetch stalls because of an icache miss. This is a cumulative count of cycles the NIP stalled for all icache misses mem_uops_retired.l1_miss_loads umask=0x1,period=200003,event=0x4 Counts the number of load micro-ops retired that miss in L1 D cache This event counts the number of load micro-ops retired that miss in L1 Data cache. Note that prefetch misses will not be counted mem_uops_retired.l2_hit_loads umask=0x2,period=200003,event=0x4 Counts the number of load micro-ops retired that hit in the L2 Supports address when precise (Precise event) mem_uops_retired.l2_miss_loads umask=0x4,period=100007,event=0x4 Counts the number of load micro-ops retired that miss in the L2 Supports address when precise (Precise event) mem_uops_retired.utlb_miss_loads umask=0x10,period=200003,event=0x4 Counts the number of load micro-ops retired that caused micro TLB miss mem_uops_retired.hitm umask=0x20,period=200003,event=0x4 Counts the loads retired that get the data from the other core in the same tile in M state Supports address when precise (Precise event) umask=0x40,period=200003,event=0x4 Counts all the load micro-ops retired This event counts the number of load micro-ops retired umask=0x80,period=200003,event=0x4 Counts all the store micro-ops retired This event counts the number of store micro-ops retired Counts the matrix events specified by MSR_OFFCORE_RESPx offcore_response.any_pf_l2.outstanding umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000070 Counts any Prefetch requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0 offcore_response.any_pf_l2.l2_hit_far_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400070 Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state offcore_response.any_pf_l2.l2_hit_far_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400070 Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode offcore_response.any_pf_l2.l2_hit_near_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080070 Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state offcore_response.any_pf_l2.l2_hit_near_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080070 Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state offcore_response.any_pf_l2.any_response umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010070 Counts any Prefetch requests that accounts for any response umask=0x1,period=100007,event=0xb7,offcore_rsp=0x40000032f7 Counts any Read request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0 offcore_response.any_read.l2_hit_far_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x10004032f7 Counts any Read request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state offcore_response.any_read.l2_hit_far_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x08004032f7 Counts any Read request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode offcore_response.any_read.l2_hit_near_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x10000832f7 Counts any Read request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state offcore_response.any_read.l2_hit_near_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x08000832f7 Counts any Read request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state umask=0x1,period=100007,event=0xb7,offcore_rsp=0x00000132f7 Counts any Read request that accounts for any response offcore_response.any_code_rd.outstanding umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000044 Counts Demand code reads and prefetch code read requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0 offcore_response.any_code_rd.l2_hit_far_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400044 Counts Demand code reads and prefetch code read requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state offcore_response.any_code_rd.l2_hit_far_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400044 Counts Demand code reads and prefetch code read requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode offcore_response.any_code_rd.l2_hit_near_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080044 Counts Demand code reads and prefetch code read requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state offcore_response.any_code_rd.l2_hit_near_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080044 Counts Demand code reads and prefetch code read requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state offcore_response.any_code_rd.any_response umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010044 Counts Demand code reads and prefetch code read requests that accounts for any response Counts Demand cacheable data write requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0 offcore_response.any_rfo.l2_hit_far_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400022 Counts Demand cacheable data write requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state offcore_response.any_rfo.l2_hit_far_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400022 Counts Demand cacheable data write requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode offcore_response.any_rfo.l2_hit_near_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080022 Counts Demand cacheable data write requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state offcore_response.any_rfo.l2_hit_near_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080022 Counts Demand cacheable data write requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state Counts Demand cacheable data write requests that accounts for any response Counts Demand cacheable data and L1 prefetch data read requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0 offcore_response.any_data_rd.l2_hit_far_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000403091 Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state offcore_response.any_data_rd.l2_hit_far_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800403091 Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode offcore_response.any_data_rd.l2_hit_near_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000083091 Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state offcore_response.any_data_rd.l2_hit_near_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800083091 Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state Counts Demand cacheable data and L1 prefetch data read requests that accounts for any response Counts any request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0 offcore_response.any_request.l2_hit_far_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000408000 Counts any request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state offcore_response.any_request.l2_hit_far_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800408000 Counts any request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode offcore_response.any_request.l2_hit_near_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000088000 Counts any request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state offcore_response.any_request.l2_hit_near_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800088000 Counts any request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state Counts any request that accounts for any response Counts all streaming stores (WC and should be programmed on PMC1) that accounts for any response offcore_response.partial_streaming_stores.any_response umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000014000 Counts Partial streaming stores (WC and should be programmed on PMC1) that accounts for any response Counts L1 data HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0 offcore_response.pf_l1_data_rd.l2_hit_far_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000402000 Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state offcore_response.pf_l1_data_rd.l2_hit_far_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800402000 Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode offcore_response.pf_l1_data_rd.l2_hit_near_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000082000 Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state offcore_response.pf_l1_data_rd.l2_hit_near_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800082000 Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state Counts L1 data HW prefetches that accounts for any response offcore_response.pf_software.outstanding Counts Software Prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0 offcore_response.pf_software.l2_hit_far_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000401000 Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state offcore_response.pf_software.l2_hit_far_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800401000 Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode offcore_response.pf_software.l2_hit_near_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000081000 Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state offcore_response.pf_software.l2_hit_near_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800081000 Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state offcore_response.pf_software.any_response Counts Software Prefetches that accounts for any response Counts Full streaming stores (WC and should be programmed on PMC1) that accounts for any response Counts Bus locks and split lock requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0 offcore_response.bus_locks.l2_hit_far_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400400 Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state offcore_response.bus_locks.l2_hit_far_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400400 Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode offcore_response.bus_locks.l2_hit_near_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080400 Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state offcore_response.bus_locks.l2_hit_near_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080400 Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state Counts Bus locks and split lock requests that accounts for any response offcore_response.uc_code_reads.outstanding umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000200 Counts UC code reads (valid only for Outstanding response type) that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0 offcore_response.uc_code_reads.l2_hit_far_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400200 Counts UC code reads (valid only for Outstanding response type) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state offcore_response.uc_code_reads.l2_hit_far_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400200 Counts UC code reads (valid only for Outstanding response type) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode offcore_response.uc_code_reads.l2_hit_near_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080200 Counts UC code reads (valid only for Outstanding response type) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state offcore_response.uc_code_reads.l2_hit_near_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080200 Counts UC code reads (valid only for Outstanding response type) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state offcore_response.uc_code_reads.any_response umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010200 Counts UC code reads (valid only for Outstanding response type) that accounts for any response offcore_response.partial_writes.l2_hit_far_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400100 Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state offcore_response.partial_writes.l2_hit_far_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400100 Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode offcore_response.partial_writes.l2_hit_near_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080100 Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state offcore_response.partial_writes.l2_hit_near_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080100 Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state offcore_response.partial_writes.any_response umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010100 Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for any response offcore_response.partial_reads.outstanding umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000080 Counts Partial reads (UC or WC and is valid only for Outstanding response type). that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0 offcore_response.partial_reads.l2_hit_far_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400080 Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state offcore_response.partial_reads.l2_hit_far_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400080 Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode offcore_response.partial_reads.l2_hit_near_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080080 Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state offcore_response.partial_reads.l2_hit_near_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080080 Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state offcore_response.partial_reads.any_response umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010080 Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for any response offcore_response.pf_l2_code_rd.outstanding umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000040 Counts L2 code HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0 offcore_response.pf_l2_code_rd.l2_hit_far_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400040 Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state offcore_response.pf_l2_code_rd.l2_hit_far_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400040 Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode offcore_response.pf_l2_code_rd.l2_hit_near_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080040 Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state offcore_response.pf_l2_code_rd.l2_hit_near_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080040 Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010040 Counts L2 code HW prefetches that accounts for any response offcore_response.pf_l2_rfo.l2_hit_far_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400020 Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state offcore_response.pf_l2_rfo.l2_hit_far_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400020 Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode offcore_response.pf_l2_rfo.l2_hit_near_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080020 Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state offcore_response.pf_l2_rfo.l2_hit_near_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080020 Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state offcore_response.pf_l2_rfo.supplier_none umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000020020 Counts L2 data RFO prefetches (includes PREFETCHW instruction) that provides no supplier details Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for any response Counts demand code reads and prefetch code reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0 offcore_response.demand_code_rd.l2_hit_far_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400004 Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state offcore_response.demand_code_rd.l2_hit_far_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400004 Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode offcore_response.demand_code_rd.l2_hit_near_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080004 Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state offcore_response.demand_code_rd.l2_hit_near_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080004 Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state Counts demand code reads and prefetch code reads that accounts for any response Counts Demand cacheable data writes that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0 offcore_response.demand_rfo.l2_hit_far_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400002 Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state offcore_response.demand_rfo.l2_hit_far_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400002 Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode offcore_response.demand_rfo.l2_hit_near_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080002 Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state offcore_response.demand_rfo.l2_hit_near_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080002 Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state Counts Demand cacheable data writes that accounts for any response Counts demand cacheable data and L1 prefetch data reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0 offcore_response.demand_data_rd.l2_hit_far_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400001 Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state offcore_response.demand_data_rd.l2_hit_far_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400001 Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode offcore_response.demand_data_rd.l2_hit_near_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080001 Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state offcore_response.demand_data_rd.l2_hit_near_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080001 Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state Counts demand cacheable data and L1 prefetch data reads that accounts for any response offcore_response.demand_data_rd.l2_hit_this_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002000001 Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in M state offcore_response.demand_rfo.l2_hit_this_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002000002 Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in M state offcore_response.demand_code_rd.l2_hit_this_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002000004 Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in M state offcore_response.pf_l2_rfo.l2_hit_this_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002000020 Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in M state offcore_response.partial_reads.l2_hit_this_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002000080 Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses which hit its own tile's L2 with data in M state offcore_response.partial_writes.l2_hit_this_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002000100 Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in M state offcore_response.uc_code_reads.l2_hit_this_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002000200 Counts UC code reads (valid only for Outstanding response type) that accounts for responses which hit its own tile's L2 with data in M state offcore_response.bus_locks.l2_hit_this_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002000400 Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in M state offcore_response.pf_software.l2_hit_this_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002001000 Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in M state offcore_response.pf_l1_data_rd.l2_hit_this_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002002000 Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in M state offcore_response.any_request.l2_hit_this_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002008000 Counts any request that accounts for responses which hit its own tile's L2 with data in M state offcore_response.any_data_rd.l2_hit_this_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002003091 Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses which hit its own tile's L2 with data in M state offcore_response.any_rfo.l2_hit_this_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002000022 Counts Demand cacheable data write requests that accounts for responses which hit its own tile's L2 with data in M state offcore_response.any_code_rd.l2_hit_this_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002000044 Counts Demand code reads and prefetch code read requests that accounts for responses which hit its own tile's L2 with data in M state offcore_response.any_read.l2_hit_this_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x00020032f7 Counts any Read request that accounts for responses which hit its own tile's L2 with data in M state offcore_response.any_pf_l2.l2_hit_this_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002000070 Counts any Prefetch requests that accounts for responses which hit its own tile's L2 with data in M state offcore_response.demand_data_rd.l2_hit_this_tile_e umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000001 Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in E state offcore_response.demand_rfo.l2_hit_this_tile_e umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000002 Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in E state offcore_response.demand_code_rd.l2_hit_this_tile_e umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000004 Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in E state offcore_response.pf_l2_rfo.l2_hit_this_tile_e umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000020 Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in E state offcore_response.pf_l2_code_rd.l2_hit_this_tile_e umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000040 Counts L2 code HW prefetches that accounts for responses which hit its own tile's L2 with data in E state offcore_response.partial_reads.l2_hit_this_tile_e umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000080 Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses which hit its own tile's L2 with data in E state offcore_response.partial_writes.l2_hit_this_tile_e umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000100 Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in E state offcore_response.uc_code_reads.l2_hit_this_tile_e umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000200 Counts UC code reads (valid only for Outstanding response type) that accounts for responses which hit its own tile's L2 with data in E state offcore_response.bus_locks.l2_hit_this_tile_e umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000400 Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in E state offcore_response.pf_software.l2_hit_this_tile_e umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004001000 Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in E state offcore_response.pf_l1_data_rd.l2_hit_this_tile_e umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004002000 Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in E state offcore_response.any_request.l2_hit_this_tile_e umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004008000 Counts any request that accounts for responses which hit its own tile's L2 with data in E state offcore_response.any_data_rd.l2_hit_this_tile_e umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004003091 Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses which hit its own tile's L2 with data in E state offcore_response.any_rfo.l2_hit_this_tile_e umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000022 Counts Demand cacheable data write requests that accounts for responses which hit its own tile's L2 with data in E state offcore_response.any_code_rd.l2_hit_this_tile_e umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000044 Counts Demand code reads and prefetch code read requests that accounts for responses which hit its own tile's L2 with data in E state offcore_response.any_read.l2_hit_this_tile_e umask=0x1,period=100007,event=0xb7,offcore_rsp=0x00040032f7 Counts any Read request that accounts for responses which hit its own tile's L2 with data in E state offcore_response.any_pf_l2.l2_hit_this_tile_e umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000070 Counts any Prefetch requests that accounts for responses which hit its own tile's L2 with data in E state offcore_response.demand_data_rd.l2_hit_this_tile_s umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008000001 Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in S state offcore_response.demand_rfo.l2_hit_this_tile_s umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008000002 Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in S state offcore_response.demand_code_rd.l2_hit_this_tile_s umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008000004 Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in S state offcore_response.pf_l2_rfo.l2_hit_this_tile_s umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008000020 Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in S state offcore_response.partial_reads.l2_hit_this_tile_s umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008000080 Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses which hit its own tile's L2 with data in S state offcore_response.partial_writes.l2_hit_this_tile_s umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008000100 Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in S state offcore_response.uc_code_reads.l2_hit_this_tile_s umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008000200 Counts UC code reads (valid only for Outstanding response type) that accounts for responses which hit its own tile's L2 with data in S state offcore_response.bus_locks.l2_hit_this_tile_s umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008000400 Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in S state offcore_response.pf_software.l2_hit_this_tile_s umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008001000 Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in S state offcore_response.pf_l1_data_rd.l2_hit_this_tile_s umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008002000 Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in S state offcore_response.any_request.l2_hit_this_tile_s umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008008000 Counts any request that accounts for responses which hit its own tile's L2 with data in S state offcore_response.any_data_rd.l2_hit_this_tile_s umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008003091 Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses which hit its own tile's L2 with data in S state offcore_response.any_rfo.l2_hit_this_tile_s umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008000022 Counts Demand cacheable data write requests that accounts for responses which hit its own tile's L2 with data in S state offcore_response.any_code_rd.l2_hit_this_tile_s umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008000044 Counts Demand code reads and prefetch code read requests that accounts for responses which hit its own tile's L2 with data in S state offcore_response.any_read.l2_hit_this_tile_s umask=0x1,period=100007,event=0xb7,offcore_rsp=0x00080032f7 Counts any Read request that accounts for responses which hit its own tile's L2 with data in S state offcore_response.demand_data_rd.l2_hit_this_tile_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000001 Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in F state offcore_response.demand_rfo.l2_hit_this_tile_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000002 Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in F state offcore_response.demand_code_rd.l2_hit_this_tile_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000004 Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in F state offcore_response.pf_l2_rfo.l2_hit_this_tile_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000020 Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in F state offcore_response.pf_l2_code_rd.l2_hit_this_tile_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000040 Counts L2 code HW prefetches that accounts for responses which hit its own tile's L2 with data in F state offcore_response.partial_reads.l2_hit_this_tile_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000080 Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses which hit its own tile's L2 with data in F state offcore_response.partial_writes.l2_hit_this_tile_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000100 Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in F state offcore_response.uc_code_reads.l2_hit_this_tile_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000200 Counts UC code reads (valid only for Outstanding response type) that accounts for responses which hit its own tile's L2 with data in F state offcore_response.bus_locks.l2_hit_this_tile_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000400 Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in F state offcore_response.pf_software.l2_hit_this_tile_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010001000 Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in F state offcore_response.pf_l1_data_rd.l2_hit_this_tile_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010002000 Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in F state offcore_response.any_request.l2_hit_this_tile_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010008000 Counts any request that accounts for responses which hit its own tile's L2 with data in F state offcore_response.any_data_rd.l2_hit_this_tile_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010003091 Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses which hit its own tile's L2 with data in F state offcore_response.any_rfo.l2_hit_this_tile_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000022 Counts Demand cacheable data write requests that accounts for responses which hit its own tile's L2 with data in F state offcore_response.any_code_rd.l2_hit_this_tile_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000044 Counts Demand code reads and prefetch code read requests that accounts for responses which hit its own tile's L2 with data in F state offcore_response.any_read.l2_hit_this_tile_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x00100032f7 Counts any Read request that accounts for responses which hit its own tile's L2 with data in F state offcore_response.any_pf_l2.l2_hit_this_tile_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000070 Counts any Prefetch requests that accounts for responses which hit its own tile's L2 with data in F state offcore_response.demand_rfo.l2_hit_near_tile umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800180002 Counts Demand cacheable data writes that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state offcore_response.demand_code_rd.l2_hit_near_tile umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800180004 Counts demand code reads and prefetch code reads that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state offcore_response.pf_l2_rfo.l2_hit_near_tile umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800180020 Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state offcore_response.pf_l2_code_rd.l2_hit_near_tile umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800180040 Counts L2 code HW prefetches that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state offcore_response.partial_reads.l2_hit_near_tile umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800180080 Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state offcore_response.partial_writes.l2_hit_near_tile umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800180100 Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state offcore_response.uc_code_reads.l2_hit_near_tile umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800180200 Counts UC code reads (valid only for Outstanding response type) that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state offcore_response.bus_locks.l2_hit_near_tile umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800180400 Counts Bus locks and split lock requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state offcore_response.pf_software.l2_hit_near_tile umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800181000 Counts Software Prefetches that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state offcore_response.pf_l1_data_rd.l2_hit_near_tile umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800182000 Counts L1 data HW prefetches that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state offcore_response.any_request.l2_hit_near_tile umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800188000 Counts any request that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state offcore_response.any_data_rd.l2_hit_near_tile umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800183091 Counts Demand cacheable data and L1 prefetch data read requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state offcore_response.any_rfo.l2_hit_near_tile umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800180022 Counts Demand cacheable data write requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state offcore_response.any_code_rd.l2_hit_near_tile umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800180044 Counts Demand code reads and prefetch code read requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state offcore_response.any_read.l2_hit_near_tile umask=0x1,period=100007,event=0xb7,offcore_rsp=0x18001832f7 Counts any Read request that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state offcore_response.any_pf_l2.l2_hit_near_tile umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800180070 Counts any Prefetch requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state offcore_response.demand_rfo.l2_hit_far_tile umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800400002 Counts Demand cacheable data writes that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode offcore_response.demand_code_rd.l2_hit_far_tile umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800400004 Counts demand code reads and prefetch code reads that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode offcore_response.pf_l2_code_rd.l2_hit_far_tile umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800400040 Counts L2 code HW prefetches that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode offcore_response.partial_reads.l2_hit_far_tile umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800400080 Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode offcore_response.partial_writes.l2_hit_far_tile umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800400100 Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode offcore_response.bus_locks.l2_hit_far_tile umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800400400 Counts Bus locks and split lock requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode offcore_response.pf_software.l2_hit_far_tile umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800401000 Counts Software Prefetches that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode offcore_response.pf_l1_data_rd.l2_hit_far_tile umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800402000 Counts L1 data HW prefetches that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode offcore_response.any_request.l2_hit_far_tile umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800408000 Counts any request that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode offcore_response.any_data_rd.l2_hit_far_tile umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800403091 Counts Demand cacheable data and L1 prefetch data read requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode offcore_response.any_rfo.l2_hit_far_tile umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800400022 Counts Demand cacheable data write requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode offcore_response.any_code_rd.l2_hit_far_tile umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800400044 Counts Demand code reads and prefetch code read requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode offcore_response.any_read.l2_hit_far_tile umask=0x1,period=100007,event=0xb7,offcore_rsp=0x18004032f7 Counts any Read request that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode offcore_response.any_pf_l2.l2_hit_far_tile umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800400070 Counts any Prefetch requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode Counts all instruction fetches, including uncacheable fetches Counts all instruction fetches that hit the instruction cache Counts all instruction fetches that miss the instruction cache or produce memory requests. An instruction fetch miss is counted only once and not once for every cycle it is outstanding Counts the number of times the MSROM starts a flow of uops Counts the number of times the machine clears due to memory ordering hazards offcore_response.any_pf_l2.mcdram_far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400070 Counts any Prefetch requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far offcore_response.any_pf_l2.mcdram_near umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200070 Counts any Prefetch requests that accounts for data responses from MCDRAM Local offcore_response.any_pf_l2.ddr_far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000070 Counts any Prefetch requests that accounts for data responses from DRAM Far offcore_response.any_pf_l2.ddr_near umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800070 Counts any Prefetch requests that accounts for data responses from DRAM Local offcore_response.any_read.mcdram_far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x01004032f7 Counts any Read request that accounts for data responses from MCDRAM Far or Other tile L2 hit far offcore_response.any_read.mcdram_near umask=0x1,period=100007,event=0xb7,offcore_rsp=0x00802032f7 Counts any Read request that accounts for data responses from MCDRAM Local offcore_response.any_read.ddr_far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x01010032f7 Counts any Read request that accounts for data responses from DRAM Far offcore_response.any_read.ddr_near umask=0x1,period=100007,event=0xb7,offcore_rsp=0x00808032f7 Counts any Read request that accounts for data responses from DRAM Local offcore_response.any_code_rd.mcdram_far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400044 Counts Demand code reads and prefetch code read requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far offcore_response.any_code_rd.mcdram_near umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200044 Counts Demand code reads and prefetch code read requests that accounts for data responses from MCDRAM Local offcore_response.any_code_rd.ddr_far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000044 Counts Demand code reads and prefetch code read requests that accounts for data responses from DRAM Far offcore_response.any_code_rd.ddr_near umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800044 Counts Demand code reads and prefetch code read requests that accounts for data responses from DRAM Local offcore_response.any_rfo.mcdram_far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400022 Counts Demand cacheable data write requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far offcore_response.any_rfo.mcdram_near umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200022 Counts Demand cacheable data write requests that accounts for data responses from MCDRAM Local offcore_response.any_rfo.ddr_far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000022 Counts Demand cacheable data write requests that accounts for data responses from DRAM Far offcore_response.any_rfo.ddr_near umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800022 Counts Demand cacheable data write requests that accounts for data responses from DRAM Local offcore_response.any_data_rd.mcdram_far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100403091 Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far offcore_response.any_data_rd.mcdram_near umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080203091 Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from MCDRAM Local offcore_response.any_data_rd.ddr_far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101003091 Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from DRAM Far offcore_response.any_data_rd.ddr_near umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080803091 Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from DRAM Local offcore_response.any_request.mcdram_far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100408000 Counts any request that accounts for data responses from MCDRAM Far or Other tile L2 hit far offcore_response.any_request.mcdram_near umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080208000 Counts any request that accounts for data responses from MCDRAM Local offcore_response.any_request.ddr_far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101008000 Counts any request that accounts for data responses from DRAM Far offcore_response.any_request.ddr_near umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080808000 Counts any request that accounts for data responses from DRAM Local offcore_response.pf_l1_data_rd.mcdram_far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100402000 Counts L1 data HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far offcore_response.pf_l1_data_rd.mcdram_near umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080202000 Counts L1 data HW prefetches that accounts for data responses from MCDRAM Local offcore_response.pf_l1_data_rd.ddr_far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101002000 Counts L1 data HW prefetches that accounts for data responses from DRAM Far offcore_response.pf_l1_data_rd.ddr_near umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080802000 Counts L1 data HW prefetches that accounts for data responses from DRAM Local offcore_response.pf_software.mcdram_far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100401000 Counts Software Prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far offcore_response.pf_software.mcdram_near umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080201000 Counts Software Prefetches that accounts for data responses from MCDRAM Local offcore_response.pf_software.ddr_far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101001000 Counts Software Prefetches that accounts for data responses from DRAM Far offcore_response.pf_software.ddr_near umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080801000 Counts Software Prefetches that accounts for data responses from DRAM Local offcore_response.bus_locks.mcdram_far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400400 Counts Bus locks and split lock requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far offcore_response.bus_locks.mcdram_near umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200400 Counts Bus locks and split lock requests that accounts for data responses from MCDRAM Local offcore_response.bus_locks.ddr_far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000400 Counts Bus locks and split lock requests that accounts for data responses from DRAM Far offcore_response.bus_locks.ddr_near umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800400 Counts Bus locks and split lock requests that accounts for data responses from DRAM Local offcore_response.uc_code_reads.mcdram_far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400200 Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from MCDRAM Far or Other tile L2 hit far offcore_response.uc_code_reads.mcdram_near umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200200 Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from MCDRAM Local offcore_response.uc_code_reads.ddr_far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000200 Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from DRAM Far offcore_response.uc_code_reads.ddr_near umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800200 Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from DRAM Local offcore_response.partial_writes.mcdram_far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400100 Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Far or Other tile L2 hit far offcore_response.partial_writes.mcdram_near umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200100 Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Local offcore_response.partial_writes.ddr_far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000100 Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Far offcore_response.partial_writes.ddr_near umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800100 Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Local offcore_response.partial_reads.non_dram umask=0x1,period=100007,event=0xb7,offcore_rsp=0x2000020080 Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from any NON_DRAM system address. This includes MMIO transactions offcore_response.partial_reads.mcdram_far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400080 Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from MCDRAM Far or Other tile L2 hit far offcore_response.partial_reads.mcdram_near umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200080 Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from MCDRAM Local offcore_response.partial_reads.ddr_far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000080 Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from DRAM Far offcore_response.partial_reads.ddr_near umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800080 Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from DRAM Local offcore_response.pf_l2_code_rd.mcdram_far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400040 Counts L2 code HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far offcore_response.pf_l2_code_rd.mcdram_near umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200040 Counts L2 code HW prefetches that accounts for data responses from MCDRAM Local offcore_response.pf_l2_code_rd.ddr_far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000040 Counts L2 code HW prefetches that accounts for data responses from DRAM Far offcore_response.pf_l2_code_rd.ddr_near umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800040 Counts L2 code HW prefetches that accounts for data responses from DRAM Local offcore_response.pf_l2_rfo.non_dram umask=0x1,period=100007,event=0xb7,offcore_rsp=0x2000020020 Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from any NON_DRAM system address. This includes MMIO transactions offcore_response.pf_l2_rfo.mcdram_far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400020 Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Far or Other tile L2 hit far offcore_response.pf_l2_rfo.mcdram_near umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200020 Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Local offcore_response.pf_l2_rfo.ddr_far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000020 Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Far offcore_response.pf_l2_rfo.ddr_near umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800020 Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Local offcore_response.demand_code_rd.mcdram_far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400004 Counts demand code reads and prefetch code reads that accounts for data responses from MCDRAM Far or Other tile L2 hit far offcore_response.demand_code_rd.mcdram_near umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200004 Counts demand code reads and prefetch code reads that accounts for data responses from MCDRAM Local offcore_response.demand_code_rd.ddr_far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000004 Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Far offcore_response.demand_code_rd.ddr_near umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800004 Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Local offcore_response.demand_rfo.mcdram_far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400002 Counts Demand cacheable data writes that accounts for data responses from MCDRAM Far or Other tile L2 hit far offcore_response.demand_rfo.mcdram_near umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200002 Counts Demand cacheable data writes that accounts for data responses from MCDRAM Local offcore_response.demand_rfo.ddr_far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000002 Counts Demand cacheable data writes that accounts for data responses from DRAM Far offcore_response.demand_rfo.ddr_near umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800002 Counts Demand cacheable data writes that accounts for data responses from DRAM Local offcore_response.demand_data_rd.mcdram_far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400001 Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM Far or Other tile L2 hit far offcore_response.demand_data_rd.mcdram_near umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200001 Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM Local offcore_response.demand_data_rd.ddr_far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000001 Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Far offcore_response.demand_data_rd.ddr_near umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800001 Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Local offcore_response.demand_data_rd.mcdram umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180600001 Counts demand cacheable data and L1 prefetch data reads that accounts for responses from MCDRAM (local and far) offcore_response.demand_rfo.mcdram umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180600002 Counts Demand cacheable data writes that accounts for responses from MCDRAM (local and far) offcore_response.demand_code_rd.mcdram umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180600004 Counts demand code reads and prefetch code reads that accounts for responses from MCDRAM (local and far) offcore_response.pf_l2_rfo.mcdram umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180600020 Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from MCDRAM (local and far) offcore_response.partial_reads.mcdram umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180600080 Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from MCDRAM (local and far) offcore_response.partial_writes.mcdram umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180600100 Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from MCDRAM (local and far) offcore_response.uc_code_reads.mcdram umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180600200 Counts UC code reads (valid only for Outstanding response type) that accounts for responses from MCDRAM (local and far) offcore_response.bus_locks.mcdram umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180600400 Counts Bus locks and split lock requests that accounts for responses from MCDRAM (local and far) offcore_response.pf_software.mcdram umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180601000 Counts Software Prefetches that accounts for responses from MCDRAM (local and far) offcore_response.any_request.mcdram umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180608000 Counts any request that accounts for responses from MCDRAM (local and far) offcore_response.any_data_rd.mcdram umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180603091 Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from MCDRAM (local and far) offcore_response.any_rfo.mcdram umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180600022 Counts Demand cacheable data write requests that accounts for responses from MCDRAM (local and far) offcore_response.any_code_rd.mcdram umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180600044 Counts Demand code reads and prefetch code read requests that accounts for responses from MCDRAM (local and far) offcore_response.any_read.mcdram umask=0x1,period=100007,event=0xb7,offcore_rsp=0x01806032f7 Counts any Read request that accounts for responses from MCDRAM (local and far) offcore_response.any_pf_l2.mcdram umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180600070 Counts any Prefetch requests that accounts for responses from MCDRAM (local and far) offcore_response.demand_data_rd.ddr umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181800001 Counts demand cacheable data and L1 prefetch data reads that accounts for responses from DDR (local and far) offcore_response.demand_rfo.ddr umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181800002 Counts Demand cacheable data writes that accounts for responses from DDR (local and far) offcore_response.demand_code_rd.ddr umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181800004 Counts demand code reads and prefetch code reads that accounts for responses from DDR (local and far) offcore_response.pf_l2_rfo.ddr umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181800020 Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from DDR (local and far) offcore_response.pf_l2_code_rd.ddr umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181800040 Counts L2 code HW prefetches that accounts for responses from DDR (local and far) offcore_response.partial_reads.ddr umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181800080 Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from DDR (local and far) offcore_response.uc_code_reads.ddr umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181800200 Counts UC code reads (valid only for Outstanding response type) that accounts for responses from DDR (local and far) offcore_response.bus_locks.ddr umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181800400 Counts Bus locks and split lock requests that accounts for responses from DDR (local and far) offcore_response.pf_software.ddr umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181801000 Counts Software Prefetches that accounts for responses from DDR (local and far) offcore_response.pf_l1_data_rd.ddr umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181802000 Counts L1 data HW prefetches that accounts for responses from DDR (local and far) offcore_response.any_request.ddr umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181808000 Counts any request that accounts for responses from DDR (local and far) offcore_response.any_data_rd.ddr umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181803091 Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from DDR (local and far) offcore_response.any_rfo.ddr umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181800022 Counts Demand cacheable data write requests that accounts for responses from DDR (local and far) offcore_response.any_code_rd.ddr umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181800044 Counts Demand code reads and prefetch code read requests that accounts for responses from DDR (local and far) offcore_response.any_read.ddr umask=0x1,period=100007,event=0xb7,offcore_rsp=0x01818032f7 Counts any Read request that accounts for responses from DDR (local and far) Counts the number of branch instructions retired (Precise event) Counts the number of branch instructions retired that were conditional jumps (Precise event) Counts the number of branch instructions retired that were conditional jumps and predicted taken (Precise event) Counts the number of near CALL branch instructions retired (Precise event) Counts the number of near relative CALL branch instructions retired (Precise event) Counts the number of near indirect CALL branch instructions retired (Precise event) Counts the number of near RET branch instructions retired (Precise event) Counts the number of branch instructions retired that were near indirect CALL or near indirect JMP (Precise event) Counts the number of mispredicted branch instructions retired (Precise event) Counts the number of mispredicted branch instructions retired that were conditional jumps (Precise event) Counts the number of mispredicted branch instructions retired that were conditional jumps and predicted taken (Precise event) Counts the number of mispredicted near indirect CALL branch instructions retired (Precise event) Counts the number of mispredicted near RET branch instructions retired (Precise event) Counts the number of mispredicted branch instructions retired that were near indirect CALL or near indirect JMP (Precise event) Counts the number of micro-ops retired that are from the complex flows issued by the micro-sequencer (MS) This event counts the number of micro-ops retired that were supplied from MSROM Counts the number of micro-ops retired This event counts the number of micro-ops (uops) retired. The processor decodes complex macro instructions into a sequence of simpler uops. Most instructions are composed of one or two uops. Some instructions are decoded into longer sequences such as repeat instructions, floating point transcendental instructions, and assists uops_retired.scalar_simd umask=0x20,period=200003,event=0xc2 Counts the number of scalar SSE, AVX, AVX2, AVX-512 micro-ops retired. More specifically, it counts scalar SSE, AVX, AVX2, AVX-512 micro-ops except for loads (memory-to-register mov-type micro ops), division, sqrt This event counts the number of scalar SSE, AVX, AVX2, AVX-512 micro-ops retired (floating point, integer and store) except for loads (memory-to-register mov-type micro ops), division, sqrt uops_retired.packed_simd umask=0x40,period=200003,event=0xc2 Counts the number of vector SSE, AVX, AVX2, AVX-512 micro-ops retired. More specifically, it counts packed SSE, AVX, AVX2, AVX-512 micro-ops (both floating point and integer) except for loads (memory-to-register mov-type micro-ops), packed byte and word multiplies This event counts the number of packed vector SSE, AVX, AVX2, and AVX-512 micro-ops retired (floating point, integer and store) except for loads (memory-to-register mov-type micro-ops), packed byte and word multiplies Counts the number of times that the machine clears due to program modifying data within 1K of a recently fetched code page Counts the number of floating operations retired that required microcode assists This event counts the number of times that the pipeline stalled due to FP operations needing assists Counts all nukes no_alloc_cycles.rob_full Counts the number of core cycles when no micro-ops are allocated and the ROB is full no_alloc_cycles.mispredicts umask=0x4,period=200003,event=0xca Counts the number of core cycles when no micro-ops are allocated and the alloc pipe is stalled waiting for a mispredicted branch to retire This event counts the number of core cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted branch to retire no_alloc_cycles.rat_stall umask=0x20,period=200003,event=0xca Counts the number of core cycles when no micro-ops are allocated and a RATstall (caused by reservation station full) is asserted no_alloc_cycles.not_delivered umask=0x90,period=200003,event=0xca Counts the number of core cycles when no micro-ops are allocated, the IQ is empty, and no other condition is blocking allocation This event counts the number of core cycles when no uops are allocated, the instruction queue is empty and the alloc pipe is stalled waiting for instructions to be fetched no_alloc_cycles.all umask=0x7f,period=200003,event=0xca Counts the total number of core cycles when no micro-ops are allocated for any reason rs_full_stall.mec umask=0x1,period=200003,event=0xcb Counts the number of core cycles when allocation pipeline is stalled and is waiting for a free MEC reservation station entry rs_full_stall.all umask=0x1f,period=200003,event=0xcb Counts the total number of core cycles the Alloc pipeline is stalled when any one of the reservation stations is full Counts the total number of instructions retired umask=0x1,period=2000003,event=0xcd Cycles the number of core cycles when divider is busy. Does not imply a stall waiting for the divider This event counts cycles when the divider is busy. More specifically cycles when the divide unit is unable to accept a new divide uop because it is busy processing a previously dispatched uop. The cycles will be counted irrespective of whether or not another divide uop is waiting to enter the divide unit (from the RS). This event counts integer divides, x87 divides, divss, divsd, sqrtss, sqrtsd event and does not count vector divides Fixed Counter: Counts the number of instructions retired This event counts the number of instructions that retire. For instructions that consist of multiple micro-ops, this event counts exactly once, as the last micro-op of the instruction retires. The event continues counting while instructions retire, including during interrupt service routines caused by hardware interrupts, faults or traps Counts the number of unhalted core clock cycles Counts the number of unhalted reference clock cycles Fixed Counter: Counts the number of unhalted core clock cycles This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter Fixed Counter: Counts the number of unhalted reference clock cycles Counts the number of times the front end resteers for any branch as a result of another branch handling mechanism in the front end Counts the number of times the front end resteers for RET branches as a result of another branch handling mechanism in the front end Counts the number of times the front end resteers for conditional branches as a result of another branch handling mechanism in the front end recycleq.ld_block_st_forward Counts the number of occurences a retired load gets blocked because its address partially overlaps with a store Supports address when precise (Precise event) recycleq.ld_block_std_notready Counts the number of occurences a retired load gets blocked because its address overlaps with a store whose data is not ready recycleq.st_splits Counts the number of occurences a retired store that is a cache line split. Each split should be counted only once This event counts the number of retired store that experienced a cache line boundary split(Precise Event). Note that each spilt should be counted only once recycleq.ld_splits Counts the number of occurences a retired load that is a cache line split. Each split should be counted only once Supports address when precise (Precise event) recycleq.lock Counts all the retired locked loads. It does not include stores because we would double count if we count stores recycleq.sta_full umask=0x20,period=200003,event=0x3 Counts the store micro-ops retired that were pushed in the rehad queue because the store address buffer is full recycleq.any_ld umask=0x40,period=200003,event=0x3 Counts any retired load that was pushed into the recycle queue for any reason recycleq.any_st umask=0x80,period=200003,event=0x3 Counts any retired store that was pushed into the recycle queue for any reason br_misp_retired.call umask=0xf9,period=200003,event=0xc5 Counts the number of mispredicted near CALL branch instructions retired (Precise event) br_misp_retired.rel_call umask=0xfd,period=200003,event=0xc5 Counts the number of mispredicted near relative CALL branch instructions retired (Precise event) br_misp_retired.far_branch umask=0xbf,period=200003,event=0xc5 Counts the number of mispredicted far branch instructions retired (Precise event) unc_m_cas_count.rd umask=0x01,event=0x3 ddr bandwidth read (CPU traffic only) (MB/sec). Unit: uncore_imc 6.4e-05MiB unc_m_cas_count.wr umask=0x02,event=0x3 ddr bandwidth write (CPU traffic only) (MB/sec). Unit: uncore_imc unc_e_rpq_inserts umask=0x01,event=0x1 mcdram bandwidth read (CPU traffic only) (MB/sec). Unit: uncore_edc_eclk uncore_edc_eclk unc_e_wpq_inserts umask=0x01,event=0x2 mcdram bandwidth write (CPU traffic only) (MB/sec). Unit: uncore_edc_eclk umask=0x8,period=200003,event=0x4 Counts the number of load micro-ops retired that cause a DTLB miss Supports address when precise (Precise event) umask=0x1,period=100003,edge=1,event=0x5 Counts the total D-side page walks that are completed or started. The page walks started in the speculative path will also be counted Counts the total number of core cycles for all the D-side page walks. The cycles for page walks started in speculative path will also be included umask=0x2,period=100003,edge=1,event=0x5 Counts the total I-side page walks that are completed Counts the total number of core cycles for all the I-side page walks. The cycles for page walks started in speculative path will also be included This event counts every cycle when an I-side (walks due to an instruction fetch) page walk is in progress umask=0x3,period=100003,edge=1,event=0x5 Counts the total page walks that are completed (I-side and D-side) Counts the total number of core cycles for all the page walks. The cycles for page walks started in speculative path will also be included This event counts every cycle when a data (D) page walk or instruction (I) page walk is in progress cache_lock_cycles.l1d umask=0x2,period=2000000,event=0x63 Cycles L1D locked cache_lock_cycles.l1d_l2 umask=0x1,period=2000000,event=0x63 Cycles L1D and L2 locked l1d.m_evict umask=0x4,period=2000000,event=0x51 L1D cache lines replaced in M state l1d.m_repl umask=0x2,period=2000000,event=0x51 L1D cache lines allocated in the M state l1d.m_snoop_evict umask=0x8,period=2000000,event=0x51 L1D snoop eviction of cache lines in M state l1d.repl umask=0x1,period=2000000,event=0x51 L1 data cache lines allocated l1d_all_ref.any umask=0x1,period=2000000,event=0x43 All references to the L1 data cache l1d_all_ref.cacheable umask=0x2,period=2000000,event=0x43 L1 data cacheable reads and writes l1d_cache_ld.e_state umask=0x4,period=2000000,event=0x40 L1 data cache read in E state l1d_cache_ld.i_state umask=0x1,period=2000000,event=0x40 L1 data cache read in I state (misses) l1d_cache_ld.m_state umask=0x8,period=2000000,event=0x40 L1 data cache read in M state l1d_cache_ld.mesi umask=0xf,period=2000000,event=0x40 L1 data cache reads l1d_cache_ld.s_state umask=0x2,period=2000000,event=0x40 L1 data cache read in S state l1d_cache_lock.e_state umask=0x4,period=2000000,event=0x42 L1 data cache load locks in E state l1d_cache_lock.hit umask=0x1,period=2000000,event=0x42 L1 data cache load lock hits l1d_cache_lock.m_state umask=0x8,period=2000000,event=0x42 L1 data cache load locks in M state l1d_cache_lock.s_state umask=0x2,period=2000000,event=0x42 L1 data cache load locks in S state l1d_cache_lock_fb_hit umask=0x1,period=2000000,event=0x53 L1D load lock accepted in fill buffer l1d_cache_prefetch_lock_fb_hit umask=0x1,period=2000000,event=0x52 L1D prefetch load lock accepted in fill buffer l1d_cache_st.e_state umask=0x4,period=2000000,event=0x41 L1 data cache stores in E state l1d_cache_st.m_state umask=0x8,period=2000000,event=0x41 L1 data cache stores in M state l1d_cache_st.s_state umask=0x2,period=2000000,event=0x41 L1 data cache stores in S state l1d_prefetch.miss umask=0x2,period=200000,event=0x4e L1D hardware prefetch misses l1d_prefetch.requests umask=0x1,period=200000,event=0x4e L1D hardware prefetch requests l1d_prefetch.triggers umask=0x4,period=200000,event=0x4e L1D hardware prefetch requests triggered l1d_wb_l2.e_state umask=0x4,period=100000,event=0x28 L1 writebacks to L2 in E state l1d_wb_l2.i_state umask=0x1,period=100000,event=0x28 L1 writebacks to L2 in I state (misses) l1d_wb_l2.m_state umask=0x8,period=100000,event=0x28 L1 writebacks to L2 in M state l1d_wb_l2.mesi umask=0xf,period=100000,event=0x28 All L1 writebacks to L2 l1d_wb_l2.s_state umask=0x2,period=100000,event=0x28 L1 writebacks to L2 in S state l2_data_rqsts.any umask=0xff,period=200000,event=0x26 All L2 data requests l2_data_rqsts.demand.e_state umask=0x4,period=200000,event=0x26 L2 data demand loads in E state l2_data_rqsts.demand.i_state umask=0x1,period=200000,event=0x26 L2 data demand loads in I state (misses) l2_data_rqsts.demand.m_state umask=0x8,period=200000,event=0x26 L2 data demand loads in M state l2_data_rqsts.demand.mesi umask=0xf,period=200000,event=0x26 L2 data demand requests l2_data_rqsts.demand.s_state umask=0x2,period=200000,event=0x26 L2 data demand loads in S state l2_data_rqsts.prefetch.e_state L2 data prefetches in E state l2_data_rqsts.prefetch.i_state umask=0x10,period=200000,event=0x26 L2 data prefetches in the I state (misses) l2_data_rqsts.prefetch.m_state umask=0x80,period=200000,event=0x26 L2 data prefetches in M state l2_data_rqsts.prefetch.mesi umask=0xf0,period=200000,event=0x26 All L2 data prefetches l2_data_rqsts.prefetch.s_state umask=0x20,period=200000,event=0x26 L2 data prefetches in the S state l2_lines_in.any umask=0x7,period=100000,event=0xf1 L2 lines alloacated l2_lines_in.e_state umask=0x4,period=100000,event=0xf1 L2 lines allocated in the E state l2_lines_in.s_state umask=0x2,period=100000,event=0xf1 L2 lines allocated in the S state l2_lines_out.any umask=0xf,period=100000,event=0xf2 L2 lines evicted umask=0x1,period=100000,event=0xf2 L2 lines evicted by a demand request umask=0x2,period=100000,event=0xf2 L2 modified lines evicted by a demand request l2_lines_out.prefetch_clean umask=0x4,period=100000,event=0xf2 L2 lines evicted by a prefetch request l2_lines_out.prefetch_dirty umask=0x8,period=100000,event=0xf2 L2 modified lines evicted by a prefetch request l2_rqsts.ifetch_hit umask=0x10,period=200000,event=0x24 L2 instruction fetch hits l2_rqsts.ifetch_miss umask=0x20,period=200000,event=0x24 L2 instruction fetch misses l2_rqsts.ifetches umask=0x30,period=200000,event=0x24 L2 instruction fetches l2_rqsts.ld_hit umask=0x1,period=200000,event=0x24 L2 load hits l2_rqsts.ld_miss umask=0x2,period=200000,event=0x24 L2 load misses l2_rqsts.loads umask=0x3,period=200000,event=0x24 L2 requests umask=0xaa,period=200000,event=0x24 All L2 misses l2_rqsts.prefetch_hit L2 prefetch hits l2_rqsts.prefetch_miss umask=0x80,period=200000,event=0x24 L2 prefetch misses l2_rqsts.prefetches umask=0xc0,period=200000,event=0x24 All L2 prefetches umask=0xff,period=200000,event=0x24 umask=0x4,period=200000,event=0x24 L2 RFO hits umask=0x8,period=200000,event=0x24 L2 RFO misses l2_rqsts.rfos umask=0xc,period=200000,event=0x24 L2 RFO requests l2_transactions.any umask=0x80,period=200000,event=0xf0 All L2 transactions l2_transactions.fill umask=0x20,period=200000,event=0xf0 L2 fill transactions l2_transactions.ifetch umask=0x4,period=200000,event=0xf0 L2 instruction fetch transactions l2_transactions.l1d_wb umask=0x10,period=200000,event=0xf0 L1D writeback to L2 transactions l2_transactions.load umask=0x1,period=200000,event=0xf0 L2 Load transactions l2_transactions.prefetch umask=0x8,period=200000,event=0xf0 L2 prefetch transactions l2_transactions.rfo umask=0x2,period=200000,event=0xf0 L2 RFO transactions l2_transactions.wb umask=0x40,period=200000,event=0xf0 L2 writeback to LLC transactions l2_write.lock.e_state umask=0x40,period=100000,event=0x27 L2 demand lock RFOs in E state l2_write.lock.hit umask=0xe0,period=100000,event=0x27 All demand L2 lock RFOs that hit the cache l2_write.lock.i_state umask=0x10,period=100000,event=0x27 L2 demand lock RFOs in I state (misses) l2_write.lock.m_state umask=0x80,period=100000,event=0x27 L2 demand lock RFOs in M state l2_write.lock.mesi umask=0xf0,period=100000,event=0x27 All demand L2 lock RFOs l2_write.lock.s_state umask=0x20,period=100000,event=0x27 L2 demand lock RFOs in S state l2_write.rfo.hit umask=0xe,period=100000,event=0x27 All L2 demand store RFOs that hit the cache l2_write.rfo.i_state umask=0x1,period=100000,event=0x27 L2 demand store RFOs in I state (misses) l2_write.rfo.m_state umask=0x8,period=100000,event=0x27 L2 demand store RFOs in M state l2_write.rfo.mesi umask=0xf,period=100000,event=0x27 All L2 demand store RFOs l2_write.rfo.s_state umask=0x2,period=100000,event=0x27 L2 demand store RFOs in S state umask=0x41,period=100000,event=0x2e Longest latency cache miss Longest latency cache reference mem_inst_retired.loads umask=0x1,period=2000000,event=0xb Instructions retired which contains a load (Precise Event) mem_inst_retired.stores umask=0x2,period=2000000,event=0xb Instructions retired which contains a store (Precise Event) mem_load_retired.hit_lfb umask=0x40,period=200000,event=0xcb Retired loads that miss L1D and hit an previously allocated LFB (Precise Event) mem_load_retired.l1d_hit umask=0x1,period=2000000,event=0xcb Retired loads that hit the L1 data cache (Precise Event) umask=0x2,period=200000,event=0xcb Retired loads that hit the L2 cache (Precise Event) mem_load_retired.llc_miss umask=0x10,period=10000,event=0xcb Retired loads that miss the LLC cache (Precise Event) mem_load_retired.llc_unshared_hit umask=0x4,period=40000,event=0xcb Retired loads that hit valid versions in the LLC cache (Precise Event) mem_load_retired.other_core_l2_hit_hitm umask=0x8,period=40000,event=0xcb Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event) mem_uncore_retired.local_dram umask=0x20,period=10000,event=0xf Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event) mem_uncore_retired.other_core_l2_hitm umask=0x2,period=40000,event=0xf Load instructions retired that HIT modified data in sibling core (Precise Event) mem_uncore_retired.remote_cache_local_home_hit umask=0x8,period=20000,event=0xf Load instructions retired remote cache HIT data source (Precise Event) mem_uncore_retired.remote_dram umask=0x10,period=10000,event=0xf Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event) mem_uncore_retired.uncacheable umask=0x80,period=4000,event=0xf Load instructions retired IO (Precise Event) offcore_requests.l1d_writeback umask=0x40,period=100000,event=0xb0 Offcore L1 data cache writebacks offcore_requests_sq_full umask=0x1,period=100000,event=0xb2 Offcore requests blocked due to Super Queue full umask=0x10,period=2000000,event=0xf4 Super Queue lock splits across a cache line store_blocks.at_ret umask=0x4,period=200000,event=0x6 Loads delayed with at-Retirement block code store_blocks.l1d_block umask=0x8,period=200000,event=0x6 Cacheable loads delayed with L1D block code mem_inst_retired.latency_above_threshold_0 umask=0x10,period=2000000,event=0xb,ldlat=0x0 Memory instructions retired above 0 clocks (Precise Event) mem_inst_retired.latency_above_threshold_1024 umask=0x10,period=100,event=0xb,ldlat=0x400 Memory instructions retired above 1024 clocks (Precise Event) mem_inst_retired.latency_above_threshold_128 umask=0x10,period=1000,event=0xb,ldlat=0x80 Memory instructions retired above 128 clocks (Precise Event) mem_inst_retired.latency_above_threshold_16 umask=0x10,period=10000,event=0xb,ldlat=0x10 Memory instructions retired above 16 clocks (Precise Event) mem_inst_retired.latency_above_threshold_16384 umask=0x10,period=5,event=0xb,ldlat=0x4000 Memory instructions retired above 16384 clocks (Precise Event) mem_inst_retired.latency_above_threshold_2048 umask=0x10,period=50,event=0xb,ldlat=0x800 Memory instructions retired above 2048 clocks (Precise Event) mem_inst_retired.latency_above_threshold_256 umask=0x10,period=500,event=0xb,ldlat=0x100 Memory instructions retired above 256 clocks (Precise Event) mem_inst_retired.latency_above_threshold_32 umask=0x10,period=5000,event=0xb,ldlat=0x20 Memory instructions retired above 32 clocks (Precise Event) mem_inst_retired.latency_above_threshold_32768 umask=0x10,period=3,event=0xb,ldlat=0x8000 Memory instructions retired above 32768 clocks (Precise Event) mem_inst_retired.latency_above_threshold_4 umask=0x10,period=50000,event=0xb,ldlat=0x4 Memory instructions retired above 4 clocks (Precise Event) mem_inst_retired.latency_above_threshold_4096 umask=0x10,period=20,event=0xb,ldlat=0x1000 Memory instructions retired above 4096 clocks (Precise Event) mem_inst_retired.latency_above_threshold_512 umask=0x10,period=200,event=0xb,ldlat=0x200 Memory instructions retired above 512 clocks (Precise Event) mem_inst_retired.latency_above_threshold_64 umask=0x10,period=2000,event=0xb,ldlat=0x40 Memory instructions retired above 64 clocks (Precise Event) mem_inst_retired.latency_above_threshold_8 umask=0x10,period=20000,event=0xb,ldlat=0x8 Memory instructions retired above 8 clocks (Precise Event) mem_inst_retired.latency_above_threshold_8192 umask=0x10,period=10,event=0xb,ldlat=0x2000 Memory instructions retired above 8192 clocks (Precise Event) offcore_response.any_data.any_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F11 Offcore data reads satisfied by any cache or DRAM offcore_response.any_data.any_location umask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF11 All offcore data reads offcore_response.any_data.io_csr_mmio umask=0x1,period=100000,event=0xb7,offcore_rsp=0x8011 Offcore data reads satisfied by the IO, CSR, MMIO unit offcore_response.any_data.llc_hit_no_other_core umask=0x1,period=100000,event=0xb7,offcore_rsp=0x111 Offcore data reads satisfied by the LLC and not found in a sibling core offcore_response.any_data.llc_hit_other_core_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x211 Offcore data reads satisfied by the LLC and HIT in a sibling core offcore_response.any_data.llc_hit_other_core_hitm umask=0x1,period=100000,event=0xb7,offcore_rsp=0x411 Offcore data reads satisfied by the LLC and HITM in a sibling core offcore_response.any_data.local_cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x711 Offcore data reads satisfied by the LLC offcore_response.any_data.local_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4711 Offcore data reads satisfied by the LLC or local DRAM offcore_response.any_data.remote_cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1811 Offcore data reads satisfied by a remote cache offcore_response.any_data.remote_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3811 Offcore data reads satisfied by a remote cache or remote DRAM offcore_response.any_data.remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1011 Offcore data reads that HIT in a remote cache offcore_response.any_data.remote_cache_hitm umask=0x1,period=100000,event=0xb7,offcore_rsp=0x811 Offcore data reads that HITM in a remote cache offcore_response.any_ifetch.any_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F44 Offcore code reads satisfied by any cache or DRAM offcore_response.any_ifetch.any_location umask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF44 All offcore code reads offcore_response.any_ifetch.io_csr_mmio umask=0x1,period=100000,event=0xb7,offcore_rsp=0x8044 Offcore code reads satisfied by the IO, CSR, MMIO unit offcore_response.any_ifetch.llc_hit_no_other_core umask=0x1,period=100000,event=0xb7,offcore_rsp=0x144 Offcore code reads satisfied by the LLC and not found in a sibling core offcore_response.any_ifetch.llc_hit_other_core_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x244 Offcore code reads satisfied by the LLC and HIT in a sibling core offcore_response.any_ifetch.llc_hit_other_core_hitm umask=0x1,period=100000,event=0xb7,offcore_rsp=0x444 Offcore code reads satisfied by the LLC and HITM in a sibling core offcore_response.any_ifetch.local_cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x744 Offcore code reads satisfied by the LLC offcore_response.any_ifetch.local_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4744 Offcore code reads satisfied by the LLC or local DRAM offcore_response.any_ifetch.remote_cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1844 Offcore code reads satisfied by a remote cache offcore_response.any_ifetch.remote_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3844 Offcore code reads satisfied by a remote cache or remote DRAM offcore_response.any_ifetch.remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1044 Offcore code reads that HIT in a remote cache offcore_response.any_ifetch.remote_cache_hitm umask=0x1,period=100000,event=0xb7,offcore_rsp=0x844 Offcore code reads that HITM in a remote cache offcore_response.any_request.any_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7FFF Offcore requests satisfied by any cache or DRAM offcore_response.any_request.any_location umask=0x1,period=100000,event=0xb7,offcore_rsp=0xFFFF All offcore requests offcore_response.any_request.io_csr_mmio umask=0x1,period=100000,event=0xb7,offcore_rsp=0x80FF Offcore requests satisfied by the IO, CSR, MMIO unit offcore_response.any_request.llc_hit_no_other_core umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1FF Offcore requests satisfied by the LLC and not found in a sibling core offcore_response.any_request.llc_hit_other_core_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2FF Offcore requests satisfied by the LLC and HIT in a sibling core offcore_response.any_request.llc_hit_other_core_hitm umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4FF Offcore requests satisfied by the LLC and HITM in a sibling core offcore_response.any_request.local_cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7FF Offcore requests satisfied by the LLC offcore_response.any_request.local_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x47FF Offcore requests satisfied by the LLC or local DRAM offcore_response.any_request.remote_cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x18FF Offcore requests satisfied by a remote cache offcore_response.any_request.remote_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x38FF Offcore requests satisfied by a remote cache or remote DRAM offcore_response.any_request.remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x10FF Offcore requests that HIT in a remote cache offcore_response.any_request.remote_cache_hitm umask=0x1,period=100000,event=0xb7,offcore_rsp=0x8FF Offcore requests that HITM in a remote cache offcore_response.any_rfo.any_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F22 Offcore RFO requests satisfied by any cache or DRAM offcore_response.any_rfo.any_location umask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF22 All offcore RFO requests offcore_response.any_rfo.io_csr_mmio umask=0x1,period=100000,event=0xb7,offcore_rsp=0x8022 Offcore RFO requests satisfied by the IO, CSR, MMIO unit offcore_response.any_rfo.llc_hit_no_other_core umask=0x1,period=100000,event=0xb7,offcore_rsp=0x122 Offcore RFO requests satisfied by the LLC and not found in a sibling core offcore_response.any_rfo.llc_hit_other_core_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x222 Offcore RFO requests satisfied by the LLC and HIT in a sibling core offcore_response.any_rfo.llc_hit_other_core_hitm umask=0x1,period=100000,event=0xb7,offcore_rsp=0x422 Offcore RFO requests satisfied by the LLC and HITM in a sibling core offcore_response.any_rfo.local_cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x722 Offcore RFO requests satisfied by the LLC offcore_response.any_rfo.local_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4722 Offcore RFO requests satisfied by the LLC or local DRAM offcore_response.any_rfo.remote_cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1822 Offcore RFO requests satisfied by a remote cache offcore_response.any_rfo.remote_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3822 Offcore RFO requests satisfied by a remote cache or remote DRAM offcore_response.any_rfo.remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1022 Offcore RFO requests that HIT in a remote cache offcore_response.any_rfo.remote_cache_hitm umask=0x1,period=100000,event=0xb7,offcore_rsp=0x822 Offcore RFO requests that HITM in a remote cache offcore_response.corewb.any_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F08 Offcore writebacks to any cache or DRAM offcore_response.corewb.any_location umask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF08 All offcore writebacks offcore_response.corewb.io_csr_mmio umask=0x1,period=100000,event=0xb7,offcore_rsp=0x8008 Offcore writebacks to the IO, CSR, MMIO unit offcore_response.corewb.llc_hit_no_other_core umask=0x1,period=100000,event=0xb7,offcore_rsp=0x108 Offcore writebacks to the LLC and not found in a sibling core offcore_response.corewb.llc_hit_other_core_hitm umask=0x1,period=100000,event=0xb7,offcore_rsp=0x408 Offcore writebacks to the LLC and HITM in a sibling core offcore_response.corewb.local_cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x708 Offcore writebacks to the LLC offcore_response.corewb.local_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4708 Offcore writebacks to the LLC or local DRAM offcore_response.corewb.remote_cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1808 Offcore writebacks to a remote cache offcore_response.corewb.remote_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3808 Offcore writebacks to a remote cache or remote DRAM offcore_response.corewb.remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1008 Offcore writebacks that HIT in a remote cache offcore_response.corewb.remote_cache_hitm umask=0x1,period=100000,event=0xb7,offcore_rsp=0x808 Offcore writebacks that HITM in a remote cache offcore_response.data_ifetch.any_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F77 Offcore code or data read requests satisfied by any cache or DRAM offcore_response.data_ifetch.any_location umask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF77 All offcore code or data read requests offcore_response.data_ifetch.io_csr_mmio umask=0x1,period=100000,event=0xb7,offcore_rsp=0x8077 Offcore code or data read requests satisfied by the IO, CSR, MMIO unit offcore_response.data_ifetch.llc_hit_no_other_core umask=0x1,period=100000,event=0xb7,offcore_rsp=0x177 Offcore code or data read requests satisfied by the LLC and not found in a sibling core offcore_response.data_ifetch.llc_hit_other_core_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x277 Offcore code or data read requests satisfied by the LLC and HIT in a sibling core offcore_response.data_ifetch.llc_hit_other_core_hitm umask=0x1,period=100000,event=0xb7,offcore_rsp=0x477 Offcore code or data read requests satisfied by the LLC and HITM in a sibling core offcore_response.data_ifetch.local_cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x777 Offcore code or data read requests satisfied by the LLC offcore_response.data_ifetch.local_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4777 Offcore code or data read requests satisfied by the LLC or local DRAM offcore_response.data_ifetch.remote_cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1877 Offcore code or data read requests satisfied by a remote cache offcore_response.data_ifetch.remote_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3877 Offcore code or data read requests satisfied by a remote cache or remote DRAM offcore_response.data_ifetch.remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1077 Offcore code or data read requests that HIT in a remote cache offcore_response.data_ifetch.remote_cache_hitm umask=0x1,period=100000,event=0xb7,offcore_rsp=0x877 Offcore code or data read requests that HITM in a remote cache offcore_response.data_in.any_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F33 Offcore request = all data, response = any cache_dram offcore_response.data_in.any_location umask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF33 Offcore request = all data, response = any location offcore_response.data_in.io_csr_mmio umask=0x1,period=100000,event=0xb7,offcore_rsp=0x8033 Offcore data reads, RFO's and prefetches satisfied by the IO, CSR, MMIO unit offcore_response.data_in.llc_hit_no_other_core umask=0x1,period=100000,event=0xb7,offcore_rsp=0x133 Offcore data reads, RFO's and prefetches statisfied by the LLC and not found in a sibling core offcore_response.data_in.llc_hit_other_core_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x233 Offcore data reads, RFO's and prefetches satisfied by the LLC and HIT in a sibling core offcore_response.data_in.llc_hit_other_core_hitm umask=0x1,period=100000,event=0xb7,offcore_rsp=0x433 Offcore data reads, RFO's and prefetches satisfied by the LLC and HITM in a sibling core offcore_response.data_in.local_cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x733 Offcore request = all data, response = local cache offcore_response.data_in.local_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4733 Offcore request = all data, response = local cache or dram offcore_response.data_in.remote_cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1833 Offcore request = all data, response = remote cache offcore_response.data_in.remote_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3833 Offcore request = all data, response = remote cache or dram offcore_response.data_in.remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1033 Offcore data reads, RFO's and prefetches that HIT in a remote cache offcore_response.data_in.remote_cache_hitm umask=0x1,period=100000,event=0xb7,offcore_rsp=0x833 Offcore data reads, RFO's and prefetches that HITM in a remote cache offcore_response.demand_data.any_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F03 Offcore demand data requests satisfied by any cache or DRAM offcore_response.demand_data.any_location umask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF03 All offcore demand data requests offcore_response.demand_data.io_csr_mmio umask=0x1,period=100000,event=0xb7,offcore_rsp=0x8003 Offcore demand data requests satisfied by the IO, CSR, MMIO unit offcore_response.demand_data.llc_hit_no_other_core umask=0x1,period=100000,event=0xb7,offcore_rsp=0x103 Offcore demand data requests satisfied by the LLC and not found in a sibling core offcore_response.demand_data.llc_hit_other_core_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x203 Offcore demand data requests satisfied by the LLC and HIT in a sibling core offcore_response.demand_data.llc_hit_other_core_hitm umask=0x1,period=100000,event=0xb7,offcore_rsp=0x403 Offcore demand data requests satisfied by the LLC and HITM in a sibling core offcore_response.demand_data.local_cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x703 Offcore demand data requests satisfied by the LLC offcore_response.demand_data.local_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4703 Offcore demand data requests satisfied by the LLC or local DRAM offcore_response.demand_data.remote_cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1803 Offcore demand data requests satisfied by a remote cache offcore_response.demand_data.remote_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3803 Offcore demand data requests satisfied by a remote cache or remote DRAM offcore_response.demand_data.remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1003 Offcore demand data requests that HIT in a remote cache offcore_response.demand_data.remote_cache_hitm umask=0x1,period=100000,event=0xb7,offcore_rsp=0x803 Offcore demand data requests that HITM in a remote cache offcore_response.demand_data_rd.any_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F01 Offcore demand data reads satisfied by any cache or DRAM offcore_response.demand_data_rd.any_location umask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF01 All offcore demand data reads offcore_response.demand_data_rd.io_csr_mmio umask=0x1,period=100000,event=0xb7,offcore_rsp=0x8001 Offcore demand data reads satisfied by the IO, CSR, MMIO unit offcore_response.demand_data_rd.llc_hit_no_other_core umask=0x1,period=100000,event=0xb7,offcore_rsp=0x101 Offcore demand data reads satisfied by the LLC and not found in a sibling core offcore_response.demand_data_rd.llc_hit_other_core_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x201 Offcore demand data reads satisfied by the LLC and HIT in a sibling core offcore_response.demand_data_rd.llc_hit_other_core_hitm umask=0x1,period=100000,event=0xb7,offcore_rsp=0x401 Offcore demand data reads satisfied by the LLC and HITM in a sibling core offcore_response.demand_data_rd.local_cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x701 Offcore demand data reads satisfied by the LLC offcore_response.demand_data_rd.local_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4701 Offcore demand data reads satisfied by the LLC or local DRAM offcore_response.demand_data_rd.remote_cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1801 Offcore demand data reads satisfied by a remote cache offcore_response.demand_data_rd.remote_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3801 Offcore demand data reads satisfied by a remote cache or remote DRAM offcore_response.demand_data_rd.remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1001 Offcore demand data reads that HIT in a remote cache offcore_response.demand_data_rd.remote_cache_hitm umask=0x1,period=100000,event=0xb7,offcore_rsp=0x801 Offcore demand data reads that HITM in a remote cache offcore_response.demand_ifetch.any_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F04 Offcore demand code reads satisfied by any cache or DRAM offcore_response.demand_ifetch.any_location umask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF04 All offcore demand code reads offcore_response.demand_ifetch.io_csr_mmio umask=0x1,period=100000,event=0xb7,offcore_rsp=0x8004 Offcore demand code reads satisfied by the IO, CSR, MMIO unit offcore_response.demand_ifetch.llc_hit_no_other_core umask=0x1,period=100000,event=0xb7,offcore_rsp=0x104 Offcore demand code reads satisfied by the LLC and not found in a sibling core offcore_response.demand_ifetch.llc_hit_other_core_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x204 Offcore demand code reads satisfied by the LLC and HIT in a sibling core offcore_response.demand_ifetch.llc_hit_other_core_hitm umask=0x1,period=100000,event=0xb7,offcore_rsp=0x404 Offcore demand code reads satisfied by the LLC and HITM in a sibling core offcore_response.demand_ifetch.local_cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x704 Offcore demand code reads satisfied by the LLC offcore_response.demand_ifetch.local_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4704 Offcore demand code reads satisfied by the LLC or local DRAM offcore_response.demand_ifetch.remote_cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1804 Offcore demand code reads satisfied by a remote cache offcore_response.demand_ifetch.remote_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3804 Offcore demand code reads satisfied by a remote cache or remote DRAM offcore_response.demand_ifetch.remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1004 Offcore demand code reads that HIT in a remote cache offcore_response.demand_ifetch.remote_cache_hitm umask=0x1,period=100000,event=0xb7,offcore_rsp=0x804 Offcore demand code reads that HITM in a remote cache offcore_response.demand_rfo.any_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F02 Offcore demand RFO requests satisfied by any cache or DRAM offcore_response.demand_rfo.any_location umask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF02 All offcore demand RFO requests offcore_response.demand_rfo.io_csr_mmio umask=0x1,period=100000,event=0xb7,offcore_rsp=0x8002 Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit offcore_response.demand_rfo.llc_hit_no_other_core umask=0x1,period=100000,event=0xb7,offcore_rsp=0x102 Offcore demand RFO requests satisfied by the LLC and not found in a sibling core offcore_response.demand_rfo.llc_hit_other_core_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x202 Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core offcore_response.demand_rfo.llc_hit_other_core_hitm umask=0x1,period=100000,event=0xb7,offcore_rsp=0x402 Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core offcore_response.demand_rfo.local_cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x702 Offcore demand RFO requests satisfied by the LLC offcore_response.demand_rfo.local_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4702 Offcore demand RFO requests satisfied by the LLC or local DRAM offcore_response.demand_rfo.remote_cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1802 Offcore demand RFO requests satisfied by a remote cache offcore_response.demand_rfo.remote_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3802 Offcore demand RFO requests satisfied by a remote cache or remote DRAM offcore_response.demand_rfo.remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1002 Offcore demand RFO requests that HIT in a remote cache offcore_response.demand_rfo.remote_cache_hitm umask=0x1,period=100000,event=0xb7,offcore_rsp=0x802 Offcore demand RFO requests that HITM in a remote cache offcore_response.other.any_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F80 Offcore other requests satisfied by any cache or DRAM offcore_response.other.any_location umask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF80 All offcore other requests offcore_response.other.io_csr_mmio umask=0x1,period=100000,event=0xb7,offcore_rsp=0x8080 Offcore other requests satisfied by the IO, CSR, MMIO unit offcore_response.other.llc_hit_no_other_core umask=0x1,period=100000,event=0xb7,offcore_rsp=0x180 Offcore other requests satisfied by the LLC and not found in a sibling core offcore_response.other.llc_hit_other_core_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x280 Offcore other requests satisfied by the LLC and HIT in a sibling core offcore_response.other.llc_hit_other_core_hitm umask=0x1,period=100000,event=0xb7,offcore_rsp=0x480 Offcore other requests satisfied by the LLC and HITM in a sibling core offcore_response.other.local_cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x780 Offcore other requests satisfied by the LLC offcore_response.other.local_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4780 Offcore other requests satisfied by the LLC or local DRAM offcore_response.other.remote_cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1880 Offcore other requests satisfied by a remote cache offcore_response.other.remote_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3880 Offcore other requests satisfied by a remote cache or remote DRAM offcore_response.other.remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1080 Offcore other requests that HIT in a remote cache offcore_response.other.remote_cache_hitm umask=0x1,period=100000,event=0xb7,offcore_rsp=0x880 Offcore other requests that HITM in a remote cache offcore_response.pf_data.any_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F30 Offcore prefetch data requests satisfied by any cache or DRAM offcore_response.pf_data.any_location umask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF30 All offcore prefetch data requests offcore_response.pf_data.io_csr_mmio umask=0x1,period=100000,event=0xb7,offcore_rsp=0x8030 Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit offcore_response.pf_data.llc_hit_no_other_core umask=0x1,period=100000,event=0xb7,offcore_rsp=0x130 Offcore prefetch data requests satisfied by the LLC and not found in a sibling core offcore_response.pf_data.llc_hit_other_core_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x230 Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core offcore_response.pf_data.llc_hit_other_core_hitm umask=0x1,period=100000,event=0xb7,offcore_rsp=0x430 Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core offcore_response.pf_data.local_cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x730 Offcore prefetch data requests satisfied by the LLC offcore_response.pf_data.local_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4730 Offcore prefetch data requests satisfied by the LLC or local DRAM offcore_response.pf_data.remote_cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1830 Offcore prefetch data requests satisfied by a remote cache offcore_response.pf_data.remote_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3830 Offcore prefetch data requests satisfied by a remote cache or remote DRAM offcore_response.pf_data.remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1030 Offcore prefetch data requests that HIT in a remote cache offcore_response.pf_data.remote_cache_hitm umask=0x1,period=100000,event=0xb7,offcore_rsp=0x830 Offcore prefetch data requests that HITM in a remote cache offcore_response.pf_data_rd.any_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F10 Offcore prefetch data reads satisfied by any cache or DRAM offcore_response.pf_data_rd.any_location umask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF10 All offcore prefetch data reads offcore_response.pf_data_rd.io_csr_mmio umask=0x1,period=100000,event=0xb7,offcore_rsp=0x8010 Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit offcore_response.pf_data_rd.llc_hit_no_other_core umask=0x1,period=100000,event=0xb7,offcore_rsp=0x110 Offcore prefetch data reads satisfied by the LLC and not found in a sibling core offcore_response.pf_data_rd.llc_hit_other_core_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x210 Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core offcore_response.pf_data_rd.llc_hit_other_core_hitm umask=0x1,period=100000,event=0xb7,offcore_rsp=0x410 Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core offcore_response.pf_data_rd.local_cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x710 Offcore prefetch data reads satisfied by the LLC offcore_response.pf_data_rd.local_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4710 Offcore prefetch data reads satisfied by the LLC or local DRAM offcore_response.pf_data_rd.remote_cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1810 Offcore prefetch data reads satisfied by a remote cache offcore_response.pf_data_rd.remote_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3810 Offcore prefetch data reads satisfied by a remote cache or remote DRAM offcore_response.pf_data_rd.remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1010 Offcore prefetch data reads that HIT in a remote cache offcore_response.pf_data_rd.remote_cache_hitm umask=0x1,period=100000,event=0xb7,offcore_rsp=0x810 Offcore prefetch data reads that HITM in a remote cache offcore_response.pf_ifetch.any_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F40 Offcore prefetch code reads satisfied by any cache or DRAM offcore_response.pf_ifetch.any_location umask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF40 All offcore prefetch code reads offcore_response.pf_ifetch.io_csr_mmio umask=0x1,period=100000,event=0xb7,offcore_rsp=0x8040 Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit offcore_response.pf_ifetch.llc_hit_no_other_core umask=0x1,period=100000,event=0xb7,offcore_rsp=0x140 Offcore prefetch code reads satisfied by the LLC and not found in a sibling core offcore_response.pf_ifetch.llc_hit_other_core_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x240 Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core offcore_response.pf_ifetch.llc_hit_other_core_hitm umask=0x1,period=100000,event=0xb7,offcore_rsp=0x440 Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core offcore_response.pf_ifetch.local_cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x740 Offcore prefetch code reads satisfied by the LLC offcore_response.pf_ifetch.local_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4740 Offcore prefetch code reads satisfied by the LLC or local DRAM offcore_response.pf_ifetch.remote_cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1840 Offcore prefetch code reads satisfied by a remote cache offcore_response.pf_ifetch.remote_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3840 Offcore prefetch code reads satisfied by a remote cache or remote DRAM offcore_response.pf_ifetch.remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1040 Offcore prefetch code reads that HIT in a remote cache offcore_response.pf_ifetch.remote_cache_hitm umask=0x1,period=100000,event=0xb7,offcore_rsp=0x840 Offcore prefetch code reads that HITM in a remote cache offcore_response.pf_rfo.any_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F20 Offcore prefetch RFO requests satisfied by any cache or DRAM offcore_response.pf_rfo.any_location umask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF20 All offcore prefetch RFO requests offcore_response.pf_rfo.io_csr_mmio umask=0x1,period=100000,event=0xb7,offcore_rsp=0x8020 Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit offcore_response.pf_rfo.llc_hit_no_other_core umask=0x1,period=100000,event=0xb7,offcore_rsp=0x120 Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core offcore_response.pf_rfo.llc_hit_other_core_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x220 Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core offcore_response.pf_rfo.llc_hit_other_core_hitm umask=0x1,period=100000,event=0xb7,offcore_rsp=0x420 Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core offcore_response.pf_rfo.local_cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x720 Offcore prefetch RFO requests satisfied by the LLC offcore_response.pf_rfo.local_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4720 Offcore prefetch RFO requests satisfied by the LLC or local DRAM offcore_response.pf_rfo.remote_cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1820 Offcore prefetch RFO requests satisfied by a remote cache offcore_response.pf_rfo.remote_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3820 Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM offcore_response.pf_rfo.remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1020 Offcore prefetch RFO requests that HIT in a remote cache offcore_response.pf_rfo.remote_cache_hitm umask=0x1,period=100000,event=0xb7,offcore_rsp=0x820 Offcore prefetch RFO requests that HITM in a remote cache offcore_response.prefetch.any_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F70 Offcore prefetch requests satisfied by any cache or DRAM offcore_response.prefetch.any_location umask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF70 All offcore prefetch requests offcore_response.prefetch.io_csr_mmio umask=0x1,period=100000,event=0xb7,offcore_rsp=0x8070 Offcore prefetch requests satisfied by the IO, CSR, MMIO unit offcore_response.prefetch.llc_hit_no_other_core umask=0x1,period=100000,event=0xb7,offcore_rsp=0x170 Offcore prefetch requests satisfied by the LLC and not found in a sibling core offcore_response.prefetch.llc_hit_other_core_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x270 Offcore prefetch requests satisfied by the LLC and HIT in a sibling core offcore_response.prefetch.llc_hit_other_core_hitm umask=0x1,period=100000,event=0xb7,offcore_rsp=0x470 Offcore prefetch requests satisfied by the LLC and HITM in a sibling core offcore_response.prefetch.local_cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x770 Offcore prefetch requests satisfied by the LLC offcore_response.prefetch.local_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4770 Offcore prefetch requests satisfied by the LLC or local DRAM offcore_response.prefetch.remote_cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1870 Offcore prefetch requests satisfied by a remote cache offcore_response.prefetch.remote_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3870 Offcore prefetch requests satisfied by a remote cache or remote DRAM offcore_response.prefetch.remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1070 Offcore prefetch requests that HIT in a remote cache offcore_response.prefetch.remote_cache_hitm umask=0x1,period=100000,event=0xb7,offcore_rsp=0x870 Offcore prefetch requests that HITM in a remote cache fp_assist.all umask=0x1,period=20000,event=0xf7 X87 Floating point assists (Precise Event) fp_assist.input umask=0x4,period=20000,event=0xf7 X87 Floating poiint assists for invalid input value (Precise Event) fp_assist.output umask=0x2,period=20000,event=0xf7 X87 Floating point assists for invalid output value (Precise Event) fp_comp_ops_exe.mmx MMX Uops fp_comp_ops_exe.sse_double_precision umask=0x80,period=2000000,event=0x10 SSE* FP double precision Uops fp_comp_ops_exe.sse_fp umask=0x4,period=2000000,event=0x10 SSE and SSE2 FP Uops fp_comp_ops_exe.sse_fp_packed umask=0x10,period=2000000,event=0x10 SSE FP packed Uops fp_comp_ops_exe.sse_fp_scalar umask=0x20,period=2000000,event=0x10 SSE FP scalar Uops fp_comp_ops_exe.sse_single_precision umask=0x40,period=2000000,event=0x10 SSE* FP single precision Uops fp_comp_ops_exe.sse2_integer umask=0x8,period=2000000,event=0x10 SSE2 integer Uops Computational floating-point operations executed fp_mmx_trans.any umask=0x3,period=2000000,event=0xcc All Floating Point to and from MMX transitions fp_mmx_trans.to_fp umask=0x1,period=2000000,event=0xcc Transitions from MMX to Floating Point instructions fp_mmx_trans.to_mmx umask=0x2,period=2000000,event=0xcc Transitions from Floating Point to MMX instructions simd_int_128.pack umask=0x4,period=200000,event=0x12 128 bit SIMD integer pack operations simd_int_128.packed_arith umask=0x20,period=200000,event=0x12 128 bit SIMD integer arithmetic operations simd_int_128.packed_logical umask=0x10,period=200000,event=0x12 128 bit SIMD integer logical operations simd_int_128.packed_mpy umask=0x1,period=200000,event=0x12 128 bit SIMD integer multiply operations simd_int_128.packed_shift umask=0x2,period=200000,event=0x12 128 bit SIMD integer shift operations simd_int_128.shuffle_move umask=0x40,period=200000,event=0x12 128 bit SIMD integer shuffle/move operations simd_int_128.unpack umask=0x8,period=200000,event=0x12 128 bit SIMD integer unpack operations simd_int_64.pack umask=0x4,period=200000,event=0xfd SIMD integer 64 bit pack operations simd_int_64.packed_arith umask=0x20,period=200000,event=0xfd SIMD integer 64 bit arithmetic operations simd_int_64.packed_logical umask=0x10,period=200000,event=0xfd SIMD integer 64 bit logical operations simd_int_64.packed_mpy umask=0x1,period=200000,event=0xfd SIMD integer 64 bit packed multiply operations simd_int_64.packed_shift umask=0x2,period=200000,event=0xfd SIMD integer 64 bit shift operations simd_int_64.shuffle_move umask=0x40,period=200000,event=0xfd SIMD integer 64 bit shuffle/move operations simd_int_64.unpack umask=0x8,period=200000,event=0xfd SIMD integer 64 bit unpack operations macro_insts.decoded umask=0x1,period=2000000,event=0xd0 Instructions decoded macro_insts.fusions_decoded umask=0x1,period=2000000,event=0xa6 Macro-fused instructions decoded two_uop_insts_decoded umask=0x1,period=2000000,event=0x19 Two Uop instructions decoded offcore_response.any_data.any_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x6011 Offcore data reads satisfied by any DRAM offcore_response.any_data.any_llc_miss umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF811 Offcore data reads that missed the LLC offcore_response.any_data.local_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4011 Offcore data reads satisfied by the local DRAM offcore_response.any_data.remote_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2011 Offcore data reads satisfied by a remote DRAM offcore_response.any_ifetch.any_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x6044 Offcore code reads satisfied by any DRAM offcore_response.any_ifetch.any_llc_miss umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF844 Offcore code reads that missed the LLC offcore_response.any_ifetch.local_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4044 Offcore code reads satisfied by the local DRAM offcore_response.any_ifetch.remote_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2044 Offcore code reads satisfied by a remote DRAM offcore_response.any_request.any_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x60FF Offcore requests satisfied by any DRAM offcore_response.any_request.any_llc_miss umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF8FF Offcore requests that missed the LLC offcore_response.any_request.local_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x40FF Offcore requests satisfied by the local DRAM offcore_response.any_request.remote_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x20FF Offcore requests satisfied by a remote DRAM offcore_response.any_rfo.any_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x6022 Offcore RFO requests satisfied by any DRAM offcore_response.any_rfo.any_llc_miss umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF822 Offcore RFO requests that missed the LLC offcore_response.any_rfo.local_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4022 Offcore RFO requests satisfied by the local DRAM offcore_response.any_rfo.remote_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2022 Offcore RFO requests satisfied by a remote DRAM offcore_response.corewb.any_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x6008 Offcore writebacks to any DRAM offcore_response.corewb.any_llc_miss umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF808 Offcore writebacks that missed the LLC offcore_response.corewb.local_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4008 Offcore writebacks to the local DRAM offcore_response.corewb.remote_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2008 Offcore writebacks to a remote DRAM offcore_response.data_ifetch.any_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x6077 Offcore code or data read requests satisfied by any DRAM offcore_response.data_ifetch.any_llc_miss umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF877 Offcore code or data read requests that missed the LLC offcore_response.data_ifetch.local_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4077 Offcore code or data read requests satisfied by the local DRAM offcore_response.data_ifetch.remote_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2077 Offcore code or data read requests satisfied by a remote DRAM offcore_response.data_in.any_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x6033 Offcore request = all data, response = any DRAM offcore_response.data_in.any_llc_miss umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF833 Offcore request = all data, response = any LLC miss offcore_response.data_in.local_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4033 Offcore data reads, RFO's and prefetches statisfied by the local DRAM offcore_response.data_in.remote_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2033 Offcore data reads, RFO's and prefetches statisfied by the remote DRAM offcore_response.demand_data.any_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x6003 Offcore demand data requests satisfied by any DRAM offcore_response.demand_data.any_llc_miss umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF803 Offcore demand data requests that missed the LLC offcore_response.demand_data.local_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4003 Offcore demand data requests satisfied by the local DRAM offcore_response.demand_data.remote_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2003 Offcore demand data requests satisfied by a remote DRAM offcore_response.demand_data_rd.any_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x6001 Offcore demand data reads satisfied by any DRAM offcore_response.demand_data_rd.any_llc_miss umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF801 Offcore demand data reads that missed the LLC offcore_response.demand_data_rd.local_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4001 Offcore demand data reads satisfied by the local DRAM offcore_response.demand_data_rd.remote_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2001 Offcore demand data reads satisfied by a remote DRAM offcore_response.demand_ifetch.any_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x6004 Offcore demand code reads satisfied by any DRAM offcore_response.demand_ifetch.any_llc_miss umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF804 Offcore demand code reads that missed the LLC offcore_response.demand_ifetch.local_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4004 Offcore demand code reads satisfied by the local DRAM offcore_response.demand_ifetch.remote_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2004 Offcore demand code reads satisfied by a remote DRAM offcore_response.demand_rfo.any_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x6002 Offcore demand RFO requests satisfied by any DRAM offcore_response.demand_rfo.any_llc_miss umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF802 Offcore demand RFO requests that missed the LLC offcore_response.demand_rfo.local_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4002 Offcore demand RFO requests satisfied by the local DRAM offcore_response.demand_rfo.remote_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2002 Offcore demand RFO requests satisfied by a remote DRAM offcore_response.other.any_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x6080 Offcore other requests satisfied by any DRAM offcore_response.other.any_llc_miss umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF880 Offcore other requests that missed the LLC offcore_response.other.remote_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2080 Offcore other requests satisfied by a remote DRAM offcore_response.pf_data.any_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x6030 Offcore prefetch data requests satisfied by any DRAM offcore_response.pf_data.any_llc_miss umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF830 Offcore prefetch data requests that missed the LLC offcore_response.pf_data.local_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4030 Offcore prefetch data requests satisfied by the local DRAM offcore_response.pf_data.remote_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2030 Offcore prefetch data requests satisfied by a remote DRAM offcore_response.pf_data_rd.any_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x6010 Offcore prefetch data reads satisfied by any DRAM offcore_response.pf_data_rd.any_llc_miss umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF810 Offcore prefetch data reads that missed the LLC offcore_response.pf_data_rd.local_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4010 Offcore prefetch data reads satisfied by the local DRAM offcore_response.pf_data_rd.remote_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2010 Offcore prefetch data reads satisfied by a remote DRAM offcore_response.pf_ifetch.any_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x6040 Offcore prefetch code reads satisfied by any DRAM offcore_response.pf_ifetch.any_llc_miss umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF840 Offcore prefetch code reads that missed the LLC offcore_response.pf_ifetch.local_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4040 Offcore prefetch code reads satisfied by the local DRAM offcore_response.pf_ifetch.remote_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2040 Offcore prefetch code reads satisfied by a remote DRAM offcore_response.pf_rfo.any_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x6020 Offcore prefetch RFO requests satisfied by any DRAM offcore_response.pf_rfo.any_llc_miss umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF820 Offcore prefetch RFO requests that missed the LLC offcore_response.pf_rfo.local_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4020 Offcore prefetch RFO requests satisfied by the local DRAM offcore_response.pf_rfo.remote_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2020 Offcore prefetch RFO requests satisfied by a remote DRAM offcore_response.prefetch.any_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x6070 Offcore prefetch requests satisfied by any DRAM offcore_response.prefetch.any_llc_miss umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF870 Offcore prefetch requests that missed the LLC offcore_response.prefetch.local_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4070 Offcore prefetch requests satisfied by the local DRAM offcore_response.prefetch.remote_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2070 Offcore prefetch requests satisfied by a remote DRAM bpu_clears.early umask=0x1,period=2000000,event=0xe8 Early Branch Prediciton Unit clears bpu_clears.late umask=0x2,period=2000000,event=0xe8 Late Branch Prediction Unit clears bpu_missed_call_ret umask=0x1,period=2000000,event=0xe5 Branch prediction unit missed call or return es_reg_renames umask=0x1,period=2000000,event=0xd5 ES segment renames io_transactions umask=0x1,period=2000000,event=0x6c I/O transactions l1i.cycles_stalled umask=0x4,period=2000000,event=0x80 L1I instruction fetch stall cycles l1i.hits umask=0x1,period=2000000,event=0x80 L1I instruction fetch hits l1i.misses umask=0x2,period=2000000,event=0x80 L1I instruction fetch misses l1i.reads umask=0x3,period=2000000,event=0x80 L1I Instruction fetches large_itlb.hit Large ITLB hit load_dispatch.any umask=0x7,period=2000000,event=0x13 All loads dispatched load_dispatch.mob umask=0x4,period=2000000,event=0x13 Loads dispatched from the MOB load_dispatch.rs Loads dispatched that bypass the MOB load_dispatch.rs_delayed umask=0x2,period=2000000,event=0x13 Loads dispatched from stage 305 partial_address_alias umask=0x1,period=200000,event=0x7 False dependencies due to partial address aliasing rat_stalls.any umask=0xf,period=2000000,event=0xd2 All RAT stall cycles rat_stalls.flags umask=0x1,period=2000000,event=0xd2 Flag stall cycles rat_stalls.registers umask=0x2,period=2000000,event=0xd2 Partial register stall cycles rat_stalls.rob_read_port umask=0x4,period=2000000,event=0xd2 ROB read port stalls cycles rat_stalls.scoreboard umask=0x8,period=2000000,event=0xd2 Scoreboard stall cycles sb_drain.any umask=0x7,period=200000,event=0x4 All Store buffer stall cycles seg_rename_stalls umask=0x1,period=2000000,event=0xd4 Segment rename stall cycles snoop_response.hit umask=0x1,period=100000,event=0xb8 Thread responded HIT to snoop snoop_response.hite umask=0x2,period=100000,event=0xb8 Thread responded HITE to snoop snoop_response.hitm umask=0x4,period=100000,event=0xb8 Thread responded HITM to snoop sq_full_stall_cycles umask=0x1,period=2000000,event=0xf6 Super Queue full stall cycles arith.cycles_div_busy arith.div inv=1,umask=0x1,period=2000000,cmask=1,edge=1,event=0x14 Divide Operations executed arith.mul umask=0x2,period=2000000,event=0x14 baclear.bad_target umask=0x2,period=2000000,event=0xe6 BACLEAR asserted with bad target address baclear.clear BACLEAR asserted, regardless of cause baclear_force_iq umask=0x1,period=2000000,event=0xa7 Instruction queue forced BACLEAR br_inst_exec.any umask=0x7f,period=200000,event=0x88 Branch instructions executed br_inst_exec.cond umask=0x1,period=200000,event=0x88 Conditional branch instructions executed br_inst_exec.direct umask=0x2,period=200000,event=0x88 Unconditional branches executed br_inst_exec.direct_near_call umask=0x10,period=20000,event=0x88 Unconditional call branches executed br_inst_exec.indirect_near_call umask=0x20,period=20000,event=0x88 Indirect call branches executed br_inst_exec.indirect_non_call umask=0x4,period=20000,event=0x88 Indirect non call branches executed br_inst_exec.near_calls umask=0x30,period=20000,event=0x88 Call branches executed br_inst_exec.non_calls umask=0x7,period=200000,event=0x88 All non call branches executed br_inst_exec.return_near umask=0x8,period=20000,event=0x88 Indirect return branches executed br_inst_exec.taken umask=0x40,period=200000,event=0x88 Taken branches executed umask=0x4,period=200000,event=0xc4 Retired branch instructions (Precise Event) umask=0x1,period=200000,event=0xc4 Retired conditional branch instructions (Precise Event) umask=0x2,period=20000,event=0xc4 Retired near call instructions (Precise Event) br_misp_exec.any umask=0x7f,period=20000,event=0x89 Mispredicted branches executed br_misp_exec.cond umask=0x1,period=20000,event=0x89 Mispredicted conditional branches executed br_misp_exec.direct umask=0x2,period=20000,event=0x89 Mispredicted unconditional branches executed br_misp_exec.direct_near_call umask=0x10,period=2000,event=0x89 Mispredicted non call branches executed br_misp_exec.indirect_near_call umask=0x20,period=2000,event=0x89 Mispredicted indirect call branches executed br_misp_exec.indirect_non_call umask=0x4,period=2000,event=0x89 Mispredicted indirect non call branches executed br_misp_exec.near_calls umask=0x30,period=2000,event=0x89 Mispredicted call branches executed br_misp_exec.non_calls umask=0x7,period=20000,event=0x89 br_misp_exec.return_near umask=0x8,period=2000,event=0x89 Mispredicted return branches executed br_misp_exec.taken umask=0x40,period=20000,event=0x89 Mispredicted taken branches executed umask=0x2,period=2000,event=0xc5 Mispredicted near retired calls (Precise Event) Reference cycles when thread is not halted (fixed counter) cpu_clk_unhalted.ref_p umask=0x1,period=100000,event=0x3c Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter) Cycles when thread is not halted (fixed counter) Cycles when thread is not halted (programmable counter) cpu_clk_unhalted.total_cycles inv=1,umask=0x0,period=2000000,cmask=2,event=0x3c Total CPU cycles ild_stall.any umask=0xf,period=2000000,event=0x87 Any Instruction Length Decoder stall cycles umask=0x4,period=2000000,event=0x87 Instruction Queue full stall cycles Length Change Prefix stall cycles ild_stall.mru Stall cycles due to BPU MRU bypass ild_stall.regen umask=0x8,period=2000000,event=0x87 Regen stall cycles inst_decoded.dec0 umask=0x1,period=2000000,event=0x18 Instructions that must be decoded by decoder 0 inst_queue_write_cycles umask=0x1,period=2000000,event=0x1e Cycles instructions are written to the instruction queue inst_queue_writes umask=0x1,period=2000000,event=0x17 Instructions written to instruction queue Instructions retired (fixed counter) Instructions retired (Programmable counter and Precise Event) (Precise event) inst_retired.mmx umask=0x4,period=2000000,event=0xc0 Retired MMX instructions (Precise Event) inst_retired.total_cycles inv=1,umask=0x1,period=2000000,cmask=16,event=0xc0 Total cycles (Precise Event) umask=0x2,period=2000000,event=0xc0 Retired floating-point operations (Precise Event) load_hit_pre umask=0x1,period=200000,event=0x4c Load operations conflicting with software prefetches lsd.active umask=0x1,period=2000000,cmask=1,event=0xa8 Cycles when uops were delivered by the LSD lsd.inactive inv=1,umask=0x1,period=2000000,cmask=1,event=0xa8 Cycles no uops were delivered by the LSD lsd_overflow umask=0x1,period=2000000,event=0x20 Loops that can't stream from the instruction queue umask=0x1,period=20000,event=0xc3 Cycles machine clear asserted machine_clears.mem_order umask=0x2,period=20000,event=0xc3 Execution pipeline restart due to Memory ordering conflicts umask=0x4,period=20000,event=0xc3 umask=0x1,period=2000000,event=0xa2 Resource related stall cycles resource_stalls.fpcw umask=0x20,period=2000000,event=0xa2 FPU control word write stall cycles resource_stalls.load umask=0x2,period=2000000,event=0xa2 Load buffer stall cycles resource_stalls.mxcsr umask=0x40,period=2000000,event=0xa2 MXCSR rename stall cycles resource_stalls.other umask=0x80,period=2000000,event=0xa2 Other Resource related stall cycles resource_stalls.rob_full umask=0x10,period=2000000,event=0xa2 ROB full stall cycles resource_stalls.rs_full umask=0x4,period=2000000,event=0xa2 Reservation Station full stall cycles resource_stalls.store umask=0x8,period=2000000,event=0xa2 Store buffer stall cycles ssex_uops_retired.packed_double umask=0x4,period=200000,event=0xc7 SIMD Packed-Double Uops retired (Precise Event) ssex_uops_retired.packed_single umask=0x1,period=200000,event=0xc7 SIMD Packed-Single Uops retired (Precise Event) ssex_uops_retired.scalar_double umask=0x8,period=200000,event=0xc7 SIMD Scalar-Double Uops retired (Precise Event) ssex_uops_retired.scalar_single umask=0x2,period=200000,event=0xc7 SIMD Scalar-Single Uops retired (Precise Event) ssex_uops_retired.vector_integer umask=0x10,period=200000,event=0xc7 SIMD Vector Integer Uops retired (Precise Event) uop_unfusion umask=0x1,period=2000000,event=0xdb Uop unfusions due to FP exceptions uops_decoded.esp_folding umask=0x4,period=2000000,event=0xd1 Stack pointer instructions decoded uops_decoded.esp_sync umask=0x8,period=2000000,event=0xd1 Stack pointer sync operations uops_decoded.ms_cycles_active umask=0x2,period=2000000,cmask=1,event=0xd1 Uops decoded by Microcode Sequencer uops_decoded.stall_cycles inv=1,umask=0x1,period=2000000,cmask=1,event=0xd1 Cycles no Uops are decoded uops_executed.core_active_cycles umask=0x3f,any=1,period=2000000,cmask=1,event=0xb1 Cycles Uops executed on any port (core count) uops_executed.core_active_cycles_no_port5 umask=0x1f,any=1,period=2000000,cmask=1,event=0xb1 Cycles Uops executed on ports 0-4 (core count) uops_executed.core_stall_count inv=1,umask=0x3f,any=1,period=2000000,cmask=1,edge=1,event=0xb1 Uops executed on any port (core count) uops_executed.core_stall_count_no_port5 inv=1,umask=0x1f,any=1,period=2000000,cmask=1,edge=1,event=0xb1 Uops executed on ports 0-4 (core count) uops_executed.core_stall_cycles inv=1,umask=0x3f,any=1,period=2000000,cmask=1,event=0xb1 Cycles no Uops issued on any port (core count) uops_executed.core_stall_cycles_no_port5 inv=1,umask=0x1f,any=1,period=2000000,cmask=1,event=0xb1 Cycles no Uops issued on ports 0-4 (core count) uops_executed.port0 umask=0x1,period=2000000,event=0xb1 Uops executed on port 0 uops_executed.port015 umask=0x40,period=2000000,event=0xb1 Uops issued on ports 0, 1 or 5 uops_executed.port015_stall_cycles inv=1,umask=0x40,period=2000000,cmask=1,event=0xb1 Cycles no Uops issued on ports 0, 1 or 5 uops_executed.port1 umask=0x2,period=2000000,event=0xb1 Uops executed on port 1 uops_executed.port2_core umask=0x4,any=1,period=2000000,event=0xb1 Uops executed on port 2 (core count) uops_executed.port234_core umask=0x80,any=1,period=2000000,event=0xb1 Uops issued on ports 2, 3 or 4 uops_executed.port3_core umask=0x8,any=1,period=2000000,event=0xb1 Uops executed on port 3 (core count) uops_executed.port4_core umask=0x10,any=1,period=2000000,event=0xb1 Uops executed on port 4 (core count) uops_executed.port5 umask=0x20,period=2000000,event=0xb1 Uops executed on port 5 umask=0x1,period=2000000,event=0xe Uops issued inv=1,umask=0x1,any=1,period=2000000,cmask=1,event=0xe Cycles no Uops were issued on any thread uops_issued.cycles_all_threads umask=0x1,any=1,period=2000000,cmask=1,event=0xe Cycles Uops were issued on either thread uops_issued.fused umask=0x2,period=2000000,event=0xe Fused Uops issued inv=1,umask=0x1,period=2000000,cmask=1,event=0xe Cycles no Uops were issued uops_retired.active_cycles umask=0x1,period=2000000,cmask=1,event=0xc2 Cycles Uops are being retired (Precise event) umask=0x1,period=2000000,event=0xc2 Uops retired (Precise Event) uops_retired.macro_fused umask=0x4,period=2000000,event=0xc2 Macro-fused Uops retired (Precise Event) umask=0x2,period=2000000,event=0xc2 Retirement slots used (Precise Event) inv=1,umask=0x1,period=2000000,cmask=1,event=0xc2 Cycles Uops are not retiring (Precise Event) inv=1,umask=0x1,period=2000000,cmask=16,event=0xc2 Total cycles using precise uop retired event (Precise Event) inst_retired.total_cycles_ps dtlb_load_misses.any umask=0x1,period=200000,event=0x8 DTLB load misses dtlb_load_misses.pde_miss umask=0x20,period=200000,event=0x8 DTLB load miss caused by low part of address umask=0x10,period=2000000,event=0x8 DTLB second level hit umask=0x2,period=200000,event=0x8 DTLB load miss page walks complete dtlb_misses.any umask=0x1,period=200000,event=0x49 DTLB misses dtlb_misses.stlb_hit umask=0x10,period=200000,event=0x49 DTLB first level misses but second level hit dtlb_misses.walk_completed umask=0x2,period=200000,event=0x49 DTLB miss page walks itlb_flush umask=0x1,period=2000000,event=0xae itlb_miss_retired umask=0x20,period=200000,event=0xc8 Retired instructions that missed the ITLB (Precise Event) itlb_misses.any umask=0x1,period=200000,event=0x85 ITLB miss umask=0x2,period=200000,event=0x85 ITLB miss page walks umask=0x80,period=200000,event=0xcb Retired loads that miss the DTLB (Precise Event) mem_store_retired.dtlb_miss Retired stores that miss the DTLB (Precise Event) Counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted Counts the RFO (Read-for-Ownership) requests that miss L2 cache Counts L2 cache misses when fetching instructions umask=0x38,period=200003,event=0x24 Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache Counts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache Counts the RFO (Read-for-Ownership) requests that hit L2 cache Counts L2 cache hits when fetching instructions, code reads umask=0xd8,period=200003,event=0x24 Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache Counts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache Counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches Counts the total number of L2 code requests Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches Counts the total number of requests from the L2 hardware prefetchers Core-originated cacheable demand requests missed L3 Spec update: SKL057 Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches from L1 and L2. It does not include all misses to the L3 Spec update: SKL057 Core-originated cacheable demand requests that refer to L3 Spec update: SKL057 Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches from L1 and L2. It does not include all accesses to the L3 Spec update: SKL057 L1D miss outstandings duration in cycles Counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch.Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type Counts duration of L1D miss outstanding in cycles Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch Number of times a request needed a FB (Fill Buffer) entry but there was no entry available for it. A request includes cacheable/uncacheable demands that are load, store or SW prefetch instructions Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace Counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.Note: A prefetch promoted to Demand is counted from the promotion point Counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation) Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore Counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore Counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS Counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS Counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore Counts both cacheable and non-cacheable code read requests Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type offcore_requests.all_requests umask=0x80,period=100003,event=0xb0 Any memory transaction that reached the SQ Counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, etc. Counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.Note: Writeback pending FIFO has six entries mem_inst_retired.stlb_miss_loads Retired load instructions that miss the STLB. (Precise Event) Supports address when precise Retired load instructions that miss the STLB Supports address when precise mem_inst_retired.stlb_miss_stores Retired store instructions that miss the STLB. (Precise Event) Supports address when precise Retired store instructions that miss the STLB Supports address when precise mem_inst_retired.lock_loads Retired load instructions with locked access. (Precise Event) Supports address when precise mem_inst_retired.split_loads Retired load instructions that split across a cacheline boundary. (Precise Event) Supports address when precise mem_inst_retired.split_stores Retired store instructions that split across a cacheline boundary. (Precise Event) Supports address when precise mem_inst_retired.all_loads All retired load instructions. (Precise Event) Supports address when precise mem_inst_retired.all_stores All retired store instructions. (Precise Event) Supports address when precise All retired store instructions Supports address when precise mem_load_retired.l1_hit Retired load instructions with L1 cache hits as data sources Supports address when precise (Precise event) Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source Supports address when precise (Precise event) Retired load instructions with L2 cache hits as data sources Supports address when precise (Precise event) mem_load_retired.l3_hit Retired load instructions with L3 cache hits as data sources Supports address when precise (Precise event) mem_load_retired.l1_miss Retired load instructions missed L1 cache as data sources Supports address when precise (Precise event) Counts retired load instructions with at least one uop that missed in the L1 cache Supports address when precise (Precise event) Retired load instructions missed L2 cache as data sources Supports address when precise (Precise event) mem_load_retired.l3_miss Retired load instructions missed L3 cache as data sources Supports address when precise (Precise event) mem_load_retired.fb_hit umask=0x40,period=100007,event=0xd1 Retired load instructions which data sources were load missed L1 but hit FB due to preceding miss to the same cache line with data not ready Supports address when precise (Precise event) Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready Supports address when precise (Precise event) mem_load_l3_hit_retired.xsnp_miss Retired load instructions which data sources were L3 hit and cross-core snoop missed in on-pkg core cache Supports address when precise (Precise event) mem_load_l3_hit_retired.xsnp_hit Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core cache Supports address when precise (Precise event) mem_load_l3_hit_retired.xsnp_hitm Retired load instructions which data sources were HitM responses from shared L3 Supports address when precise (Precise event) mem_load_l3_hit_retired.xsnp_none Retired load instructions which data sources were hits in L3 without snoops required Supports address when precise (Precise event) mem_load_misc_retired.uc umask=0x4,period=100007,event=0xd4 Retired instructions with at least 1 uncacheable load or lock Supports address when precise (Precise event) Counts L2 writebacks that access L2 cache umask=0x1f,period=100003,event=0xf1 Counts the number of L2 cache lines filling the L2. Counting does not cover rejects l2_lines_out.silent umask=0x1,period=200003,event=0xf2 Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event l2_lines_out.non_silent umask=0x2,period=200003,event=0xf2 Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3 l2_lines_out.useless_pref umask=0x4,period=200003,event=0xf2 This event is deprecated. Refer to new event L2_LINES_OUT.USELESS_HWPF l2_lines_out.useless_hwpf Counts the number of lines that have been hardware prefetched but not used and now evicted by L2 cache Number of cache line split locks sent to uncore Counts the number of cache line split locks sent to the uncore offcore_response.other.l4_hit_local_l4.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0408000 offcore_response.other.l4_hit_local_l4.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000408000 offcore_response.other.l4_hit_local_l4.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400408000 offcore_response.other.l4_hit_local_l4.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200408000 offcore_response.other.l4_hit_local_l4.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100408000 offcore_response.other.l4_hit_local_l4.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080408000 offcore_response.other.l4_hit_local_l4.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040408000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC01C8000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10001C8000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04001C8000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02001C8000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01001C8000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00801C8000 offcore_response.other.l3_hit.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00401C8000 offcore_response.other.l3_hit_s.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0108000 offcore_response.other.l3_hit_s.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000108000 offcore_response.other.l3_hit_s.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400108000 offcore_response.other.l3_hit_s.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200108000 offcore_response.other.l3_hit_s.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100108000 offcore_response.other.l3_hit_s.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080108000 offcore_response.other.l3_hit_s.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040108000 offcore_response.other.l3_hit_e.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0088000 offcore_response.other.l3_hit_e.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000088000 offcore_response.other.l3_hit_e.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400088000 offcore_response.other.l3_hit_e.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200088000 offcore_response.other.l3_hit_e.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100088000 offcore_response.other.l3_hit_e.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080088000 offcore_response.other.l3_hit_e.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040088000 offcore_response.other.l3_hit_m.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0048000 offcore_response.other.l3_hit_m.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000048000 offcore_response.other.l3_hit_m.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400048000 offcore_response.other.l3_hit_m.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200048000 offcore_response.other.l3_hit_m.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100048000 offcore_response.other.l3_hit_m.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080048000 offcore_response.other.l3_hit_m.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040048000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0028000 offcore_response.other.supplier_none.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040028000 offcore_response.demand_code_rd.l4_hit_local_l4.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0400004 Counts demand instruction fetches and L1 instruction cache prefetches that offcore_response.demand_code_rd.l4_hit_local_l4.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000400004 offcore_response.demand_code_rd.l4_hit_local_l4.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400400004 offcore_response.demand_code_rd.l4_hit_local_l4.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200400004 offcore_response.demand_code_rd.l4_hit_local_l4.snoop_not_needed offcore_response.demand_code_rd.l4_hit_local_l4.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080400004 offcore_response.demand_code_rd.l4_hit_local_l4.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040400004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC01C0004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10001C0004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04001C0004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02001C0004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01001C0004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00801C0004 offcore_response.demand_code_rd.l3_hit.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00401C0004 offcore_response.demand_code_rd.l3_hit_s.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0100004 offcore_response.demand_code_rd.l3_hit_s.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000100004 offcore_response.demand_code_rd.l3_hit_s.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400100004 offcore_response.demand_code_rd.l3_hit_s.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200100004 offcore_response.demand_code_rd.l3_hit_s.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100100004 offcore_response.demand_code_rd.l3_hit_s.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080100004 offcore_response.demand_code_rd.l3_hit_s.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040100004 offcore_response.demand_code_rd.l3_hit_e.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0080004 offcore_response.demand_code_rd.l3_hit_e.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000080004 offcore_response.demand_code_rd.l3_hit_e.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400080004 offcore_response.demand_code_rd.l3_hit_e.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200080004 offcore_response.demand_code_rd.l3_hit_e.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100080004 offcore_response.demand_code_rd.l3_hit_e.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080080004 offcore_response.demand_code_rd.l3_hit_e.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040080004 offcore_response.demand_code_rd.l3_hit_m.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0040004 offcore_response.demand_code_rd.l3_hit_m.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000040004 offcore_response.demand_code_rd.l3_hit_m.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400040004 offcore_response.demand_code_rd.l3_hit_m.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200040004 offcore_response.demand_code_rd.l3_hit_m.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100040004 offcore_response.demand_code_rd.l3_hit_m.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080040004 offcore_response.demand_code_rd.l3_hit_m.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040040004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0020004 offcore_response.demand_code_rd.supplier_none.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040020004 Counts demand instruction fetches and L1 instruction cache prefetches that have any response type offcore_response.demand_rfo.l4_hit_local_l4.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0400002 offcore_response.demand_rfo.l4_hit_local_l4.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000400002 offcore_response.demand_rfo.l4_hit_local_l4.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400400002 offcore_response.demand_rfo.l4_hit_local_l4.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200400002 offcore_response.demand_rfo.l4_hit_local_l4.snoop_not_needed offcore_response.demand_rfo.l4_hit_local_l4.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080400002 offcore_response.demand_rfo.l4_hit_local_l4.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040400002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC01C0002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10001C0002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04001C0002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02001C0002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01001C0002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00801C0002 offcore_response.demand_rfo.l3_hit.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00401C0002 offcore_response.demand_rfo.l3_hit_s.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0100002 offcore_response.demand_rfo.l3_hit_s.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000100002 offcore_response.demand_rfo.l3_hit_s.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400100002 offcore_response.demand_rfo.l3_hit_s.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200100002 offcore_response.demand_rfo.l3_hit_s.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100100002 offcore_response.demand_rfo.l3_hit_s.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080100002 offcore_response.demand_rfo.l3_hit_s.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040100002 offcore_response.demand_rfo.l3_hit_e.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0080002 offcore_response.demand_rfo.l3_hit_e.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000080002 offcore_response.demand_rfo.l3_hit_e.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400080002 offcore_response.demand_rfo.l3_hit_e.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200080002 offcore_response.demand_rfo.l3_hit_e.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100080002 offcore_response.demand_rfo.l3_hit_e.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080080002 offcore_response.demand_rfo.l3_hit_e.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040080002 offcore_response.demand_rfo.l3_hit_m.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0040002 offcore_response.demand_rfo.l3_hit_m.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000040002 offcore_response.demand_rfo.l3_hit_m.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400040002 offcore_response.demand_rfo.l3_hit_m.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200040002 offcore_response.demand_rfo.l3_hit_m.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100040002 offcore_response.demand_rfo.l3_hit_m.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080040002 offcore_response.demand_rfo.l3_hit_m.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040040002 offcore_response.demand_rfo.supplier_none.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0020002 offcore_response.demand_rfo.supplier_none.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020002 offcore_response.demand_rfo.supplier_none.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020002 offcore_response.demand_rfo.supplier_none.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020002 offcore_response.demand_rfo.supplier_none.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020002 offcore_response.demand_rfo.supplier_none.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020002 offcore_response.demand_rfo.supplier_none.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040020002 offcore_response.demand_data_rd.l4_hit_local_l4.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0400001 offcore_response.demand_data_rd.l4_hit_local_l4.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000400001 offcore_response.demand_data_rd.l4_hit_local_l4.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400400001 offcore_response.demand_data_rd.l4_hit_local_l4.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200400001 offcore_response.demand_data_rd.l4_hit_local_l4.snoop_not_needed offcore_response.demand_data_rd.l4_hit_local_l4.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080400001 offcore_response.demand_data_rd.l4_hit_local_l4.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040400001 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC01C0001 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10001C0001 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04001C0001 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02001C0001 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01001C0001 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00801C0001 offcore_response.demand_data_rd.l3_hit.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00401C0001 offcore_response.demand_data_rd.l3_hit_s.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0100001 offcore_response.demand_data_rd.l3_hit_s.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000100001 offcore_response.demand_data_rd.l3_hit_s.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400100001 offcore_response.demand_data_rd.l3_hit_s.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200100001 offcore_response.demand_data_rd.l3_hit_s.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100100001 offcore_response.demand_data_rd.l3_hit_s.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080100001 offcore_response.demand_data_rd.l3_hit_s.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040100001 offcore_response.demand_data_rd.l3_hit_e.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0080001 offcore_response.demand_data_rd.l3_hit_e.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000080001 offcore_response.demand_data_rd.l3_hit_e.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400080001 offcore_response.demand_data_rd.l3_hit_e.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200080001 offcore_response.demand_data_rd.l3_hit_e.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100080001 offcore_response.demand_data_rd.l3_hit_e.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080080001 offcore_response.demand_data_rd.l3_hit_e.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040080001 offcore_response.demand_data_rd.l3_hit_m.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0040001 offcore_response.demand_data_rd.l3_hit_m.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000040001 offcore_response.demand_data_rd.l3_hit_m.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400040001 offcore_response.demand_data_rd.l3_hit_m.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200040001 offcore_response.demand_data_rd.l3_hit_m.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100040001 offcore_response.demand_data_rd.l3_hit_m.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080040001 offcore_response.demand_data_rd.l3_hit_m.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040040001 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0020001 offcore_response.demand_data_rd.supplier_none.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040020001 Counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1 Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB) Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ Counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ Counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ Counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ Counts the number of cycles 4 uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. Counting includes uops that may 'bypass' the IDQ. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB) Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. Counting includes uops that may 'bypass' the IDQ. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB) Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS icache_16b.ifdata_stall Cycles where a code fetch is stalled due to L1 instruction cache miss Cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity icache_64b.iftag_hit umask=0x1,period=200003,event=0x83 Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity icache_64b.iftag_miss umask=0x2,period=200003,event=0x83 Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity icache_64b.iftag_stall umask=0x4,period=200003,event=0x83 Cycles where a code fetch is stalled due to L1 instruction cache tag miss Counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding “4 – x” when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread. b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions). c. Instruction Decode Queue (IDQ) delivers four uops Counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4 Counts, on the per-thread basis, cycles when less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >= 3 Cycles with less than 2 uops delivered by the front-end Cycles with less than 3 uops delivered by the front-end Counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 0–2 cycles frontend_retired.dsb_miss umask=0x1,period=100007,event=0xc6,frontend=0x11 Retired Instructions who experienced decode stream buffer (DSB - the decoded instruction-cache) miss. Precise Event (Precise event) Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss (Precise event) frontend_retired.l1i_miss umask=0x1,period=100007,event=0xc6,frontend=0x12 Retired Instructions who experienced Instruction L1 Cache true miss. Precise Event (Precise event) frontend_retired.l2_miss umask=0x1,period=100007,event=0xc6,frontend=0x13 Retired Instructions who experienced Instruction L2 Cache true miss. Precise Event (Precise event) frontend_retired.itlb_miss umask=0x1,period=100007,event=0xc6,frontend=0x14 Retired Instructions who experienced iTLB true miss. Precise Event (Precise event) Counts retired Instructions that experienced iTLB (Instruction TLB) true miss (Precise event) frontend_retired.stlb_miss umask=0x1,period=100007,event=0xc6,frontend=0x15 Retired Instructions who experienced STLB (2nd level TLB) true miss. Precise Event (Precise event) Counts retired Instructions that experienced STLB (2nd level TLB) true miss (Precise event) frontend_retired.latency_ge_2 umask=0x1,period=100007,event=0xc6,frontend=0x400206 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall. Precise Event (Precise event) frontend_retired.latency_ge_2_bubbles_ge_2 umask=0x1,period=100007,event=0xc6,frontend=0x200206 Retired instructions that are fetched after an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall. Precise Event (Precise event) frontend_retired.latency_ge_4 umask=0x1,period=100007,event=0xc6,frontend=0x400406 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall. Precise Event (Precise event) frontend_retired.latency_ge_8 umask=0x1,period=100007,event=0xc6,frontend=0x400806 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall (Precise event) Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops (Precise event) frontend_retired.latency_ge_16 umask=0x1,period=100007,event=0xc6,frontend=0x401006 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall. Precise Event (Precise event) Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops (Precise event) frontend_retired.latency_ge_32 umask=0x1,period=100007,event=0xc6,frontend=0x402006 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall. Precise Event (Precise event) Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops (Precise event) frontend_retired.latency_ge_64 umask=0x1,period=100007,event=0xc6,frontend=0x404006 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall. Precise Event (Precise event) frontend_retired.latency_ge_128 umask=0x1,period=100007,event=0xc6,frontend=0x408006 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall. Precise Event (Precise event) frontend_retired.latency_ge_256 umask=0x1,period=100007,event=0xc6,frontend=0x410006 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall. Precise Event (Precise event) frontend_retired.latency_ge_512 umask=0x1,period=100007,event=0xc6,frontend=0x420006 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall. Precise Event (Precise event) frontend_retired.latency_ge_2_bubbles_ge_1 umask=0x1,period=100007,event=0xc6,frontend=0x100206 Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall. Precise Event (Precise event) Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall (Precise event) frontend_retired.latency_ge_2_bubbles_ge_3 umask=0x1,period=100007,event=0xc6,frontend=0x300206 Retired instructions that are fetched after an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall. Precise Event (Precise event) tx_mem.abort_capacity Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes Unfriendly TSX abort triggered by a vzeroupper instruction offcore_requests_outstanding.l3_miss_demand_data_rd umask=0x10,period=2000003,event=0x60 Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle offcore_requests_outstanding.cycles_with_l3_miss_demand_data_rd umask=0x10,period=2000003,cmask=1,event=0x60 Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ offcore_requests_outstanding.l3_miss_demand_data_rd_ge_6 umask=0x10,period=2000003,cmask=6,event=0x60 Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ cycle_activity.cycles_l3_miss Cycles while L3 cache miss demand load is outstanding cycle_activity.stalls_l3_miss Execution stalls while L3 cache miss demand load is outstanding offcore_requests.l3_miss_demand_data_rd umask=0x10,period=100003,event=0xb0 Demand Data Read requests who miss L3 cache Counts the number of machine clears due to memory order conflicts Spec update: SKL089 Counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:a. memory disambiguation,b. external snoop, orc. cross SMT-HW-thread snoop (stores) hitting load buffer Spec update: SKL089 Number of times we entered an HLE region. Does not count nested transactions Number of times HLE abort was triggered. (PEBS) (Precise event) hle_retired.aborted_mem hle_retired.aborted_timer Number of times an HLE execution aborted due to hardware timer expiration hle_retired.aborted_unfriendly Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.) hle_retired.aborted_memtype hle_retired.aborted_events Number of times an HLE execution aborted due to unfriendly events (such as interrupts) Number of times we entered an RTM region. Does not count nested transactions Number of times RTM abort was triggered. (PEBS) (Precise event) rtm_retired.aborted_mem rtm_retired.aborted_timer Number of times an RTM execution aborted due to uncommon conditions rtm_retired.aborted_unfriendly rtm_retired.aborted_memtype rtm_retired.aborted_events Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles (Must be precise) Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency (Must be precise) Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles (Must be precise) Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency (Must be precise) Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles (Must be precise) Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency (Must be precise) Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles (Must be precise) Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency (Must be precise) Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles (Must be precise) Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency (Must be precise) Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles (Must be precise) Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency (Must be precise) Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles (Must be precise) Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency (Must be precise) Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles (Must be precise) Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency (Must be precise) offcore_response.other.l3_miss.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFC408000 offcore_response.other.l3_miss.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x203C408000 offcore_response.other.l3_miss.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x103C408000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C408000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C408000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C408000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC408000 offcore_response.other.l3_miss.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x007C408000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC4008000 offcore_response.other.l3_miss_local_dram.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0044008000 offcore_response.other.l4_hit_local_l4.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000408000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20001C8000 offcore_response.other.l3_hit_s.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000108000 offcore_response.other.l3_hit_e.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000088000 offcore_response.other.l3_hit_m.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000048000 offcore_response.demand_code_rd.l3_miss.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFC400004 offcore_response.demand_code_rd.l3_miss.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x203C400004 offcore_response.demand_code_rd.l3_miss.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x103C400004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C400004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C400004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C400004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC400004 offcore_response.demand_code_rd.l3_miss.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x007C400004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC4000004 offcore_response.demand_code_rd.l3_miss_local_dram.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0044000004 offcore_response.demand_code_rd.l4_hit_local_l4.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000400004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20001C0004 offcore_response.demand_code_rd.l3_hit_s.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000100004 offcore_response.demand_code_rd.l3_hit_e.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000080004 offcore_response.demand_code_rd.l3_hit_m.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000040004 offcore_response.demand_rfo.l3_miss.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFC400002 offcore_response.demand_rfo.l3_miss.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x203C400002 offcore_response.demand_rfo.l3_miss.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x103C400002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C400002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C400002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C400002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC400002 offcore_response.demand_rfo.l3_miss.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x007C400002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC4000002 offcore_response.demand_rfo.l3_miss_local_dram.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000002 offcore_response.demand_rfo.l3_miss_local_dram.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000002 offcore_response.demand_rfo.l3_miss_local_dram.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000002 offcore_response.demand_rfo.l3_miss_local_dram.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000002 offcore_response.demand_rfo.l3_miss_local_dram.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000002 offcore_response.demand_rfo.l3_miss_local_dram.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000002 offcore_response.demand_rfo.l3_miss_local_dram.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0044000002 offcore_response.demand_rfo.l4_hit_local_l4.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000400002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20001C0002 offcore_response.demand_rfo.l3_hit_s.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000100002 offcore_response.demand_rfo.l3_hit_e.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000080002 offcore_response.demand_rfo.l3_hit_m.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000040002 offcore_response.demand_rfo.supplier_none.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020002 offcore_response.demand_data_rd.l3_miss.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFC400001 offcore_response.demand_data_rd.l3_miss.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x203C400001 offcore_response.demand_data_rd.l3_miss.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x103C400001 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C400001 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C400001 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C400001 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC400001 offcore_response.demand_data_rd.l3_miss.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x007C400001 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC4000001 offcore_response.demand_data_rd.l3_miss_local_dram.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0044000001 offcore_response.demand_data_rd.l4_hit_local_l4.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000400001 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20001C0001 offcore_response.demand_data_rd.l3_hit_s.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000100001 offcore_response.demand_data_rd.l3_hit_e.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000080001 offcore_response.demand_data_rd.l3_hit_m.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000040001 sw_prefetch_access.nta umask=0x1,period=2000003,event=0x32 Number of PREFETCHNTA instructions executed sw_prefetch_access.t0 umask=0x2,period=2000003,event=0x32 Number of PREFETCHT0 instructions executed sw_prefetch_access.t1_t2 umask=0x4,period=2000003,event=0x32 Number of PREFETCHT1 or PREFETCHT2 instructions executed sw_prefetch_access.prefetchw umask=0x8,period=2000003,event=0x32 Number of PREFETCHW instructions executed Number of hardware interrupts received by the processor Counts the number of hardware interruptions received by the processor Counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, Counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case Loads blocked by overlapping with store buffer that cannot be forwarded Counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when:a. preceding store conflicts with the load (incomplete overlap),b. store forwarding is impossible due to u-arch limitations,c. preceding lock RMW operations are not forwarded,d. store has the no-forward bit set (uncacheable/page-split/masked stores),e. all-blocking stores are used (mostly, fences and port I/O), and others.The most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events. See the table of not supported store forwards in the Optimization Guide Counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased umask=0x1,period=2000003,event=0xd Core cycles the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event umask=0x1,any=1,period=2000003,event=0xd int_misc.clear_resteer_cycles umask=0x80,period=2000003,event=0xd Cycles the issue-stage is waiting for front-end to fetch from resteered path following branch misprediction or machine clear events Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS) Counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread uops_issued.vector_width_mismatch umask=0x2,period=2000003,event=0xe Uops inserted at issue-stage in order to preserve upper bits of vector registers Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to “Mixing Intel AVX and Intel SSE Code” section of the Optimization Guide arith.divider_active umask=0x1,period=2000003,cmask=1,event=0x14 Cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations cpu_clk_unhalted.ring0_trans umask=0x0,edge=1,period=100007,cmask=1,event=0x3c Counts when there is a transition from ring 1, 2 or 3 to ring 0 Counts when the Current Privilege Level (CPL) transitions from ring 1, 2 or 3 to ring 0 (Kernel) umask=0x1,period=2503,event=0x3c Core crystal clock cycles when the thread is unhalted umask=0x1,any=1,period=2503,event=0x3c Core crystal clock cycles when at least one thread on the physical core is unhalted Core crystal clock cycles when this thread is unhalted and the other thread is halted umask=0x2,period=2503,event=0x3c Demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions partial_rat_stalls.scoreboard umask=0x1,period=2000003,event=0x59 Cycles where the pipeline is stalled due to serializing operations This event counts cycles during which the microcode scoreboard stalls happen Counts cycles during which the reservation station (RS) is empty for the thread.; Note: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate front-end Latency Bound issues Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 2 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 3 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 4 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 7 Counts resource-related stall cycles Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end umask=0x10,period=2000003,cmask=16,event=0xa3 umask=0x14,period=2000003,cmask=20,event=0xa3 exe_activity.exe_bound_0_ports umask=0x1,period=2000003,event=0xa6 Cycles where no uops were executed, the Reservation Station was not empty, the Store Buffer was full and there was no outstanding load Counts cycles during which no uops were executed on all ports and Reservation Station (RS) was not empty exe_activity.1_ports_util umask=0x2,period=2000003,event=0xa6 Cycles total of 1 uop is executed on all ports and Reservation Station was not empty Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty exe_activity.2_ports_util umask=0x4,period=2000003,event=0xa6 Cycles total of 2 uops are executed on all ports and Reservation Station was not empty Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty exe_activity.3_ports_util umask=0x8,period=2000003,event=0xa6 Cycles total of 3 uops are executed on all ports and Reservation Station was not empty Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty exe_activity.4_ports_util umask=0x10,period=2000003,event=0xa6 Cycles total of 4 uops are executed on all ports and Reservation Station was not empty Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty exe_activity.bound_on_stores umask=0x40,period=2000003,event=0xa6 Cycles where the Store Buffer was full and no outstanding load Number of uops delivered to the back-end by the LSD(Loop Stream Detector) Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector) Counts the cycles when 4 uops are delivered by the LSD (Loop-stream detector) Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread inv=1,umask=0x2,period=2000003,cmask=1,event=0xb1 uops_executed.x87 umask=0x10,period=2000003,event=0xb1 Counts the number of x87 uops dispatched Counts the number of x87 uops executed Number of instructions retired. General Counter - architectural event Spec update: SKL091, SKL044 Counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two) Spec update: SKL091, SKL044 Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution Spec update: SKL091, SKL044 (Must be precise) A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled Spec update: SKL091, SKL044 (Must be precise) inv=1,umask=0x1,period=2000003,cmask=10,event=0xc0 Number of cycles using always true condition applied to PEBS instructions retired event Spec update: SKL091, SKL044 (Must be precise) Number of cycles using an always true condition applied to PEBS instructions retired event. (inst_ret< 16) Spec update: SKL091, SKL044 (Must be precise) other_assists.any umask=0x3f,period=100003,event=0xc1 Number of times a microcode assist is invoked by HW other than FP-assist. Examples include AD (page Access Dirty) and AVX* related assists Retirement slots used Counts the retirement slots used inv=1,umask=0x2,period=2000003,cmask=1,event=0xc2 inv=1,umask=0x2,period=2000003,cmask=10,event=0xc2 Counts self-modifying code (SMC) detected, which causes a machine clear All (macro) branch instructions retired Spec update: SKL091 Counts all (macro) branch instructions retired Spec update: SKL091 Conditional branch instructions retired Spec update: SKL091 (Precise event) This is a precise version (that is, uses PEBS) of the event that counts conditional branch instructions retired Spec update: SKL091 (Precise event) Direct and indirect near call instructions retired Spec update: SKL091 (Precise event) This is a precise version (that is, uses PEBS) of the event that counts both direct and indirect near call instructions retired Spec update: SKL091 (Precise event) All (macro) branch instructions retired Spec update: SKL091 (Must be precise) This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired Spec update: SKL091 (Must be precise) Return instructions retired Spec update: SKL091 (Precise event) This is a precise version (that is, uses PEBS) of the event that counts return instructions retired Spec update: SKL091 (Precise event) Counts all not taken macro branch instructions retired Spec update: SKL091 (Precise event) This is a precise version (that is, uses PEBS) of the event that counts not taken branch instructions retired Spec update: SKL091 (Precise event) Taken branch instructions retired Spec update: SKL091 (Precise event) This is a precise version (that is, uses PEBS) of the event that counts taken branch instructions retired Spec update: SKL091 (Precise event) Counts the number of far branch instructions retired Spec update: SKL091 (Precise event) This is a precise version (that is, uses PEBS) of the event that counts far branch instructions retired Spec update: SKL091 (Precise event) Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path umask=0x2,period=400009,event=0xc5 Mispredicted direct and indirect near call instructions retired (Precise event) This event counts both taken and not taken retired mispredicted direct and indirect near calls, including both register and memory indirect (Precise event) Increments whenever there is an update to the LBR array Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT rob_misc_events.pause_inst umask=0x40,period=2000003,event=0xcc Number of retired PAUSE instructions (that do not end up with a VMExit to the VMM; TSX aborted Instructions may be counted). This event is not supported on first SKL and KBL products umask=0x1,period=100003,event=0xe6 Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore skl metrics min( 1 , uops_issued.any / ( (uops_retired.retire_slots / inst_retired.any) * 64 * ( icache_64b.iftag_hit + icache_64b.iftag_miss ) / 4.1 ) ) idq.dsb_uops / (idq.dsb_uops + idq.mite_uops + idq.ms_uops) inst_retired.any / mem_inst_retired.all_loads inst_retired.any / mem_inst_retired.all_stores uops_executed.thread / (( uops_executed.core_cycles_ge_1 / 2 ) if #smt_on else uops_executed.core_cycles_ge_1) ( ((br_misp_retired.all_branches / ( br_misp_retired.all_branches + machine_clears.count )) * (( uops_issued.any - uops_retired.retire_slots + 4 * int_misc.recovery_cycles ) / (4 * cycles))) + (4 * idq_uops_not_delivered.cycles_0_uops_deliv.core / (4 * cycles)) * (( int_misc.clear_resteer_cycles + 9 * baclears.any ) / cycles) / (4 * idq_uops_not_delivered.cycles_0_uops_deliv.core / (4 * cycles)) ) * (4 * cycles) / br_misp_retired.all_branches ( ((br_misp_retired.all_branches / ( br_misp_retired.all_branches + machine_clears.count )) * (( uops_issued.any - uops_retired.retire_slots + 4 * (( int_misc.recovery_cycles_any / 2 )) ) / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) ))))) + (4 * idq_uops_not_delivered.cycles_0_uops_deliv.core / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )))) * (( int_misc.clear_resteer_cycles + 9 * baclears.any ) / cycles) / (4 * idq_uops_not_delivered.cycles_0_uops_deliv.core / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )))) ) * (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) ))) / br_misp_retired.all_branches l1d_pend_miss.pending / ( mem_load_retired.l1_miss + mem_load_retired.fb_hit ) ( itlb_misses.walk_pending + dtlb_load_misses.walk_pending + dtlb_store_misses.walk_pending + ept.walk_pending ) / ( 2 * cycles ) ( itlb_misses.walk_pending + dtlb_load_misses.walk_pending + dtlb_store_misses.walk_pending + ept.walk_pending ) / ( 2 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )) ) 64 * offcore_requests.all_requests / 1000000000 / duration_time L3_Cache_Access_BW 1000 * mem_load_retired.l1_miss / inst_retired.any 1000 * mem_load_retired.l2_miss / inst_retired.any 1000 * mem_load_retired.l3_miss / inst_retired.any arb@event\=0x80\,umask\=0x2@ / arb@event\=0x80\,umask\=0x2\,thresh\=1@ Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions. ) inst_retired.any / ( br_inst_retired.far_branch / 2 ) IpFarBranch Unit: uncore_arb Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic Counts demand data loads that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed Page walk completed due to a demand data load to a 4K page Counts page walks completed due to demand data loads whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault Page walk completed due to a demand data load to a 2M/4M page Counts page walks completed due to demand data loads whose address translations missed in the TLB and were mapped to 2M/4M pages. The page walks can end with or without a page fault Page walk completed due to a demand data load to a 1G page Load miss in all TLB levels causes a page walk that completes. (All page sizes) Counts demand data loads that caused a completed page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels. The page walk can end with or without a fault Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake microarchitecture dtlb_load_misses.walk_active umask=0x10,period=100003,cmask=1,event=0x8 Cycles when at least one PMH is busy with a page walk for a load. EPT page walk duration are excluded in Skylake Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load Loads that miss the DTLB and hit the STLB Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB) Counts demand data stores that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed Page walk completed due to a demand data store to a 2M/4M page Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 2M/4M pages. The page walks can end with or without a page fault Page walk completed due to a demand data store to a 1G page Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 1G pages. The page walks can end with or without a page fault Store misses in all TLB levels causes a page walk that completes. (All page sizes) Counts demand data stores that caused a completed page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels. The page walk can end with or without a fault umask=0x10,period=2000003,event=0x49 Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake microarchitecture dtlb_store_misses.walk_active umask=0x10,period=100003,cmask=1,event=0x49 Cycles when at least one PMH is busy with a page walk for a store. EPT page walk duration are excluded in Skylake Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store Stores that miss the DTLB and hit the STLB Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB) Counts 1 per cycle for each PMH that is busy with a EPT (Extended Page Table) walk for any request type Counts cycles for each PMH (Page Miss Handler) that is busy with an EPT (Extended Page Table) walk for any request type Counts page walks of any page size (4K/2M/4M/1G) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB, but the walk need not have completed Counts completed page walks (4K page size) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB. The page walk can end with or without a fault Counts code misses in all ITLB levels that caused a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault Code miss in all TLB levels causes a page walk that completes. (1G) Counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault Code miss in all TLB levels causes a page walk that completes. (All page sizes) Counts completed page walks (2M and 4M page sizes) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB. The page walk can end with or without a fault Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake michroarchitecture itlb_misses.walk_active umask=0x10,period=100003,cmask=1,event=0x85 Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake microarchitecture Instruction fetch requests that miss the ITLB and hit the STLB Counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific) Counts the number of DTLB flush attempts of the thread-specific entries Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.) Counts the number of request from the L2 that were not accepted into the XQ This event counts the number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the IDI link. The XQ may reject transactions from the L2Q (non-cacheable requests), BBS (L2 misses) and WOB (L2 write-back victims) Counts the number of request that were not accepted into the L2Q because the L2Q is FULL Counts the number of (demand and L1 prefetchers) core requests rejected by the L2Q due to a full or nearly full w condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to insure fairness between cores, or to delay a core?s dirty eviction when the address conflicts incoming external snoops. (Note that L2 prefetcher requests that are dropped are not counted by this event.) L2 cache requests from this core This event counts requests originating from the core that references a cache line in the L2 cache This event counts the total number of L2 cache references and the number of L2 cache misses respectively Counts cycles that fetch is stalled due to an outstanding ICache miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ICache miss. Note: this event is not the same as the total number of cycles spent retrieving instruction cache lines from the memory hierarchy.
Counts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes. This will include cycles due to an ITLB miss, ICache miss and other events rehabq.ld_block_st_forward Loads blocked due to store forward restriction (Precise event) This event counts the number of retired loads that were prohibited from receiving forwarded data from the store because of address mismatch (Precise event) rehabq.ld_block_std_notready Loads blocked due to store data not ready This event counts the cases where a forward was technically possible, but did not occur because the store data was not available at the right time rehabq.st_splits Store uops that split cache line boundary This event counts the number of retire stores that experienced cache line boundary splits rehabq.ld_splits Load uops that split cache line boundary (Precise event) This event counts the number of retire loads that experienced cache line boundary splits (Precise event) rehabq.lock Uops with lock semantics This event counts the number of retired memory operations with lock semantics. These are either implicit locked instructions such as the XCHG instruction or instructions with an explicit LOCK prefix (0xF0) rehabq.sta_full Store address buffer full This event counts the number of retired stores that are delayed because there is not a store address buffer available rehabq.any_ld Any reissued load uops This event counts the number of load uops reissued from Rehabq rehabq.any_st Any reissued store uops This event counts the number of store uops reissued from Rehabq Loads missed L1 This event counts the number of load ops retired that miss in L1 Data cache. Note that prefetch misses will not be counted Loads hit L2 (Precise event) This event counts the number of load ops retired that hit in the L2 (Precise event) Loads missed L2 (Precise event) This event counts the number of load ops retired that miss in the L2 (Precise event) mem_uops_retired.utlb_miss Loads missed UTLB This event counts the number of load ops retired that had UTLB miss Cross core or cross module hitm (Precise event) This event counts the number of load ops retired that got data from the other core or from the other module (Precise event) All Loads This event counts the number of load ops retired All Stores This event counts the number of store ops retired offcore_response.any_code_rd.l2_miss.any umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680000044 Counts any code reads (demand & prefetch) that miss L2 offcore_response.any_code_rd.l2_miss.hitm_other_core umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000000044 Counts any code reads (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache offcore_response.any_code_rd.l2_miss.hit_other_core_no_fwd umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400000044 Counts any code reads (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded offcore_response.any_code_rd.l2_miss.snoop_miss umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200000044 Counts any code reads (demand & prefetch) that miss L2 with a snoop miss response Counts any code reads (demand & prefetch) that have any response type umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680000022 Counts any rfo reads (demand & prefetch) that miss L2 Counts any rfo reads (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache Counts any rfo reads (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded offcore_response.any_rfo.l2_miss.snoop_miss Counts any rfo reads (demand & prefetch) that miss L2 with a snoop miss response Counts any rfo reads (demand & prefetch) that have any response type umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680003091 Counts any data read (demand & prefetch) that miss L2 Counts any data read (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache Counts any data read (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded offcore_response.any_data_rd.l2_miss.snoop_miss Counts any data read (demand & prefetch) that miss L2 with a snoop miss response Counts any data read (demand & prefetch) that have any response type umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680004800 Counts streaming store that miss L2 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000008008 Counts any request that hit in the other module where modified copies were found in other core's L1 cache umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400008008 Counts any request that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded offcore_response.any_request.l2_miss.snoop_miss umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200008008 Counts any request that miss L2 with a snoop miss response umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000018008 Counts any request that have any response type umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680002000 Counts DCU hardware prefetcher data read that miss L2 Counts DCU hardware prefetcher data read that hit in the other module where modified copies were found in other core's L1 cache Counts DCU hardware prefetcher data read that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded offcore_response.pf_l1_data_rd.l2_miss.snoop_miss Counts DCU hardware prefetcher data read that miss L2 with a snoop miss response Counts DCU hardware prefetcher data read that have any response type umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680000100 Countsof demand RFO requests to write to partial cache lines that miss L2 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680000080 Counts demand reads of partial cache lines (including UC and WC) that miss L2 offcore_response.pf_l2_code_rd.l2_miss.any umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680000040 Counts code reads generated by L2 prefetchers that miss L2 offcore_response.pf_l2_code_rd.l2_miss.hit_other_core_no_fwd umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400000040 Counts code reads generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded offcore_response.pf_l2_code_rd.l2_miss.snoop_miss umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200000040 Counts code reads generated by L2 prefetchers that miss L2 with a snoop miss response umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680000020 Counts RFO requests generated by L2 prefetchers that miss L2 Counts RFO requests generated by L2 prefetchers that hit in the other module where modified copies were found in other core's L1 cache Counts RFO requests generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded offcore_response.pf_l2_rfo.l2_miss.snoop_miss Counts RFO requests generated by L2 prefetchers that miss L2 with a snoop miss response umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680000010 Counts data cacheline reads generated by L2 prefetchers that miss L2 Counts data cacheline reads generated by L2 prefetchers that hit in the other module where modified copies were found in other core's L1 cache Counts data cacheline reads generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded offcore_response.pf_l2_data_rd.l2_miss.snoop_miss Counts data cacheline reads generated by L2 prefetchers that miss L2 with a snoop miss response umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680000008 Counts writeback (modified to exclusive) that miss L2 offcore_response.corewb.l2_miss.no_snoop_needed umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080000008 Counts writeback (modified to exclusive) that miss L2 with no details on snoop-related information Counts demand and DCU prefetch instruction cacheline that are are outstanding, per cycle, from the time of the L2 miss to when any response is received umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680000004 Counts demand and DCU prefetch instruction cacheline that miss L2 Counts demand and DCU prefetch instruction cacheline that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded offcore_response.demand_code_rd.l2_miss.snoop_miss Counts demand and DCU prefetch instruction cacheline that miss L2 with a snoop miss response Counts demand and DCU prefetch instruction cacheline that have any response type Counts demand and DCU prefetch RFOs that are are outstanding, per cycle, from the time of the L2 miss to when any response is received umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680000002 Counts demand and DCU prefetch RFOs that miss L2 Counts demand and DCU prefetch RFOs that hit in the other module where modified copies were found in other core's L1 cache Counts demand and DCU prefetch RFOs that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded offcore_response.demand_rfo.l2_miss.snoop_miss Counts demand and DCU prefetch RFOs that miss L2 with a snoop miss response Counts demand and DCU prefetch data read that are are outstanding, per cycle, from the time of the L2 miss to when any response is received umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680000001 Counts demand and DCU prefetch data read that miss L2 Counts demand and DCU prefetch data read that hit in the other module where modified copies were found in other core's L1 cache Counts demand and DCU prefetch data read that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded offcore_response.demand_data_rd.l2_miss.snoop_miss Counts demand and DCU prefetch data read that miss L2 with a snoop miss response Counts demand and DCU prefetch data read that have any response type This event counts all instruction fetches, not including most uncacheable
fetches Instruction fetches from Icache This event counts all instruction fetches from the instruction cache This event counts all instruction fetches that miss the Instruction cache or produce memory requests. This includes uncacheable fetches. An instruction fetch miss is counted only once and not once for every cycle it is outstanding Counts the number of times entered into a ucode flow in the FEC. Includes inserted flows due to front-end detected faults or assists. Speculative count Counts the number of times the MSROM starts a flow of UOPS. It does not count every time a UOP is read from the microcode ROM. The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine. Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort. The event will count MSROM startups for UOPS that are speculative, and subsequently cleared by branch mispredict or machine clear. Background: UOPS are produced by two mechanisms. Either they are generated by hardware that decodes instructions into UOPS, or they are delivered by a ROM (called the MSROM) that holds UOPS associated with a specific instruction. MSROM UOPS might also be delivered in response to some condition such as a fault or other exceptional condition. This event is an excellent mechanism for detecting instructions that require the use of MSROM instructions Counts the number of times a decode restriction reduced the decode throughput due to wrong instruction length prediction Stalls due to Memory ordering This event counts the number of times that pipeline was cleared due to memory ordering issues umask=0x3f,period=200003,event=0x86 Counts the number of branch instructions retired.. (Precise event) ALL_BRANCHES counts the number of any branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) Counts the number of JCC branch instructions retired (Precise event) JCC counts the number of conditional branch (JCC) instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) Counts the number of taken JCC branch instructions retired (Precise event) TAKEN_JCC counts the number of taken conditional branch (JCC) instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) CALL counts the number of near CALL branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) REL_CALL counts the number of near relative CALL branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) IND_CALL counts the number of near indirect CALL branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) RETURN counts the number of near RET branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) Counts the number of near indirect JMP and near indirect CALL branch instructions retired (Precise event) NON_RETURN_IND counts the number of near indirect JMP and near indirect CALL branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) FAR counts the number of far branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) ALL_BRANCHES counts the number of any mispredicted branch instructions retired. This umask is an architecturally defined event. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa. When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event) Counts the number of mispredicted JCC branch instructions retired (Precise event) JCC counts the number of mispredicted conditional branches (JCC) instructions retired. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa. When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event) Counts the number of mispredicted taken JCC branch instructions retired (Precise event) TAKEN_JCC counts the number of mispredicted taken conditional branch (JCC) instructions retired. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa. When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event) IND_CALL counts the number of mispredicted near indirect CALL branch instructions retired. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa. When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event) RETURN counts the number of mispredicted near RET branch instructions retired. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa. When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event) Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired (Precise event) NON_RETURN_IND counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa. When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event) MSROM micro-ops retired This event counts the number of micro-ops retired. The processor decodes complex macro instructions into a sequence of simpler micro-ops. Most instructions are composed of one or two micro-ops. Some instructions are decoded into longer sequences such as repeat instructions, floating point transcendental instructions, and assists. In some cases micro-op sequences are fused or whole instructions are fused into one micro-op. See other UOPS_RETIRED events for differentiating retired fused and non-fused micro-ops This event counts the number of times that a program writes to a code section. Self-modifying code causes a severe penalty in all Intel? architecture processors Stalls due to FP assists This event counts the number of times that pipeline stalled due to FP operations needing assists Counts all machine clears Machine clears happen when something happens in the machine that causes the hardware to need to take special care to get the right answer. When such a condition is signaled on an instruction, the front end of the machine is notified that it must restart, so no more instructions will be decoded from the current path. All instructions "older" than this one will be allowed to finish. This instruction and all "younger" instructions must be cleared, since they must not be allowed to complete. Essentially, the hardware waits until the problematic instruction is the oldest instruction in the machine. This means all older instructions are retired, and all pending stores (from older instructions) are completed. Then the new path of instructions from the front end are allowed to start into the machine. There are many conditions that might cause a machine clear (including the receipt of an interrupt, or a trap or a fault). All those conditions (including but not limited to MACHINE_CLEARS.MEMORY_ORDERING, MACHINE_CLEARS.SMC, and MACHINE_CLEARS.FP_ASSIST) are captured in the ANY event. In addition, some conditions can be specifically counted (i.e. SMC, MEMORY_ORDERING, FP_ASSIST). However, the sum of SMC, MEMORY_ORDERING, and FP_ASSIST machine clears will not necessarily equal the number of ANY Counts the number of cycles when no uops are allocated and the ROB is full (less than 2 entries available) Counts the number of cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted jump to retire. After the misprediction is detected, the front end will start immediately but the allocate pipe stalls until the mispredicted Counts the number of cycles when no uops are allocated and a RATstall is asserted umask=0x50,period=200003,event=0xca Counts the number of cycles when no uops are allocated, the IQ is empty, and no other condition is blocking allocation The NO_ALLOC_CYCLES.NOT_DELIVERED event is used to measure front-end inefficiencies, i.e. when front-end of the machine is not delivering micro-ops to the back-end and the back-end is not stalled. This event can be used to identify if the machine is truly front-end bound. When this event occurs, it is an indication that the front-end of the machine is operating at less than its theoretical peak performance. Background: We can think of the processor pipeline as being divided into 2 broader parts: Front-end and Back-end. Front-end is responsible for fetching the instruction, decoding into micro-ops (uops) in machine understandable format and putting them into a micro-op queue to be consumed by back end. The back-end then takes these micro-ops, allocates the required resources. When all resources are ready, micro-ops are executed. If the back-end is not ready to accept micro-ops from the front-end, then we do not want to count these as front-end bottlenecks. However, whenever we have bottlenecks in the back-end, we will have allocation unit stalls and eventually forcing the front-end to wait until the back-end is ready to receive more UOPS. This event counts the cycles only when back-end is requesting more uops and front-end is not able to provide them. Some examples of conditions that cause front-end efficiencies are: Icache misses, ITLB misses, and decoder restrictions that limit the the front-end bandwidth umask=0x3f,period=200003,event=0xca Counts the number of cycles when no uops are allocated for any reason The NO_ALLOC_CYCLES.ALL event counts the number of cycles when the front-end does not provide any instructions to be allocated for any reason. This event indicates the cycles where an allocation stalls occurs, and no UOPS are allocated in that cycle Counts the number of cycles and allocation pipeline is stalled and is waiting for a free MEC reservation station entry. The cycles should be appropriately counted in case of the cracked ops e.g. In case of a cracked load-op, the load portion is sent to M Counts the number of cycles the Alloc pipeline is stalled when any one of the RSs (IEC, FPC and MEC) is full. This event is a superset of all the individual RS stall event counts This event counts the number of instructions that retire execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers Cycles the divider is busy. Does not imply a stall waiting for the divider Cycles the divider is busy.This event counts the cycles when the divide unit is unable to accept a new divide UOP because it is busy processing a previously dispatched UOP. The cycles will be counted irrespective of whether or not another divide UOP is waiting to enter the divide unit (from the RS). This event might count cycles while a divide is in progress even if the RS is empty. The divide instruction is one of the longest latency instructions in the machine. Hence, it has a special event associated with it to help determine if divides are delaying the retirement of instructions This event counts the number of instructions that retire. For instructions that consist of multiple micro-ops, this event counts exactly once, as the last micro-op of the instruction retires. The event continues counting while instructions retire, including during interrupt service routines caused by hardware interrupts, faults or traps. Background: Modern microprocessors employ extensive pipelining and speculative techniques. Since sometimes an instruction is started but never completed, the notion of "retirement" is introduced. A retired instruction is one that commits its states. Or stated differently, an instruction might be abandoned at some point. No instruction is truly finished until it retires. This counter measures the number of completed instructions. The fixed event is INST_RETIRED.ANY and the programmable event is INST_RETIRED.ANY_P Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. In systems with a constant core frequency, this event can give you a measurement of the elapsed time while the core was not in halt state by dividing the event count by the core frequency. This event is architecturally defined and is a designated fixed counter. CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.CORE_P use the core frequency which may change from time to time. CPU_CLK_UNHALTE.REF_TSC and CPU_CLK_UNHALTED.REF are not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. The fixed events are CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.REF_TSC and the programmable events are CPU_CLK_UNHALTED.CORE_P and CPU_CLK_UNHALTED.REF Counts the number of reference cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. Divide this event count by core frequency to determine the elapsed time while the core was not in halt state. Divide this event count by core frequency to determine the elapsed time while the core was not in halt state. This event is architecturally defined and is a designated fixed counter. CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.CORE_P use the core frequency which may change from time to time. CPU_CLK_UNHALTE.REF_TSC and CPU_CLK_UNHALTED.REF are not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. The fixed events are CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.REF_TSC and the programmable events are CPU_CLK_UNHALTED.CORE_P and CPU_CLK_UNHALTED.REF This event counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time This event counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time Counts the number of baclears The BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end. The BACLEARS.ANY event counts the number of baclears for any type of branch Counts the number of RETURN baclears The BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end. The BACLEARS.RETURN event counts the number of RETURN baclears Counts the number of JCC baclears The BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end. The BACLEARS.COND event counts the number of JCC (Jump on Condtional Code) baclears ALL_TAKEN_BRANCHES counts the number of all taken branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Must be precise) Loads missed DTLB (Precise event) This event counts the number of load ops retired that had DTLB miss (Precise event) D-side page-walks This event counts when a data (D) page walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks Duration of D-side page-walks in core cycles This event counts every cycle when a D-side (walks due to a load) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks I-side page-walks This event counts when an instruction (I) page walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks Duration of I-side page-walks in core cycles This event counts every cycle when a I-side (walks due to an instruction fetch) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks Total page walks that are completed (I-side and D-side) This event counts when a data (D) page walk or an instruction (I) page walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks Total cycles for all the page walks. (I-side and D-side) This event counts every cycle when a data (D) page walk or instruction (I) page walk is in progress. Since a pagewalk implies a TLB miss, the approximate cost of a TLB miss can be determined from this event Retired load uops that miss the STLB. (Precise Event - PEBS) (Precise event) Retired store uops that miss the STLB. (Precise Event - PEBS) (Precise event) Retired load uops with locked access. (Precise Event - PEBS) (Precise event) Retired load uops that split across a cacheline boundary. (Precise Event - PEBS) (Precise event) This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K). (Precise Event - PEBS) (Precise event) Retired store uops that split across a cacheline boundary. (Precise Event - PEBS) (Precise event) This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K). (Precise Event - PEBS) (Precise event) All retired load uops. (Precise Event - PEBS) (Precise event) This event counts the number of load uops retired (Precise Event) (Precise event) All retired store uops. (Precise Event - PEBS) (Precise event) This event counts the number of store uops retired. (Precise Event - PEBS) (Precise event) Retired load uops with L1 cache hits as data sources. (Precise Event - PEBS) (Precise event) Retired load uops with L2 cache hits as data sources. (Precise Event - PEBS) (Precise event) Retired load uops which data sources were data hits in LLC without snoops required. (Precise Event - PEBS) (Precise event) This event counts retired load uops that hit in the last-level (L3) cache without snoops required. (Precise Event - PEBS) (Precise event) Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. (Precise Event - PEBS) (Precise event) Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS) (Precise event) Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS) (Precise event) This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a non-modified state. (Precise Event - PEBS) (Precise event) Retired load uops which data sources were HitM responses from shared LLC. (Precise Event - PEBS) (Precise event) This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a modified state, so the line had to be invalidated in that L2 cache and transferred to the requesting L2. (Precise Event - PEBS) (Precise event) Retired load uops which data sources were hits in LLC without snoops required. (Precise Event - PEBS) (Precise event) mem_load_uops_misc_retired.llc_miss umask=0x2,period=100007,event=0xd4 Retired load uops with unknown information as data source in cache serviced the load. (Precise Event - PEBS) (Precise event) This event counts retired demand loads that missed the last-level (L3) cache. This means that the load is usually satisfied from memory in a client system or possibly from the remote socket in a server. Demand loads are non speculative load uops. (Precise Event - PEBS) (Precise event) offcore_response.all_code_rd.llc_hit.hitm_other_core umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0244 Counts demand & prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded offcore_response.all_code_rd.llc_hit.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0244 Counts demand & prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean response Counts demand & prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean response offcore_response.all_pf_code_rd.llc_hit.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0240 Counts all prefetch code reads that hit in the LLC offcore_response.all_pf_code_rd.llc_hit.hit_other_core_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0240 Counts prefetch code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded offcore_response.all_pf_code_rd.llc_hit.hitm_other_core umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0240 Counts prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded offcore_response.all_pf_code_rd.llc_hit.no_snoop_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0240 Counts prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores offcore_response.all_pf_code_rd.llc_hit.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0240 Counts prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean response Counts all prefetch data reads that hit in the LLC Counts prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean response offcore_response.all_pf_rfo.llc_hit.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0120 Counts all prefetch RFOs that hit in the LLC offcore_response.all_pf_rfo.llc_hit.hit_other_core_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0120 Counts prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded offcore_response.all_pf_rfo.llc_hit.hitm_other_core umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0120 Counts prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded offcore_response.all_pf_rfo.llc_hit.no_snoop_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0120 Counts prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores offcore_response.all_pf_rfo.llc_hit.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0120 Counts prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean response Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops sent to sibling cores return clean response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0122 Counts demand & prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0122 Counts demand & prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded offcore_response.all_rfo.llc_hit.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0122 Counts demand & prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean response COREWB & ANY_RESPONSE umask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0004 Counts demand code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0004 Counts demand code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded offcore_response.demand_code_rd.llc_hit.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0004 Counts demand code reads that hit in the LLC and the snoops sent to sibling cores return clean response Counts demand data reads that hit in the LLC and the snoops sent to sibling cores return clean response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0002 Counts demand data writes (RFOs) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded offcore_response.demand_rfo.llc_hit.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0002 Counts demand data writes (RFOs) that hit in the LLC and the snoops sent to sibling cores return clean response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2380408000 offcore_response.pf_l2_code_rd.llc_hit.hit_other_core_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0040 Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded offcore_response.pf_l2_code_rd.llc_hit.hitm_other_core umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0040 Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded offcore_response.pf_l2_code_rd.llc_hit.no_snoop_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0040 Counts prefetch (that bring data to L2) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores offcore_response.pf_l2_code_rd.llc_hit.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0040 Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoops sent to sibling cores return clean response Counts all prefetch (that bring data to L2) data reads that hit in the LLC umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0020 Counts all prefetch (that bring data to L2) RFOs that hit in the LLC offcore_response.pf_l2_rfo.llc_hit.hit_other_core_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0020 Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded offcore_response.pf_l2_rfo.llc_hit.hitm_other_core umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0020 Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded offcore_response.pf_l2_rfo.llc_hit.no_snoop_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0020 Counts prefetch (that bring data to L2) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores offcore_response.pf_l2_rfo.llc_hit.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0020 Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops sent to sibling cores return clean response offcore_response.pf_llc_code_rd.llc_hit.hit_other_core_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0200 Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded offcore_response.pf_llc_code_rd.llc_hit.hitm_other_core umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0200 Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded offcore_response.pf_llc_code_rd.llc_hit.no_snoop_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0200 Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores offcore_response.pf_llc_code_rd.llc_hit.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0200 Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops sent to sibling cores return clean response Counts all prefetch (that bring data to LLC only) data reads that hit in the LLC umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0100 Counts all prefetch (that bring data to LLC only) RFOs that hit in the LLC offcore_response.pf_llc_rfo.llc_hit.hit_other_core_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0100 Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded offcore_response.pf_llc_rfo.llc_hit.hitm_other_core umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0100 Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded offcore_response.pf_llc_rfo.llc_hit.no_snoop_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0100 Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores offcore_response.pf_llc_rfo.llc_hit.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0100 Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops sent to sibling cores return clean response Counts all demand data reads Counts all demand rfo's Counts all demand & prefetch prefetch RFOs Counts all data/code/rfo references (demand & prefetch) offcore_response.data_in.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10433 REQUEST = DATA_INTO_CORE and RESPONSE = ANY_RESPONSE offcore_response.demand_rfo.llc_hit_m.hitm REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_M and SNOOP = HITM offcore_response.pf_ifetch.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10040 REQUEST = PF_RFO and RESPONSE = ANY_RESPONSE offcore_response.pf_l_data_rd.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10080 REQUEST = PF_LLC_DATA_RD and RESPONSE = ANY_RESPONSE offcore_response.pf_l_ifetch.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10200 REQUEST = PF_LLC_IFETCH and RESPONSE = ANY_RESPONSE This event counts cycles during which the microcode sequencer assisted the front-end in delivering uops. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance. See the Intel® 64 and IA-32 Architectures Optimization Reference Manual for more information Number of any page walk that had a miss in LLC. Does not necessary cause a SUSPEND offcore_response.all_pf_code_rd.llc_miss.dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400240 Counts all prefetch code reads that miss the LLC and the data returned from dram offcore_response.all_pf_data_rd.llc_miss.dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400090 Counts all prefetch data reads that miss the LLC and the data returned from dram offcore_response.all_pf_rfo.llc_miss.dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400120 Counts all prefetch RFOs that miss the LLC and the data returned from dram offcore_response.all_rfo.llc_miss.dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400122 Counts all demand & prefetch RFOs that miss the LLC and the data returned from dram offcore_response.demand_rfo.llc_miss.dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400002 Counts demand data writes (RFOs) that miss the LLC and the data returned from dram offcore_response.pf_l2_code_rd.llc_miss.dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400040 Counts all prefetch (that bring data to L2) code reads that miss the LLC and the data returned from dram offcore_response.pf_l2_data_rd.llc_miss.dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400010 Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from dram offcore_response.pf_l2_rfo.llc_miss.dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400020 Counts all prefetch (that bring data to L2) RFOs that miss the LLC and the data returned from dram offcore_response.pf_llc_code_rd.llc_miss.dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400200 Counts all prefetch (that bring data to LLC only) code reads that miss the LLC and the data returned from dram offcore_response.pf_llc_data_rd.llc_miss.dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400080 Counts all prefetch (that bring data to LLC only) data reads that miss the LLC and the data returned from dram offcore_response.pf_llc_rfo.llc_miss.dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400100 Counts all prefetch (that bring data to LLC only) RFOs that miss the LLC and the data returned from dram This event counts all data requests (demand/prefetch data reads and demand data writes (RFOs) that miss the LLC where the data is returned from local DRAM offcore_response.any_request.llc_miss_local.dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1f80408fff REQUEST = ANY_REQUEST and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM This event counts any requests that miss the LLC where the data was returned from local DRAM offcore_response.data_in_socket.llc_miss_local.any_llc_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x17004001b3 REQUEST = DATA_IN_SOCKET and RESPONSE = LLC_MISS_LOCAL and SNOOP = ANY_LLC_HIT offcore_response.demand_ifetch.llc_miss_local.dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1f80400004 REQUEST = DEMAND_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM offcore_response.pf_data_rd.llc_miss_local.dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1f80400010 REQUEST = PF_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM offcore_response.pf_ifetch.llc_miss_local.dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1f80400040 REQUEST = PF_RFO and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM offcore_response.pf_l_data_rd.llc_miss_local.dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1f80400080 REQUEST = PF_LLC_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM offcore_response.pf_l_ifetch.llc_miss_local.dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1f80400200 REQUEST = PF_LLC_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceeding smaller uncompleted store. See the table of not supported store forwards in the Intel® 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued This event counts the number of cycles spent executing performance-sensitive flags-merging uops. For example, shift CL (merge_arith_flags). For more details, See the Intel® 64 and IA-32 Architectures Optimization Reference Manual This event counts the number of cycles with at least one slow LEA uop being allocated. A uop is generally considered as slow LEA if it has three sources (for example, two sources and immediate) regardless of whether it is a result of LEA instruction or not. Examples of the slow LEA uop are or uops with base, index, and offset source operands using base and index reqisters, where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel® 64 and IA-32 Architectures Optimization Reference Manual for more details about slow LEA instructions Actually retired uops. (Precise Event - PEBS) (Precise event) This event counts the number of micro-ops retired. (Precise Event) (Precise event) This event counts the number of retirement slots used each cycle. There are potentially 4 slots that can be used each cycle - meaning, 4 micro-ops or 4 instructions could retire each cycle. This event is used in determining the 'Retiring' category of the Top-Down pipeline slots characterization. (Precise Event - PEBS) (Precise event) Direct and indirect mispredicted near call instructions retired. (Precise Event - PEBS) (Precise event) Mispredicted not taken branch instructions retired.(Precise Event - PEBS) (Precise event) Mispredicted taken branch instructions retired. (Precise Event - PEBS) (Precise event) snb metrics offcore_requests.any umask=0x80,period=100000,event=0xb0 offcore_requests.any.read umask=0x8,period=100000,event=0xb0 Offcore read requests offcore_requests.any.rfo umask=0x10,period=100000,event=0xb0 Offcore RFO requests offcore_requests.demand.read_code umask=0x2,period=100000,event=0xb0 Offcore demand code read requests offcore_requests.demand.read_data umask=0x1,period=100000,event=0xb0 Offcore demand data read requests offcore_requests.demand.rfo umask=0x4,period=100000,event=0xb0 Offcore demand RFO requests offcore_requests_outstanding.any.read umask=0x8,period=2000000,event=0x60 Outstanding offcore reads offcore_requests_outstanding.any.read_not_empty umask=0x8,period=2000000,cmask=1,event=0x60 Cycles offcore reads busy offcore_requests_outstanding.demand.read_code umask=0x2,period=2000000,event=0x60 Outstanding offcore demand code reads offcore_requests_outstanding.demand.read_code_not_empty umask=0x2,period=2000000,cmask=1,event=0x60 Cycles offcore demand code read busy offcore_requests_outstanding.demand.read_data umask=0x1,period=2000000,event=0x60 Outstanding offcore demand data reads offcore_requests_outstanding.demand.read_data_not_empty umask=0x1,period=2000000,cmask=1,event=0x60 Cycles offcore demand data read busy offcore_requests_outstanding.demand.rfo umask=0x4,period=2000000,event=0x60 Outstanding offcore demand RFOs offcore_requests_outstanding.demand.rfo_not_empty umask=0x4,period=2000000,cmask=1,event=0x60 Cycles offcore demand RFOs busy sq_misc.lru_hints umask=0x4,period=2000000,event=0xf4 Super Queue LRU hints sent to LLC offcore_response.any_data.all_local_dram_and_remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5011 REQUEST = ANY_DATA read and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f11 REQUEST = ANY_DATA read and RESPONSE = ANY_CACHE_DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0xff11 REQUEST = ANY_DATA read and RESPONSE = ANY_LOCATION REQUEST = ANY_DATA read and RESPONSE = IO_CSR_MMIO REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_NO_OTHER_CORE REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HIT REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HITM REQUEST = ANY_DATA read and RESPONSE = LOCAL_CACHE offcore_response.any_data.local_dram_and_remote_cache_hit REQUEST = ANY_DATA read and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = ANY_DATA read and RESPONSE = REMOTE_CACHE_HITM offcore_response.any_ifetch.all_local_dram_and_remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5044 REQUEST = ANY IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f44 REQUEST = ANY IFETCH and RESPONSE = ANY_CACHE_DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0xff44 REQUEST = ANY IFETCH and RESPONSE = ANY_LOCATION REQUEST = ANY IFETCH and RESPONSE = IO_CSR_MMIO REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM REQUEST = ANY IFETCH and RESPONSE = LOCAL_CACHE offcore_response.any_ifetch.local_dram_and_remote_cache_hit REQUEST = ANY IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = ANY IFETCH and RESPONSE = REMOTE_CACHE_HITM offcore_response.any_request.all_local_dram_and_remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x50ff REQUEST = ANY_REQUEST and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7fff REQUEST = ANY_REQUEST and RESPONSE = ANY_CACHE_DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0xffff REQUEST = ANY_REQUEST and RESPONSE = ANY_LOCATION umask=0x1,period=100000,event=0xb7,offcore_rsp=0x80ff REQUEST = ANY_REQUEST and RESPONSE = IO_CSR_MMIO umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1ff REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_NO_OTHER_CORE umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2ff REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HIT umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4ff REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HITM umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7ff REQUEST = ANY_REQUEST and RESPONSE = LOCAL_CACHE offcore_response.any_request.local_dram_and_remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x10ff REQUEST = ANY_REQUEST and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT umask=0x1,period=100000,event=0xb7,offcore_rsp=0x8ff REQUEST = ANY_REQUEST and RESPONSE = REMOTE_CACHE_HITM offcore_response.any_rfo.all_local_dram_and_remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5022 REQUEST = ANY RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f22 REQUEST = ANY RFO and RESPONSE = ANY_CACHE_DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0xff22 REQUEST = ANY RFO and RESPONSE = ANY_LOCATION REQUEST = ANY RFO and RESPONSE = IO_CSR_MMIO REQUEST = ANY RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE REQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT REQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM REQUEST = ANY RFO and RESPONSE = LOCAL_CACHE offcore_response.any_rfo.local_dram_and_remote_cache_hit REQUEST = ANY RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = ANY RFO and RESPONSE = REMOTE_CACHE_HITM offcore_response.corewb.all_local_dram_and_remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5008 REQUEST = CORE_WB and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f08 REQUEST = CORE_WB and RESPONSE = ANY_CACHE_DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0xff08 REQUEST = CORE_WB and RESPONSE = ANY_LOCATION REQUEST = CORE_WB and RESPONSE = IO_CSR_MMIO REQUEST = CORE_WB and RESPONSE = LLC_HIT_NO_OTHER_CORE offcore_response.corewb.llc_hit_other_core_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x208 REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HIT REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HITM REQUEST = CORE_WB and RESPONSE = LOCAL_CACHE offcore_response.corewb.local_dram_and_remote_cache_hit REQUEST = CORE_WB and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = CORE_WB and RESPONSE = REMOTE_CACHE_HITM offcore_response.data_ifetch.all_local_dram_and_remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5077 REQUEST = DATA_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f77 REQUEST = DATA_IFETCH and RESPONSE = ANY_CACHE_DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0xff77 REQUEST = DATA_IFETCH and RESPONSE = ANY_LOCATION REQUEST = DATA_IFETCH and RESPONSE = IO_CSR_MMIO REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM REQUEST = DATA_IFETCH and RESPONSE = LOCAL_CACHE offcore_response.data_ifetch.local_dram_and_remote_cache_hit REQUEST = DATA_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = DATA_IFETCH and RESPONSE = REMOTE_CACHE_HITM offcore_response.data_in.all_local_dram_and_remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5033 REQUEST = DATA_IN and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f33 REQUEST = DATA_IN and RESPONSE = ANY_CACHE_DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0xff33 REQUEST = DATA_IN and RESPONSE = ANY_LOCATION REQUEST = DATA_IN and RESPONSE = IO_CSR_MMIO REQUEST = DATA_IN and RESPONSE = LLC_HIT_NO_OTHER_CORE REQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HIT REQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HITM REQUEST = DATA_IN and RESPONSE = LOCAL_CACHE offcore_response.data_in.local_dram_and_remote_cache_hit REQUEST = DATA_IN and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = DATA_IN and RESPONSE = REMOTE_CACHE_HITM offcore_response.demand_data.all_local_dram_and_remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5003 REQUEST = DEMAND_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f03 REQUEST = DEMAND_DATA and RESPONSE = ANY_CACHE_DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0xff03 REQUEST = DEMAND_DATA and RESPONSE = ANY_LOCATION REQUEST = DEMAND_DATA and RESPONSE = IO_CSR_MMIO REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_NO_OTHER_CORE REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HIT REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITM REQUEST = DEMAND_DATA and RESPONSE = LOCAL_CACHE offcore_response.demand_data.local_dram_and_remote_cache_hit REQUEST = DEMAND_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = DEMAND_DATA and RESPONSE = REMOTE_CACHE_HITM offcore_response.demand_data_rd.all_local_dram_and_remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5001 REQUEST = DEMAND_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f01 REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_CACHE_DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0xff01 REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_LOCATION REQUEST = DEMAND_DATA_RD and RESPONSE = IO_CSR_MMIO REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_CORE REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HIT REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITM REQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_CACHE offcore_response.demand_data_rd.local_dram_and_remote_cache_hit REQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = DEMAND_DATA_RD and RESPONSE = REMOTE_CACHE_HITM offcore_response.demand_ifetch.all_local_dram_and_remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5004 REQUEST = DEMAND_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f04 REQUEST = DEMAND_IFETCH and RESPONSE = ANY_CACHE_DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0xff04 REQUEST = DEMAND_IFETCH and RESPONSE = ANY_LOCATION REQUEST = DEMAND_IFETCH and RESPONSE = IO_CSR_MMIO REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM REQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_CACHE offcore_response.demand_ifetch.local_dram_and_remote_cache_hit REQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = DEMAND_IFETCH and RESPONSE = REMOTE_CACHE_HITM offcore_response.demand_rfo.all_local_dram_and_remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5002 REQUEST = DEMAND_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f02 REQUEST = DEMAND_RFO and RESPONSE = ANY_CACHE_DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0xff02 REQUEST = DEMAND_RFO and RESPONSE = ANY_LOCATION REQUEST = DEMAND_RFO and RESPONSE = IO_CSR_MMIO REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM REQUEST = DEMAND_RFO and RESPONSE = LOCAL_CACHE offcore_response.demand_rfo.local_dram_and_remote_cache_hit REQUEST = DEMAND_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = DEMAND_RFO and RESPONSE = REMOTE_CACHE_HITM offcore_response.other.all_local_dram_and_remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5080 REQUEST = OTHER and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f80 REQUEST = OTHER and RESPONSE = ANY_CACHE_DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0xff80 REQUEST = OTHER and RESPONSE = ANY_LOCATION REQUEST = OTHER and RESPONSE = IO_CSR_MMIO REQUEST = OTHER and RESPONSE = LLC_HIT_NO_OTHER_CORE REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HIT REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HITM REQUEST = OTHER and RESPONSE = LOCAL_CACHE offcore_response.other.local_dram_and_remote_cache_hit REQUEST = OTHER and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = OTHER and RESPONSE = REMOTE_CACHE_HITM offcore_response.pf_data.all_local_dram_and_remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5050 REQUEST = PF_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f50 REQUEST = PF_DATA and RESPONSE = ANY_CACHE_DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0xff50 REQUEST = PF_DATA and RESPONSE = ANY_LOCATION umask=0x1,period=100000,event=0xb7,offcore_rsp=0x8050 REQUEST = PF_DATA and RESPONSE = IO_CSR_MMIO umask=0x1,period=100000,event=0xb7,offcore_rsp=0x150 REQUEST = PF_DATA and RESPONSE = LLC_HIT_NO_OTHER_CORE umask=0x1,period=100000,event=0xb7,offcore_rsp=0x250 REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HIT umask=0x1,period=100000,event=0xb7,offcore_rsp=0x450 REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITM umask=0x1,period=100000,event=0xb7,offcore_rsp=0x750 REQUEST = PF_DATA and RESPONSE = LOCAL_CACHE offcore_response.pf_data.local_dram_and_remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1050 REQUEST = PF_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT umask=0x1,period=100000,event=0xb7,offcore_rsp=0x850 REQUEST = PF_DATA and RESPONSE = REMOTE_CACHE_HITM offcore_response.pf_data_rd.all_local_dram_and_remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5010 REQUEST = PF_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f10 REQUEST = PF_DATA_RD and RESPONSE = ANY_CACHE_DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0xff10 REQUEST = PF_DATA_RD and RESPONSE = ANY_LOCATION REQUEST = PF_DATA_RD and RESPONSE = IO_CSR_MMIO REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_CORE REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HIT REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITM REQUEST = PF_DATA_RD and RESPONSE = LOCAL_CACHE offcore_response.pf_data_rd.local_dram_and_remote_cache_hit REQUEST = PF_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = PF_DATA_RD and RESPONSE = REMOTE_CACHE_HITM offcore_response.pf_ifetch.all_local_dram_and_remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5040 REQUEST = PF_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f40 REQUEST = PF_RFO and RESPONSE = ANY_CACHE_DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0xff40 REQUEST = PF_RFO and RESPONSE = ANY_LOCATION REQUEST = PF_RFO and RESPONSE = IO_CSR_MMIO REQUEST = PF_RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM REQUEST = PF_RFO and RESPONSE = LOCAL_CACHE offcore_response.pf_ifetch.local_dram_and_remote_cache_hit REQUEST = PF_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = PF_RFO and RESPONSE = REMOTE_CACHE_HITM offcore_response.pf_rfo.all_local_dram_and_remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5020 REQUEST = PF_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f20 REQUEST = PF_IFETCH and RESPONSE = ANY_CACHE_DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0xff20 REQUEST = PF_IFETCH and RESPONSE = ANY_LOCATION REQUEST = PF_IFETCH and RESPONSE = IO_CSR_MMIO REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM REQUEST = PF_IFETCH and RESPONSE = LOCAL_CACHE offcore_response.pf_rfo.local_dram_and_remote_cache_hit REQUEST = PF_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = PF_IFETCH and RESPONSE = REMOTE_CACHE_HITM offcore_response.prefetch.all_local_dram_and_remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5070 REQUEST = PREFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f70 REQUEST = PREFETCH and RESPONSE = ANY_CACHE_DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0xff70 REQUEST = PREFETCH and RESPONSE = ANY_LOCATION REQUEST = PREFETCH and RESPONSE = IO_CSR_MMIO REQUEST = PREFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM REQUEST = PREFETCH and RESPONSE = LOCAL_CACHE offcore_response.prefetch.local_dram_and_remote_cache_hit REQUEST = PREFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = PREFETCH and RESPONSE = REMOTE_CACHE_HITM misalign_mem_ref.store umask=0x2,period=200000,event=0x5 Misaligned store references offcore_response.any_data.any_dram_and_remote_fwd umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3011 REQUEST = ANY_DATA read and RESPONSE = ANY_DRAM AND REMOTE_FWD umask=0x1,period=100000,event=0xb7,offcore_rsp=0xf811 REQUEST = ANY_DATA read and RESPONSE = ANY_LLC_MISS offcore_response.any_data.other_local_dram REQUEST = ANY_DATA read and RESPONSE = OTHER_LOCAL_DRAM REQUEST = ANY_DATA read and RESPONSE = REMOTE_DRAM offcore_response.any_ifetch.any_dram_and_remote_fwd umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3044 REQUEST = ANY IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD umask=0x1,period=100000,event=0xb7,offcore_rsp=0xf844 REQUEST = ANY IFETCH and RESPONSE = ANY_LLC_MISS offcore_response.any_ifetch.other_local_dram REQUEST = ANY IFETCH and RESPONSE = OTHER_LOCAL_DRAM REQUEST = ANY IFETCH and RESPONSE = REMOTE_DRAM offcore_response.any_request.any_dram_and_remote_fwd umask=0x1,period=100000,event=0xb7,offcore_rsp=0x30ff REQUEST = ANY_REQUEST and RESPONSE = ANY_DRAM AND REMOTE_FWD umask=0x1,period=100000,event=0xb7,offcore_rsp=0xf8ff REQUEST = ANY_REQUEST and RESPONSE = ANY_LLC_MISS offcore_response.any_request.other_local_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x40ff REQUEST = ANY_REQUEST and RESPONSE = OTHER_LOCAL_DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0x20ff REQUEST = ANY_REQUEST and RESPONSE = REMOTE_DRAM offcore_response.any_rfo.any_dram_and_remote_fwd umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3022 REQUEST = ANY RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD umask=0x1,period=100000,event=0xb7,offcore_rsp=0xf822 REQUEST = ANY RFO and RESPONSE = ANY_LLC_MISS offcore_response.any_rfo.other_local_dram REQUEST = ANY RFO and RESPONSE = OTHER_LOCAL_DRAM REQUEST = ANY RFO and RESPONSE = REMOTE_DRAM offcore_response.corewb.any_dram_and_remote_fwd umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3008 REQUEST = CORE_WB and RESPONSE = ANY_DRAM AND REMOTE_FWD umask=0x1,period=100000,event=0xb7,offcore_rsp=0xf808 REQUEST = CORE_WB and RESPONSE = ANY_LLC_MISS offcore_response.corewb.other_local_dram REQUEST = CORE_WB and RESPONSE = OTHER_LOCAL_DRAM REQUEST = CORE_WB and RESPONSE = REMOTE_DRAM offcore_response.data_ifetch.any_dram_and_remote_fwd umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3077 REQUEST = DATA_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD umask=0x1,period=100000,event=0xb7,offcore_rsp=0xf877 REQUEST = DATA_IFETCH and RESPONSE = ANY_LLC_MISS offcore_response.data_ifetch.other_local_dram REQUEST = DATA_IFETCH and RESPONSE = OTHER_LOCAL_DRAM REQUEST = DATA_IFETCH and RESPONSE = REMOTE_DRAM offcore_response.data_in.any_dram_and_remote_fwd umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3033 REQUEST = DATA_IN and RESPONSE = ANY_DRAM AND REMOTE_FWD umask=0x1,period=100000,event=0xb7,offcore_rsp=0xf833 REQUEST = DATA_IN and RESPONSE = ANY_LLC_MISS offcore_response.data_in.other_local_dram REQUEST = DATA_IN and RESPONSE = OTHER_LOCAL_DRAM REQUEST = DATA_IN and RESPONSE = REMOTE_DRAM offcore_response.demand_data.any_dram_and_remote_fwd umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3003 REQUEST = DEMAND_DATA and RESPONSE = ANY_DRAM AND REMOTE_FWD umask=0x1,period=100000,event=0xb7,offcore_rsp=0xf803 REQUEST = DEMAND_DATA and RESPONSE = ANY_LLC_MISS offcore_response.demand_data.other_local_dram REQUEST = DEMAND_DATA and RESPONSE = OTHER_LOCAL_DRAM REQUEST = DEMAND_DATA and RESPONSE = REMOTE_DRAM offcore_response.demand_data_rd.any_dram_and_remote_fwd umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3001 REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_DRAM AND REMOTE_FWD umask=0x1,period=100000,event=0xb7,offcore_rsp=0xf801 REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_LLC_MISS offcore_response.demand_data_rd.other_local_dram REQUEST = DEMAND_DATA_RD and RESPONSE = OTHER_LOCAL_DRAM REQUEST = DEMAND_DATA_RD and RESPONSE = REMOTE_DRAM offcore_response.demand_ifetch.any_dram_and_remote_fwd umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3004 REQUEST = DEMAND_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD umask=0x1,period=100000,event=0xb7,offcore_rsp=0xf804 REQUEST = DEMAND_IFETCH and RESPONSE = ANY_LLC_MISS offcore_response.demand_ifetch.other_local_dram REQUEST = DEMAND_IFETCH and RESPONSE = OTHER_LOCAL_DRAM REQUEST = DEMAND_IFETCH and RESPONSE = REMOTE_DRAM offcore_response.demand_rfo.any_dram_and_remote_fwd umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3002 REQUEST = DEMAND_RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD umask=0x1,period=100000,event=0xb7,offcore_rsp=0xf802 REQUEST = DEMAND_RFO and RESPONSE = ANY_LLC_MISS offcore_response.demand_rfo.other_local_dram REQUEST = DEMAND_RFO and RESPONSE = OTHER_LOCAL_DRAM REQUEST = DEMAND_RFO and RESPONSE = REMOTE_DRAM offcore_response.other.any_dram_and_remote_fwd umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3080 REQUEST = OTHER and RESPONSE = ANY_DRAM AND REMOTE_FWD umask=0x1,period=100000,event=0xb7,offcore_rsp=0xf880 REQUEST = OTHER and RESPONSE = ANY_LLC_MISS offcore_response.other.other_local_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4080 REQUEST = OTHER and RESPONSE = OTHER_LOCAL_DRAM REQUEST = OTHER and RESPONSE = REMOTE_DRAM offcore_response.pf_data.any_dram_and_remote_fwd umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3050 REQUEST = PF_DATA and RESPONSE = ANY_DRAM AND REMOTE_FWD umask=0x1,period=100000,event=0xb7,offcore_rsp=0xf850 REQUEST = PF_DATA and RESPONSE = ANY_LLC_MISS offcore_response.pf_data.other_local_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4050 REQUEST = PF_DATA and RESPONSE = OTHER_LOCAL_DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2050 REQUEST = PF_DATA and RESPONSE = REMOTE_DRAM offcore_response.pf_data_rd.any_dram_and_remote_fwd umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3010 REQUEST = PF_DATA_RD and RESPONSE = ANY_DRAM AND REMOTE_FWD umask=0x1,period=100000,event=0xb7,offcore_rsp=0xf810 REQUEST = PF_DATA_RD and RESPONSE = ANY_LLC_MISS offcore_response.pf_data_rd.other_local_dram REQUEST = PF_DATA_RD and RESPONSE = OTHER_LOCAL_DRAM REQUEST = PF_DATA_RD and RESPONSE = REMOTE_DRAM offcore_response.pf_ifetch.any_dram_and_remote_fwd umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3040 REQUEST = PF_RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD umask=0x1,period=100000,event=0xb7,offcore_rsp=0xf840 REQUEST = PF_RFO and RESPONSE = ANY_LLC_MISS offcore_response.pf_ifetch.other_local_dram REQUEST = PF_RFO and RESPONSE = OTHER_LOCAL_DRAM REQUEST = PF_RFO and RESPONSE = REMOTE_DRAM offcore_response.pf_rfo.any_dram_and_remote_fwd umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3020 REQUEST = PF_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD umask=0x1,period=100000,event=0xb7,offcore_rsp=0xf820 REQUEST = PF_IFETCH and RESPONSE = ANY_LLC_MISS offcore_response.pf_rfo.other_local_dram REQUEST = PF_IFETCH and RESPONSE = OTHER_LOCAL_DRAM REQUEST = PF_IFETCH and RESPONSE = REMOTE_DRAM offcore_response.prefetch.any_dram_and_remote_fwd umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3070 REQUEST = PREFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD umask=0x1,period=100000,event=0xb7,offcore_rsp=0xf870 REQUEST = PREFETCH and RESPONSE = ANY_LLC_MISS offcore_response.prefetch.other_local_dram REQUEST = PREFETCH and RESPONSE = OTHER_LOCAL_DRAM REQUEST = PREFETCH and RESPONSE = REMOTE_DRAM load_block.overlap_store umask=0x2,period=200000,event=0x3 Loads that partially overlap an earlier store snoopq_requests.code umask=0x4,period=100000,event=0xb4 Snoop code requests snoopq_requests.data umask=0x1,period=100000,event=0xb4 Snoop data requests snoopq_requests.invalidate umask=0x2,period=100000,event=0xb4 Snoop invalidate requests snoopq_requests_outstanding.code Outstanding snoop code requests snoopq_requests_outstanding.code_not_empty umask=0x4,period=2000000,cmask=1,event=0xb3 Cycles snoop code requests queued snoopq_requests_outstanding.data Outstanding snoop data requests snoopq_requests_outstanding.data_not_empty umask=0x1,period=2000000,cmask=1,event=0xb3 Cycles snoop data requests queued snoopq_requests_outstanding.invalidate Outstanding snoop invalidate requests snoopq_requests_outstanding.invalidate_not_empty umask=0x2,period=2000000,cmask=1,event=0xb3 Cycles snoop invalidate requests queued umask=0x4,period=20000,event=0xc5 Mispredicted retired branch instructions (Precise Event) umask=0x1,period=20000,event=0xc5 Mispredicted conditional retired branches (Precise Event) dtlb_load_misses.large_walk_completed umask=0x80,period=200000,event=0x8 DTLB load miss large page walks dtlb_load_misses.walk_cycles umask=0x4,period=200000,event=0x8 DTLB load miss page walk cycles dtlb_misses.large_walk_completed umask=0x80,period=200000,event=0x49 DTLB miss large page walks dtlb_misses.pde_miss umask=0x20,period=200000,event=0x49 DTLB misses casued by low part of address dtlb_misses.walk_cycles umask=0x4,period=2000000,event=0x49 DTLB miss page walk cycles umask=0x10,period=2000000,event=0x4f Extended Page Table walk cycles itlb_misses.large_walk_completed umask=0x80,period=200000,event=0x85 ITLB miss large page walks itlb_misses.walk_cycles umask=0x4,period=2000000,event=0x85 ITLB miss page walk cycles offcore_requests.uncached_mem umask=0x20,period=100000,event=0xb0 Offcore uncached memory accesses umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2711 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5811 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2744 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5844 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x27FF umask=0x1,period=100000,event=0xb7,offcore_rsp=0x58FF umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2722 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5822 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2708 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5808 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2777 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5877 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2733 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5833 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2703 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5803 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2701 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5801 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2704 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5804 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2702 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5802 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2780 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5880 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F50 umask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF50 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2750 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1850 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5850 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2710 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5810 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2740 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5840 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2720 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5820 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2770 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5870 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x6050 umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF850 mem_uncore_retired.local_hitm mem_uncore_retired.local_dram_and_remote_cache_hit Load instructions retired local dram and remote cache HIT data sources (Precise Event) mem_uncore_retired.remote_hitm umask=0x4,period=40000,event=0xf Retired loads that hit remote socket in modified state (Precise Event) Cycles thread is active inv=1,umask=0x3f,period=2000000,cmask=1,edge=1,event=0xb1 inv=1,umask=0x1f,period=2000000,cmask=1,edge=1,event=0xb1 DTLB misses caused by low part of address. Count also includes 2M page references because 2M pages do not use the PDE umask=0x2,cmask=1,period=2000003,event=0x60 mem_load_l3_miss_retired.local_dram Retired load instructions which data sources missed L3 but serviced from local dram Supports address when precise (Precise event) mem_load_l3_miss_retired.remote_dram umask=0x2,period=100007,event=0xd3 Retired load instructions which data sources missed L3 but serviced from remote dram Supports address when precise (Precise event) mem_load_l3_miss_retired.remote_hitm Retired load instructions whose data sources was remote HITM Supports address when precise (Precise event) mem_load_l3_miss_retired.remote_fwd umask=0x8,period=100007,event=0xd3 Retired load instructions whose data sources was forwarded from a remote cache Supports address when precise (Precise event) Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared state. A non-threaded event Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines can be either in modified state or clean state. Modified lines may either be written back to L3 or directly written to memory and not allocated in L3. Clean lines may either be allocated in L3 or dropped offcore_response.demand_data_rd.l3_hit.no_snoop_needed Counts demand data reads TBD TBD offcore_response.demand_rfo.l3_hit.no_snoop_needed Counts all demand data writes (RFOs) TBD TBD offcore_response.demand_code_rd.l3_hit.no_snoop_needed Counts demand instruction fetches and L1 instruction cache prefetches that TBD TBD offcore_response.pf_l2_data_rd.l3_hit.no_snoop_needed Counts prefetch (that bring data to L2) data reads TBD TBD offcore_response.pf_l2_data_rd.l3_hit.hit_other_core_no_fwd offcore_response.pf_l2_data_rd.l3_hit.hitm_other_core offcore_response.pf_l2_rfo.l3_hit.no_snoop_needed Counts all prefetch (that bring data to L2) RFOs TBD TBD offcore_response.pf_l2_rfo.l3_hit.hit_other_core_no_fwd offcore_response.pf_l2_rfo.l3_hit.hitm_other_core offcore_response.pf_l3_data_rd.l3_hit.no_snoop_needed Counts all prefetch (that bring data to LLC only) data reads TBD TBD offcore_response.pf_l3_data_rd.l3_hit.hit_other_core_no_fwd offcore_response.pf_l3_data_rd.l3_hit.hitm_other_core offcore_response.pf_l3_rfo.l3_hit.no_snoop_needed Counts all prefetch (that bring data to LLC only) RFOs TBD TBD offcore_response.pf_l3_rfo.l3_hit.hit_other_core_no_fwd offcore_response.pf_l3_rfo.l3_hit.hitm_other_core offcore_response.pf_l1d_and_sw.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010400 Counts L1 data cache hardware prefetch requests and software prefetch requests have any response type offcore_response.pf_l1d_and_sw.l3_hit.no_snoop_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0400 Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD offcore_response.pf_l1d_and_sw.l3_hit.hit_other_core_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0400 offcore_response.pf_l1d_and_sw.l3_hit.hitm_other_core umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0400 offcore_response.pf_l1d_and_sw.l3_hit.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0400 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010490 TBD have any response type offcore_response.all_pf_data_rd.l3_hit.no_snoop_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0490 TBD TBD TBD offcore_response.all_pf_data_rd.l3_hit.hit_other_core_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0490 offcore_response.all_pf_data_rd.l3_hit.hitm_other_core umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0490 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0490 offcore_response.all_pf_rfo.l3_hit.no_snoop_needed offcore_response.all_pf_rfo.l3_hit.hit_other_core_no_fwd offcore_response.all_pf_rfo.l3_hit.hitm_other_core umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010491 offcore_response.all_data_rd.l3_hit.no_snoop_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0491 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0491 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0491 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0491 offcore_response.all_rfo.l3_hit.no_snoop_needed offcore_response.demand_data_rd.l3_hit.snoop_hit_with_fwd offcore_response.demand_rfo.l3_hit.snoop_hit_with_fwd offcore_response.demand_code_rd.l3_hit.snoop_hit_with_fwd offcore_response.pf_l2_data_rd.l3_hit.snoop_hit_with_fwd offcore_response.pf_l2_rfo.l3_hit.snoop_hit_with_fwd offcore_response.pf_l3_data_rd.l3_hit.snoop_hit_with_fwd offcore_response.pf_l3_rfo.l3_hit.snoop_hit_with_fwd offcore_response.pf_l1d_and_sw.l3_hit.snoop_hit_with_fwd Counts L1 data cache hardware prefetch requests and software prefetch requests offcore_response.all_pf_data_rd.l3_hit.snoop_hit_with_fwd TBD offcore_response.all_pf_rfo.l3_hit.snoop_hit_with_fwd offcore_response.all_data_rd.l3_hit.snoop_hit_with_fwd offcore_response.all_rfo.l3_hit.snoop_hit_with_fwd fp_arith_inst_retired.512b_packed_double umask=0x40,period=2000003,event=0xc7 Number of Packed Double-Precision FP arithmetic instructions (Use operation multiplier of 8) fp_arith_inst_retired.512b_packed_single umask=0x80,period=2000003,event=0xc7 Number of Packed Single-Precision FP arithmetic instructions (Use operation multiplier of 16) umask=0x10,cmask=6,period=2000003,event=0x60 umask=0x10,cmask=1,period=2000003,event=0x60 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBC000001 offcore_response.demand_data_rd.l3_miss.remote_hit_forward umask=0x1,period=100003,event=0xb7,offcore_rsp=0x083FC00001 Counts demand data reads TBD offcore_response.demand_data_rd.l3_miss.remote_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x103FC00001 offcore_response.demand_data_rd.l3_miss.snoop_miss_or_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063FC00001 offcore_response.demand_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063B800001 offcore_response.demand_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0604000001 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBC000002 offcore_response.demand_rfo.l3_miss.remote_hit_forward umask=0x1,period=100003,event=0xb7,offcore_rsp=0x083FC00002 Counts all demand data writes (RFOs) TBD offcore_response.demand_rfo.l3_miss.remote_hitm offcore_response.demand_rfo.l3_miss.snoop_miss_or_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063FC00002 offcore_response.demand_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063B800002 offcore_response.demand_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0604000002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBC000004 offcore_response.demand_code_rd.l3_miss.remote_hit_forward umask=0x1,period=100003,event=0xb7,offcore_rsp=0x083FC00004 Counts demand instruction fetches and L1 instruction cache prefetches that TBD offcore_response.demand_code_rd.l3_miss.remote_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x103FC00004 offcore_response.demand_code_rd.l3_miss.snoop_miss_or_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063FC00004 offcore_response.demand_code_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063B800004 offcore_response.demand_code_rd.l3_miss_local_dram.snoop_miss_or_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0604000004 offcore_response.pf_l2_data_rd.l3_miss.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBC000010 offcore_response.pf_l2_data_rd.l3_miss.remote_hit_forward umask=0x1,period=100003,event=0xb7,offcore_rsp=0x083FC00010 Counts prefetch (that bring data to L2) data reads TBD offcore_response.pf_l2_data_rd.l3_miss.remote_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x103FC00010 offcore_response.pf_l2_data_rd.l3_miss.snoop_miss_or_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063FC00010 offcore_response.pf_l2_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063B800010 offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0604000010 offcore_response.pf_l2_rfo.l3_miss.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBC000020 offcore_response.pf_l2_rfo.l3_miss.remote_hit_forward umask=0x1,period=100003,event=0xb7,offcore_rsp=0x083FC00020 Counts all prefetch (that bring data to L2) RFOs TBD offcore_response.pf_l2_rfo.l3_miss.remote_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x103FC00020 offcore_response.pf_l2_rfo.l3_miss.snoop_miss_or_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063FC00020 offcore_response.pf_l2_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063B800020 offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0604000020 offcore_response.pf_l3_data_rd.l3_miss.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBC000080 offcore_response.pf_l3_data_rd.l3_miss.remote_hit_forward umask=0x1,period=100003,event=0xb7,offcore_rsp=0x083FC00080 Counts all prefetch (that bring data to LLC only) data reads TBD offcore_response.pf_l3_data_rd.l3_miss.remote_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x103FC00080 offcore_response.pf_l3_data_rd.l3_miss.snoop_miss_or_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063FC00080 offcore_response.pf_l3_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063B800080 offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0604000080 offcore_response.pf_l3_rfo.l3_miss.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBC000100 offcore_response.pf_l3_rfo.l3_miss.remote_hit_forward umask=0x1,period=100003,event=0xb7,offcore_rsp=0x083FC00100 Counts all prefetch (that bring data to LLC only) RFOs TBD offcore_response.pf_l3_rfo.l3_miss.remote_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x103FC00100 offcore_response.pf_l3_rfo.l3_miss.snoop_miss_or_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063FC00100 offcore_response.pf_l3_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063B800100 offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0604000100 offcore_response.pf_l1d_and_sw.l3_miss.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBC000400 offcore_response.pf_l1d_and_sw.l3_miss.remote_hit_forward umask=0x1,period=100003,event=0xb7,offcore_rsp=0x083FC00400 Counts L1 data cache hardware prefetch requests and software prefetch requests TBD offcore_response.pf_l1d_and_sw.l3_miss.remote_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x103FC00400 offcore_response.pf_l1d_and_sw.l3_miss.snoop_miss_or_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063FC00400 offcore_response.pf_l1d_and_sw.l3_miss_remote_dram.snoop_miss_or_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063B800400 offcore_response.pf_l1d_and_sw.l3_miss_local_dram.snoop_miss_or_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0604000400 offcore_response.all_pf_data_rd.l3_miss.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBC000490 offcore_response.all_pf_data_rd.l3_miss.remote_hit_forward umask=0x1,period=100003,event=0xb7,offcore_rsp=0x083FC00490 TBD TBD offcore_response.all_pf_data_rd.l3_miss.remote_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x103FC00490 offcore_response.all_pf_data_rd.l3_miss.snoop_miss_or_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063FC00490 offcore_response.all_pf_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063B800490 offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0604000490 offcore_response.all_pf_rfo.l3_miss.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBC000120 offcore_response.all_pf_rfo.l3_miss.remote_hit_forward umask=0x1,period=100003,event=0xb7,offcore_rsp=0x083FC00120 offcore_response.all_pf_rfo.l3_miss.remote_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x103FC00120 offcore_response.all_pf_rfo.l3_miss.snoop_miss_or_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063FC00120 offcore_response.all_pf_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063B800120 offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0604000120 offcore_response.all_data_rd.l3_miss.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBC000491 offcore_response.all_data_rd.l3_miss.remote_hit_forward umask=0x1,period=100003,event=0xb7,offcore_rsp=0x083FC00491 offcore_response.all_data_rd.l3_miss.remote_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x103FC00491 offcore_response.all_data_rd.l3_miss.snoop_miss_or_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063FC00491 offcore_response.all_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063B800491 offcore_response.all_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0604000491 offcore_response.all_rfo.l3_miss.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBC000122 offcore_response.all_rfo.l3_miss.remote_hit_forward umask=0x1,period=100003,event=0xb7,offcore_rsp=0x083FC00122 offcore_response.all_rfo.l3_miss.remote_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x103FC00122 offcore_response.all_rfo.l3_miss.snoop_miss_or_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063FC00122 offcore_response.all_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063B800122 offcore_response.all_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd core_power.lvl0_turbo_license umask=0x7,period=200003,event=0x28 Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes core_power.lvl1_turbo_license umask=0x18,period=200003,event=0x28 Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions core_power.lvl2_turbo_license umask=0x20,period=200003,event=0x28 Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server michroarchtecture). This includes high current AVX 512-bit instructions core_power.throttle umask=0x40,period=200003,event=0x28 Core cycles the core was throttled due to a pending power level request Core cycles the out-of-order engine was throttled due to a pending power level request core_snoop_response.rsp_ihiti umask=0x1,period=2000003,event=0xef core_snoop_response.rsp_ihitfse umask=0x2,period=2000003,event=0xef core_snoop_response.rsp_shitfse umask=0x4,period=2000003,event=0xef core_snoop_response.rsp_sfwdm umask=0x8,period=2000003,event=0xef core_snoop_response.rsp_ifwdm umask=0x10,period=2000003,event=0xef core_snoop_response.rsp_ifwdfe umask=0x20,period=2000003,event=0xef core_snoop_response.rsp_sfwdfe umask=0x40,period=2000003,event=0xef idi_misc.wb_upgrade umask=0x2,period=100003,event=0xfe Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly idi_misc.wb_downgrade umask=0x4,period=100003,event=0xfe Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly umask=0x1,cmask=1,period=2000003,event=0x14 edge=1,umask=0x0,cmask=1,period=100007,event=0x3c edge=1,inv=1,umask=0x1,cmask=1,period=2000003,event=0x5e umask=0x10,cmask=16,period=2000003,event=0xa3 umask=0x14,cmask=20,period=2000003,event=0xa3 inv=1,umask=0x2,cmask=1,period=2000003,event=0xb1 inv=1,umask=0x1,cmask=10,period=2000003,event=0xc0 inv=1,umask=0x2,cmask=10,period=2000003,event=0xc2 inv=1,umask=0x2,cmask=1,period=2000003,event=0xc2 skx metrics (( 1 * ( fp_arith_inst_retired.scalar_single + fp_arith_inst_retired.scalar_double ) + 2 * fp_arith_inst_retired.128b_packed_double + 4 * ( fp_arith_inst_retired.128b_packed_single + fp_arith_inst_retired.256b_packed_double ) + 8 * ( fp_arith_inst_retired.256b_packed_single + fp_arith_inst_retired.512b_packed_double ) + 16 * fp_arith_inst_retired.512b_packed_single )) / cycles (( 1 * ( fp_arith_inst_retired.scalar_single + fp_arith_inst_retired.scalar_double ) + 2 * fp_arith_inst_retired.128b_packed_double + 4 * ( fp_arith_inst_retired.128b_packed_single + fp_arith_inst_retired.256b_packed_double ) + 8 * ( fp_arith_inst_retired.256b_packed_single + fp_arith_inst_retired.512b_packed_double ) + 16 * fp_arith_inst_retired.512b_packed_single )) / (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )) Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory) 1000 * l2_lines_out.silent / inst_retired.any L2_Evictions_Silent_PKI Rate of non silent evictions from the L2 cache per Kilo instruction 1000 * l2_lines_out.non_silent / inst_retired.any L2_Evictions_NonSilent_PKI ( (( 1 * ( fp_arith_inst_retired.scalar_single + fp_arith_inst_retired.scalar_double ) + 2 * fp_arith_inst_retired.128b_packed_double + 4 * ( fp_arith_inst_retired.128b_packed_single + fp_arith_inst_retired.256b_packed_double ) + 8 * ( fp_arith_inst_retired.256b_packed_single + fp_arith_inst_retired.512b_packed_double ) + 16 * fp_arith_inst_retired.512b_packed_single )) / 1000000000 ) / duration_time 1000000000 * ( cha@event\=0x36\\\,umask\=0x21@ / cha@event\=0x35\\\,umask\=0x21@ ) / ( cha_0@event\=0x0@ / duration_time ) cha@event\=0x36\\\,umask\=0x21@ / cha@event\=0x36\\\,umask\=0x21\\\,thresh\=1@ cha_0@event\=0x0@ unc_m_act_count.wr DRAM Page Activate commands sent due to a write request. Unit: uncore_imc Counts DRAM Page Activate commands sent on this channel due to a write request to the iMC (Memory Controller). Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS (Column Access Select) command unc_m_cas_count.all umask=0xF,event=0x4 All DRAM CAS Commands issued. Unit: uncore_imc Counts all CAS (Column Address Select) commands issued to DRAM per memory channel. CAS commands are issued to specify the address to read or write on DRAM, so this event increments for every read and write. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not unc_m_cas_count.rd_reg umask=0x1,event=0x4 All DRAM Read CAS Commands issued (does not include underfills) . Unit: uncore_imc Counts CAS (Column Access Select) regular read commands issued to DRAM on a per channel basis. CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every regular read. This event only counts regular reads and does not includes underfill reads due to partial write requests. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not unc_m_cas_count.rd_underfill umask=0x2,event=0x4 DRAM Underfill Read CAS Commands issued. Unit: uncore_imc Counts CAS (Column Access Select) underfill read commands issued to DRAM due to a partial write, on a per channel basis. CAS commands are issued to specify the address to read or write on DRAM, and this command counts underfill reads. Partial writes must be completed by first reading in the underfill from DRAM and then merging in the partial write data before writing the full line back to DRAM. This event will generally count about the same as the number of partial writes, but may be slightly less because of partials hitting in the WPQ (due to a previous write request) unc_m_rpq_inserts Read Pending Queue Allocations. Unit: uncore_imc Counts the number of read requests allocated into the Read Pending Queue (RPQ). This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. The requests deallocate after the read CAS command has been issued to DRAM. This event counts both Isochronous and non-Isochronous requests which were issued to the RPQ Read Pending Queue Occupancy. Unit: uncore_imc Counts the number of entries in the Read Pending Queue (RPQ) at each cycle. This can then be used to calculate both the average occupancy of the queue (in conjunction with the number of cycles not empty) and the average latency in the queue (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate from the RPQ after the CAS command has been issued to memory unc_m_wpq_inserts event=0x20 Write Pending Queue Allocations. Unit: uncore_imc Counts the number of writes requests allocated into the Write Pending Queue (WPQ). The WPQ is used to schedule writes out to the memory controller and to track the requests. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC (Memory Controller). The write requests deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC unc_m_wpq_occupancy event=0x81 Write Pending Queue Occupancy. Unit: uncore_imc Counts the number of entries in the Write Pending Queue (WPQ) at each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule writes out to the memory controller and to track the requests unc_cha_clockticks Uncore cache clock ticks. Unit: uncore_cha uncore other uncore_cha umask=0x21,event=0x35,config1=0x40e33 LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.ia_miss. Unit: uncore_cha umask=0x21,event=0x35,config1=0x40040e33 MMIO reads. Derived from unc_cha_tor_inserts.ia_miss. Unit: uncore_cha umask=0x21,event=0x35,config1=0x40041e33 MMIO writes. Derived from unc_cha_tor_inserts.ia_miss. Unit: uncore_cha umask=0x21,event=0x35,config1=0x41833 Streaming stores (full cache line). Derived from unc_cha_tor_inserts.ia_miss. Unit: uncore_cha umask=0x21,event=0x35,config1=0x41a33 Streaming stores (partial cache line). Derived from unc_cha_tor_inserts.ia_miss. Unit: uncore_cha unc_cha_requests.reads umask=0x03,event=0x50 read requests from home agent. Unit: uncore_cha unc_cha_requests.reads_local umask=0x01,event=0x50 read requests from local home agent. Unit: uncore_cha unc_cha_requests.reads_remote umask=0x02,event=0x50 read requests from remote home agent. Unit: uncore_cha unc_cha_requests.writes umask=0x0C,event=0x50 write requests from home agent. Unit: uncore_cha unc_cha_requests.writes_local umask=0x04,event=0x50 write requests from local home agent. Unit: uncore_cha unc_cha_requests.writes_remote umask=0x08,event=0x50 write requests from remote home agent. Unit: uncore_cha upi_data_bandwidth_tx umask=0x0F,event=0x2 UPI interconnect send bandwidth for payload. Derived from unc_upi_txl_flits.all_data. Unit: uncore_upi ll uncore_upi ll 7.11E-06Bytes fc_mask=0x07,ch_mask=0x01,umask=0x04,event=0x83,ch_mask=0x1f PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0. Unit: uncore_iio uncore_iio 4Bytes unc_iio_data_req_of_cpu.mem_read.part0 + unc_iio_data_req_of_cpu.mem_read.part1 + unc_iio_data_req_of_cpu.mem_read.part2 + unc_iio_data_req_of_cpu.mem_read.part3 LLC_MISSES.PCIE_READ fc_mask=0x07,ch_mask=0x01,umask=0x01,event=0x83,ch_mask=0x1f PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0. Unit: uncore_iio unc_iio_data_req_of_cpu.mem_write.part0 +unc_iio_data_req_of_cpu.mem_write.part1 +unc_iio_data_req_of_cpu.mem_write.part2 +unc_iio_data_req_of_cpu.mem_write.part3 LLC_MISSES.PCIE_WRITE unc_iio_data_req_of_cpu.mem_write.part0 fc_mask=0x07,ch_mask=0x01,umask=0x01,event=0x83 PCI Express bandwidth writing at IIO, part 0. Unit: uncore_iio unc_iio_data_req_of_cpu.mem_write.part1 fc_mask=0x07,ch_mask=0x02,umask=0x01,event=0x83 PCI Express bandwidth writing at IIO, part 1. Unit: uncore_iio unc_iio_data_req_of_cpu.mem_write.part2 fc_mask=0x07,ch_mask=0x04,umask=0x01,event=0x83 PCI Express bandwidth writing at IIO, part 2. Unit: uncore_iio unc_iio_data_req_of_cpu.mem_write.part3 fc_mask=0x07,ch_mask=0x08,umask=0x01,event=0x83 PCI Express bandwidth writing at IIO, part 3. Unit: uncore_iio unc_iio_data_req_of_cpu.mem_read.part0 fc_mask=0x07,ch_mask=0x01,umask=0x04,event=0x83 PCI Express bandwidth reading at IIO, part 0. Unit: uncore_iio unc_iio_data_req_of_cpu.mem_read.part1 fc_mask=0x07,ch_mask=0x02,umask=0x04,event=0x83 PCI Express bandwidth reading at IIO, part 1. Unit: uncore_iio unc_iio_data_req_of_cpu.mem_read.part2 fc_mask=0x07,ch_mask=0x04,umask=0x04,event=0x83 PCI Express bandwidth reading at IIO, part 2. Unit: uncore_iio unc_iio_data_req_of_cpu.mem_read.part3 fc_mask=0x07,ch_mask=0x08,umask=0x04,event=0x83 PCI Express bandwidth reading at IIO, part 3. Unit: uncore_iio unc_cha_core_snp.core_gtone umask=0x42,event=0x33 Core Cross Snoops Issued; Multiple Core Requests. Unit: uncore_cha Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) unc_cha_core_snp.evict_gtone umask=0x82,event=0x33 Core Cross Snoops Issued; Multiple Eviction. Unit: uncore_cha unc_cha_dir_lookup.no_snp umask=0x02,event=0x53 Multi-socket cacheline Directory state lookups; Snoop Not Needed. Unit: uncore_cha Counts transactions that looked into the multi-socket cacheline Directory state, and therefore did not send a snoop because the Directory indicated it was not needed unc_cha_dir_lookup.snp umask=0x01,event=0x53 Multi-socket cacheline Directory state lookups; Snoop Needed. Unit: uncore_cha Counts transactions that looked into the multi-socket cacheline Directory state, and sent one or more snoops, because the Directory indicated it was needed unc_cha_dir_update.ha umask=0x01,event=0x54 Multi-socket cacheline Directory state updates; Directory Updated memory write from the HA pipe. Unit: uncore_cha Counts only multi-socket cacheline Directory state updates memory writes issued from the HA pipe. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines unc_cha_dir_update.tor umask=0x02,event=0x54 Multi-socket cacheline Directory state updates; Directory Updated memory write from TOR pipe. Unit: uncore_cha Counts only multi-socket cacheline Directory state updates due to memory writes issued from the TOR pipe which are the result of remote transaction hitting the SF/LLC and returning data Core2Core. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines unc_cha_hitme_hit.ex_rds umask=0x01,event=0x5f Read request from a remote socket which hit in the HitMe Cache to a line In the E state. Unit: uncore_cha Counts read requests from a remote socket which hit in the HitME cache (used to cache the multi-socket Directory state) to a line in the E(Exclusive) state. This includes the following read opcodes (RdCode, RdData, RdDataMigratory, RdCur, RdInv*, Inv*) unc_cha_imc_reads_count.normal umask=0x01,event=0x59 Normal priority reads issued to the memory controller from the CHA. Unit: uncore_cha Counts when a normal (Non-Isochronous) read is issued to any of the memory controller channels from the CHA unc_cha_imc_writes_count.full umask=0x01,event=0x5b CHA to iMC Full Line Writes Issued; Full Line Non-ISOCH. Unit: uncore_cha Counts when a normal (Non-Isochronous) full line write is issued from the CHA to the any of the memory controller channels unc_cha_misc.rfo_hit_s umask=0x08,event=0x39 Number of times that an RFO hit in S state. Unit: uncore_cha Counts when a RFO (the Read for Ownership issued before a write) request hit a cacheline in the S (Shared) state unc_cha_requests.invitoe_local umask=0x10,event=0x50 Local requests for exclusive ownership of a cache line without receiving data. Unit: uncore_cha Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA unc_cha_requests.invitoe_remote umask=0x20,event=0x50 Local requests for exclusive ownership of a cache line without receiving data. Unit: uncore_cha Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA unc_cha_snoop_resp.rspcnflcts umask=0x40,event=0x5c RspCnflct* Snoop Responses Received. Unit: uncore_cha Counts when a a transaction with the opcode type RspCnflct* Snoop Response was received. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent. This triggers conflict resolution hardware. This covers both the opcode RspCnflct and RspCnflctWbI unc_cha_snoop_resp.rspi umask=0x01,event=0x5c RspI Snoop Responses Received. Unit: uncore_cha Counts when a transaction with the opcode type RspI Snoop Response was received which indicates the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO: the Read for Ownership issued before a write hits non-modified data) unc_cha_snoop_resp.rspifwd umask=0x04,event=0x5c RspIFwd Snoop Responses Received. Unit: uncore_cha Counts when a a transaction with the opcode type RspIFwd Snoop Response was received which indicates a remote caching agent forwarded the data and the requesting agent is able to acquire the data in E (Exclusive) or M (modified) states. This is commonly returned with RFO (the Read for Ownership issued before a write) transactions. The snoop could have either been to a cacheline in the M,E,F (Modified, Exclusive or Forward) states unc_cha_snoop_resp.rspsfwd umask=0x08,event=0x5c RspSFwd Snoop Responses Received. Unit: uncore_cha Counts when a a transaction with the opcode type RspSFwd Snoop Response was received which indicates a remote caching agent forwarded the data but held on to its current copy. This is common for data and code reads that hit in a remote socket in E (Exclusive) or F (Forward) state unc_cha_snoop_resp.rsp_fwd_wb umask=0x20,event=0x5c Rsp*Fwd*WB Snoop Responses Received. Unit: uncore_cha Counts when a transaction with the opcode type Rsp*Fwd*WB Snoop Response was received which indicates the data was written back to it's home socket, and the cacheline was forwarded to the requestor socket. This snoop response is only used in >= 4 socket systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to it's home socket to be written back to memory unc_cha_snoop_resp.rsp_wbwb umask=0x10,event=0x5c Rsp*WB Snoop Responses Received. Unit: uncore_cha Counts when a transaction with the opcode type Rsp*WB Snoop Response was received which indicates which indicates the data was written back to it's home. This is returned when a non-RFO request hits a cacheline in the Modified state. The Cache can either downgrade the cacheline to a S (Shared) or I (Invalid) state depending on how the system has been configured. This response will also be sent when a cache requests E (Exclusive) ownership of a cache line without receiving data, because the cache must acquire ownership unc_iio_clockticks Clockticks of the IIO Traffic Controller. Unit: uncore_iio Counts clockticks of the 1GHz trafiic controller clock in the IIO unit unc_iio_data_req_by_cpu.mem_read.part0 fc_mask=0x07,ch_mask=0x01,umask=0x04,event=0xc0 Read request for 4 bytes made by the CPU to IIO Part0. Unit: uncore_iio Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) to the MMIO space of a card on IIO Part0. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.mem_read.part1 fc_mask=0x07,ch_mask=0x02,umask=0x04,event=0xc0 Read request for 4 bytes made by the CPU to IIO Part1. Unit: uncore_iio Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.mem_read.part2 fc_mask=0x07,ch_mask=0x04,umask=0x04,event=0xc0 Read request for 4 bytes made by the CPU to IIO Part2. Unit: uncore_iio Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.mem_read.part3 fc_mask=0x07,ch_mask=0x08,umask=0x04,event=0xc0 Read request for 4 bytes made by the CPU to IIO Part3. Unit: uncore_iio Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.mem_write.part0 fc_mask=0x07,ch_mask=0x01,umask=0x01,event=0xc0 Write request of 4 bytes made to IIO Part0 by the CPU. Unit: uncore_iio Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.mem_write.part1 fc_mask=0x07,ch_mask=0x02,umask=0x01,event=0xc0 Write request of 4 bytes made to IIO Part1 by the CPU. Unit: uncore_iio Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.mem_write.part2 fc_mask=0x07,ch_mask=0x04,umask=0x01,event=0xc0 Write request of 4 bytes made to IIO Part2 by the CPU . Unit: uncore_iio Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part2 by a unit on the main die (generally a core). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.mem_write.part3 fc_mask=0x07,ch_mask=0x08,umask=0x01,event=0xc0 Write request of 4 bytes made to IIO Part3 by the CPU . Unit: uncore_iio Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part3 by a unit on the main die (generally a core). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.mem_read.part0 fc_mask=0x07,ch_mask=0x01,umask=0x04,event=0xc1 Read request for up to a 64 byte transaction is made by the CPU to IIO Part0. Unit: uncore_iio Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) to the MMIO space of a card on IIO Part0. In the general case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.mem_read.part1 fc_mask=0x07,ch_mask=0x02,umask=0x04,event=0xc1 Read request for up to a 64 byte transaction is made by the CPU to IIO Part1. Unit: uncore_iio Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.mem_read.part2 fc_mask=0x07,ch_mask=0x04,umask=0x04,event=0xc1 Read request for up to a 64 byte transaction is made by the CPU to IIO Part2. Unit: uncore_iio Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.mem_read.part3 fc_mask=0x07,ch_mask=0x08,umask=0x04,event=0xc1 Read request for up to a 64 byte transaction is made by the CPU to IIO Part3. Unit: uncore_iio Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.mem_write.part0 fc_mask=0x07,ch_mask=0x01,umask=0x01,event=0xc1 Write request of up to a 64 byte transaction is made to IIO Part0 by the CPU. Unit: uncore_iio Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.mem_write.part1 fc_mask=0x07,ch_mask=0x02,umask=0x01,event=0xc1 Write request of up to a 64 byte transaction is made to IIO Part1 by the CPU. Unit: uncore_iio Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.mem_write.part2 fc_mask=0x07,ch_mask=0x04,umask=0x01,event=0xc1 Write request of up to a 64 byte transaction is made to IIO Part2 by the CPU . Unit: uncore_iio Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part2 by a unit on the main die (generally a core). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.mem_write.part3 fc_mask=0x07,ch_mask=0x08,umask=0x01,event=0xc1 Write request of up to a 64 byte transaction is made to IIO Part3 by the CPU . Unit: uncore_iio Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part3 by a unit on the main die (generally a core). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.mem_read.part0 fc_mask=0x07,ch_mask=0x01,umask=0x04,event=0x84 Read request for up to a 64 byte transaction is made by IIO Part0 to Memory. Unit: uncore_iio Counts every read request for up to a 64 byte transaction of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.mem_read.part1 fc_mask=0x07,ch_mask=0x02,umask=0x04,event=0x84 Read request for up to a 64 byte transaction is made by IIO Part1 to Memory. Unit: uncore_iio Counts every read request for up to a 64 byte transaction of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.mem_read.part2 fc_mask=0x07,ch_mask=0x04,umask=0x04,event=0x84 Read request for up to a 64 byte transaction is made by IIO Part2 to Memory. Unit: uncore_iio Counts every read request for up to a 64 byte transaction of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.mem_read.part3 fc_mask=0x07,ch_mask=0x08,umask=0x04,event=0x84 Read request for up to a 64 byte transaction is made by IIO Part3 to Memory. Unit: uncore_iio Counts every read request for up to a 64 byte transaction of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.mem_write.part0 fc_mask=0x07,ch_mask=0x01,umask=0x01,event=0x84 Write request of up to a 64 byte transaction is made by IIO Part0 to Memory. Unit: uncore_iio Counts every write request of up to a 64 byte transaction of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.mem_write.part1 fc_mask=0x07,ch_mask=0x02,umask=0x01,event=0x84 Write request of up to a 64 byte transaction is made by IIO Part1 to Memory. Unit: uncore_iio Counts every write request of up to a 64 byte transaction of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.mem_write.part2 fc_mask=0x07,ch_mask=0x04,umask=0x01,event=0x84 Write request of up to a 64 byte transaction is made by IIO Part2 to Memory. Unit: uncore_iio Counts every write request of up to a 64 byte transaction of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.mem_write.part3 fc_mask=0x07,ch_mask=0x08,umask=0x01,event=0x84 Write request of up to a 64 byte transaction is made by IIO Part3 to Memory. Unit: uncore_iio Counts every write request of up to a 64 byte transaction of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_m2m_bypass_m2m_egress.not_taken umask=0x2,event=0x22 Traffic in which the M2M to iMC Bypass was not taken. Unit: uncore_m2m Counts traffic in which the M2M (Mesh to Memory) to iMC (Memory Controller) bypass was not taken uncore_m2m unc_m2m_direct2core_not_taken_dirstate event=0x24 Cycles when direct to core mode (which bypasses the CHA) was disabled. Unit: uncore_m2m Counts cycles when direct to core mode (which bypasses the CHA) was disabled unc_m2m_direct2core_taken event=0x23 Messages sent direct to core (bypassing the CHA). Unit: uncore_m2m Counts when messages were sent direct to core (bypassing the CHA) unc_m2m_direct2core_txn_override event=0x25 Number of reads in which direct to core transaction were overridden. Unit: uncore_m2m Counts reads in which direct to core transactions (which would have bypassed the CHA) were overridden unc_m2m_direct2upi_not_taken_credits event=0x28 Number of reads in which direct to Intel UPI transactions were overridden. Unit: uncore_m2m Counts reads in which direct to Intel Ultra Path Interconnect (UPI) transactions (which would have bypassed the CHA) were overridden unc_m2m_direct2upi_not_taken_dirstate event=0x27 Cycles when direct to Intel UPI was disabled. Unit: uncore_m2m Counts cycles when the ability to send messages direct to the Intel Ultra Path Interconnect (bypassing the CHA) was disabled unc_m2m_direct2upi_taken event=0x26 Messages sent direct to the Intel UPI. Unit: uncore_m2m Counts when messages were sent direct to the Intel Ultra Path Interconnect (bypassing the CHA) unc_m2m_direct2upi_txn_override event=0x29 Number of reads that a message sent direct2 Intel UPI was overridden. Unit: uncore_m2m Counts when a read message that was sent direct to the Intel Ultra Path Interconnect (bypassing the CHA) was overridden unc_m2m_directory_lookup.any umask=0x1,event=0x2d Multi-socket cacheline Directory lookups (any state found). Unit: uncore_m2m Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state, and found the cacheline marked in Any State (A, I, S or unused) unc_m2m_directory_lookup.state_a umask=0x8,event=0x2d Multi-socket cacheline Directory lookups (cacheline found in A state) . Unit: uncore_m2m Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state, and found the cacheline marked in the A (SnoopAll) state, indicating the cacheline is stored in another socket in any state, and we must snoop the other sockets to make sure we get the latest data. The data may be stored in any state in the local socket unc_m2m_directory_lookup.state_i umask=0x2,event=0x2d Multi-socket cacheline Directory lookup (cacheline found in I state) . Unit: uncore_m2m Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state , and found the cacheline marked in the I (Invalid) state indicating the cacheline is not stored in another socket, and so there is no need to snoop the other sockets for the latest data. The data may be stored in any state in the local socket unc_m2m_directory_lookup.state_s umask=0x4,event=0x2d Multi-socket cacheline Directory lookup (cacheline found in S state) . Unit: uncore_m2m Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state , and found the cacheline marked in the S (Shared) state indicating the cacheline is either stored in another socket in the S(hared) state , and so there is no need to snoop the other sockets for the latest data. The data may be stored in any state in the local socket unc_m2m_directory_update.a2i umask=0x20,event=0x2e Multi-socket cacheline Directory update from A to I. Unit: uncore_m2m Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from A (SnoopAll) to I (Invalid) unc_m2m_directory_update.a2s umask=0x40,event=0x2e Multi-socket cacheline Directory update from A to S. Unit: uncore_m2m Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from A (SnoopAll) to S (Shared) unc_m2m_directory_update.any umask=0x1,event=0x2e Multi-socket cacheline Directory update from/to Any state . Unit: uncore_m2m Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory to a new state unc_m2m_directory_update.i2a umask=0x4,event=0x2e Multi-socket cacheline Directory update from I to A. Unit: uncore_m2m Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from I (Invalid) to A (SnoopAll) unc_m2m_directory_update.i2s umask=0x2,event=0x2e Multi-socket cacheline Directory update from I to S. Unit: uncore_m2m Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from I (Invalid) to S (Shared) unc_m2m_directory_update.s2a umask=0x10,event=0x2e Multi-socket cacheline Directory update from S to A. Unit: uncore_m2m Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from S (Shared) to A (SnoopAll) unc_m2m_directory_update.s2i umask=0x8,event=0x2e Multi-socket cacheline Directory update from S to I. Unit: uncore_m2m Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from S (Shared) to I (Invalid) unc_m2m_imc_reads.all umask=0x4,event=0x37 Reads to iMC issued. Unit: uncore_m2m Counts when the M2M (Mesh to Memory) issues reads to the iMC (Memory Controller) unc_m2m_imc_reads.normal Reads to iMC issued at Normal Priority (Non-Isochronous). Unit: uncore_m2m Counts when the M2M (Mesh to Memory) issues reads to the iMC (Memory Controller). It only counts normal priority non-isochronous reads unc_m2m_imc_writes.all umask=0x10,event=0x38 Writes to iMC issued. Unit: uncore_m2m Counts when the M2M (Mesh to Memory) issues writes to the iMC (Memory Controller) unc_m2m_imc_writes.partial umask=0x2,event=0x38 Partial Non-Isochronous writes to the iMC. Unit: uncore_m2m Counts when the M2M (Mesh to Memory) issues partial writes to the iMC (Memory Controller). It only counts normal priority non-isochronous writes unc_m2m_prefcam_demand_promotions event=0x56 Prefecth requests that got turn into a demand request. Unit: uncore_m2m Counts when the M2M (Mesh to Memory) promotes a outstanding request in the prefetch queue due to a subsequent demand read request that entered the M2M with the same address. Explanatory Side Note: The Prefecth queue is made of CAM (Content Addressable Memory) unc_m2m_prefcam_inserts event=0x57 Inserts into the Memory Controller Prefetch Queue. Unit: uncore_m2m Counts when the M2M (Mesh to Memory) receives a prefetch request and inserts it into its outstanding prefetch queue. Explanatory Side Note: the prefect queue is made from CAM: Content Addressable Memory unc_m2m_rxc_ad_inserts AD Ingress (from CMS) Queue Inserts. Unit: uncore_m2m Counts when the a new entry is Received(RxC) and then added to the AD (Address Ring) Ingress Queue from the CMS (Common Mesh Stop). This is generally used for reads, and unc_m3upi_upi_prefetch_spawn Prefetches generated by the flow control queue of the M3UPI unit. Unit: uncore_m3upi Count cases where flow control queue that sits between the Intel Ultra Path Interconnect (UPI) and the mesh spawns a prefetch to the iMC (Memory Controller) uncore_m3upi unc_upi_clockticks Clocks of the Intel Ultra Path Interconnect (UPI). Unit: uncore_upi ll Counts clockticks of the fixed frequency clock controlling the Intel Ultra Path Interconnect (UPI). This clock runs at1/8th the 'GT/s' speed of the UPI link. For example, a 9.6GT/s link will have a fixed Frequency of 1.2 Ghz unc_upi_direct_attempts.d2c umask=0x1,event=0x12 Data Response packets that go direct to core. Unit: uncore_upi ll Counts Data Response (DRS) packets that attempted to go direct to core bypassing the CHA unc_upi_direct_attempts.d2u umask=0x2,event=0x12 Data Response packets that go direct to Intel UPI. Unit: uncore_upi ll Counts Data Response (DRS) packets that attempted to go direct to Intel Ultra Path Interconnect (UPI) bypassing the CHA unc_upi_l1_power_cycles event=0x21 Cycles Intel UPI is in L1 power mode (shutdown). Unit: uncore_upi ll Counts cycles when the Intel Ultra Path Interconnect (UPI) is in L1 power mode. L1 is a mode that totally shuts down the UPI link. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another, this event only coutns when both links are shutdown unc_upi_rxl0p_power_cycles Cycles the Rx of the Intel UPI is in L0p power mode. Unit: uncore_upi ll Counts cycles when the the receive side (Rx) of the Intel Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power unc_upi_rxl_bypassed.slot0 umask=0x1,event=0x31 FLITs received which bypassed the Slot0 Receive Buffer. Unit: uncore_upi ll Counts incoming FLITs (FLow control unITs) which bypassed the slot0 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency unc_upi_rxl_bypassed.slot1 umask=0x2,event=0x31 Counts incoming FLITs (FLow control unITs) which bypassed the slot1 RxQ buffer (Receive Queue) and passed directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency unc_upi_rxl_bypassed.slot2 umask=0x4,event=0x31 Counts incoming FLITs (FLow control unITs) which bypassed the slot2 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency unc_upi_rxl_flits.all_data umask=0x0F,event=0x3 Valid data FLITs received from any slot. Unit: uncore_upi ll Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) received from any of the 3 Intel Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unit unc_upi_rxl_flits.all_null umask=0x27,event=0x3 Null FLITs received from any slot. Unit: uncore_upi ll Counts null FLITs (80 bit FLow control unITs) received from any of the 3 Intel Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unit unc_upi_rxl_flits.non_data umask=0x97,event=0x3 Protocol header and credit FLITs received from any slot. Unit: uncore_upi ll Counts protocol header and credit FLITs (80 bit FLow control unITs) received from any of the 3 UPI slots on this UPI unit unc_upi_txl0p_power_cycles Cycles in which the Tx of the Intel Ultra Path Interconnect (UPI) is in L0p power mode. Unit: uncore_upi ll Counts cycles when the transmit side (Tx) of the Intel Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power unc_upi_txl_bypassed event=0x41 FLITs that bypassed the TxL Buffer. Unit: uncore_upi ll Counts incoming FLITs (FLow control unITs) which bypassed the TxL(transmit) FLIT buffer and pass directly out the UPI Link. Generally, when data is transmitted across the Intel Ultra Path Interconnect (UPI), it will bypass the TxQ and pass directly to the link. However, the TxQ will be used in L0p (Low Power) mode and (Link Layer Retry) LLR mode, increasing latency to transfer out to the link unc_upi_txl_flits.all_null umask=0x27,event=0x2 Null FLITs transmitted from any slot. Unit: uncore_upi ll Counts null FLITs (80 bit FLow control unITs) transmitted via any of the 3 Intel Ulra Path Interconnect (UPI) slots on this UPI unit unc_upi_txl_flits.idle umask=0x47,event=0x2 Idle FLITs transmitted. Unit: uncore_upi ll Counts when the Intel Ultra Path Interconnect(UPI) transmits an idle FLIT(80 bit FLow control unITs). Every UPI cycle must be sending either data FLITs, protocol/credit FLITs or idle FLITs unc_upi_txl_flits.non_data umask=0x97,event=0x2 Protocol header and credit FLITs transmitted across any slot. Unit: uncore_upi ll Counts protocol header and credit FLITs (80 bit FLow control unITs) transmitted across any of the 3 UPI (Ultra Path Interconnect) slots on this UPI unit umask=0x10,cmask=1,period=100003,event=0x8 umask=0x10,cmask=1,period=100003,event=0x49 umask=0x10,cmask=1,period=100003,event=0x85 offcore_response.other.supplier_none.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400028000 This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD offcore_response.demand_rfo.pmm_hit_local_pmm.snoop_not_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE offcore_response.all_data_rd.l3_hit_f.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP period=200003,umask=0x27,event=0x24 offcore_response.all_data_rd.l3_hit_m.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP offcore_response.pf_l2_data_rd.l3_hit_m.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_MISS period=50021,umask=0x4,event=0xd1 Counts retired load instructions with at least one uop that hit in the L3 cache Supports address when precise (Precise event) offcore_response.demand_data_rd.pmm_hit_local_pmm.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP offcore_response.all_data_rd.l3_hit.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD period=200003,umask=0x40,event=0xf0 period=100003,umask=0x1f,event=0xf1 offcore_response.demand_rfo.l3_hit_f.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP offcore_response.pf_l3_data_rd.l3_hit_m.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NONE offcore_response.all_reads.l3_hit_e.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08000807F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD period=200003,umask=0x1,event=0xf2 offcore_response.pf_l3_data_rd.l3_hit_e.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED offcore_response.pf_l2_rfo.l3_hit_s.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP offcore_response.demand_data_rd.l3_hit_f.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP offcore_response.demand_data_rd.l3_hit_s.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD offcore_response.demand_code_rd.l3_hit_f.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l3_data_rd.l3_hit_s.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP offcore_response.pf_l2_rfo.l3_hit_f.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE offcore_response.pf_l3_rfo.l3_hit_f.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP offcore_response.pf_l2_rfo.l3_hit_m.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP offcore_response.all_pf_data_rd.l3_hit_f.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80028000 This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.ANY_SNOOP offcore_response.all_reads.pmm_hit_local_pmm.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F804007F7 This event is deprecated. Refer to new event OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP offcore_response.pf_l1d_and_sw.l3_hit_s.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_MISS offcore_response.pf_l1d_and_sw.supplier_none.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_MISS offcore_response.pf_l1d_and_sw.l3_hit_m.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD period=200003,umask=0x3f,event=0x24 period=100007,umask=0x8,event=0xd3 Retired load instructions whose data sources was forwarded from a remote cache Supports address when precise offcore_response.all_pf_data_rd.pmm_hit_local_pmm.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP offcore_response.all_pf_data_rd.pmm_hit_local_pmm.snoop_not_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED offcore_response.all_data_rd.supplier_none.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD period=20011,umask=0x2,event=0xd2 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP offcore_response.all_rfo.l3_hit_s.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD period=100003,umask=0x8,event=0xd1 offcore_response.other.l3_hit_s.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800108000 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD offcore_response.all_rfo.supplier_none.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020122 This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS offcore_response.pf_l2_data_rd.l3_hit_f.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.SNOOP_NONE offcore_response.pf_l2_rfo.l3_hit_s.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE offcore_response.demand_rfo.pmm_hit_local_pmm.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200048000 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.SNOOP_MISS offcore_response.pf_l1d_and_sw.l3_hit_e.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD offcore_response.all_rfo.l3_hit_f.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE offcore_response.demand_data_rd.l3_hit_m.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED offcore_response.all_rfo.l3_hit_e.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS offcore_response.all_rfo.supplier_none.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020122 This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD offcore_response.all_rfo.l3_hit_f.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD any=1,cmask=1,period=2000003,umask=0x1,event=0x48 offcore_response.other.l3_hit_f.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400208000 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l2_data_rd.l3_hit_s.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE offcore_response.pf_l3_data_rd.supplier_none.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE offcore_response.all_data_rd.l3_hit_s.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE offcore_response.pf_l2_rfo.l3_hit_f.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP period=100003,umask=0x80,event=0xb0 offcore_response.pf_l2_data_rd.l3_hit_f.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED offcore_response.all_pf_rfo.l3_hit_f.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED offcore_response.all_pf_rfo.l3_hit_m.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS offcore_response.other.l3_hit_m.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100048000 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED offcore_response.other.supplier_none.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000028000 This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE offcore_response.pf_l1d_and_sw.l3_hit_f.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD period=100007,umask=0x4,event=0xd4 mem_load_l3_miss_retired.remote_pmm period=100007,umask=0x10,event=0xd3 Retired load instructions with remote Intel® Optane™ DC persistent memory as the data source where the data request missed all caches. Precise event Supports address when precise (Precise event) Counts retired load instructions with remote Intel® Optane™ DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode). Precise event Supports address when precise (Precise event) offcore_response.all_rfo.l3_hit_e.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l1d_and_sw.l3_hit_e.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP offcore_response.all_reads.l3_hit_e.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02000807F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD offcore_response.demand_rfo.l3_hit_e.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED offcore_response.pf_l2_data_rd.l3_hit_e.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD offcore_response.demand_data_rd.pmm_hit_local_pmm.snoop_not_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.ANY_RESPONSE period=100003,umask=0x8,event=0xd2 offcore_response.all_rfo.pmm_hit_local_pmm.snoop_not_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400122 This event is deprecated. Refer to new event OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED period=200003,umask=0xe1,event=0x24 offcore_response.pf_l2_rfo.l3_hit_f.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD offcore_response.all_data_rd.l3_hit_m.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS offcore_response.pf_l2_data_rd.l3_hit_m.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200028000 This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.SNOOP_MISS cmask=1,period=2000003,umask=0x4,event=0x60 offcore_response.demand_data_rd.l3_hit_s.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED period=100003,umask=0x10,event=0xf4 offcore_response.pf_l3_rfo.l3_hit_f.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.SNOOP_MISS offcore_response.demand_rfo.l3_hit_s.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD period=200003,umask=0xc4,event=0x24 offcore_response.all_pf_rfo.l3_hit_f.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NONE offcore_response.all_reads.l3_hit_s.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10001007F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE offcore_response.all_rfo.l3_hit_m.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l2_data_rd.l3_hit_s.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD offcore_response.all_reads.l3_hit_s.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02001007F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.SNOOP_MISS offcore_response.all_pf_rfo.supplier_none.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD offcore_response.all_pf_rfo.l3_hit_m.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD offcore_response.pf_l2_rfo.l3_hit_m.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD offcore_response.all_reads.l3_hit_s.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08001007F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD offcore_response.all_reads.l3_hit.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C07F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD period=20011,umask=0x4,event=0xd2 offcore_response.pf_l2_rfo.l3_hit_f.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.SNOOP_NONE offcore_response.pf_l3_data_rd.l3_hit_f.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED offcore_response.other.l3_hit_m.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400048000 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x42,event=0xd0 Retired store instructions that split across a cacheline boundary Supports address when precise (Precise event) Counts retired store instructions that split across a cacheline boundary Supports address when precise (Precise event) period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010122 This event is deprecated. Refer to new event OCR.ALL_RFO.ANY_RESPONSE offcore_response.all_pf_rfo.l3_hit_s.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.ANY_RESPONSE offcore_response.all_data_rd.supplier_none.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE offcore_response.all_pf_rfo.l3_hit_s.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.ANY_RESPONSE offcore_response.pf_l1d_and_sw.l3_hit_e.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_NONE offcore_response.pf_l3_data_rd.pmm_hit_local_pmm.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE offcore_response.pf_l3_data_rd.pmm_hit_local_pmm.snoop_not_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED offcore_response.all_pf_rfo.l3_hit_e.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD offcore_response.demand_data_rd.l3_hit_e.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD offcore_response.all_data_rd.l3_hit_s.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD offcore_response.demand_rfo.l3_hit_s.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l3_rfo.pmm_hit_local_pmm.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.ANY_RESPONSE offcore_response.all_pf_data_rd.l3_hit_s.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE offcore_response.pf_l2_rfo.pmm_hit_local_pmm.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C8000 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP offcore_response.pf_l2_rfo.l3_hit_f.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED offcore_response.pf_l1d_and_sw.l3_hit_f.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP offcore_response.all_pf_rfo.l3_hit_m.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l2_rfo.l3_hit_m.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP offcore_response.all_pf_rfo.l3_hit_s.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP offcore_response.demand_rfo.pmm_hit_local_pmm.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP offcore_response.all_data_rd.l3_hit_m.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD period=2000003,umask=0x2,event=0x48 period=100003,umask=0x1,event=0xb7 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE offcore_response.pf_l2_data_rd.supplier_none.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD offcore_response.all_pf_data_rd.l3_hit_f.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP offcore_response.pf_l3_rfo.l3_hit.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD offcore_response.demand_data_rd.l3_hit_m.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD period=2000003,umask=0x1,event=0xb2 offcore_response.pf_l2_rfo.l3_hit_f.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.SNOOP_MISS offcore_response.all_pf_data_rd.l3_hit_f.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP offcore_response.all_data_rd.pmm_hit_local_pmm.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE offcore_response.all_reads.supplier_none.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10000207F7 This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE offcore_response.all_pf_rfo.l3_hit_e.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD period=50021,umask=0x10,event=0xd1 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.SNOOP_MISS offcore_response.pf_l1d_and_sw.l3_hit_f.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_NONE offcore_response.demand_code_rd.pmm_hit_local_pmm.snoop_not_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED offcore_response.all_pf_rfo.supplier_none.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED offcore_response.pf_l3_rfo.l3_hit_f.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED offcore_response.pf_l3_data_rd.l3_hit_m.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200088000 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C8000 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.SNOOP_NONE offcore_response.demand_data_rd.l3_hit_f.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED offcore_response.pf_l2_rfo.l3_hit_e.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP offcore_response.all_pf_data_rd.pmm_hit_local_pmm.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP offcore_response.pf_l1d_and_sw.pmm_hit_local_pmm.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP offcore_response.pf_l2_rfo.pmm_hit_local_pmm.snoop_not_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED period=200003,umask=0x38,event=0x24 offcore_response.all_reads.l3_hit_m.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08000407F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD offcore_response.pf_l3_rfo.l3_hit_f.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP offcore_response.pf_l1d_and_sw.l3_hit_m.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_MISS offcore_response.demand_code_rd.l3_hit_s.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l3_data_rd.l3_hit_e.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_MISS offcore_response.all_reads.l3_hit_m.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10000407F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE offcore_response.all_reads.supplier_none.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00800207F7 This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.ANY_RESPONSE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020122 This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS offcore_response.all_rfo.pmm_hit_local_pmm.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400122 This event is deprecated. Refer to new event OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.ANY_RESPONSE offcore_response.all_pf_data_rd.l3_hit.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD offcore_response.pf_l2_rfo.supplier_none.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE offcore_response.all_rfo.l3_hit_s.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS offcore_response.demand_data_rd.l3_hit_f.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_NONE offcore_response.pf_l3_data_rd.supplier_none.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l2_data_rd.l3_hit_m.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED offcore_response.pf_l3_rfo.l3_hit_e.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE offcore_response.all_reads.supplier_none.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08000207F7 This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD period=100007,umask=0x20,event=0xd1 Counts retired load instructions with at least one uop that missed in the L3 cache Supports address when precise (Precise event) offcore_response.pf_l3_rfo.l3_hit_f.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE offcore_response.demand_rfo.supplier_none.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080028000 This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.SNOOP_NONE offcore_response.all_data_rd.supplier_none.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED offcore_response.all_pf_rfo.l3_hit_e.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP offcore_response.pf_l3_rfo.supplier_none.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD period=100003,umask=0x41,event=0x2e offcore_response.all_pf_data_rd.l3_hit_f.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE offcore_response.pf_l3_data_rd.l3_hit_f.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_MISS offcore_response.all_pf_rfo.l3_hit_e.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE offcore_response.pf_l2_data_rd.supplier_none.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED offcore_response.pf_l1d_and_sw.supplier_none.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP offcore_response.pf_l1d_and_sw.l3_hit_s.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP offcore_response.other.l3_hit.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C8000 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD offcore_response.all_pf_rfo.l3_hit_m.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD offcore_response.demand_rfo.l3_hit_f.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS offcore_response.pf_l3_rfo.l3_hit_f.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.SNOOP_NONE offcore_response.all_reads.pmm_hit_local_pmm.snoop_not_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01004007F7 This event is deprecated. Refer to new event OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED offcore_response.all_pf_rfo.l3_hit_e.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED period=2000003,umask=0x4,event=0x60 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD offcore_response.pf_l3_rfo.l3_hit_s.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE offcore_response.pf_l3_rfo.supplier_none.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.HITM_OTHER_CORE offcore_response.pf_l2_data_rd.l3_hit_e.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_NONE offcore_response.pf_l2_data_rd.pmm_hit_local_pmm.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE period=200003,umask=0x2,event=0xf2 offcore_response.pf_l2_data_rd.l3_hit_m.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE offcore_response.all_reads.pmm_hit_local_pmm.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00804007F7 This event is deprecated. Refer to new event OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD offcore_response.pf_l3_rfo.l3_hit_s.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD period=200003,umask=0xc2,event=0x24 offcore_response.pf_l3_data_rd.l3_hit_s.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD offcore_response.demand_data_rd.l3_hit_f.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l3_rfo.supplier_none.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD period=2000003,umask=0x8,event=0x60 offcore_response.other.l3_hit_s.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400108000 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00000107F7 This event is deprecated. Refer to new event OCR.ALL_READS.ANY_RESPONSE offcore_response.all_reads.l3_hit_e.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F800807F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS offcore_response.all_rfo.l3_hit_s.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED offcore_response.all_rfo.l3_hit_s.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP offcore_response.pf_l2_data_rd.l3_hit_m.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP offcore_response.pf_l2_data_rd.l3_hit_f.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_MISS offcore_response.pf_l3_rfo.l3_hit_s.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP offcore_response.demand_data_rd.l3_hit_f.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD offcore_response.other.pmm_hit_local_pmm.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080408000 This event is deprecated. Refer to new event OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE offcore_response.pf_l1d_and_sw.l3_hit_m.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_NONE offcore_response.pf_l1d_and_sw.l3_hit_m.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED offcore_response.all_data_rd.l3_hit_e.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE offcore_response.pf_l3_data_rd.l3_hit_f.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP offcore_response.all_rfo.l3_hit_m.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080088000 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.SNOOP_NONE offcore_response.all_pf_data_rd.l3_hit_m.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE offcore_response.all_rfo.l3_hit_s.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD offcore_response.demand_code_rd.supplier_none.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED offcore_response.pf_l3_data_rd.l3_hit_s.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NONE offcore_response.pf_l3_data_rd.l3_hit_f.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED offcore_response.pf_l3_rfo.l3_hit_e.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD offcore_response.all_reads.l3_hit_s.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F801007F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.ANY_SNOOP offcore_response.pf_l1d_and_sw.l3_hit_s.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE offcore_response.pf_l1d_and_sw.supplier_none.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE offcore_response.all_pf_data_rd.l3_hit_m.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080048000 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.SNOOP_NONE period=2000003,umask=0x1,event=0x51 offcore_response.pf_l2_data_rd.supplier_none.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS offcore_response.pf_l2_data_rd.l3_hit_f.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD offcore_response.all_rfo.l3_hit_e.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD offcore_response.pf_l2_data_rd.l3_hit_f.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD offcore_response.all_rfo.l3_hit_f.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP offcore_response.all_pf_data_rd.l3_hit_m.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD offcore_response.demand_rfo.l3_hit_s.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE offcore_response.all_data_rd.l3_hit_e.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE period=200003,umask=0xc1,event=0x24 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C07F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE offcore_response.pf_l2_data_rd.l3_hit_s.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED period=2000003,umask=0x81,event=0xd0 All retired load instructions Supports address when precise (Precise event) offcore_response.pf_l1d_and_sw.l3_hit_f.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD offcore_response.other.l3_hit_s.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000108000 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_MISS offcore_response.pf_l2_data_rd.l3_hit_e.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE offcore_response.all_data_rd.l3_hit_m.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD offcore_response.other.l3_hit_f.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800208000 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.ANY_RESPONSE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE offcore_response.other.l3_hit_f.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080208000 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.SNOOP_MISS offcore_response.pf_l2_rfo.l3_hit_s.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD offcore_response.pf_l2_rfo.l3_hit_s.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.SNOOP_MISS offcore_response.pf_l3_rfo.l3_hit_e.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP offcore_response.demand_rfo.l3_hit_f.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD offcore_response.all_pf_rfo.l3_hit_s.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE offcore_response.all_pf_data_rd.l3_hit_f.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED offcore_response.all_data_rd.l3_hit_e.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE offcore_response.all_rfo.l3_hit_s.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS offcore_response.pf_l3_rfo.l3_hit_m.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE offcore_response.pf_l2_rfo.l3_hit_e.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD offcore_response.demand_data_rd.l3_hit.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP offcore_response.pf_l3_rfo.l3_hit_e.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED offcore_response.pf_l2_data_rd.l3_hit_f.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80108000 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED offcore_response.all_pf_data_rd.l3_hit_e.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP offcore_response.all_reads.l3_hit_e.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10000807F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE offcore_response.pf_l1d_and_sw.l3_hit_m.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE cmask=1,period=2000003,umask=0x1,event=0x60 offcore_response.pf_l2_rfo.l3_hit_e.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l1d_and_sw.l3_hit.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE offcore_response.demand_data_rd.l3_hit_f.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_MISS offcore_response.pf_l2_data_rd.l3_hit_f.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.ANY_RESPONSE offcore_response.other.l3_hit_e.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000088000 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE offcore_response.demand_code_rd.l3_hit.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD cmask=1,period=2000003,umask=0x8,event=0x60 offcore_response.pf_l2_rfo.l3_hit_f.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD offcore_response.all_pf_data_rd.l3_hit_e.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE offcore_response.all_rfo.l3_hit_e.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP offcore_response.pf_l2_data_rd.pmm_hit_local_pmm.snoop_not_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED offcore_response.all_pf_data_rd.l3_hit_m.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP offcore_response.all_pf_rfo.l3_hit_m.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x41,event=0xd0 Retired load instructions that split across a cacheline boundary Supports address when precise (Precise event) Counts retired load instructions that split across a cacheline boundary Supports address when precise (Precise event) offcore_response.pf_l3_data_rd.l3_hit_m.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD cmask=6,period=2000003,umask=0x1,event=0x60 offcore_response.all_data_rd.l3_hit_s.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l3_rfo.l3_hit_m.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.ANY_SNOOP period=100003,umask=0x12,event=0xd0 Retired store instructions that miss the STLB Supports address when precise (Precise event) offcore_response.demand_data_rd.pmm_hit_local_pmm.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE period=200003,umask=0xe2,event=0x24 offcore_response.all_pf_rfo.pmm_hit_local_pmm.snoop_not_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED offcore_response.all_reads.l3_hit.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C07F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l2_data_rd.l3_hit_s.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_NONE offcore_response.all_rfo.l3_hit_e.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED offcore_response.pf_l3_data_rd.l3_hit_m.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED offcore_response.all_data_rd.l3_hit_m.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED offcore_response.all_pf_rfo.l3_hit_s.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD offcore_response.all_pf_data_rd.l3_hit_s.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD offcore_response.all_reads.l3_hit.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C07F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED offcore_response.pf_l2_rfo.l3_hit_m.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.SNOOP_MISS offcore_response.all_reads.l3_hit_s.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01001007F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED offcore_response.all_rfo.l3_hit_m.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP offcore_response.other.supplier_none.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100028000 This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED offcore_response.all_reads.l3_hit_m.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02000407F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020122 This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP offcore_response.all_pf_data_rd.l3_hit_e.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l1d_and_sw.l3_hit_e.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE offcore_response.demand_code_rd.l3_hit_e.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD offcore_response.demand_code_rd.l3_hit_s.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED offcore_response.all_data_rd.pmm_hit_local_pmm.snoop_not_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED offcore_response.demand_code_rd.l3_hit_e.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED offcore_response.demand_data_rd.supplier_none.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD offcore_response.demand_code_rd.l3_hit_f.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_NONE offcore_response.other.l3_hit_e.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400088000 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l2_data_rd.l3_hit_m.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l1d_and_sw.l3_hit_s.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED offcore_response.pf_l1d_and_sw.supplier_none.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED offcore_response.pf_l3_rfo.l3_hit_m.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD offcore_response.other.l3_hit_e.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100088000 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED offcore_response.all_data_rd.l3_hit_s.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE offcore_response.pf_l3_data_rd.l3_hit_f.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISS period=200003,umask=0xf8,event=0x24 offcore_response.all_rfo.l3_hit_f.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS offcore_response.demand_data_rd.l3_hit_e.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l1d_and_sw.l3_hit_f.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED offcore_response.all_data_rd.l3_hit_e.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED offcore_response.all_pf_data_rd.l3_hit_e.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE offcore_response.demand_rfo.l3_hit_m.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED offcore_response.pf_l3_data_rd.l3_hit_e.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP offcore_response.pf_l1d_and_sw.l3_hit_f.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_MISS period=200003,umask=0xe4,event=0x24 offcore_response.pf_l2_data_rd.l3_hit_s.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP offcore_response.pf_l3_rfo.l3_hit_e.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED offcore_response.demand_rfo.l3_hit_m.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD period=200003,umask=0xe7,event=0x24 period=100007,umask=0x2,event=0xd3 offcore_response.all_reads.supplier_none.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F800207F7 This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP offcore_response.all_reads.l3_hit_m.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01000407F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED offcore_response.all_pf_data_rd.l3_hit_e.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD offcore_response.pf_l3_rfo.l3_hit_s.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.SNOOP_MISS period=200003,umask=0x24,event=0x24 offcore_response.pf_l3_data_rd.l3_hit_s.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_MISS offcore_response.all_pf_rfo.l3_hit_e.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE offcore_response.pf_l3_rfo.l3_hit_m.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.SNOOP_NONE offcore_response.all_data_rd.l3_hit_e.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD period=2000003,umask=0x1,event=0x60 offcore_response.all_rfo.l3_hit.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD offcore_response.demand_code_rd.l3_hit_f.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD offcore_response.all_reads.l3_hit_m.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04000407F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l2_rfo.l3_hit_s.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD cmask=1,period=2000003,umask=0x2,event=0x60 offcore_response.all_reads.supplier_none.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01000207F7 This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED offcore_response.all_rfo.supplier_none.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020122 This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD offcore_response.demand_rfo.l3_hit_m.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE offcore_response.pf_l3_data_rd.l3_hit_m.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP offcore_response.all_pf_data_rd.supplier_none.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP offcore_response.pf_l3_rfo.l3_hit_m.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD offcore_response.all_pf_data_rd.l3_hit_s.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE offcore_response.demand_code_rd.l3_hit_s.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD period=100003,umask=0x4f,event=0x2e period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE offcore_response.pf_l2_rfo.l3_hit_e.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE offcore_response.demand_data_rd.supplier_none.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD offcore_response.other.l3_hit_f.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000208000 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE offcore_response.pf_l2_rfo.l3_hit_e.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED offcore_response.demand_rfo.l3_hit_f.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP offcore_response.pf_l3_rfo.pmm_hit_local_pmm.snoop_not_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED offcore_response.all_data_rd.l3_hit_m.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED period=100003,umask=0x11,event=0xd0 Retired load instructions that miss the STLB Supports address when precise (Precise event) offcore_response.pf_l3_rfo.supplier_none.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED offcore_response.all_rfo.l3_hit_f.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS offcore_response.pf_l2_data_rd.pmm_hit_local_pmm.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP offcore_response.pf_l3_data_rd.pmm_hit_local_pmm.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP offcore_response.demand_code_rd.l3_hit_f.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP mem_load_retired.local_pmm period=100003,umask=0x80,event=0xd1 Retired load instructions with local Intel® Optane™ DC persistent memory as the data source where the data request missed all caches. Precise event Supports address when precise (Precise event) Counts retired load instructions with local Intel® Optane™ DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode). Precise event Supports address when precise (Precise event) offcore_response.demand_rfo.l3_hit.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD offcore_response.pf_l2_data_rd.l3_hit_m.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.ANY_RESPONSE offcore_response.pf_l1d_and_sw.l3_hit.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD offcore_response.all_pf_rfo.l3_hit_f.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD offcore_response.all_pf_data_rd.l3_hit_s.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED period=200003,umask=0x4,event=0xf2 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.SNOOP_NONE offcore_response.all_data_rd.l3_hit_s.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS period=200003,umask=0x21,event=0x24 offcore_response.demand_data_rd.l3_hit_e.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE offcore_response.demand_rfo.supplier_none.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE period=20011,umask=0x1,event=0xd2 offcore_response.other.supplier_none.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800028000 This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD offcore_response.pf_l3_data_rd.l3_hit.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD offcore_response.pf_l1d_and_sw.l3_hit.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS period=200003,umask=0xff,event=0x24 offcore_response.pf_l1d_and_sw.l3_hit_s.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_NONE offcore_response.pf_l1d_and_sw.supplier_none.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_NONE cmask=1,period=2000003,umask=0x1,event=0x48 offcore_response.pf_l2_rfo.l3_hit_s.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080108000 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.SNOOP_NONE offcore_response.pf_l3_data_rd.l3_hit_e.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD offcore_response.all_pf_rfo.l3_hit_s.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS offcore_response.all_pf_data_rd.l3_hit_m.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE offcore_response.demand_rfo.supplier_none.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE offcore_response.pf_l3_rfo.l3_hit_e.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP offcore_response.all_rfo.l3_hit_m.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP offcore_response.other.l3_hit.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C8000 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD offcore_response.all_data_rd.l3_hit_s.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS offcore_response.all_reads.l3_hit_f.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02002007F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.SNOOP_MISS offcore_response.pf_l3_data_rd.l3_hit_f.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_NONE offcore_response.pf_l1d_and_sw.pmm_hit_local_pmm.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE offcore_response.pf_l2_rfo.supplier_none.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD offcore_response.demand_code_rd.supplier_none.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD offcore_response.all_reads.l3_hit_s.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00801007F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.SNOOP_NONE offcore_response.pf_l3_rfo.l3_hit_s.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS offcore_response.demand_rfo.l3_hit_s.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200108000 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS offcore_response.all_pf_rfo.l3_hit_m.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP offcore_response.all_data_rd.l3_hit_f.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD offcore_response.pf_l3_data_rd.l3_hit_e.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS offcore_response.all_data_rd.l3_hit_f.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD offcore_response.all_rfo.pmm_hit_local_pmm.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400122 This event is deprecated. Refer to new event OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE offcore_response.other.l3_hit_e.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800088000 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD offcore_response.all_rfo.l3_hit_m.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE offcore_response.all_reads.l3_hit_f.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01002007F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS offcore_response.demand_rfo.l3_hit_m.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD offcore_response.demand_rfo.l3_hit_e.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE period=100007,umask=0x21,event=0xd0 Retired load instructions with locked access Supports address when precise (Precise event) period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l3_rfo.l3_hit_e.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE offcore_response.pf_l2_rfo.l3_hit_m.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.SNOOP_NONE offcore_response.pf_l1d_and_sw.l3_hit_f.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD period=2000003,umask=0x82,event=0xd0 All retired store instructions Supports address when precise (Precise event) offcore_response.pf_l1d_and_sw.l3_hit_e.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED offcore_response.demand_code_rd.l3_hit_e.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD offcore_response.all_pf_rfo.l3_hit_s.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED period=100007,umask=0x1,event=0xd3 Retired load instructions which data sources missed L3 but serviced from local DRAM Supports address when precise (Precise event) offcore_response.all_data_rd.supplier_none.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD offcore_response.demand_code_rd.l3_hit_m.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l3_data_rd.l3_hit_s.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE offcore_response.all_pf_rfo.pmm_hit_local_pmm.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE offcore_response.demand_code_rd.l3_hit_m.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD offcore_response.all_reads.supplier_none.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04000207F7 This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD offcore_response.all_pf_data_rd.supplier_none.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE offcore_response.all_pf_data_rd.l3_hit_m.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE offcore_response.demand_rfo.l3_hit_e.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD offcore_response.other.l3_hit_s.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100108000 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED offcore_response.pf_l1d_and_sw.l3_hit_m.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP offcore_response.demand_rfo.l3_hit_f.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE offcore_response.demand_data_rd.l3_hit_m.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE offcore_response.pf_l2_rfo.l3_hit_e.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE offcore_response.all_rfo.l3_hit_e.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.SNOOP_NONE offcore_response.other.l3_hit_m.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000048000 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE offcore_response.all_reads.l3_hit_e.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01000807F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED offcore_response.demand_code_rd.supplier_none.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE period=100003,umask=0x4,event=0xb0 offcore_response.all_data_rd.l3_hit_m.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP offcore_response.pf_l3_rfo.l3_hit_f.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l3_data_rd.l3_hit_s.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED offcore_response.demand_code_rd.l3_hit_m.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE offcore_response.pf_l3_data_rd.l3_hit_m.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE offcore_response.all_reads.supplier_none.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02000207F7 This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS offcore_response.pf_l1d_and_sw.l3_hit_e.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb0 offcore_response.all_reads.l3_hit_s.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04001007F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE offcore_response.demand_code_rd.l3_hit_f.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_MISS offcore_response.demand_data_rd.l3_hit_m.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE offcore_response.pf_l3_rfo.l3_hit_s.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.SNOOP_NONE offcore_response.pf_l2_data_rd.l3_hit.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD offcore_response.all_pf_data_rd.supplier_none.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD offcore_response.demand_code_rd.l3_hit_m.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED offcore_response.pf_l3_data_rd.l3_hit_f.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD offcore_response.all_pf_rfo.l3_hit_f.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS period=100007,umask=0x4,event=0xd3 offcore_response.pf_l2_data_rd.l3_hit_e.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISS offcore_response.pf_l3_rfo.l3_hit_m.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000018000 This event is deprecated. Refer to new event OCR.OTHER.ANY_RESPONSE offcore_response.pf_l2_rfo.supplier_none.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED offcore_response.all_data_rd.l3_hit_f.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE period=200003,umask=0x22,event=0x24 offcore_response.pf_l2_data_rd.l3_hit_s.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_MISS offcore_response.pf_l2_data_rd.l3_hit_e.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_MISS period=200003,umask=0xd8,event=0x24 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE offcore_response.pf_l2_rfo.l3_hit_s.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP offcore_response.demand_rfo.supplier_none.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l2_rfo.l3_hit.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD offcore_response.all_pf_data_rd.l3_hit_s.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD offcore_response.demand_data_rd.supplier_none.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE period=100003,umask=0x2,event=0xb0 offcore_response.all_pf_rfo.pmm_hit_local_pmm.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP offcore_response.pf_l2_data_rd.l3_hit_s.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP offcore_response.all_rfo.l3_hit_m.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS offcore_response.all_rfo.supplier_none.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020122 This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE offcore_response.other.pmm_hit_local_pmm.snoop_not_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100408000 This event is deprecated. Refer to new event OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD offcore_response.demand_code_rd.l3_hit_f.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80088000 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.ANY_SNOOP offcore_response.demand_code_rd.l3_hit_e.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD offcore_response.demand_data_rd.l3_hit_s.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE offcore_response.all_reads.l3_hit_f.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08002007F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD offcore_response.pf_l3_rfo.l3_hit_s.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED offcore_response.demand_data_rd.supplier_none.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED offcore_response.pf_l3_data_rd.l3_hit_e.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP offcore_response.all_pf_rfo.l3_hit.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS offcore_response.pf_l3_rfo.pmm_hit_local_pmm.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED offcore_response.pf_l2_rfo.l3_hit_m.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020122 This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE offcore_response.pf_l3_data_rd.l3_hit_m.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE offcore_response.pf_l2_data_rd.l3_hit_e.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP offcore_response.other.pmm_hit_local_pmm.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80408000 This event is deprecated. Refer to new event OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP offcore_response.all_pf_rfo.l3_hit_m.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED offcore_response.all_rfo.l3_hit_f.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD offcore_response.demand_data_rd.l3_hit_f.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE offcore_response.demand_data_rd.l3_hit_s.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD offcore_response.all_reads.l3_hit.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C07F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.SNOOP_MISS offcore_response.all_reads.l3_hit.snoop_hit_with_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C07F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD offcore_response.all_pf_data_rd.l3_hit_m.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.ANY_RESPONSE offcore_response.all_reads.l3_hit_m.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00800407F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.SNOOP_NONE offcore_response.demand_data_rd.l3_hit_e.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED offcore_response.all_reads.l3_hit.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C07F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.ANY_SNOOP offcore_response.pf_l1d_and_sw.supplier_none.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD offcore_response.all_reads.l3_hit_e.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00800807F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP offcore_response.pf_l1d_and_sw.l3_hit_s.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD period=100007,umask=0x40,event=0xd1 offcore_response.all_pf_rfo.l3_hit_f.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD offcore_response.pf_l2_data_rd.l3_hit_e.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.SNOOP_MISS offcore_response.all_pf_data_rd.l3_hit_e.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS offcore_response.demand_code_rd.l3_hit_s.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE offcore_response.all_pf_rfo.l3_hit_e.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONE offcore_response.all_reads.l3_hit_m.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F800407F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.ANY_SNOOP offcore_response.pf_l1d_and_sw.l3_hit_m.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l2_rfo.l3_hit_e.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.SNOOP_NONE offcore_response.other.l3_hit_f.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200208000 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.SNOOP_MISS offcore_response.all_pf_data_rd.supplier_none.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD offcore_response.all_rfo.l3_hit_f.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE offcore_response.all_data_rd.l3_hit_f.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED offcore_response.all_pf_data_rd.l3_hit_e.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80048000 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.ANY_SNOOP offcore_response.pf_l3_data_rd.supplier_none.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP period=100003,umask=0x2,event=0xd1 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS offcore_response.all_pf_data_rd.l3_hit_f.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS offcore_response.pf_l2_rfo.pmm_hit_local_pmm.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP offcore_response.all_reads.l3_hit_f.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00802007F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.SNOOP_NONE period=2000003,umask=0x1,event=0x48 offcore_response.demand_rfo.l3_hit_e.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD offcore_response.demand_code_rd.l3_hit_f.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD offcore_response.all_pf_data_rd.l3_hit_s.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP offcore_response.all_pf_data_rd.l3_hit_f.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD offcore_response.all_pf_rfo.l3_hit_f.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP offcore_response.pf_l1d_and_sw.l3_hit_e.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD offcore_response.pf_l1d_and_sw.pmm_hit_local_pmm.snoop_not_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED offcore_response.all_pf_rfo.l3_hit_f.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE offcore_response.demand_code_rd.supplier_none.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE offcore_response.all_pf_rfo.supplier_none.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE offcore_response.demand_rfo.l3_hit_f.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD offcore_response.all_data_rd.l3_hit_e.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C07F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l2_data_rd.supplier_none.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED offcore_response.all_data_rd.l3_hit_s.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED offcore_response.other.l3_hit_f.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80208000 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.ANY_SNOOP offcore_response.all_reads.l3_hit_e.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04000807F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP offcore_response.other.l3_hit.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C8000 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED offcore_response.demand_code_rd.pmm_hit_local_pmm.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP offcore_response.pf_l3_data_rd.l3_hit_s.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l2_rfo.supplier_none.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD offcore_response.all_pf_rfo.supplier_none.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD offcore_response.demand_code_rd.pmm_hit_local_pmm.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE offcore_response.all_data_rd.pmm_hit_local_pmm.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP offcore_response.all_reads.l3_hit_f.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10002007F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE offcore_response.other.l3_hit.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C8000 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD offcore_response.pf_l3_data_rd.l3_hit_e.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS offcore_response.pf_l1d_and_sw.l3_hit_s.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l1d_and_sw.supplier_none.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l2_rfo.l3_hit_m.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE offcore_response.all_rfo.l3_hit_e.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE period=2000003,umask=0x1,event=0xd1 period=100003,umask=0x8,event=0xb0 offcore_response.other.l3_hit_m.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800048000 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD offcore_response.other.l3_hit_f.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100208000 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED offcore_response.pf_l3_data_rd.supplier_none.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE offcore_response.all_data_rd.l3_hit_f.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C8000 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.ANY_SNOOP offcore_response.demand_rfo.l3_hit_f.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD offcore_response.all_rfo.l3_hit_m.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE offcore_response.all_data_rd.l3_hit_e.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS period=2000003,umask=0x2,event=0x60 offcore_response.all_data_rd.l3_hit_f.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE offcore_response.all_pf_data_rd.l3_hit_s.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE offcore_response.pf_l3_rfo.l3_hit_m.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED offcore_response.other.l3_hit.snoop_hit_with_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C8000 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.SNOOP_HIT_WITH_FWD offcore_response.all_reads.l3_hit_f.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F802007F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE offcore_response.all_rfo.l3_hit_s.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP offcore_response.all_reads.l3_hit_f.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04002007F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.ANY_RESPONSE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE clx metrics idq.dsb_uops / (idq.dsb_uops + lsd.uops + idq.mite_uops + idq.ms_uops) Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches ( 1000000000 * ( imc@event\=0xe0\\\,umask\=0x1@ / imc@event\=0xe3@ ) / imc_0@event\=0x0@ ) if 1 if 0 == 1 else 0 else 0 MEM_PMM_Read_Latency Average 3DXP Memory Bandwidth Use for reads [GB / sec] ( ( 64 * imc@event\=0xe3@ / 1000000000 ) / duration_time ) if 1 if 0 == 1 else 0 else 0 PMM_Read_BW Average 3DXP Memory Bandwidth Use for Writes [GB / sec] ( ( 64 * imc@event\=0xe7@ / 1000000000 ) / duration_time ) if 1 if 0 == 1 else 0 else 0 PMM_Write_BW period=2000003,umask=0x2,event=0xc7 Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element period=2000003,umask=0x8,event=0xc7 Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element period=2000003,umask=0x40,event=0xc7 Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element period=2000003,umask=0x20,event=0xc7 Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element period=2000003,umask=0x1,event=0xc7 Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element period=2000003,umask=0x80,event=0xc7 Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element cmask=1,period=100003,umask=0x1e,event=0xca period=2000003,umask=0x4,event=0xc7 Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT14 RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element period=2000003,umask=0x10,event=0xc7 Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element cmask=4,period=2000003,umask=0x1,event=0x9c period=100007,umask=0x1,event=0xc6,frontend=0x13 Retired Instructions who experienced Instruction L2 Cache true miss (Precise event) period=2000003,umask=0x20,event=0x79 period=100007,umask=0x1,event=0xc6,frontend=0x200206 Retired instructions that are fetched after an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall (Precise event) period=100007,umask=0x1,event=0xc6,frontend=0x300206 Retired instructions that are fetched after an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall (Precise event) period=100007,umask=0x1,event=0xc6,frontend=0x100206 Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall (Precise event) cmask=1,inv=1,period=2000003,umask=0x1,event=0x9c period=2000003,umask=0x30,event=0x79 period=100007,umask=0x1,event=0xc6,frontend=0x12 Retired Instructions who experienced Instruction L1 Cache true miss (Precise event) cmask=1,period=2000003,umask=0x1,event=0x9c cmask=1,period=2000003,umask=0x8,event=0x79 period=100007,umask=0x1,event=0xc6,frontend=0x11 Retired Instructions who experienced decode stream buffer (DSB - the decoded instruction-cache) miss (Precise event) period=2000003,umask=0x4,event=0x79 cmask=1,period=2000003,umask=0x30,event=0x79 cmask=1,period=2000003,umask=0x4,event=0x79 period=2000003,umask=0x1,event=0x9c Counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread. b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions). c. Instruction Decode Queue (IDQ) delivers four uops period=2000003,umask=0x2,event=0xab Counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles period=100007,umask=0x1,event=0xc6,frontend=0x400806 period=100007,umask=0x1,event=0xc6,frontend=0x400206 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall (Precise event) period=100007,umask=0x1,event=0xc6,frontend=0x400406 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall (Precise event) cmask=1,period=2000003,umask=0x10,event=0x79 period=200003,umask=0x2,event=0x83 period=100007,umask=0x1,event=0xc6,frontend=0x408006 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall (Precise event) cmask=3,period=2000003,umask=0x1,event=0x9c period=200003,umask=0x1,event=0x83 period=100007,umask=0x1,event=0xc6,frontend=0x404006 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall (Precise event) period=100007,umask=0x1,event=0xc6,frontend=0x15 Retired Instructions who experienced STLB (2nd level TLB) true miss (Precise event) period=2000003,umask=0x8,event=0x79 period=100007,umask=0x1,event=0xc6,frontend=0x410006 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall (Precise event) period=2000003,umask=0x4,event=0x80 cmask=1,period=2000003,umask=0x24,event=0x79 period=100007,umask=0x1,event=0xc6,frontend=0x401006 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall (Precise event) cmask=2,period=2000003,umask=0x1,event=0x9c period=100007,umask=0x1,event=0xc6,frontend=0x402006 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall (Precise event) Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops (Precise event) cmask=1,edge=1,period=2000003,umask=0x30,event=0x79 period=100007,umask=0x1,event=0xc6,frontend=0x14 Retired Instructions who experienced iTLB true miss (Precise event) cmask=1,period=2000003,umask=0x18,event=0x79 period=100007,umask=0x1,event=0xc6,frontend=0x420006 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall (Precise event) cmask=4,period=2000003,umask=0x24,event=0x79 cmask=4,period=2000003,umask=0x18,event=0x79 period=200003,umask=0x4,event=0x83 ocr.all_reads.l3_miss_local_dram.snoop_miss_or_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x06040007F7 ALL_READS & L3_MISS_LOCAL_DRAM & SNOOP_MISS_OR_NO_FWD ocr.all_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800491 ALL_DATA_RD & L3_MISS_REMOTE_DRAM & SNOOP_MISS_OR_NO_FWD ocr.pf_l3_rfo.l3_miss_local_dram.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000100 Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS_LOCAL_DRAM & NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS offcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS offcore_response.pf_l3_rfo.l3_miss.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED ocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000400 Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS_REMOTE_HOP1_DRAM & ANY_SNOOP offcore_response.all_pf_data_rd.l3_miss_local_dram.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM offcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE ocr.pf_l3_rfo.l3_miss_local_dram.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000100 offcore_response.pf_l3_rfo.l3_miss.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000100 Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS_REMOTE_HOP1_DRAM & ANY_SNOOP offcore_response.other.l3_miss_local_dram.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804008000 This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD offcore_response.all_reads.l3_miss_local_dram.snoop_miss_or_no_fwd This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD ocr.all_data_rd.l3_miss.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000491 ALL_DATA_RD & L3_MISS & HIT_OTHER_CORE_NO_FWD offcore_response.pf_l2_data_rd.l3_miss.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD ocr.pf_l3_data_rd.l3_miss_local_dram.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000080 Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_NO_FWD offcore_response.pf_l2_data_rd.l3_miss_local_dram.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD offcore_response.all_reads.l3_miss_local_dram.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01040007F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED ocr.pf_l1d_and_sw.l3_miss_local_dram.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000400 Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS_LOCAL_DRAM & NO_SNOOP_NEEDED offcore_response.demand_code_rd.l3_miss.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_CORE ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000010 Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP period=2000003,umask=0x8,event=0xc9 ocr.pf_l2_data_rd.l3_miss_local_dram.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000010 Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS_LOCAL_DRAM & ANY_SNOOP offcore_response.all_reads.l3_miss_local_dram.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10040007F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE offcore_response.demand_rfo.l3_miss.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED offcore_response.demand_code_rd.l3_miss_remote_hop1_dram.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE ocr.pf_l1d_and_sw.l3_miss.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000400 Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS & ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONE ocr.all_reads.l3_miss_remote_hop1_dram.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08100007F7 ALL_READS & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP ocr.pf_l2_rfo.l3_miss_local_dram.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000020 Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS_LOCAL_DRAM & NO_SNOOP_NEEDED offcore_response.pf_l2_rfo.l3_miss_local_dram.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD ocr.pf_l1d_and_sw.l3_miss_local_dram.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000400 ocr.all_pf_rfo.l3_miss.any_snoop ALL_PF_RFO & L3_MISS & ANY_SNOOP offcore_response.demand_rfo.l3_miss_local_dram.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD ocr.pf_l2_rfo.l3_miss.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000020 Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS & HIT_OTHER_CORE_FWD offcore_response.other.l3_miss_remote_hop1_dram.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410008000 This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD ocr.demand_rfo.l3_miss_remote_hop1_dram.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000002 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD offcore_response.all_reads.l3_miss_local_dram.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F840007F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP offcore_response.all_data_rd.l3_miss_remote_hop1_dram.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS offcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS offcore_response.pf_l3_rfo.l3_miss_local_dram.no_snoop_needed This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED offcore_response.all_pf_data_rd.l3_miss_local_dram.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE ocr.demand_code_rd.l3_miss_remote_hop1_dram.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000004 Counts all demand code reads DEMAND_CODE_RD & L3_MISS_REMOTE_HOP1_DRAM & HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS ocr.pf_l3_rfo.l3_miss_local_dram.any_snoop Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS_LOCAL_DRAM & ANY_SNOOP period=2000003,umask=0x4,event=0x54 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.SNOOP_MISS period=2000003,umask=0x1,event=0x54 ocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.snoop_miss ocr.all_pf_rfo.l3_miss_local_dram.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000120 ALL_PF_RFO & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_FWD ocr.demand_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000002 Counts all demand data writes (RFOs) DEMAND_RFO & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_NO_FWD offcore_response.demand_code_rd.l3_miss_local_dram.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD offcore_response.all_pf_rfo.l3_miss_local_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD ocr.all_rfo.l3_miss.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000122 ALL_RFO & L3_MISS & HIT_OTHER_CORE_FWD offcore_response.all_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD ocr.other.l3_miss_local_dram.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104008000 Counts any other requests OTHER & L3_MISS_LOCAL_DRAM & NO_SNOOP_NEEDED period=2000003,umask=0x10,event=0x5d period=2000003,umask=0x8,event=0x5d period=2000003,umask=0x4,event=0x5d period=2000003,umask=0x2,event=0x5d period=2000003,umask=0x1,event=0x5d offcore_response.all_rfo.l3_miss_local_dram.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED ocr.demand_rfo.l3_miss_remote_hop1_dram.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000002 Counts all demand data writes (RFOs) DEMAND_RFO & L3_MISS_REMOTE_HOP1_DRAM & HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD ocr.pf_l2_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800010 Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS_REMOTE_DRAM & SNOOP_MISS_OR_NO_FWD offcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE offcore_response.pf_l1d_and_sw.l3_miss.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS ocr.pf_l2_data_rd.l3_miss_local_dram.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000010 ocr.all_pf_data_rd.l3_miss.remote_hit_forward ALL_PF_DATA_RD & L3_MISS & REMOTE_HIT_FORWARD ocr.all_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800122 ALL_RFO & L3_MISS_REMOTE_DRAM & SNOOP_MISS_OR_NO_FWD ocr.pf_l1d_and_sw.l3_miss_local_dram.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000400 Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_NO_FWD ocr.pf_l2_rfo.l3_miss.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000020 Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS & HIT_OTHER_CORE_NO_FWD ocr.pf_l1d_and_sw.l3_miss.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000400 Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS & SNOOP_MISS offcore_response.all_reads.l3_miss_remote_dram.snoop_miss_or_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B8007F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD offcore_response.all_data_rd.l3_miss.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED ocr.demand_data_rd.l3_miss_local_dram.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000001 offcore_response.demand_rfo.l3_miss_remote_hop1_dram.hitm_other_core This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE offcore_response.all_reads.l3_miss_local_dram.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00840007F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_NONE offcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE offcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED offcore_response.all_reads.l3_miss_remote_hop1_dram.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10100007F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE offcore_response.demand_code_rd.l3_miss.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED period=2000003,umask=0x10,event=0xc9 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD ocr.demand_code_rd.l3_miss.remote_hit_forward period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00004 Counts all demand code reads DEMAND_CODE_RD & L3_MISS & REMOTE_HIT_FORWARD offcore_response.demand_rfo.l3_miss.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD ocr.all_reads.l3_miss_remote_hop1_dram.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F900007F7 ALL_READS & L3_MISS_REMOTE_HOP1_DRAM & ANY_SNOOP ocr.pf_l3_rfo.l3_miss_local_dram.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000100 Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_FWD offcore_response.pf_l2_data_rd.l3_miss_local_dram.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP ocr.all_reads.l3_miss_local_dram.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04040007F7 ALL_READS & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_NO_FWD offcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS ocr.pf_l2_data_rd.l3_miss.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000010 Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS & HIT_OTHER_CORE_FWD ocr.demand_rfo.l3_miss.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000002 Counts all demand data writes (RFOs) DEMAND_RFO & L3_MISS & SNOOP_MISS ocr.pf_l3_data_rd.l3_miss_local_dram.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000080 Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS_LOCAL_DRAM & NO_SNOOP_NEEDED ocr.all_pf_data_rd.l3_miss.remote_hitm ALL_PF_DATA_RD & L3_MISS & REMOTE_HITM ocr.demand_code_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000004 Counts all demand code reads DEMAND_CODE_RD & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_FWD ocr.demand_code_rd.l3_miss.snoop_miss Counts all demand code reads DEMAND_CODE_RD & L3_MISS & SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD offcore_response.pf_l3_data_rd.l3_miss_local_dram.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000010 ocr.pf_l1d_and_sw.l3_miss.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000400 Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS & NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE ocr.pf_l1d_and_sw.l3_miss.remote_hit_forward period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00400 Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS & REMOTE_HIT_FORWARD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS period=2000003,umask=0x2,event=0xc8 offcore_response.all_rfo.l3_miss_local_dram.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP offcore_response.demand_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD ocr.all_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000491 ALL_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_FWD ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000010 Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & HITM_OTHER_CORE ocr.all_data_rd.l3_miss_local_dram.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000491 ALL_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISS offcore_response.demand_data_rd.l3_miss_remote_hop1_dram.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS ocr.pf_l2_data_rd.l3_miss.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000010 Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS & HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.REMOTE_HITM ocr.all_pf_data_rd.l3_miss.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000490 ALL_PF_DATA_RD & L3_MISS & HITM_OTHER_CORE ocr.all_rfo.l3_miss_local_dram.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000122 ALL_RFO & L3_MISS_LOCAL_DRAM & SNOOP_MISS ocr.demand_rfo.l3_miss.no_snoop_needed Counts all demand data writes (RFOs) DEMAND_RFO & L3_MISS & NO_SNOOP_NEEDED ocr.pf_l3_data_rd.l3_miss.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000080 Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS & SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.SNOOP_NONE ocr.all_reads.l3_miss.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C0007F7 ALL_READS & L3_MISS & SNOOP_MISS offcore_response.demand_code_rd.l3_miss_local_dram.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.REMOTE_HITM ocr.all_reads.l3_miss.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C0007F7 ALL_READS & L3_MISS & HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE ocr.pf_l2_rfo.l3_miss.remote_hit_forward period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00020 Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS & REMOTE_HIT_FORWARD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84008000 This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP offcore_response.demand_rfo.l3_miss_remote_hop1_dram.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE ocr.demand_code_rd.l3_miss_local_dram.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000004 Counts all demand code reads DEMAND_CODE_RD & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_FWD ocr.all_pf_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000120 ALL_PF_RFO & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD offcore_response.pf_l3_data_rd.l3_miss_local_dram.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE offcore_response.demand_code_rd.l3_miss_remote_hop1_dram.hitm_other_core This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD ocr.all_pf_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000490 ALL_PF_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & NO_SNOOP_NEEDED ocr.other.l3_miss_remote_hop1_dram.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110008000 Counts any other requests OTHER & L3_MISS_REMOTE_HOP1_DRAM & NO_SNOOP_NEEDED ocr.pf_l3_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS_REMOTE_DRAM & SNOOP_MISS_OR_NO_FWD ocr.other.l3_miss.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC008000 Counts any other requests OTHER & L3_MISS & SNOOP_NONE ocr.all_rfo.l3_miss_local_dram.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000122 ALL_RFO & L3_MISS_LOCAL_DRAM & HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD ocr.demand_rfo.l3_miss.remote_hitm period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00002 Counts all demand data writes (RFOs) DEMAND_RFO & L3_MISS & REMOTE_HITM period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD offcore_response.all_pf_rfo.l3_miss_local_dram.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE ocr.all_reads.l3_miss_local_dram.any_snoop ALL_READS & L3_MISS_LOCAL_DRAM & ANY_SNOOP offcore_response.demand_code_rd.l3_miss_remote_hop1_dram.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP offcore_response.all_reads.l3_miss.snoop_miss This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.SNOOP_MISS offcore_response.all_rfo.l3_miss_remote_hop1_dram.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED ocr.all_pf_data_rd.l3_miss.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000490 ALL_PF_DATA_RD & L3_MISS & ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD ocr.all_reads.l3_miss_local_dram.hitm_other_core ALL_READS & L3_MISS_LOCAL_DRAM & HITM_OTHER_CORE offcore_response.all_reads.l3_miss.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C0007F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED ocr.demand_rfo.l3_miss_remote_hop1_dram.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000002 Counts all demand data writes (RFOs) DEMAND_RFO & L3_MISS_REMOTE_HOP1_DRAM & ANY_SNOOP ocr.other.l3_miss_local_dram.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004008000 Counts any other requests OTHER & L3_MISS_LOCAL_DRAM & HITM_OTHER_CORE period=1009,umask=0x1,event=0xcd,ldlat=0x80 offcore_response.all_reads.l3_miss.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C0007F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD period=2000003,umask=0x40,event=0x54 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204008000 This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS ocr.pf_l2_data_rd.l3_miss.snoop_miss Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS & SNOOP_MISS offcore_response.all_data_rd.l3_miss.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE offcore_response.all_rfo.l3_miss.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE ocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000400 Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE offcore_response.all_data_rd.l3_miss.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD ocr.all_pf_rfo.l3_miss_local_dram.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000120 ALL_PF_RFO & L3_MISS_LOCAL_DRAM & ANY_SNOOP ocr.all_pf_data_rd.l3_miss.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000490 ALL_PF_DATA_RD & L3_MISS & NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP ocr.all_pf_data_rd.l3_miss_local_dram.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000490 ALL_PF_DATA_RD & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_FWD ocr.demand_rfo.l3_miss.hit_other_core_fwd Counts all demand data writes (RFOs) DEMAND_RFO & L3_MISS & HIT_OTHER_CORE_FWD ocr.all_data_rd.l3_miss.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000491 ALL_DATA_RD & L3_MISS & ANY_SNOOP offcore_response.pf_l3_data_rd.l3_miss.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISS ocr.pf_l3_rfo.l3_miss_local_dram.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000100 Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_NO_FWD offcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP ocr.all_pf_rfo.l3_miss.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000120 ALL_PF_RFO & L3_MISS & HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC008000 This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.ANY_SNOOP ocr.pf_l3_rfo.l3_miss.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000100 Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS & SNOOP_MISS ocr.demand_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd Counts all demand data writes (RFOs) DEMAND_RFO & L3_MISS_LOCAL_DRAM & SNOOP_MISS_OR_NO_FWD ocr.other.l3_miss_remote_hop1_dram.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090008000 ocr.all_rfo.l3_miss_local_dram.no_snoop_needed ALL_RFO & L3_MISS_LOCAL_DRAM & NO_SNOOP_NEEDED ocr.all_pf_data_rd.l3_miss.snoop_miss ALL_PF_DATA_RD & L3_MISS & SNOOP_MISS ocr.all_rfo.l3_miss_remote_hop1_dram.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000122 ALL_RFO & L3_MISS_REMOTE_HOP1_DRAM & ANY_SNOOP offcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE offcore_response.all_pf_data_rd.l3_miss.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD ocr.all_pf_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000120 ALL_PF_RFO & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD offcore_response.demand_data_rd.l3_miss_remote_hop1_dram.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE ocr.all_pf_rfo.l3_miss_local_dram.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000120 ALL_PF_RFO & L3_MISS_LOCAL_DRAM & SNOOP_MISS ocr.demand_data_rd.l3_miss.any_snoop Counts demand data reads DEMAND_DATA_RD & L3_MISS & ANY_SNOOP period=2000003,umask=0x40,event=0xc9 ocr.all_pf_rfo.l3_miss_remote_hop1_dram.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000120 ALL_PF_RFO & L3_MISS_REMOTE_HOP1_DRAM & HITM_OTHER_CORE ocr.all_pf_data_rd.l3_miss_local_dram.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000490 ALL_PF_DATA_RD & L3_MISS_LOCAL_DRAM & ANY_SNOOP ocr.pf_l2_data_rd.l3_miss.remote_hit_forward period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00010 Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS & REMOTE_HIT_FORWARD ocr.all_rfo.l3_miss_local_dram.snoop_none ALL_RFO & L3_MISS_LOCAL_DRAM & SNOOP_NONE ocr.all_reads.l3_miss_remote_hop1_dram.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00900007F7 ALL_READS & L3_MISS_REMOTE_HOP1_DRAM & SNOOP_NONE offcore_response.pf_l2_data_rd.l3_miss.hitm_other_core This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CORE ocr.pf_l1d_and_sw.l3_miss_local_dram.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000400 Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS_LOCAL_DRAM & ANY_SNOOP ocr.all_reads.l3_miss_local_dram.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02040007F7 ALL_READS & L3_MISS_LOCAL_DRAM & SNOOP_MISS ocr.all_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000122 ALL_RFO & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_NO_FWD ocr.demand_data_rd.l3_miss_local_dram.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000001 Counts demand data reads DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & HITM_OTHER_CORE offcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP ocr.all_rfo.l3_miss.remote_hit_forward period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00122 ALL_RFO & L3_MISS & REMOTE_HIT_FORWARD offcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD ocr.all_reads.l3_miss_remote_dram.snoop_miss_or_no_fwd ALL_READS & L3_MISS_REMOTE_DRAM & SNOOP_MISS_OR_NO_FWD ocr.all_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd ALL_RFO & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_FWD ocr.pf_l2_data_rd.l3_miss.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000010 Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS & NO_SNOOP_NEEDED ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000020 Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_NO_FWD ocr.demand_rfo.l3_miss_local_dram.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000002 Counts all demand data writes (RFOs) DEMAND_RFO & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_FWD offcore_response.demand_code_rd.l3_miss_local_dram.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE ocr.all_pf_data_rd.l3_miss_local_dram.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000490 ALL_PF_DATA_RD & L3_MISS_LOCAL_DRAM & NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD offcore_response.other.l3_miss_local_dram.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404008000 This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000100 Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_FWD offcore_response.all_pf_data_rd.l3_miss.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED ocr.demand_data_rd.l3_miss_local_dram.snoop_miss This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP ocr.pf_l3_rfo.l3_miss.hitm_other_core Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS & HITM_OTHER_CORE ocr.other.l3_miss_remote_dram.snoop_miss_or_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B808000 Counts any other requests OTHER & L3_MISS_REMOTE_DRAM & SNOOP_MISS_OR_NO_FWD period=2000003,umask=0x8,event=0x54 ocr.other.l3_miss_local_dram.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084008000 offcore_response.demand_data_rd.l3_miss_local_dram.hitm_other_core This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE offcore_response.pf_l3_rfo.l3_miss_local_dram.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE offcore_response.demand_rfo.l3_miss.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE ocr.all_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000491 ALL_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISS_OR_NO_FWD offcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS ocr.all_pf_data_rd.l3_miss.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000490 ALL_PF_DATA_RD & L3_MISS & HIT_OTHER_CORE_FWD ocr.demand_data_rd.l3_miss_remote_hop1_dram.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000001 Counts demand data reads DEMAND_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & ANY_SNOOP offcore_response.demand_code_rd.l3_miss.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD offcore_response.all_data_rd.l3_miss_local_dram.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000010 Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & ANY_SNOOP offcore_response.all_reads.l3_miss.remote_hit_forward period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC007F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD offcore_response.other.l3_miss_local_dram.snoop_miss_or_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604008000 This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS offcore_response.all_reads.l3_miss.remote_hitm period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC007F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.REMOTE_HITM ocr.demand_data_rd.l3_miss.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000001 Counts demand data reads DEMAND_DATA_RD & L3_MISS & SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.SNOOP_MISS ocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000080 ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000100 Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_NO_FWD ocr.demand_code_rd.l3_miss_local_dram.hit_other_core_no_fwd Counts all demand code reads DEMAND_CODE_RD & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.SNOOP_NONE offcore_response.other.l3_miss_remote_dram.snoop_miss_or_no_fwd This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD ocr.demand_rfo.l3_miss.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000002 Counts all demand data writes (RFOs) DEMAND_RFO & L3_MISS & HIT_OTHER_CORE_NO_FWD offcore_response.demand_rfo.l3_miss_local_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP ocr.all_pf_data_rd.l3_miss_local_dram.hitm_other_core ALL_PF_DATA_RD & L3_MISS_LOCAL_DRAM & HITM_OTHER_CORE ocr.other.l3_miss.remote_hit_forward period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC08000 Counts any other requests OTHER & L3_MISS & REMOTE_HIT_FORWARD ocr.demand_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd Counts all demand data writes (RFOs) DEMAND_RFO & L3_MISS_REMOTE_DRAM & SNOOP_MISS_OR_NO_FWD ocr.pf_l2_rfo.l3_miss_local_dram.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000020 Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS_LOCAL_DRAM & HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE ocr.demand_rfo.l3_miss_local_dram.hit_other_core_no_fwd Counts all demand data writes (RFOs) DEMAND_RFO & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_NO_FWD ocr.all_pf_rfo.l3_miss_remote_hop1_dram.any_snoop ALL_PF_RFO & L3_MISS_REMOTE_HOP1_DRAM & ANY_SNOOP ocr.all_reads.l3_miss_remote_hop1_dram.hitm_other_core ALL_READS & L3_MISS_REMOTE_HOP1_DRAM & HITM_OTHER_CORE ocr.pf_l1d_and_sw.l3_miss_local_dram.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000400 offcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.any_snoop This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP ocr.demand_rfo.l3_miss_local_dram.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM offcore_response.all_reads.l3_miss_local_dram.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08040007F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD offcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE ocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.snoop_none offcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE offcore_response.other.l3_miss_remote_hop1_dram.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90008000 This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.REMOTE_HITM ocr.demand_code_rd.l3_miss_local_dram.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000004 Counts all demand code reads DEMAND_CODE_RD & L3_MISS_LOCAL_DRAM & ANY_SNOOP ocr.other.l3_miss_remote_hop1_dram.hit_other_core_no_fwd Counts any other requests OTHER & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_NO_FWD ocr.demand_code_rd.l3_miss_local_dram.hitm_other_core Counts all demand code reads DEMAND_CODE_RD & L3_MISS_LOCAL_DRAM & HITM_OTHER_CORE offcore_response.all_pf_rfo.l3_miss.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD offcore_response.demand_data_rd.l3_miss.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORE offcore_response.all_reads.l3_miss_remote_hop1_dram.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01100007F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED ocr.demand_data_rd.l3_miss_local_dram.any_snoop Counts demand data reads DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & ANY_SNOOP offcore_response.pf_l2_data_rd.l3_miss_local_dram.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE ocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.any_snoop Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & ANY_SNOOP ocr.other.l3_miss_local_dram.hit_other_core_fwd Counts any other requests OTHER & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_FWD ocr.demand_data_rd.l3_miss_remote_hop1_dram.snoop_miss ocr.pf_l2_rfo.l3_miss.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000020 Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS & NO_SNOOP_NEEDED ocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000080 Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & NO_SNOOP_NEEDED offcore_response.all_pf_data_rd.l3_miss_local_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD offcore_response.pf_l2_rfo.l3_miss.hit_other_core_fwd This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD ocr.pf_l3_rfo.l3_miss.no_snoop_needed Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS & NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE offcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.ANY_SNOOP period=2000003,umask=0x20,event=0xc9 ocr.all_pf_rfo.l3_miss.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000120 ALL_PF_RFO & L3_MISS & SNOOP_MISS offcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP ocr.pf_l3_data_rd.l3_miss.hitm_other_core Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS & HITM_OTHER_CORE ocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000080 offcore_response.demand_rfo.l3_miss_remote_hop1_dram.snoop_miss This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS ocr.pf_l3_data_rd.l3_miss_local_dram.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000080 Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS_LOCAL_DRAM & ANY_SNOOP offcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS ocr.all_pf_rfo.l3_miss_local_dram.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000120 ALL_PF_RFO & L3_MISS_LOCAL_DRAM & NO_SNOOP_NEEDED ocr.demand_code_rd.l3_miss.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000004 Counts all demand code reads DEMAND_CODE_RD & L3_MISS & ANY_SNOOP ocr.all_reads.l3_miss.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC0007F7 ALL_READS & L3_MISS & ANY_SNOOP offcore_response.all_pf_data_rd.l3_miss.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD ocr.pf_l2_rfo.l3_miss.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000020 Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS & SNOOP_NONE offcore_response.demand_rfo.l3_miss_remote_hop1_dram.any_snoop This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP period=2000003,umask=0x4,event=0xc9 ocr.pf_l2_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS_LOCAL_DRAM & SNOOP_MISS_OR_NO_FWD offcore_response.all_pf_data_rd.l3_miss_local_dram.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED offcore_response.pf_l2_rfo.l3_miss.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD ocr.pf_l2_rfo.l3_miss_local_dram.hit_other_core_no_fwd Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_NO_FWD ocr.pf_l3_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS_LOCAL_DRAM & SNOOP_MISS_OR_NO_FWD ocr.other.l3_miss_remote_hop1_dram.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010008000 Counts any other requests OTHER & L3_MISS_REMOTE_HOP1_DRAM & HITM_OTHER_CORE ocr.all_data_rd.l3_miss_local_dram.snoop_none ALL_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NONE ocr.all_pf_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd ALL_PF_DATA_RD & L3_MISS_REMOTE_DRAM & SNOOP_MISS_OR_NO_FWD offcore_response.pf_l3_rfo.l3_miss_local_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD ocr.pf_l3_data_rd.l3_miss.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000080 Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS & ANY_SNOOP offcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD ocr.demand_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000001 Counts demand data reads DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISS_OR_NO_FWD offcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD cmask=1,period=2000003,umask=0x10,event=0x60 offcore_response.pf_l2_data_rd.l3_miss.hit_other_core_fwd This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD period=100003,umask=0x2,event=0xc3 period=2000003,umask=0x10,event=0x54 offcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS ocr.demand_rfo.l3_miss_remote_hop1_dram.snoop_none ocr.pf_l3_data_rd.l3_miss_local_dram.hitm_other_core Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS_LOCAL_DRAM & HITM_OTHER_CORE ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000010 ocr.all_rfo.l3_miss_remote_hop1_dram.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000122 ALL_RFO & L3_MISS_REMOTE_HOP1_DRAM & HITM_OTHER_CORE offcore_response.all_rfo.l3_miss.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD ocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000080 Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_FWD ocr.demand_data_rd.l3_miss.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000001 Counts demand data reads DEMAND_DATA_RD & L3_MISS & HIT_OTHER_CORE_FWD ocr.other.l3_miss_remote_hop1_dram.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810008000 Counts any other requests OTHER & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD offcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.snoop_none This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE ocr.pf_l2_rfo.l3_miss.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000020 Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS & HITM_OTHER_CORE ocr.demand_rfo.l3_miss_local_dram.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000002 Counts all demand data writes (RFOs) DEMAND_RFO & L3_MISS_LOCAL_DRAM & NO_SNOOP_NEEDED ocr.all_reads.l3_miss.no_snoop_needed ALL_READS & L3_MISS & NO_SNOOP_NEEDED ocr.demand_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000001 Counts demand data reads DEMAND_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_NO_FWD period=2000003,umask=0x80,event=0xc9 ocr.all_reads.l3_miss_remote_hop1_dram.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04100007F7 ALL_READS & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_NO_FWD ocr.all_pf_rfo.l3_miss.snoop_none ALL_PF_RFO & L3_MISS & SNOOP_NONE ocr.demand_data_rd.l3_miss.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000001 Counts demand data reads DEMAND_DATA_RD & L3_MISS & HIT_OTHER_CORE_NO_FWD ocr.all_rfo.l3_miss.snoop_miss ALL_RFO & L3_MISS & SNOOP_MISS offcore_response.other.l3_miss_remote_hop1_dram.no_snoop_needed This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED offcore_response.other.l3_miss_remote_hop1_dram.hitm_other_core This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE ocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000400 Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS_REMOTE_HOP1_DRAM & NO_SNOOP_NEEDED cmask=6,period=2000003,umask=0x6,event=0xa3 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS ocr.pf_l1d_and_sw.l3_miss.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000400 Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS & SNOOP_NONE ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.snoop_none ocr.demand_data_rd.l3_miss.hitm_other_core Counts demand data reads DEMAND_DATA_RD & L3_MISS & HITM_OTHER_CORE ocr.pf_l1d_and_sw.l3_miss.remote_hitm period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00400 Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS & REMOTE_HITM offcore_response.pf_l1d_and_sw.l3_miss_local_dram.snoop_miss This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS ocr.other.l3_miss_local_dram.snoop_miss offcore_response.other.l3_miss_remote_hop1_dram.snoop_none This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE offcore_response.all_reads.l3_miss_remote_hop1_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD ocr.demand_code_rd.l3_miss_local_dram.snoop_miss_or_no_fwd Counts all demand code reads DEMAND_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISS_OR_NO_FWD This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD ocr.demand_code_rd.l3_miss.snoop_none Counts all demand code reads DEMAND_CODE_RD & L3_MISS & SNOOP_NONE This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD ocr.all_reads.l3_miss.remote_hit_forward ALL_READS & L3_MISS & REMOTE_HIT_FORWARD offcore_response.demand_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED ocr.all_rfo.l3_miss.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000122 ALL_RFO & L3_MISS & NO_SNOOP_NEEDED ocr.pf_l3_rfo.l3_miss.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000100 Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS & HIT_OTHER_CORE_FWD ocr.demand_code_rd.l3_miss_remote_hop1_dram.any_snoop Counts all demand code reads DEMAND_CODE_RD & L3_MISS_REMOTE_HOP1_DRAM & ANY_SNOOP ocr.all_pf_rfo.l3_miss.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000120 ALL_PF_RFO & L3_MISS & NO_SNOOP_NEEDED offcore_response.all_reads.l3_miss_remote_hop1_dram.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02100007F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS ocr.all_reads.l3_miss.remote_hitm ALL_READS & L3_MISS & REMOTE_HITM offcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED ocr.pf_l3_rfo.l3_miss.any_snoop Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS & ANY_SNOOP offcore_response.demand_code_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS offcore_response.all_data_rd.l3_miss_remote_hop1_dram.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP ocr.all_data_rd.l3_miss_local_dram.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000491 ALL_DATA_RD & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM period=2000003,umask=0x10,event=0xc8 ocr.all_rfo.l3_miss.remote_hitm ALL_RFO & L3_MISS & REMOTE_HITM ocr.all_data_rd.l3_miss_remote_hop1_dram.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000491 ALL_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & SNOOP_NONE ocr.pf_l3_data_rd.l3_miss.remote_hitm Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS & REMOTE_HITM ocr.demand_code_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800004 Counts all demand code reads DEMAND_CODE_RD & L3_MISS_REMOTE_DRAM & SNOOP_MISS_OR_NO_FWD ocr.all_pf_data_rd.l3_miss_local_dram.hit_other_core_no_fwd ALL_PF_DATA_RD & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_NO_FWD ocr.other.l3_miss_remote_hop1_dram.any_snoop Counts any other requests OTHER & L3_MISS_REMOTE_HOP1_DRAM & ANY_SNOOP ocr.all_pf_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd ALL_PF_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE ocr.other.l3_miss.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C008000 Counts any other requests OTHER & L3_MISS & SNOOP_MISS offcore_response.pf_l1d_and_sw.l3_miss_local_dram.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE ocr.other.l3_miss_local_dram.snoop_miss_or_no_fwd Counts any other requests OTHER & L3_MISS_LOCAL_DRAM & SNOOP_MISS_OR_NO_FWD ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.no_snoop_needed Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS_REMOTE_HOP1_DRAM & NO_SNOOP_NEEDED period=100007,umask=0x1,event=0xcd,ldlat=0x20 offcore_response.pf_l3_data_rd.l3_miss.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD ocr.all_rfo.l3_miss_remote_hop1_dram.no_snoop_needed ALL_RFO & L3_MISS_REMOTE_HOP1_DRAM & NO_SNOOP_NEEDED ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000020 Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_FWD ocr.pf_l3_data_rd.l3_miss.remote_hit_forward Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS & REMOTE_HIT_FORWARD ocr.demand_code_rd.l3_miss_remote_hop1_dram.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000004 offcore_response.pf_l3_data_rd.l3_miss_local_dram.no_snoop_needed This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED ocr.all_rfo.l3_miss_remote_hop1_dram.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000122 ALL_RFO & L3_MISS_REMOTE_HOP1_DRAM & SNOOP_MISS ocr.pf_l3_rfo.l3_miss.snoop_none Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS & SNOOP_NONE ocr.demand_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000002 Counts all demand data writes (RFOs) DEMAND_RFO & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_FWD ocr.demand_data_rd.l3_miss.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000001 Counts demand data reads DEMAND_DATA_RD & L3_MISS & SNOOP_MISS period=2000003,umask=0x8,event=0xc8 offcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD ocr.all_rfo.l3_miss.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000122 ALL_RFO & L3_MISS & SNOOP_NONE ocr.all_pf_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800120 ALL_PF_RFO & L3_MISS_REMOTE_DRAM & SNOOP_MISS_OR_NO_FWD offcore_response.other.l3_miss.remote_hitm period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC08000 This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.REMOTE_HITM offcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP offcore_response.demand_code_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.SNOOP_MISS ocr.pf_l2_data_rd.l3_miss_local_dram.hit_other_core_fwd Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_FWD offcore_response.all_data_rd.l3_miss_local_dram.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED offcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.snoop_none This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE ocr.other.l3_miss.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C008000 Counts any other requests OTHER & L3_MISS & HIT_OTHER_CORE_NO_FWD ocr.other.l3_miss_remote_hop1_dram.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210008000 ocr.pf_l3_data_rd.l3_miss_local_dram.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000080 ocr.demand_data_rd.l3_miss.remote_hit_forward period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00001 Counts demand data reads DEMAND_DATA_RD & L3_MISS & REMOTE_HIT_FORWARD ocr.all_reads.l3_miss.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC0007F7 ALL_READS & L3_MISS & SNOOP_NONE offcore_response.all_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED offcore_response.all_reads.l3_miss.any_snoop This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.ANY_SNOOP offcore_response.all_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000020 Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS_REMOTE_HOP1_DRAM & NO_SNOOP_NEEDED offcore_response.demand_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD offcore_response.all_data_rd.l3_miss_local_dram.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD ocr.pf_l2_data_rd.l3_miss_local_dram.hitm_other_core Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS_LOCAL_DRAM & HITM_OTHER_CORE offcore_response.all_data_rd.l3_miss_local_dram.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE offcore_response.pf_l2_rfo.l3_miss_local_dram.no_snoop_needed This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED ocr.pf_l2_rfo.l3_miss_local_dram.any_snoop Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS_LOCAL_DRAM & ANY_SNOOP ocr.all_pf_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000120 ALL_PF_RFO & L3_MISS_LOCAL_DRAM & SNOOP_MISS_OR_NO_FWD ocr.all_pf_rfo.l3_miss_remote_hop1_dram.snoop_none ALL_PF_RFO & L3_MISS_REMOTE_HOP1_DRAM & SNOOP_NONE ocr.pf_l3_rfo.l3_miss.remote_hit_forward period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00100 Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS & REMOTE_HIT_FORWARD ocr.all_data_rd.l3_miss.snoop_miss ALL_DATA_RD & L3_MISS & SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD ocr.all_pf_data_rd.l3_miss.hit_other_core_no_fwd ALL_PF_DATA_RD & L3_MISS & HIT_OTHER_CORE_NO_FWD ocr.demand_code_rd.l3_miss_local_dram.no_snoop_needed Counts all demand code reads DEMAND_CODE_RD & L3_MISS_LOCAL_DRAM & NO_SNOOP_NEEDED ocr.demand_data_rd.l3_miss_local_dram.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000001 Counts demand data reads DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP offcore_response.all_rfo.l3_miss_local_dram.hitm_other_core This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE offcore_response.pf_l2_rfo.l3_miss_local_dram.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD offcore_response.demand_data_rd.l3_miss_remote_hop1_dram.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE ocr.all_rfo.l3_miss_local_dram.hit_other_core_no_fwd ALL_RFO & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONE offcore_response.all_pf_rfo.l3_miss.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.snoop_miss offcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED ocr.all_pf_rfo.l3_miss.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000120 ALL_PF_RFO & L3_MISS & HITM_OTHER_CORE offcore_response.all_pf_rfo.l3_miss.hitm_other_core This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE offcore_response.pf_l1d_and_sw.l3_miss.snoop_none This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_NONE ocr.demand_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed Counts demand data reads DEMAND_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & NO_SNOOP_NEEDED ocr.pf_l2_rfo.l3_miss.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000020 Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS & ANY_SNOOP offcore_response.all_reads.l3_miss.snoop_none This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.SNOOP_NONE ocr.pf_l2_rfo.l3_miss.snoop_miss Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS & SNOOP_MISS offcore_response.demand_data_rd.l3_miss_local_dram.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED offcore_response.pf_l3_rfo.l3_miss.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS offcore_response.pf_l3_data_rd.l3_miss.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD offcore_response.demand_code_rd.l3_miss.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD offcore_response.demand_data_rd.l3_miss_local_dram.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD ocr.all_data_rd.l3_miss_remote_hop1_dram.any_snoop ALL_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & ANY_SNOOP offcore_response.all_rfo.l3_miss.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.no_snoop_needed This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED ocr.pf_l1d_and_sw.l3_miss_local_dram.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000400 Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS_LOCAL_DRAM & HITM_OTHER_CORE ocr.demand_rfo.l3_miss.snoop_none Counts all demand data writes (RFOs) DEMAND_RFO & L3_MISS & SNOOP_NONE ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.hitm_other_core Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS_REMOTE_HOP1_DRAM & HITM_OTHER_CORE ocr.all_pf_rfo.l3_miss_remote_hop1_dram.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000120 ALL_PF_RFO & L3_MISS_REMOTE_HOP1_DRAM & NO_SNOOP_NEEDED ocr.other.l3_miss.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C008000 Counts any other requests OTHER & L3_MISS & HITM_OTHER_CORE offcore_response.demand_code_rd.l3_miss_local_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD offcore_response.other.l3_miss_local_dram.no_snoop_needed This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED period=503,umask=0x1,event=0xcd,ldlat=0x100 ocr.demand_code_rd.l3_miss_local_dram.snoop_miss offcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000100 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD offcore_response.pf_l3_data_rd.l3_miss.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED period=20011,umask=0x1,event=0xcd,ldlat=0x10 offcore_response.pf_l1d_and_sw.l3_miss.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD ocr.pf_l2_rfo.l3_miss_local_dram.snoop_none period=2000003,umask=0x20,event=0x54 ocr.pf_l3_data_rd.l3_miss.snoop_miss Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS & SNOOP_MISS offcore_response.all_data_rd.l3_miss_remote_hop1_dram.snoop_none This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE offcore_response.pf_l1d_and_sw.l3_miss_local_dram.any_snoop This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.ANY_SNOOP ocr.demand_data_rd.l3_miss_remote_hop1_dram.snoop_none ocr.pf_l2_data_rd.l3_miss.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000010 Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS & SNOOP_NONE ocr.demand_rfo.l3_miss_local_dram.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000002 Counts all demand data writes (RFOs) DEMAND_RFO & L3_MISS_LOCAL_DRAM & HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD period=2000003,umask=0x2,event=0x54 period=2000003,umask=0x40,event=0xc8 period=2000003,umask=0x1,event=0xc9 ocr.all_rfo.l3_miss_local_dram.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000122 ALL_RFO & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_FWD ocr.all_pf_data_rd.l3_miss_remote_hop1_dram.snoop_miss ALL_PF_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & SNOOP_MISS ocr.other.l3_miss_local_dram.hit_other_core_no_fwd Counts any other requests OTHER & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_NO_FWD offcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.snoop_miss This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS ocr.demand_data_rd.l3_miss_remote_hop1_dram.hitm_other_core Counts demand data reads DEMAND_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE ocr.all_pf_data_rd.l3_miss_remote_hop1_dram.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000490 ALL_PF_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE period=101,umask=0x1,event=0xcd,ldlat=0x200 period=2000003,umask=0x20,event=0xc8 ocr.pf_l2_data_rd.l3_miss_local_dram.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000010 Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_NO_FWD offcore_response.pf_l2_rfo.l3_miss.hitm_other_core This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE offcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD offcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.hitm_other_core This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP ocr.pf_l2_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISS_OR_NO_FWD ocr.all_reads.l3_miss_remote_hop1_dram.snoop_miss ALL_READS & L3_MISS_REMOTE_HOP1_DRAM & SNOOP_MISS offcore_response.all_reads.l3_miss.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C0007F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE offcore_response.pf_l2_rfo.l3_miss.no_snoop_needed This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED ocr.demand_code_rd.l3_miss.no_snoop_needed Counts all demand code reads DEMAND_CODE_RD & L3_MISS & NO_SNOOP_NEEDED ocr.pf_l1d_and_sw.l3_miss.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000400 Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS & HITM_OTHER_CORE offcore_response.demand_rfo.l3_miss_remote_hop1_dram.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000002 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED offcore_response.all_rfo.l3_miss_remote_hop1_dram.hitm_other_core This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE ocr.demand_data_rd.l3_miss.remote_hitm Counts demand data reads DEMAND_DATA_RD & L3_MISS & REMOTE_HITM ocr.demand_data_rd.l3_miss.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000001 Counts demand data reads DEMAND_DATA_RD & L3_MISS & NO_SNOOP_NEEDED ocr.pf_l2_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS_REMOTE_DRAM & SNOOP_MISS_OR_NO_FWD offcore_response.all_reads.l3_miss_remote_hop1_dram.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD ocr.pf_l3_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000080 Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISS_OR_NO_FWD ocr.all_rfo.l3_miss.any_snoop ALL_RFO & L3_MISS & ANY_SNOOP ocr.all_pf_data_rd.l3_miss_remote_hop1_dram.any_snoop ALL_PF_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & ANY_SNOOP offcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.hitm_other_core This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD ocr.demand_code_rd.l3_miss.hit_other_core_fwd Counts all demand code reads DEMAND_CODE_RD & L3_MISS & HIT_OTHER_CORE_FWD ocr.pf_l2_data_rd.l3_miss.remote_hitm period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00010 Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS & REMOTE_HITM cmask=6,period=2000003,umask=0x10,event=0x60 period=2003,umask=0x1,event=0xcd,ldlat=0x40 ocr.all_rfo.l3_miss.hitm_other_core ALL_RFO & L3_MISS & HITM_OTHER_CORE offcore_response.demand_rfo.l3_miss.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l2_data_rd.l3_miss_local_dram.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD ocr.all_pf_data_rd.l3_miss.snoop_none ALL_PF_DATA_RD & L3_MISS & SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.REMOTE_HITM offcore_response.all_rfo.l3_miss_remote_hop1_dram.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE ocr.other.l3_miss.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C008000 Counts any other requests OTHER & L3_MISS & NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD ocr.pf_l1d_and_sw.l3_miss_remote_dram.snoop_miss_or_no_fwd Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS_REMOTE_DRAM & SNOOP_MISS_OR_NO_FWD ocr.other.l3_miss.any_snoop Counts any other requests OTHER & L3_MISS & ANY_SNOOP ocr.demand_code_rd.l3_miss_remote_hop1_dram.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000004 Counts all demand code reads DEMAND_CODE_RD & L3_MISS_REMOTE_HOP1_DRAM & NO_SNOOP_NEEDED ocr.all_rfo.l3_miss.hit_other_core_no_fwd ALL_RFO & L3_MISS & HIT_OTHER_CORE_NO_FWD ocr.all_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd ALL_RFO & L3_MISS_LOCAL_DRAM & SNOOP_MISS_OR_NO_FWD ocr.pf_l3_data_rd.l3_miss.hit_other_core_fwd Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS & HIT_OTHER_CORE_FWD ocr.all_pf_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd ALL_PF_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISS_OR_NO_FWD offcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.snoop_miss This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM ocr.all_pf_rfo.l3_miss.remote_hit_forward ALL_PF_RFO & L3_MISS & REMOTE_HIT_FORWARD offcore_response.pf_l3_data_rd.l3_miss_local_dram.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD ocr.all_pf_rfo.l3_miss_local_dram.hitm_other_core ALL_PF_RFO & L3_MISS_LOCAL_DRAM & HITM_OTHER_CORE ocr.other.l3_miss_local_dram.any_snoop Counts any other requests OTHER & L3_MISS_LOCAL_DRAM & ANY_SNOOP ocr.pf_l3_rfo.l3_miss.hit_other_core_no_fwd Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS & HIT_OTHER_CORE_NO_FWD offcore_response.other.l3_miss.hitm_other_core This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HITM_OTHER_CORE ocr.demand_rfo.l3_miss_local_dram.any_snoop Counts all demand data writes (RFOs) DEMAND_RFO & L3_MISS_LOCAL_DRAM & ANY_SNOOP ocr.demand_rfo.l3_miss.hitm_other_core Counts all demand data writes (RFOs) DEMAND_RFO & L3_MISS & HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM offcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD ocr.all_data_rd.l3_miss_remote_hop1_dram.snoop_miss ALL_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & SNOOP_MISS cmask=2,period=2000003,umask=0x2,event=0xa3 ocr.other.l3_miss.remote_hitm Counts any other requests OTHER & L3_MISS & REMOTE_HITM offcore_response.all_rfo.l3_miss.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED ocr.demand_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800001 Counts demand data reads DEMAND_DATA_RD & L3_MISS_REMOTE_DRAM & SNOOP_MISS_OR_NO_FWD offcore_response.other.l3_miss.no_snoop_needed This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.NO_SNOOP_NEEDED ocr.pf_l3_data_rd.l3_miss.hit_other_core_no_fwd Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS & HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000122 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP ocr.all_pf_rfo.l3_miss_remote_hop1_dram.snoop_miss ALL_PF_RFO & L3_MISS_REMOTE_HOP1_DRAM & SNOOP_MISS offcore_response.all_reads.l3_miss.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD ocr.demand_rfo.l3_miss_remote_hop1_dram.no_snoop_needed Counts all demand data writes (RFOs) DEMAND_RFO & L3_MISS_REMOTE_HOP1_DRAM & NO_SNOOP_NEEDED ocr.all_data_rd.l3_miss.snoop_none ALL_DATA_RD & L3_MISS & SNOOP_NONE ocr.all_data_rd.l3_miss.no_snoop_needed ALL_DATA_RD & L3_MISS & NO_SNOOP_NEEDED ocr.all_rfo.l3_miss_local_dram.any_snoop ALL_RFO & L3_MISS_LOCAL_DRAM & ANY_SNOOP ocr.all_pf_data_rd.l3_miss_local_dram.snoop_none ALL_PF_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NONE ocr.demand_data_rd.l3_miss_local_dram.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000001 Counts demand data reads DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_FWD offcore_response.other.l3_miss.remote_hit_forward This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.REMOTE_HIT_FORWARD offcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD ocr.all_data_rd.l3_miss.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000491 ALL_DATA_RD & L3_MISS & HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.ANY_SNOOP ocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.hitm_other_core Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & HITM_OTHER_CORE offcore_response.demand_data_rd.l3_miss.hit_other_core_fwd This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD ocr.all_data_rd.l3_miss_local_dram.no_snoop_needed ALL_DATA_RD & L3_MISS_LOCAL_DRAM & NO_SNOOP_NEEDED offcore_response.other.l3_miss_local_dram.hitm_other_core This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE ocr.demand_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000001 Counts demand data reads DEMAND_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_FWD offcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.snoop_miss This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS ocr.pf_l2_data_rd.l3_miss_local_dram.no_snoop_needed Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS_LOCAL_DRAM & NO_SNOOP_NEEDED period=2000003,umask=0x2,event=0xc9 ocr.pf_l1d_and_sw.l3_miss_local_dram.snoop_miss_or_no_fwd Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS_LOCAL_DRAM & SNOOP_MISS_OR_NO_FWD ocr.all_data_rd.l3_miss_local_dram.hitm_other_core ALL_DATA_RD & L3_MISS_LOCAL_DRAM & HITM_OTHER_CORE period=2000003,umask=0x80,event=0xc8 period=2000003,umask=0x10,event=0x60 ocr.demand_rfo.l3_miss.any_snoop Counts all demand data writes (RFOs) DEMAND_RFO & L3_MISS & ANY_SNOOP ocr.all_pf_data_rd.l3_miss_local_dram.snoop_miss ALL_PF_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISS offcore_response.all_reads.l3_miss_local_dram.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE offcore_response.demand_data_rd.l3_miss_local_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD offcore_response.all_reads.l3_miss_remote_hop1_dram.any_snoop This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP offcore_response.all_pf_rfo.l3_miss.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE offcore_response.other.l3_miss.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM ocr.all_reads.l3_miss_local_dram.no_snoop_needed ALL_READS & L3_MISS_LOCAL_DRAM & NO_SNOOP_NEEDED ocr.demand_code_rd.l3_miss.hit_other_core_no_fwd Counts all demand code reads DEMAND_CODE_RD & L3_MISS & HIT_OTHER_CORE_NO_FWD ocr.pf_l3_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS_REMOTE_DRAM & SNOOP_MISS_OR_NO_FWD offcore_response.pf_l1d_and_sw.l3_miss.hitm_other_core This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE ocr.all_pf_rfo.l3_miss_local_dram.snoop_none ALL_PF_RFO & L3_MISS_LOCAL_DRAM & SNOOP_NONE offcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP offcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.hitm_other_core This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE ocr.all_data_rd.l3_miss.remote_hitm ALL_DATA_RD & L3_MISS & REMOTE_HITM ocr.all_rfo.l3_miss_remote_hop1_dram.snoop_none ALL_RFO & L3_MISS_REMOTE_HOP1_DRAM & SNOOP_NONE offcore_response.demand_data_rd.l3_miss.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l1d_and_sw.l3_miss_local_dram.snoop_none This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_NONE This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD offcore_response.all_pf_rfo.l3_miss_local_dram.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD ocr.demand_code_rd.l3_miss.remote_hitm Counts all demand code reads DEMAND_CODE_RD & L3_MISS & REMOTE_HITM ocr.all_data_rd.l3_miss_local_dram.hit_other_core_fwd ALL_DATA_RD & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_FWD ocr.demand_rfo.l3_miss.remote_hit_forward Counts all demand data writes (RFOs) DEMAND_RFO & L3_MISS & REMOTE_HIT_FORWARD This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISS offcore_response.all_pf_data_rd.l3_miss.hitm_other_core This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD ocr.demand_rfo.l3_miss_local_dram.snoop_none ocr.pf_l3_rfo.l3_miss.remote_hitm Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS & REMOTE_HITM This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD offcore_response.demand_rfo.l3_miss_local_dram.no_snoop_needed This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED ocr.pf_l3_data_rd.l3_miss_local_dram.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000080 offcore_response.all_rfo.l3_miss_local_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD offcore_response.demand_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS offcore_response.pf_l1d_and_sw.l3_miss_local_dram.no_snoop_needed This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED ocr.pf_l3_data_rd.l3_miss.no_snoop_needed Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS & NO_SNOOP_NEEDED offcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.any_snoop This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP offcore_response.pf_l1d_and_sw.l3_miss_local_dram.hitm_other_core This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE offcore_response.other.l3_miss.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C008000 This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWD offcore_response.demand_code_rd.l3_miss_remote_hop1_dram.no_snoop_needed This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED offcore_response.demand_data_rd.l3_miss.no_snoop_needed This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED ocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000400 Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_FWD ocr.pf_l3_data_rd.l3_miss_local_dram.hit_other_core_fwd Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_FWD offcore_response.other.l3_miss_remote_hop1_dram.snoop_miss This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS ocr.pf_l3_rfo.l3_miss_local_dram.snoop_miss ocr.all_data_rd.l3_miss.remote_hit_forward ALL_DATA_RD & L3_MISS & REMOTE_HIT_FORWARD This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP period=100003,umask=0x10,event=0xb0 ocr.all_reads.l3_miss_remote_hop1_dram.no_snoop_needed ALL_READS & L3_MISS_REMOTE_HOP1_DRAM & NO_SNOOP_NEEDED ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_FWD offcore_response.pf_l1d_and_sw.l3_miss.no_snoop_needed This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED offcore_response.all_reads.l3_miss_local_dram.snoop_miss This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS ocr.all_pf_rfo.l3_miss_local_dram.hit_other_core_no_fwd ALL_PF_RFO & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_NO_FWD offcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.no_snoop_needed This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED offcore_response.all_reads.l3_miss_remote_hop1_dram.snoop_none This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP offcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.SNOOP_NONE offcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD ocr.pf_l1d_and_sw.l3_miss.hit_other_core_no_fwd Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS & HIT_OTHER_CORE_NO_FWD ocr.demand_code_rd.l3_miss.hitm_other_core Counts all demand code reads DEMAND_CODE_RD & L3_MISS & HITM_OTHER_CORE ocr.all_data_rd.l3_miss_remote_hop1_dram.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000491 ALL_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & HITM_OTHER_CORE offcore_response.pf_l1d_and_sw.l3_miss.snoop_miss This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS ocr.pf_l2_rfo.l3_miss_local_dram.hit_other_core_fwd Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_FWD ocr.pf_l2_rfo.l3_miss_local_dram.snoop_miss ocr.all_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed ALL_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & NO_SNOOP_NEEDED ocr.all_reads.l3_miss_local_dram.hit_other_core_fwd ALL_READS & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_FWD ocr.pf_l3_rfo.l3_miss_local_dram.hitm_other_core Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS_LOCAL_DRAM & HITM_OTHER_CORE ocr.demand_code_rd.l3_miss_local_dram.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000004 offcore_response.all_rfo.l3_miss_remote_hop1_dram.any_snoop This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM offcore_response.demand_rfo.l3_miss_local_dram.hitm_other_core This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE offcore_response.all_pf_rfo.l3_miss_local_dram.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED period=2000003,umask=0x4,event=0xc8 This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.SNOOP_MISS offcore_response.pf_l2_data_rd.l3_miss.no_snoop_needed This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.snoop_none ocr.pf_l2_data_rd.l3_miss_local_dram.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000010 ocr.demand_code_rd.l3_miss_remote_hop1_dram.snoop_none ocr.all_data_rd.l3_miss.hit_other_core_fwd ALL_DATA_RD & L3_MISS & HIT_OTHER_CORE_FWD offcore_response.all_data_rd.l3_miss_remote_hop1_dram.hitm_other_core This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE offcore_response.pf_l1d_and_sw.l3_miss_local_dram.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD ocr.all_pf_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd ALL_PF_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_FWD ocr.all_data_rd.l3_miss_local_dram.any_snoop ALL_DATA_RD & L3_MISS_LOCAL_DRAM & ANY_SNOOP offcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD ocr.pf_l2_data_rd.l3_miss.any_snoop Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS & ANY_SNOOP offcore_response.all_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD ocr.demand_code_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd Counts all demand code reads DEMAND_CODE_RD & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_NO_FWD offcore_response.demand_code_rd.l3_miss_remote_hop1_dram.snoop_miss This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS offcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE ocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_NO_FWD offcore_response.all_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD offcore_response.demand_data_rd.l3_miss_remote_hop1_dram.any_snoop This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP ocr.demand_data_rd.l3_miss_local_dram.no_snoop_needed Counts demand data reads DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD offcore_response.all_data_rd.l3_miss.hitm_other_core This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE ocr.pf_l2_data_rd.l3_miss.hit_other_core_no_fwd Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS & HIT_OTHER_CORE_NO_FWD offcore_response.pf_l3_rfo.l3_miss.hit_other_core_fwd This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD ocr.pf_l1d_and_sw.l3_miss_local_dram.hit_other_core_fwd Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_FWD ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.any_snoop Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS_REMOTE_HOP1_DRAM & ANY_SNOOP offcore_response.all_rfo.l3_miss_remote_hop1_dram.snoop_miss This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS offcore_response.demand_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD offcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.any_snoop This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP ocr.all_pf_data_rd.l3_miss_remote_hop1_dram.snoop_none ALL_PF_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & SNOOP_NONE ocr.pf_l1d_and_sw.l3_miss.hit_other_core_fwd Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS & HIT_OTHER_CORE_FWD offcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED ocr.pf_l2_rfo.l3_miss.remote_hitm Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS & REMOTE_HITM period=2000003,umask=0x1,event=0xc8 offcore_response.pf_l2_rfo.l3_miss_local_dram.hitm_other_core This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE ocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hitm_other_core Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS_REMOTE_HOP1_DRAM & HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD ocr.all_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd ALL_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_NO_FWD ocr.all_pf_rfo.l3_miss.hit_other_core_fwd ALL_PF_RFO & L3_MISS & HIT_OTHER_CORE_FWD offcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD ocr.all_reads.l3_miss.hitm_other_core ALL_READS & L3_MISS & HITM_OTHER_CORE offcore_response.pf_l3_rfo.l3_miss_local_dram.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.hitm_other_core Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS_REMOTE_HOP1_DRAM & HITM_OTHER_CORE ocr.other.l3_miss.hit_other_core_fwd Counts any other requests OTHER & L3_MISS & HIT_OTHER_CORE_FWD offcore_response.other.l3_miss_remote_hop1_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD ocr.all_pf_rfo.l3_miss.remote_hitm ALL_PF_RFO & L3_MISS & REMOTE_HITM This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS ocr.all_reads.l3_miss_local_dram.snoop_none ALL_READS & L3_MISS_LOCAL_DRAM & SNOOP_NONE period=100003,umask=0x1,event=0xcd,ldlat=0x4 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.SNOOP_MISS period=50021,umask=0x1,event=0xcd,ldlat=0x8 ocr.all_reads.l3_miss.hit_other_core_fwd ALL_READS & L3_MISS & HIT_OTHER_CORE_FWD ocr.pf_l2_data_rd.l3_hit_s.hit_other_core_no_fwd Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_S & HIT_OTHER_CORE_NO_FWD ocr.all_pf_rfo.l3_hit_s.hitm_other_core ALL_PF_RFO & L3_HIT_S & HITM_OTHER_CORE ocr.all_reads.l3_hit_f.no_snoop_needed ALL_READS & L3_HIT_F & NO_SNOOP_NEEDED ocr.all_data_rd.l3_hit.snoop_hit_with_fwd ALL_DATA_RD & L3_HIT & SNOOP_HIT_WITH_FWD ocr.all_rfo.supplier_none.snoop_miss ALL_RFO & SUPPLIER_NONE & SNOOP_MISS ocr.all_reads.l3_hit_m.hit_other_core_fwd ALL_READS & L3_HIT_M & HIT_OTHER_CORE_FWD ocr.demand_code_rd.l3_hit_s.hitm_other_core Counts all demand code reads DEMAND_CODE_RD & L3_HIT_S & HITM_OTHER_CORE ocr.other.l3_hit_e.snoop_none ocr.demand_data_rd.l3_hit_s.no_snoop_needed Counts demand data reads DEMAND_DATA_RD & L3_HIT_S & NO_SNOOP_NEEDED ocr.all_rfo.l3_hit_s.no_snoop_needed ALL_RFO & L3_HIT_S & NO_SNOOP_NEEDED ocr.other.supplier_none.hitm_other_core Counts any other requests OTHER & SUPPLIER_NONE & HITM_OTHER_CORE ocr.demand_rfo.l3_hit_m.no_snoop_needed Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_M & NO_SNOOP_NEEDED ocr.pf_l2_rfo.l3_hit_f.hit_other_core_no_fwd Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_F & HIT_OTHER_CORE_NO_FWD ocr.all_pf_rfo.l3_hit_s.hit_other_core_fwd ALL_PF_RFO & L3_HIT_S & HIT_OTHER_CORE_FWD ocr.demand_code_rd.l3_hit_e.any_snoop Counts all demand code reads DEMAND_CODE_RD & L3_HIT_E & ANY_SNOOP ocr.all_pf_rfo.l3_hit.any_snoop ALL_PF_RFO & L3_HIT & ANY_SNOOP ocr.all_data_rd.l3_hit_s.hitm_other_core ALL_DATA_RD & L3_HIT_S & HITM_OTHER_CORE ocr.all_pf_rfo.l3_hit_s.any_snoop ALL_PF_RFO & L3_HIT_S & ANY_SNOOP ocr.demand_data_rd.l3_hit_s.hit_other_core_no_fwd Counts demand data reads DEMAND_DATA_RD & L3_HIT_S & HIT_OTHER_CORE_NO_FWD ocr.demand_data_rd.l3_hit.snoop_miss Counts demand data reads DEMAND_DATA_RD & L3_HIT & SNOOP_MISS ocr.other.l3_hit_m.hitm_other_core Counts any other requests OTHER & L3_HIT_M & HITM_OTHER_CORE ocr.pf_l2_rfo.supplier_none.hit_other_core_no_fwd Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWD ocr.demand_rfo.l3_hit_s.snoop_none ocr.pf_l3_data_rd.l3_hit_e.hit_other_core_no_fwd Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_E & HIT_OTHER_CORE_NO_FWD ocr.pf_l3_data_rd.l3_hit_f.hit_other_core_no_fwd Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_F & HIT_OTHER_CORE_NO_FWD ocr.all_reads.l3_hit_m.no_snoop_needed ALL_READS & L3_HIT_M & NO_SNOOP_NEEDED ocr.other.l3_hit_e.any_snoop Counts any other requests OTHER & L3_HIT_E & ANY_SNOOP ocr.pf_l2_rfo.l3_hit.hit_other_core_fwd Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT & HIT_OTHER_CORE_FWD ocr.all_pf_rfo.l3_hit_e.hitm_other_core ALL_PF_RFO & L3_HIT_E & HITM_OTHER_CORE ocr.all_pf_data_rd.l3_hit.hitm_other_core ALL_PF_DATA_RD & L3_HIT & HITM_OTHER_CORE ocr.all_rfo.supplier_none.no_snoop_needed ALL_RFO & SUPPLIER_NONE & NO_SNOOP_NEEDED ocr.all_data_rd.l3_hit_f.hitm_other_core ALL_DATA_RD & L3_HIT_F & HITM_OTHER_CORE ocr.other.pmm_hit_local_pmm.any_snoop Counts any other requests OTHER & PMM_HIT_LOCAL_PMM & ANY_SNOOP ocr.all_pf_data_rd.supplier_none.hitm_other_core ALL_PF_DATA_RD & SUPPLIER_NONE & HITM_OTHER_CORE ocr.all_reads.pmm_hit_local_pmm.any_snoop ALL_READS & PMM_HIT_LOCAL_PMM & ANY_SNOOP period=100003,umask=0x4,event=0xfe ocr.demand_rfo.l3_hit_e.snoop_none ocr.demand_code_rd.l3_hit.hitm_other_core Counts all demand code reads DEMAND_CODE_RD & L3_HIT & HITM_OTHER_CORE ocr.all_pf_rfo.l3_hit_e.hit_other_core_no_fwd ALL_PF_RFO & L3_HIT_E & HIT_OTHER_CORE_NO_FWD ocr.demand_data_rd.l3_hit_f.snoop_miss ocr.demand_code_rd.l3_hit_m.any_snoop Counts all demand code reads DEMAND_CODE_RD & L3_HIT_M & ANY_SNOOP ocr.other.l3_hit_s.any_snoop Counts any other requests OTHER & L3_HIT_S & ANY_SNOOP ocr.other.l3_hit.hit_other_core_no_fwd Counts any other requests OTHER & L3_HIT & HIT_OTHER_CORE_NO_FWD ocr.all_data_rd.pmm_hit_local_pmm.any_snoop ALL_DATA_RD & PMM_HIT_LOCAL_PMM & ANY_SNOOP ocr.pf_l2_data_rd.l3_hit.snoop_hit_with_fwd ocr.other.l3_hit_s.no_snoop_needed Counts any other requests OTHER & L3_HIT_S & NO_SNOOP_NEEDED ocr.all_reads.l3_hit_f.snoop_miss ALL_READS & L3_HIT_F & SNOOP_MISS ocr.pf_l1d_and_sw.l3_hit.snoop_hit_with_fwd ocr.all_pf_data_rd.l3_hit_m.hit_other_core_no_fwd ALL_PF_DATA_RD & L3_HIT_M & HIT_OTHER_CORE_NO_FWD ocr.pf_l2_rfo.l3_hit_e.hitm_other_core Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_E & HITM_OTHER_CORE ocr.demand_code_rd.supplier_none.snoop_none ocr.all_pf_rfo.l3_hit_e.hit_other_core_fwd ALL_PF_RFO & L3_HIT_E & HIT_OTHER_CORE_FWD ocr.all_rfo.l3_hit_s.hit_other_core_no_fwd ALL_RFO & L3_HIT_S & HIT_OTHER_CORE_NO_FWD ocr.pf_l3_rfo.l3_hit.snoop_hit_with_fwd ocr.all_pf_data_rd.l3_hit_s.hit_other_core_fwd ALL_PF_DATA_RD & L3_HIT_S & HIT_OTHER_CORE_FWD ocr.other.l3_hit.snoop_miss Counts any other requests OTHER & L3_HIT & SNOOP_MISS ocr.pf_l1d_and_sw.l3_hit_e.snoop_miss ocr.demand_data_rd.l3_hit_s.hit_other_core_fwd Counts demand data reads DEMAND_DATA_RD & L3_HIT_S & HIT_OTHER_CORE_FWD ocr.all_rfo.l3_hit.snoop_miss ALL_RFO & L3_HIT & SNOOP_MISS ocr.demand_rfo.l3_hit_m.hitm_other_core Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_M & HITM_OTHER_CORE ocr.pf_l3_data_rd.l3_hit_s.any_snoop Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_S & ANY_SNOOP ocr.all_rfo.l3_hit_f.hitm_other_core ALL_RFO & L3_HIT_F & HITM_OTHER_CORE ocr.other.l3_hit_e.hit_other_core_fwd Counts any other requests OTHER & L3_HIT_E & HIT_OTHER_CORE_FWD ocr.all_data_rd.supplier_none.snoop_miss ALL_DATA_RD & SUPPLIER_NONE & SNOOP_MISS ocr.pf_l2_data_rd.l3_hit_e.hit_other_core_no_fwd Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_E & HIT_OTHER_CORE_NO_FWD ocr.pf_l1d_and_sw.l3_hit.snoop_none Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT & SNOOP_NONE ocr.demand_rfo.l3_hit_e.any_snoop Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_E & ANY_SNOOP ocr.all_rfo.l3_hit_m.snoop_miss ALL_RFO & L3_HIT_M & SNOOP_MISS ocr.all_rfo.l3_hit.hitm_other_core ALL_RFO & L3_HIT & HITM_OTHER_CORE ocr.pf_l3_data_rd.l3_hit.snoop_none Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT & SNOOP_NONE ocr.demand_data_rd.l3_hit_e.snoop_none ocr.pf_l1d_and_sw.l3_hit_m.snoop_miss ocr.pf_l2_rfo.any_response ocr.demand_rfo.supplier_none.hit_other_core_fwd Counts all demand data writes (RFOs) DEMAND_RFO & SUPPLIER_NONE & HIT_OTHER_CORE_FWD ocr.demand_code_rd.l3_hit_f.snoop_miss ocr.other.supplier_none.snoop_miss ocr.pf_l3_rfo.l3_hit_e.no_snoop_needed Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_E & NO_SNOOP_NEEDED ocr.pf_l3_data_rd.pmm_hit_local_pmm.snoop_not_needed Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDED ocr.all_reads.l3_hit_e.hit_other_core_fwd ALL_READS & L3_HIT_E & HIT_OTHER_CORE_FWD ocr.all_rfo.l3_hit_f.hit_other_core_no_fwd ALL_RFO & L3_HIT_F & HIT_OTHER_CORE_NO_FWD ocr.pf_l2_rfo.l3_hit_m.snoop_none ocr.demand_data_rd.l3_hit_f.any_snoop Counts demand data reads DEMAND_DATA_RD & L3_HIT_F & ANY_SNOOP ocr.demand_data_rd.l3_hit_m.hit_other_core_fwd Counts demand data reads DEMAND_DATA_RD & L3_HIT_M & HIT_OTHER_CORE_FWD ocr.pf_l1d_and_sw.pmm_hit_local_pmm.snoop_none Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & PMM_HIT_LOCAL_PMM & SNOOP_NONE ocr.pf_l3_rfo.l3_hit.hitm_other_core Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT & HITM_OTHER_CORE ocr.pf_l2_data_rd.l3_hit_m.no_snoop_needed Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_M & NO_SNOOP_NEEDED ocr.other.l3_hit_m.hit_other_core_fwd Counts any other requests OTHER & L3_HIT_M & HIT_OTHER_CORE_FWD ocr.demand_data_rd.l3_hit_e.hitm_other_core Counts demand data reads DEMAND_DATA_RD & L3_HIT_E & HITM_OTHER_CORE ocr.all_data_rd.l3_hit_e.no_snoop_needed ALL_DATA_RD & L3_HIT_E & NO_SNOOP_NEEDED ocr.pf_l2_rfo.l3_hit_s.snoop_none ocr.pf_l2_rfo.l3_hit_e.no_snoop_needed Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_E & NO_SNOOP_NEEDED ocr.demand_rfo.l3_hit.any_snoop Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT & ANY_SNOOP ocr.all_data_rd.supplier_none.hit_other_core_no_fwd ALL_DATA_RD & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWD ocr.pf_l2_data_rd.supplier_none.no_snoop_needed Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & SUPPLIER_NONE & NO_SNOOP_NEEDED ocr.all_pf_data_rd.supplier_none.hit_other_core_fwd ALL_PF_DATA_RD & SUPPLIER_NONE & HIT_OTHER_CORE_FWD ocr.all_rfo.l3_hit.no_snoop_needed ALL_RFO & L3_HIT & NO_SNOOP_NEEDED ocr.demand_data_rd.supplier_none.no_snoop_needed Counts demand data reads DEMAND_DATA_RD & SUPPLIER_NONE & NO_SNOOP_NEEDED ocr.demand_data_rd.l3_hit.snoop_none Counts demand data reads DEMAND_DATA_RD & L3_HIT & SNOOP_NONE ocr.pf_l3_rfo.supplier_none.snoop_miss ocr.pf_l2_data_rd.l3_hit_f.snoop_miss ocr.all_pf_data_rd.l3_hit_s.hit_other_core_no_fwd ALL_PF_DATA_RD & L3_HIT_S & HIT_OTHER_CORE_NO_FWD ocr.all_pf_data_rd.any_response ALL_PF_DATA_RD & ANY_RESPONSE have any response type ocr.other.l3_hit_s.hit_other_core_fwd Counts any other requests OTHER & L3_HIT_S & HIT_OTHER_CORE_FWD ocr.all_pf_rfo.l3_hit.snoop_miss ALL_PF_RFO & L3_HIT & SNOOP_MISS ocr.pf_l1d_and_sw.l3_hit_m.hit_other_core_no_fwd Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_M & HIT_OTHER_CORE_NO_FWD ocr.pf_l2_data_rd.supplier_none.hit_other_core_no_fwd Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWD ocr.other.l3_hit_m.snoop_miss ocr.all_data_rd.l3_hit_s.snoop_miss ALL_DATA_RD & L3_HIT_S & SNOOP_MISS ocr.all_rfo.l3_hit_m.any_snoop ALL_RFO & L3_HIT_M & ANY_SNOOP ocr.demand_rfo.l3_hit_f.hit_other_core_fwd Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_F & HIT_OTHER_CORE_FWD ocr.pf_l3_rfo.supplier_none.hitm_other_core Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & SUPPLIER_NONE & HITM_OTHER_CORE ocr.all_reads.l3_hit_e.any_snoop ALL_READS & L3_HIT_E & ANY_SNOOP ocr.pf_l1d_and_sw.l3_hit_e.no_snoop_needed Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_E & NO_SNOOP_NEEDED ocr.pf_l3_rfo.supplier_none.any_snoop Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & SUPPLIER_NONE & ANY_SNOOP ocr.all_pf_data_rd.l3_hit_f.hitm_other_core ALL_PF_DATA_RD & L3_HIT_F & HITM_OTHER_CORE ocr.all_reads.supplier_none.hit_other_core_fwd ALL_READS & SUPPLIER_NONE & HIT_OTHER_CORE_FWD ocr.all_reads.supplier_none.hit_other_core_no_fwd ALL_READS & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWD ocr.all_pf_data_rd.l3_hit_e.snoop_miss ALL_PF_DATA_RD & L3_HIT_E & SNOOP_MISS ocr.all_data_rd.l3_hit_f.hit_other_core_no_fwd ALL_DATA_RD & L3_HIT_F & HIT_OTHER_CORE_NO_FWD ocr.all_pf_rfo.l3_hit_e.no_snoop_needed ALL_PF_RFO & L3_HIT_E & NO_SNOOP_NEEDED ocr.all_rfo.l3_hit_e.hit_other_core_fwd ALL_RFO & L3_HIT_E & HIT_OTHER_CORE_FWD ocr.all_data_rd.l3_hit_f.any_snoop ALL_DATA_RD & L3_HIT_F & ANY_SNOOP ocr.pf_l3_rfo.l3_hit.snoop_none Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT & SNOOP_NONE ocr.demand_data_rd.l3_hit_e.hit_other_core_fwd Counts demand data reads DEMAND_DATA_RD & L3_HIT_E & HIT_OTHER_CORE_FWD ocr.demand_data_rd.l3_hit_e.no_snoop_needed Counts demand data reads DEMAND_DATA_RD & L3_HIT_E & NO_SNOOP_NEEDED ocr.other.l3_hit_e.hit_other_core_no_fwd Counts any other requests OTHER & L3_HIT_E & HIT_OTHER_CORE_NO_FWD ocr.all_rfo.l3_hit_m.hitm_other_core ALL_RFO & L3_HIT_M & HITM_OTHER_CORE ocr.demand_data_rd.l3_hit_m.snoop_miss ocr.all_rfo.any_response ALL_RFO & ANY_RESPONSE have any response type ocr.demand_code_rd.any_response ocr.demand_code_rd.l3_hit_e.snoop_miss ocr.pf_l3_rfo.l3_hit_m.snoop_miss ocr.demand_rfo.l3_hit.snoop_hit_with_fwd ocr.pf_l1d_and_sw.pmm_hit_local_pmm.any_snoop Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & PMM_HIT_LOCAL_PMM & ANY_SNOOP ocr.demand_data_rd.l3_hit.hit_other_core_fwd Counts demand data reads DEMAND_DATA_RD & L3_HIT & HIT_OTHER_CORE_FWD ocr.pf_l2_rfo.l3_hit.any_snoop Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT & ANY_SNOOP ocr.pf_l2_rfo.l3_hit_e.hit_other_core_no_fwd Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_E & HIT_OTHER_CORE_NO_FWD ocr.pf_l2_rfo.pmm_hit_local_pmm.snoop_not_needed Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDED ocr.pf_l2_rfo.l3_hit_f.any_snoop Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_F & ANY_SNOOP ocr.pf_l3_data_rd.supplier_none.hitm_other_core Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & SUPPLIER_NONE & HITM_OTHER_CORE ocr.all_reads.l3_hit.snoop_miss ALL_READS & L3_HIT & SNOOP_MISS ocr.all_pf_data_rd.supplier_none.snoop_miss ALL_PF_DATA_RD & SUPPLIER_NONE & SNOOP_MISS ocr.demand_data_rd.l3_hit_f.hit_other_core_no_fwd Counts demand data reads DEMAND_DATA_RD & L3_HIT_F & HIT_OTHER_CORE_NO_FWD ocr.pf_l2_data_rd.pmm_hit_local_pmm.snoop_none Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & PMM_HIT_LOCAL_PMM & SNOOP_NONE ocr.pf_l3_rfo.l3_hit_e.snoop_miss ocr.demand_rfo.l3_hit_f.snoop_none ocr.pf_l2_rfo.supplier_none.snoop_none ocr.other.l3_hit_e.no_snoop_needed Counts any other requests OTHER & L3_HIT_E & NO_SNOOP_NEEDED ocr.pf_l3_rfo.l3_hit_f.hit_other_core_no_fwd Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_F & HIT_OTHER_CORE_NO_FWD ocr.all_pf_data_rd.l3_hit_f.any_snoop ALL_PF_DATA_RD & L3_HIT_F & ANY_SNOOP ocr.all_pf_rfo.l3_hit_m.hit_other_core_fwd ALL_PF_RFO & L3_HIT_M & HIT_OTHER_CORE_FWD ocr.all_reads.supplier_none.any_snoop ALL_READS & SUPPLIER_NONE & ANY_SNOOP ocr.pf_l3_data_rd.l3_hit_f.any_snoop Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_F & ANY_SNOOP ocr.pf_l2_data_rd.l3_hit.snoop_none Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT & SNOOP_NONE ocr.all_data_rd.l3_hit_s.no_snoop_needed ALL_DATA_RD & L3_HIT_S & NO_SNOOP_NEEDED ocr.all_pf_rfo.supplier_none.snoop_miss ALL_PF_RFO & SUPPLIER_NONE & SNOOP_MISS ocr.all_rfo.l3_hit_m.hit_other_core_no_fwd ALL_RFO & L3_HIT_M & HIT_OTHER_CORE_NO_FWD ocr.all_reads.supplier_none.snoop_none ALL_READS & SUPPLIER_NONE & SNOOP_NONE ocr.all_data_rd.l3_hit_s.hit_other_core_fwd ALL_DATA_RD & L3_HIT_S & HIT_OTHER_CORE_FWD ocr.pf_l1d_and_sw.supplier_none.snoop_miss ocr.all_rfo.pmm_hit_local_pmm.snoop_none ALL_RFO & PMM_HIT_LOCAL_PMM & SNOOP_NONE ocr.all_pf_data_rd.supplier_none.snoop_none ALL_PF_DATA_RD & SUPPLIER_NONE & SNOOP_NONE ocr.all_reads.l3_hit_e.snoop_miss ALL_READS & L3_HIT_E & SNOOP_MISS ocr.pf_l3_rfo.pmm_hit_local_pmm.snoop_not_needed Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDED ocr.all_data_rd.l3_hit_m.snoop_none ALL_DATA_RD & L3_HIT_M & SNOOP_NONE ocr.all_rfo.pmm_hit_local_pmm.any_snoop ALL_RFO & PMM_HIT_LOCAL_PMM & ANY_SNOOP ocr.all_rfo.l3_hit_m.hit_other_core_fwd ALL_RFO & L3_HIT_M & HIT_OTHER_CORE_FWD ocr.demand_code_rd.l3_hit_m.hit_other_core_no_fwd Counts all demand code reads DEMAND_CODE_RD & L3_HIT_M & HIT_OTHER_CORE_NO_FWD ocr.pf_l2_data_rd.l3_hit_f.snoop_none ocr.pf_l2_data_rd.l3_hit_m.hit_other_core_no_fwd Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_M & HIT_OTHER_CORE_NO_FWD ocr.demand_data_rd.l3_hit.hit_other_core_no_fwd Counts demand data reads DEMAND_DATA_RD & L3_HIT & HIT_OTHER_CORE_NO_FWD ocr.all_pf_rfo.l3_hit.hit_other_core_fwd ALL_PF_RFO & L3_HIT & HIT_OTHER_CORE_FWD ocr.pf_l3_rfo.l3_hit_f.hit_other_core_fwd Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_F & HIT_OTHER_CORE_FWD ocr.pf_l3_data_rd.l3_hit_s.hit_other_core_no_fwd Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_S & HIT_OTHER_CORE_NO_FWD ocr.demand_data_rd.l3_hit_e.any_snoop Counts demand data reads DEMAND_DATA_RD & L3_HIT_E & ANY_SNOOP ocr.pf_l1d_and_sw.l3_hit_f.no_snoop_needed Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_F & NO_SNOOP_NEEDED ocr.pf_l2_data_rd.l3_hit_s.any_snoop Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_S & ANY_SNOOP ocr.demand_data_rd.l3_hit_f.snoop_none ocr.demand_code_rd.l3_hit_e.snoop_none ocr.pf_l2_data_rd.supplier_none.snoop_miss ocr.all_pf_data_rd.l3_hit_f.snoop_miss ALL_PF_DATA_RD & L3_HIT_F & SNOOP_MISS ocr.all_pf_data_rd.l3_hit_m.any_snoop ALL_PF_DATA_RD & L3_HIT_M & ANY_SNOOP ocr.demand_code_rd.supplier_none.hitm_other_core Counts all demand code reads DEMAND_CODE_RD & SUPPLIER_NONE & HITM_OTHER_CORE ocr.demand_code_rd.l3_hit.hit_other_core_fwd Counts all demand code reads DEMAND_CODE_RD & L3_HIT & HIT_OTHER_CORE_FWD ocr.demand_code_rd.supplier_none.hit_other_core_no_fwd Counts all demand code reads DEMAND_CODE_RD & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWD ocr.pf_l2_rfo.l3_hit_s.hitm_other_core Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_S & HITM_OTHER_CORE ocr.demand_rfo.l3_hit_m.snoop_miss ocr.all_rfo.l3_hit_f.hit_other_core_fwd ALL_RFO & L3_HIT_F & HIT_OTHER_CORE_FWD ocr.all_rfo.l3_hit_e.hit_other_core_no_fwd ALL_RFO & L3_HIT_E & HIT_OTHER_CORE_NO_FWD ocr.demand_rfo.supplier_none.hitm_other_core Counts all demand data writes (RFOs) DEMAND_RFO & SUPPLIER_NONE & HITM_OTHER_CORE period=200003,umask=0x7,event=0x28 ocr.other.supplier_none.snoop_none ocr.all_pf_data_rd.pmm_hit_local_pmm.snoop_none ALL_PF_DATA_RD & PMM_HIT_LOCAL_PMM & SNOOP_NONE ocr.demand_rfo.l3_hit_m.hit_other_core_fwd Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_M & HIT_OTHER_CORE_FWD ocr.demand_rfo.l3_hit_f.no_snoop_needed Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_F & NO_SNOOP_NEEDED ocr.all_rfo.supplier_none.snoop_none ALL_RFO & SUPPLIER_NONE & SNOOP_NONE ocr.pf_l2_rfo.pmm_hit_local_pmm.snoop_none Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & PMM_HIT_LOCAL_PMM & SNOOP_NONE ocr.demand_code_rd.l3_hit_e.hitm_other_core Counts all demand code reads DEMAND_CODE_RD & L3_HIT_E & HITM_OTHER_CORE ocr.all_data_rd.l3_hit_s.any_snoop ALL_DATA_RD & L3_HIT_S & ANY_SNOOP ocr.all_reads.l3_hit_f.hit_other_core_fwd ALL_READS & L3_HIT_F & HIT_OTHER_CORE_FWD ocr.all_data_rd.l3_hit_f.snoop_miss ALL_DATA_RD & L3_HIT_F & SNOOP_MISS ocr.all_pf_rfo.supplier_none.snoop_none ALL_PF_RFO & SUPPLIER_NONE & SNOOP_NONE ocr.all_pf_rfo.any_response ALL_PF_RFO & ANY_RESPONSE have any response type ocr.all_rfo.l3_hit.hit_other_core_no_fwd ALL_RFO & L3_HIT & HIT_OTHER_CORE_NO_FWD ocr.pf_l3_rfo.l3_hit_m.hitm_other_core Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_M & HITM_OTHER_CORE ocr.demand_code_rd.l3_hit_f.any_snoop Counts all demand code reads DEMAND_CODE_RD & L3_HIT_F & ANY_SNOOP ocr.pf_l2_data_rd.l3_hit_e.any_snoop Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_E & ANY_SNOOP ocr.all_reads.l3_hit_m.snoop_miss ALL_READS & L3_HIT_M & SNOOP_MISS ocr.pf_l2_rfo.l3_hit.snoop_miss Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT & SNOOP_MISS ocr.pf_l3_data_rd.l3_hit_m.no_snoop_needed Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_M & NO_SNOOP_NEEDED ocr.demand_rfo.l3_hit.snoop_miss Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT & SNOOP_MISS period=200003,umask=0x40,event=0x28 ocr.demand_rfo.l3_hit.hitm_other_core Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT & HITM_OTHER_CORE ocr.pf_l2_rfo.l3_hit_f.snoop_miss ocr.demand_code_rd.l3_hit_e.hit_other_core_fwd Counts all demand code reads DEMAND_CODE_RD & L3_HIT_E & HIT_OTHER_CORE_FWD ocr.demand_code_rd.supplier_none.snoop_miss ocr.pf_l1d_and_sw.l3_hit_m.any_snoop Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_M & ANY_SNOOP ocr.all_pf_rfo.l3_hit_m.snoop_none ALL_PF_RFO & L3_HIT_M & SNOOP_NONE ocr.demand_data_rd.l3_hit_s.hitm_other_core Counts demand data reads DEMAND_DATA_RD & L3_HIT_S & HITM_OTHER_CORE ocr.demand_rfo.l3_hit_m.any_snoop Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_M & ANY_SNOOP ocr.demand_data_rd.l3_hit.no_snoop_needed Counts demand data reads hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores ocr.pf_l1d_and_sw.l3_hit_m.snoop_none ocr.pf_l2_data_rd.l3_hit_s.hitm_other_core Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_S & HITM_OTHER_CORE ocr.all_rfo.supplier_none.hit_other_core_fwd ALL_RFO & SUPPLIER_NONE & HIT_OTHER_CORE_FWD ocr.other.any_response ocr.demand_code_rd.l3_hit_s.hit_other_core_no_fwd Counts all demand code reads DEMAND_CODE_RD & L3_HIT_S & HIT_OTHER_CORE_NO_FWD ocr.demand_code_rd.supplier_none.hit_other_core_fwd Counts all demand code reads DEMAND_CODE_RD & SUPPLIER_NONE & HIT_OTHER_CORE_FWD ocr.pf_l2_rfo.l3_hit_e.any_snoop Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_E & ANY_SNOOP ocr.pf_l2_data_rd.supplier_none.any_snoop Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & SUPPLIER_NONE & ANY_SNOOP ocr.demand_rfo.supplier_none.no_snoop_needed Counts all demand data writes (RFOs) DEMAND_RFO & SUPPLIER_NONE & NO_SNOOP_NEEDED ocr.pf_l2_data_rd.l3_hit_e.snoop_none ocr.all_pf_rfo.l3_hit.no_snoop_needed ALL_PF_RFO & L3_HIT & NO_SNOOP_NEEDED ocr.demand_data_rd.any_response ocr.demand_code_rd.l3_hit.snoop_miss Counts all demand code reads DEMAND_CODE_RD & L3_HIT & SNOOP_MISS ocr.other.l3_hit_f.snoop_none ocr.pf_l2_rfo.supplier_none.any_snoop Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & SUPPLIER_NONE & ANY_SNOOP ocr.pf_l3_data_rd.l3_hit_s.hitm_other_core Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_S & HITM_OTHER_CORE ocr.demand_rfo.pmm_hit_local_pmm.snoop_none Counts all demand data writes (RFOs) DEMAND_RFO & PMM_HIT_LOCAL_PMM & SNOOP_NONE ocr.demand_rfo.l3_hit_s.no_snoop_needed Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_S & NO_SNOOP_NEEDED ocr.all_pf_rfo.l3_hit_m.no_snoop_needed ALL_PF_RFO & L3_HIT_M & NO_SNOOP_NEEDED ocr.all_pf_rfo.l3_hit_e.snoop_miss ALL_PF_RFO & L3_HIT_E & SNOOP_MISS ocr.demand_data_rd.supplier_none.any_snoop Counts demand data reads DEMAND_DATA_RD & SUPPLIER_NONE & ANY_SNOOP ocr.all_data_rd.any_response ALL_DATA_RD & ANY_RESPONSE have any response type ocr.pf_l3_rfo.l3_hit_e.hitm_other_core Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_E & HITM_OTHER_CORE ocr.all_rfo.l3_hit_s.snoop_none ALL_RFO & L3_HIT_S & SNOOP_NONE ocr.pf_l2_rfo.l3_hit_e.snoop_none ocr.demand_code_rd.l3_hit_f.hit_other_core_fwd Counts all demand code reads DEMAND_CODE_RD & L3_HIT_F & HIT_OTHER_CORE_FWD ocr.all_pf_rfo.pmm_hit_local_pmm.snoop_none ALL_PF_RFO & PMM_HIT_LOCAL_PMM & SNOOP_NONE ocr.pf_l3_data_rd.supplier_none.hit_other_core_no_fwd Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWD ocr.demand_rfo.l3_hit_m.snoop_none ocr.all_pf_rfo.l3_hit_f.snoop_none ALL_PF_RFO & L3_HIT_F & SNOOP_NONE ocr.pf_l3_rfo.l3_hit_f.no_snoop_needed Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_F & NO_SNOOP_NEEDED ocr.all_pf_rfo.l3_hit_e.any_snoop ALL_PF_RFO & L3_HIT_E & ANY_SNOOP ocr.other.l3_hit.hit_other_core_fwd Counts any other requests OTHER & L3_HIT & HIT_OTHER_CORE_FWD ocr.pf_l3_rfo.l3_hit_m.snoop_none ocr.all_pf_data_rd.l3_hit_m.hit_other_core_fwd ALL_PF_DATA_RD & L3_HIT_M & HIT_OTHER_CORE_FWD ocr.pf_l3_rfo.supplier_none.hit_other_core_fwd Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & SUPPLIER_NONE & HIT_OTHER_CORE_FWD ocr.all_pf_data_rd.l3_hit_e.hitm_other_core ALL_PF_DATA_RD & L3_HIT_E & HITM_OTHER_CORE ocr.pf_l2_rfo.l3_hit_f.hitm_other_core Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_F & HITM_OTHER_CORE ocr.pf_l1d_and_sw.supplier_none.no_snoop_needed Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & SUPPLIER_NONE & NO_SNOOP_NEEDED ocr.pf_l3_rfo.l3_hit_m.hit_other_core_no_fwd Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_M & HIT_OTHER_CORE_NO_FWD ocr.pf_l3_rfo.l3_hit_f.hitm_other_core Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_F & HITM_OTHER_CORE ocr.pf_l3_rfo.supplier_none.no_snoop_needed Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & SUPPLIER_NONE & NO_SNOOP_NEEDED ocr.pf_l3_rfo.l3_hit_s.snoop_none ocr.all_data_rd.l3_hit.no_snoop_needed ALL_DATA_RD & L3_HIT & NO_SNOOP_NEEDED ocr.all_reads.l3_hit.hit_other_core_fwd ALL_READS & L3_HIT & HIT_OTHER_CORE_FWD ocr.demand_code_rd.l3_hit.snoop_none Counts all demand code reads DEMAND_CODE_RD & L3_HIT & SNOOP_NONE ocr.all_data_rd.pmm_hit_local_pmm.snoop_none ALL_DATA_RD & PMM_HIT_LOCAL_PMM & SNOOP_NONE ocr.all_data_rd.supplier_none.snoop_none ALL_DATA_RD & SUPPLIER_NONE & SNOOP_NONE ocr.demand_rfo.pmm_hit_local_pmm.snoop_not_needed Counts all demand data writes (RFOs) DEMAND_RFO & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDED ocr.all_pf_data_rd.l3_hit.hit_other_core_fwd ALL_PF_DATA_RD & L3_HIT & HIT_OTHER_CORE_FWD ocr.all_data_rd.l3_hit.hitm_other_core ALL_DATA_RD & L3_HIT & HITM_OTHER_CORE ocr.pf_l1d_and_sw.l3_hit_m.hit_other_core_fwd Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_M & HIT_OTHER_CORE_FWD ocr.demand_data_rd.l3_hit_m.any_snoop Counts demand data reads DEMAND_DATA_RD & L3_HIT_M & ANY_SNOOP ocr.pf_l1d_and_sw.l3_hit_f.hit_other_core_fwd Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_F & HIT_OTHER_CORE_FWD ocr.all_data_rd.l3_hit.hit_other_core_no_fwd ALL_DATA_RD & L3_HIT & HIT_OTHER_CORE_NO_FWD ocr.pf_l3_rfo.l3_hit.snoop_miss Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT & SNOOP_MISS ocr.pf_l2_data_rd.l3_hit_s.no_snoop_needed Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_S & NO_SNOOP_NEEDED ocr.pf_l3_rfo.l3_hit_s.hitm_other_core Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_S & HITM_OTHER_CORE ocr.all_data_rd.l3_hit_e.any_snoop ALL_DATA_RD & L3_HIT_E & ANY_SNOOP ocr.pf_l3_rfo.pmm_hit_local_pmm.any_snoop Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & PMM_HIT_LOCAL_PMM & ANY_SNOOP ocr.all_reads.l3_hit_f.hitm_other_core ALL_READS & L3_HIT_F & HITM_OTHER_CORE ocr.pf_l1d_and_sw.l3_hit.hit_other_core_no_fwd Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT & HIT_OTHER_CORE_NO_FWD ocr.all_pf_rfo.l3_hit.hitm_other_core ALL_PF_RFO & L3_HIT & HITM_OTHER_CORE ocr.other.l3_hit_s.snoop_miss ocr.pf_l3_rfo.l3_hit.hit_other_core_fwd Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT & HIT_OTHER_CORE_FWD ocr.pf_l1d_and_sw.supplier_none.any_snoop Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & SUPPLIER_NONE & ANY_SNOOP ocr.pf_l2_data_rd.any_response ocr.demand_rfo.l3_hit_s.hit_other_core_no_fwd Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_S & HIT_OTHER_CORE_NO_FWD ocr.all_data_rd.l3_hit_m.hitm_other_core ALL_DATA_RD & L3_HIT_M & HITM_OTHER_CORE period=100003,umask=0x2,event=0xfe ocr.pf_l2_data_rd.l3_hit_f.hit_other_core_fwd Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_F & HIT_OTHER_CORE_FWD ocr.demand_code_rd.l3_hit.snoop_hit_with_fwd ocr.other.l3_hit_m.no_snoop_needed Counts any other requests OTHER & L3_HIT_M & NO_SNOOP_NEEDED ocr.all_pf_data_rd.l3_hit.snoop_hit_with_fwd ALL_PF_DATA_RD & L3_HIT & SNOOP_HIT_WITH_FWD ocr.all_pf_data_rd.l3_hit_m.no_snoop_needed ALL_PF_DATA_RD & L3_HIT_M & NO_SNOOP_NEEDED ocr.pf_l1d_and_sw.l3_hit_f.any_snoop Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_F & ANY_SNOOP ocr.all_data_rd.l3_hit_f.snoop_none ALL_DATA_RD & L3_HIT_F & SNOOP_NONE ocr.pf_l2_data_rd.l3_hit_s.snoop_miss ocr.all_pf_rfo.l3_hit_f.no_snoop_needed ALL_PF_RFO & L3_HIT_F & NO_SNOOP_NEEDED ocr.demand_code_rd.l3_hit_s.no_snoop_needed Counts all demand code reads DEMAND_CODE_RD & L3_HIT_S & NO_SNOOP_NEEDED ocr.pf_l2_data_rd.l3_hit_m.snoop_none ocr.pf_l2_rfo.l3_hit.hit_other_core_no_fwd Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT & HIT_OTHER_CORE_NO_FWD ocr.pf_l2_data_rd.l3_hit.snoop_miss Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT & SNOOP_MISS ocr.pf_l1d_and_sw.pmm_hit_local_pmm.snoop_not_needed Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDED ocr.pf_l2_rfo.pmm_hit_local_pmm.any_snoop Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & PMM_HIT_LOCAL_PMM & ANY_SNOOP ocr.all_reads.l3_hit.hitm_other_core ALL_READS & L3_HIT & HITM_OTHER_CORE ocr.pf_l1d_and_sw.l3_hit_s.no_snoop_needed Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_S & NO_SNOOP_NEEDED ocr.demand_code_rd.l3_hit_m.no_snoop_needed Counts all demand code reads DEMAND_CODE_RD & L3_HIT_M & NO_SNOOP_NEEDED ocr.all_reads.l3_hit.hit_other_core_no_fwd ALL_READS & L3_HIT & HIT_OTHER_CORE_NO_FWD ocr.all_pf_data_rd.l3_hit_f.no_snoop_needed ALL_PF_DATA_RD & L3_HIT_F & NO_SNOOP_NEEDED ocr.other.supplier_none.no_snoop_needed Counts any other requests OTHER & SUPPLIER_NONE & NO_SNOOP_NEEDED ocr.pf_l3_data_rd.l3_hit_e.any_snoop Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_E & ANY_SNOOP ocr.other.pmm_hit_local_pmm.snoop_none Counts any other requests OTHER & PMM_HIT_LOCAL_PMM & SNOOP_NONE ocr.all_reads.l3_hit_s.hit_other_core_fwd ALL_READS & L3_HIT_S & HIT_OTHER_CORE_FWD period=2000003,umask=0x4,event=0x32 ocr.pf_l2_data_rd.pmm_hit_local_pmm.snoop_not_needed Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDED ocr.demand_data_rd.supplier_none.snoop_none ocr.pf_l2_rfo.l3_hit_m.any_snoop Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_M & ANY_SNOOP ocr.pf_l2_rfo.supplier_none.hitm_other_core Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & SUPPLIER_NONE & HITM_OTHER_CORE ocr.all_data_rd.l3_hit_m.hit_other_core_fwd ALL_DATA_RD & L3_HIT_M & HIT_OTHER_CORE_FWD ocr.pf_l2_rfo.l3_hit_f.no_snoop_needed Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_F & NO_SNOOP_NEEDED ocr.all_rfo.l3_hit_f.snoop_miss ALL_RFO & L3_HIT_F & SNOOP_MISS ocr.pf_l2_rfo.l3_hit_f.snoop_none ocr.pf_l1d_and_sw.supplier_none.hitm_other_core Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & SUPPLIER_NONE & HITM_OTHER_CORE ocr.all_pf_rfo.l3_hit.hit_other_core_no_fwd ALL_PF_RFO & L3_HIT & HIT_OTHER_CORE_NO_FWD ocr.pf_l3_data_rd.any_response ocr.all_pf_data_rd.supplier_none.any_snoop ALL_PF_DATA_RD & SUPPLIER_NONE & ANY_SNOOP ocr.pf_l3_rfo.l3_hit_m.any_snoop Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_M & ANY_SNOOP ocr.all_rfo.supplier_none.hitm_other_core ALL_RFO & SUPPLIER_NONE & HITM_OTHER_CORE ocr.pf_l2_data_rd.l3_hit.hit_other_core_no_fwd Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT & HIT_OTHER_CORE_NO_FWD ocr.all_rfo.l3_hit_f.any_snoop ALL_RFO & L3_HIT_F & ANY_SNOOP ocr.all_pf_data_rd.l3_hit_s.hitm_other_core ALL_PF_DATA_RD & L3_HIT_S & HITM_OTHER_CORE ocr.all_rfo.l3_hit_s.any_snoop ALL_RFO & L3_HIT_S & ANY_SNOOP ocr.other.pmm_hit_local_pmm.snoop_not_needed Counts any other requests OTHER & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDED ocr.pf_l2_rfo.l3_hit.snoop_none Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT & SNOOP_NONE ocr.demand_rfo.l3_hit.no_snoop_needed Counts all demand data writes (RFOs) hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores ocr.all_reads.l3_hit_s.hit_other_core_no_fwd ALL_READS & L3_HIT_S & HIT_OTHER_CORE_NO_FWD ocr.other.l3_hit_m.any_snoop Counts any other requests OTHER & L3_HIT_M & ANY_SNOOP ocr.all_pf_data_rd.l3_hit_s.any_snoop ALL_PF_DATA_RD & L3_HIT_S & ANY_SNOOP ocr.demand_rfo.l3_hit_f.hitm_other_core Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_F & HITM_OTHER_CORE ocr.all_data_rd.l3_hit_e.hitm_other_core ALL_DATA_RD & L3_HIT_E & HITM_OTHER_CORE ocr.all_reads.l3_hit_e.no_snoop_needed ALL_READS & L3_HIT_E & NO_SNOOP_NEEDED ocr.pf_l1d_and_sw.l3_hit_s.hit_other_core_no_fwd Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_S & HIT_OTHER_CORE_NO_FWD ocr.demand_rfo.l3_hit_f.snoop_miss ocr.demand_code_rd.l3_hit_s.any_snoop Counts all demand code reads DEMAND_CODE_RD & L3_HIT_S & ANY_SNOOP ocr.pf_l1d_and_sw.any_response ocr.demand_data_rd.l3_hit_f.no_snoop_needed Counts demand data reads DEMAND_DATA_RD & L3_HIT_F & NO_SNOOP_NEEDED ocr.other.l3_hit.snoop_hit_with_fwd ocr.all_pf_rfo.l3_hit_s.no_snoop_needed ALL_PF_RFO & L3_HIT_S & NO_SNOOP_NEEDED ocr.pf_l2_data_rd.l3_hit_m.hit_other_core_fwd Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_M & HIT_OTHER_CORE_FWD ocr.pf_l3_data_rd.l3_hit_s.snoop_none ocr.all_rfo.supplier_none.hit_other_core_no_fwd ALL_RFO & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWD ocr.other.l3_hit_e.hitm_other_core Counts any other requests OTHER & L3_HIT_E & HITM_OTHER_CORE ocr.all_reads.l3_hit.any_snoop ALL_READS & L3_HIT & ANY_SNOOP ocr.all_reads.pmm_hit_local_pmm.snoop_none ALL_READS & PMM_HIT_LOCAL_PMM & SNOOP_NONE ocr.other.supplier_none.hit_other_core_no_fwd Counts any other requests OTHER & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWD ocr.all_pf_data_rd.l3_hit.any_snoop ALL_PF_DATA_RD & L3_HIT & ANY_SNOOP ocr.demand_code_rd.pmm_hit_local_pmm.snoop_not_needed Counts all demand code reads DEMAND_CODE_RD & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDED ocr.demand_data_rd.l3_hit.hitm_other_core Counts demand data reads DEMAND_DATA_RD & L3_HIT & HITM_OTHER_CORE ocr.demand_rfo.supplier_none.snoop_miss ocr.all_reads.l3_hit.snoop_hit_with_fwd ALL_READS & L3_HIT & SNOOP_HIT_WITH_FWD ocr.demand_code_rd.pmm_hit_local_pmm.snoop_none Counts all demand code reads DEMAND_CODE_RD & PMM_HIT_LOCAL_PMM & SNOOP_NONE ocr.demand_data_rd.l3_hit_s.snoop_miss ocr.all_reads.l3_hit.snoop_none ALL_READS & L3_HIT & SNOOP_NONE ocr.pf_l3_data_rd.l3_hit_e.hitm_other_core Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_E & HITM_OTHER_CORE ocr.all_pf_data_rd.supplier_none.no_snoop_needed ALL_PF_DATA_RD & SUPPLIER_NONE & NO_SNOOP_NEEDED ocr.other.supplier_none.any_snoop Counts any other requests OTHER & SUPPLIER_NONE & ANY_SNOOP ocr.all_pf_data_rd.l3_hit.no_snoop_needed ALL_PF_DATA_RD & L3_HIT & NO_SNOOP_NEEDED ocr.pf_l2_rfo.l3_hit_f.hit_other_core_fwd Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_F & HIT_OTHER_CORE_FWD ocr.all_reads.l3_hit_s.no_snoop_needed ALL_READS & L3_HIT_S & NO_SNOOP_NEEDED ocr.all_rfo.l3_hit_s.hitm_other_core ALL_RFO & L3_HIT_S & HITM_OTHER_CORE ocr.all_rfo.l3_hit.snoop_hit_with_fwd ALL_RFO & L3_HIT & SNOOP_HIT_WITH_FWD ocr.all_reads.l3_hit_m.any_snoop ALL_READS & L3_HIT_M & ANY_SNOOP ocr.all_reads.l3_hit.no_snoop_needed ALL_READS & L3_HIT & NO_SNOOP_NEEDED ocr.all_reads.any_response ALL_READS & ANY_RESPONSE have any response type ocr.all_data_rd.l3_hit.hit_other_core_fwd ALL_DATA_RD & L3_HIT & HIT_OTHER_CORE_FWD ocr.all_data_rd.l3_hit_m.no_snoop_needed ALL_DATA_RD & L3_HIT_M & NO_SNOOP_NEEDED ocr.pf_l3_data_rd.supplier_none.any_snoop Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & SUPPLIER_NONE & ANY_SNOOP ocr.other.l3_hit_f.hitm_other_core Counts any other requests OTHER & L3_HIT_F & HITM_OTHER_CORE ocr.all_data_rd.l3_hit.any_snoop ALL_DATA_RD & L3_HIT & ANY_SNOOP ocr.pf_l1d_and_sw.l3_hit_m.hitm_other_core Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_M & HITM_OTHER_CORE ocr.pf_l2_data_rd.l3_hit_e.hit_other_core_fwd Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_E & HIT_OTHER_CORE_FWD ocr.pf_l3_rfo.pmm_hit_local_pmm.snoop_none Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & PMM_HIT_LOCAL_PMM & SNOOP_NONE ocr.pf_l3_data_rd.l3_hit_s.hit_other_core_fwd Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_S & HIT_OTHER_CORE_FWD ocr.pf_l3_rfo.l3_hit_e.snoop_none ocr.pf_l2_data_rd.l3_hit_e.snoop_miss ocr.all_pf_rfo.pmm_hit_local_pmm.any_snoop ALL_PF_RFO & PMM_HIT_LOCAL_PMM & ANY_SNOOP ocr.pf_l1d_and_sw.l3_hit_e.snoop_none ocr.all_pf_data_rd.l3_hit.snoop_miss ALL_PF_DATA_RD & L3_HIT & SNOOP_MISS ocr.other.l3_hit.snoop_none Counts any other requests OTHER & L3_HIT & SNOOP_NONE ocr.other.supplier_none.hit_other_core_fwd Counts any other requests OTHER & SUPPLIER_NONE & HIT_OTHER_CORE_FWD ocr.all_data_rd.l3_hit_e.snoop_none ALL_DATA_RD & L3_HIT_E & SNOOP_NONE ocr.demand_rfo.l3_hit_s.hitm_other_core Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_S & HITM_OTHER_CORE ocr.all_reads.l3_hit_s.hitm_other_core ALL_READS & L3_HIT_S & HITM_OTHER_CORE ocr.all_reads.l3_hit_f.any_snoop ALL_READS & L3_HIT_F & ANY_SNOOP ocr.all_reads.l3_hit_m.hit_other_core_no_fwd ALL_READS & L3_HIT_M & HIT_OTHER_CORE_NO_FWD ocr.all_reads.l3_hit_s.snoop_none ALL_READS & L3_HIT_S & SNOOP_NONE ocr.pf_l3_data_rd.l3_hit.snoop_miss Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT & SNOOP_MISS ocr.all_pf_data_rd.l3_hit_e.snoop_none ALL_PF_DATA_RD & L3_HIT_E & SNOOP_NONE ocr.pf_l1d_and_sw.supplier_none.hit_other_core_no_fwd Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWD ocr.pf_l1d_and_sw.l3_hit_s.hit_other_core_fwd Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_S & HIT_OTHER_CORE_FWD ocr.all_reads.l3_hit_e.hit_other_core_no_fwd ALL_READS & L3_HIT_E & HIT_OTHER_CORE_NO_FWD ocr.demand_code_rd.l3_hit_s.snoop_miss ocr.all_data_rd.l3_hit_s.snoop_none ALL_DATA_RD & L3_HIT_S & SNOOP_NONE ocr.demand_rfo.supplier_none.any_snoop Counts all demand data writes (RFOs) DEMAND_RFO & SUPPLIER_NONE & ANY_SNOOP ocr.pf_l3_data_rd.l3_hit.any_snoop Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT & ANY_SNOOP ocr.all_rfo.l3_hit.snoop_none ALL_RFO & L3_HIT & SNOOP_NONE ocr.all_pf_data_rd.l3_hit_m.snoop_none ALL_PF_DATA_RD & L3_HIT_M & SNOOP_NONE ocr.demand_rfo.l3_hit.hit_other_core_no_fwd Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT & HIT_OTHER_CORE_NO_FWD ocr.pf_l3_rfo.supplier_none.hit_other_core_no_fwd Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWD ocr.all_pf_rfo.l3_hit_m.hit_other_core_no_fwd ALL_PF_RFO & L3_HIT_M & HIT_OTHER_CORE_NO_FWD ocr.all_reads.l3_hit_e.snoop_none ALL_READS & L3_HIT_E & SNOOP_NONE ocr.demand_data_rd.supplier_none.hitm_other_core Counts demand data reads DEMAND_DATA_RD & SUPPLIER_NONE & HITM_OTHER_CORE ocr.all_reads.supplier_none.snoop_miss ALL_READS & SUPPLIER_NONE & SNOOP_MISS ocr.pf_l3_data_rd.l3_hit_f.hitm_other_core Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_F & HITM_OTHER_CORE period=2000003,umask=0x2,event=0x32 ocr.all_rfo.l3_hit.hit_other_core_fwd ALL_RFO & L3_HIT & HIT_OTHER_CORE_FWD ocr.demand_data_rd.l3_hit_f.hit_other_core_fwd Counts demand data reads DEMAND_DATA_RD & L3_HIT_F & HIT_OTHER_CORE_FWD ocr.all_data_rd.l3_hit_s.hit_other_core_no_fwd ALL_DATA_RD & L3_HIT_S & HIT_OTHER_CORE_NO_FWD ocr.all_reads.l3_hit_m.snoop_none ALL_READS & L3_HIT_M & SNOOP_NONE ocr.pf_l2_rfo.l3_hit_s.snoop_miss period=200003,umask=0x20,event=0x28 ocr.pf_l1d_and_sw.l3_hit.hitm_other_core Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT & HITM_OTHER_CORE ocr.pf_l2_rfo.l3_hit.no_snoop_needed Counts all prefetch (that bring data to L2) RFOs hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores ocr.pf_l1d_and_sw.l3_hit_e.hitm_other_core Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_E & HITM_OTHER_CORE ocr.all_pf_rfo.l3_hit_f.hit_other_core_no_fwd ALL_PF_RFO & L3_HIT_F & HIT_OTHER_CORE_NO_FWD ocr.pf_l3_data_rd.pmm_hit_local_pmm.any_snoop Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & PMM_HIT_LOCAL_PMM & ANY_SNOOP ocr.demand_code_rd.supplier_none.any_snoop Counts all demand code reads DEMAND_CODE_RD & SUPPLIER_NONE & ANY_SNOOP ocr.pf_l1d_and_sw.l3_hit_s.any_snoop Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_S & ANY_SNOOP ocr.demand_rfo.l3_hit_e.hit_other_core_fwd Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_E & HIT_OTHER_CORE_FWD ocr.all_pf_rfo.l3_hit_f.snoop_miss ALL_PF_RFO & L3_HIT_F & SNOOP_MISS ocr.demand_code_rd.l3_hit.hit_other_core_no_fwd Counts all demand code reads DEMAND_CODE_RD & L3_HIT & HIT_OTHER_CORE_NO_FWD ocr.all_pf_data_rd.l3_hit_f.hit_other_core_no_fwd ALL_PF_DATA_RD & L3_HIT_F & HIT_OTHER_CORE_NO_FWD ocr.other.l3_hit_f.any_snoop Counts any other requests OTHER & L3_HIT_F & ANY_SNOOP ocr.pf_l1d_and_sw.l3_hit_s.snoop_none ocr.all_reads.supplier_none.no_snoop_needed ALL_READS & SUPPLIER_NONE & NO_SNOOP_NEEDED ocr.all_pf_data_rd.l3_hit_f.snoop_none ALL_PF_DATA_RD & L3_HIT_F & SNOOP_NONE ocr.demand_rfo.l3_hit_s.hit_other_core_fwd Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_S & HIT_OTHER_CORE_FWD ocr.all_reads.l3_hit_f.snoop_none ALL_READS & L3_HIT_F & SNOOP_NONE ocr.pf_l1d_and_sw.l3_hit.any_snoop Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT & ANY_SNOOP ocr.pf_l3_data_rd.l3_hit.hitm_other_core Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT & HITM_OTHER_CORE ocr.pf_l3_rfo.l3_hit_s.hit_other_core_no_fwd Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_S & HIT_OTHER_CORE_NO_FWD ocr.pf_l2_data_rd.l3_hit_f.no_snoop_needed Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_F & NO_SNOOP_NEEDED ocr.all_pf_rfo.l3_hit_m.hitm_other_core ALL_PF_RFO & L3_HIT_M & HITM_OTHER_CORE ocr.demand_code_rd.l3_hit_f.hitm_other_core Counts all demand code reads DEMAND_CODE_RD & L3_HIT_F & HITM_OTHER_CORE ocr.demand_rfo.l3_hit.hit_other_core_fwd Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT & HIT_OTHER_CORE_FWD ocr.pf_l3_data_rd.l3_hit_f.hit_other_core_fwd Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_F & HIT_OTHER_CORE_FWD ocr.pf_l3_data_rd.l3_hit_m.hit_other_core_fwd Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_M & HIT_OTHER_CORE_FWD ocr.all_pf_data_rd.pmm_hit_local_pmm.any_snoop ALL_PF_DATA_RD & PMM_HIT_LOCAL_PMM & ANY_SNOOP ocr.pf_l1d_and_sw.supplier_none.hit_other_core_fwd Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & SUPPLIER_NONE & HIT_OTHER_CORE_FWD ocr.all_data_rd.l3_hit.snoop_none ALL_DATA_RD & L3_HIT & SNOOP_NONE ocr.demand_rfo.l3_hit_s.any_snoop Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_S & ANY_SNOOP ocr.all_rfo.l3_hit_s.snoop_miss ALL_RFO & L3_HIT_S & SNOOP_MISS ocr.all_pf_data_rd.l3_hit_e.any_snoop ALL_PF_DATA_RD & L3_HIT_E & ANY_SNOOP ocr.pf_l3_data_rd.l3_hit_e.snoop_miss ocr.pf_l2_rfo.l3_hit_m.hit_other_core_no_fwd Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_M & HIT_OTHER_CORE_NO_FWD ocr.pf_l3_rfo.l3_hit.any_snoop Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT & ANY_SNOOP ocr.all_data_rd.l3_hit_m.snoop_miss ALL_DATA_RD & L3_HIT_M & SNOOP_MISS ocr.pf_l3_data_rd.l3_hit_m.snoop_none ocr.pf_l3_rfo.l3_hit.no_snoop_needed Counts all prefetch (that bring data to LLC only) RFOs hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores ocr.pf_l3_data_rd.pmm_hit_local_pmm.snoop_none Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & PMM_HIT_LOCAL_PMM & SNOOP_NONE ocr.all_pf_rfo.l3_hit_f.hit_other_core_fwd ALL_PF_RFO & L3_HIT_F & HIT_OTHER_CORE_FWD ocr.all_pf_rfo.l3_hit_e.snoop_none ALL_PF_RFO & L3_HIT_E & SNOOP_NONE ocr.demand_rfo.l3_hit_e.hitm_other_core Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_E & HITM_OTHER_CORE ocr.all_pf_data_rd.l3_hit_m.snoop_miss ALL_PF_DATA_RD & L3_HIT_M & SNOOP_MISS ocr.demand_rfo.l3_hit_e.no_snoop_needed Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_E & NO_SNOOP_NEEDED ocr.pf_l2_rfo.supplier_none.hit_other_core_fwd Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & SUPPLIER_NONE & HIT_OTHER_CORE_FWD ocr.other.l3_hit_m.snoop_none ocr.demand_rfo.l3_hit_e.hit_other_core_no_fwd Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_E & HIT_OTHER_CORE_NO_FWD ocr.demand_data_rd.l3_hit_e.snoop_miss ocr.all_rfo.l3_hit_f.no_snoop_needed ALL_RFO & L3_HIT_F & NO_SNOOP_NEEDED ocr.all_pf_data_rd.l3_hit_e.no_snoop_needed ALL_PF_DATA_RD & L3_HIT_E & NO_SNOOP_NEEDED ocr.demand_code_rd.l3_hit_m.snoop_miss ocr.demand_rfo.l3_hit_m.hit_other_core_no_fwd Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_M & HIT_OTHER_CORE_NO_FWD ocr.demand_data_rd.l3_hit_m.hitm_other_core Counts demand data reads DEMAND_DATA_RD & L3_HIT_M & HITM_OTHER_CORE ocr.pf_l1d_and_sw.l3_hit_f.hitm_other_core Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_F & HITM_OTHER_CORE ocr.pf_l1d_and_sw.l3_hit_s.snoop_miss ocr.demand_data_rd.pmm_hit_local_pmm.snoop_not_needed Counts demand data reads DEMAND_DATA_RD & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDED ocr.all_rfo.l3_hit_m.no_snoop_needed ALL_RFO & L3_HIT_M & NO_SNOOP_NEEDED ocr.demand_data_rd.pmm_hit_local_pmm.any_snoop Counts demand data reads DEMAND_DATA_RD & PMM_HIT_LOCAL_PMM & ANY_SNOOP ocr.all_data_rd.l3_hit_f.no_snoop_needed ALL_DATA_RD & L3_HIT_F & NO_SNOOP_NEEDED ocr.demand_rfo.pmm_hit_local_pmm.any_snoop Counts all demand data writes (RFOs) DEMAND_RFO & PMM_HIT_LOCAL_PMM & ANY_SNOOP ocr.pf_l2_data_rd.pmm_hit_local_pmm.any_snoop Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & PMM_HIT_LOCAL_PMM & ANY_SNOOP ocr.other.l3_hit.any_snoop Counts any other requests OTHER & L3_HIT & ANY_SNOOP ocr.pf_l3_data_rd.l3_hit_f.no_snoop_needed Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_F & NO_SNOOP_NEEDED ocr.all_pf_rfo.l3_hit_s.snoop_miss ALL_PF_RFO & L3_HIT_S & SNOOP_MISS ocr.pf_l2_data_rd.l3_hit.hitm_other_core Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT & HITM_OTHER_CORE ocr.all_reads.l3_hit_e.hitm_other_core ALL_READS & L3_HIT_E & HITM_OTHER_CORE ocr.pf_l2_data_rd.l3_hit_s.snoop_none ocr.demand_code_rd.pmm_hit_local_pmm.any_snoop Counts all demand code reads DEMAND_CODE_RD & PMM_HIT_LOCAL_PMM & ANY_SNOOP ocr.all_data_rd.l3_hit_e.hit_other_core_no_fwd ALL_DATA_RD & L3_HIT_E & HIT_OTHER_CORE_NO_FWD ocr.demand_data_rd.supplier_none.hit_other_core_fwd Counts demand data reads DEMAND_DATA_RD & SUPPLIER_NONE & HIT_OTHER_CORE_FWD ocr.other.l3_hit_f.hit_other_core_fwd Counts any other requests OTHER & L3_HIT_F & HIT_OTHER_CORE_FWD ocr.pf_l3_rfo.supplier_none.snoop_none ocr.demand_data_rd.l3_hit.any_snoop Counts demand data reads DEMAND_DATA_RD & L3_HIT & ANY_SNOOP ocr.pf_l3_data_rd.l3_hit_m.snoop_miss ocr.pf_l1d_and_sw.l3_hit.snoop_miss Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT & SNOOP_MISS ocr.all_pf_rfo.l3_hit.snoop_hit_with_fwd ALL_PF_RFO & L3_HIT & SNOOP_HIT_WITH_FWD ocr.all_pf_rfo.supplier_none.hitm_other_core ALL_PF_RFO & SUPPLIER_NONE & HITM_OTHER_CORE ocr.other.l3_hit_s.hit_other_core_no_fwd Counts any other requests OTHER & L3_HIT_S & HIT_OTHER_CORE_NO_FWD ocr.all_pf_data_rd.l3_hit.hit_other_core_no_fwd ALL_PF_DATA_RD & L3_HIT & HIT_OTHER_CORE_NO_FWD ocr.other.l3_hit_s.snoop_none ocr.pf_l3_data_rd.supplier_none.snoop_miss ocr.all_reads.pmm_hit_local_pmm.snoop_not_needed ALL_READS & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDED ocr.pf_l2_data_rd.l3_hit_m.any_snoop Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_M & ANY_SNOOP ocr.pf_l2_data_rd.l3_hit_f.any_snoop Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_F & ANY_SNOOP ocr.demand_code_rd.l3_hit.no_snoop_needed Counts all demand code reads hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores ocr.pf_l3_rfo.l3_hit_f.snoop_miss ocr.pf_l3_data_rd.l3_hit_f.snoop_none ocr.pf_l2_rfo.l3_hit_m.snoop_miss ocr.pf_l3_data_rd.supplier_none.no_snoop_needed Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & SUPPLIER_NONE & NO_SNOOP_NEEDED ocr.all_reads.l3_hit_m.hitm_other_core ALL_READS & L3_HIT_M & HITM_OTHER_CORE ocr.pf_l3_data_rd.l3_hit_s.snoop_miss ocr.all_reads.supplier_none.hitm_other_core ALL_READS & SUPPLIER_NONE & HITM_OTHER_CORE ocr.all_data_rd.l3_hit_m.any_snoop ALL_DATA_RD & L3_HIT_M & ANY_SNOOP ocr.all_rfo.l3_hit_e.no_snoop_needed ALL_RFO & L3_HIT_E & NO_SNOOP_NEEDED ocr.pf_l1d_and_sw.l3_hit_f.hit_other_core_no_fwd Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_F & HIT_OTHER_CORE_NO_FWD ocr.pf_l3_rfo.l3_hit_f.any_snoop Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_F & ANY_SNOOP ocr.pf_l2_data_rd.l3_hit_m.snoop_miss ocr.pf_l3_data_rd.l3_hit_e.snoop_none ocr.demand_code_rd.l3_hit_f.snoop_none ocr.other.l3_hit.no_snoop_needed Counts any other requests hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores ocr.all_pf_rfo.l3_hit_f.hitm_other_core ALL_PF_RFO & L3_HIT_F & HITM_OTHER_CORE ocr.pf_l3_rfo.l3_hit_s.no_snoop_needed Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_S & NO_SNOOP_NEEDED ocr.demand_data_rd.l3_hit.snoop_hit_with_fwd ocr.all_rfo.l3_hit.any_snoop ALL_RFO & L3_HIT & ANY_SNOOP ocr.pf_l3_rfo.l3_hit.hit_other_core_no_fwd Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT & HIT_OTHER_CORE_NO_FWD ocr.pf_l2_data_rd.l3_hit_e.no_snoop_needed Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_E & NO_SNOOP_NEEDED ocr.other.l3_hit_e.snoop_miss ocr.pf_l1d_and_sw.l3_hit_e.any_snoop Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_E & ANY_SNOOP ocr.all_data_rd.supplier_none.any_snoop ALL_DATA_RD & SUPPLIER_NONE & ANY_SNOOP ocr.all_rfo.l3_hit_m.snoop_none ALL_RFO & L3_HIT_M & SNOOP_NONE ocr.pf_l2_rfo.supplier_none.no_snoop_needed Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & SUPPLIER_NONE & NO_SNOOP_NEEDED ocr.all_pf_data_rd.pmm_hit_local_pmm.snoop_not_needed ALL_PF_DATA_RD & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDED ocr.demand_rfo.supplier_none.snoop_none ocr.demand_rfo.l3_hit_s.snoop_miss ocr.all_rfo.supplier_none.any_snoop ALL_RFO & SUPPLIER_NONE & ANY_SNOOP ocr.pf_l3_data_rd.supplier_none.hit_other_core_fwd Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & SUPPLIER_NONE & HIT_OTHER_CORE_FWD ocr.demand_data_rd.supplier_none.hit_other_core_no_fwd Counts demand data reads DEMAND_DATA_RD & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWD ocr.all_pf_data_rd.l3_hit_m.hitm_other_core ALL_PF_DATA_RD & L3_HIT_M & HITM_OTHER_CORE period=2000003,umask=0x8,event=0x32 ocr.all_pf_data_rd.l3_hit_s.snoop_miss ALL_PF_DATA_RD & L3_HIT_S & SNOOP_MISS ocr.pf_l2_rfo.l3_hit_s.hit_other_core_fwd Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_S & HIT_OTHER_CORE_FWD ocr.all_data_rd.l3_hit_e.hit_other_core_fwd ALL_DATA_RD & L3_HIT_E & HIT_OTHER_CORE_FWD ocr.all_pf_rfo.l3_hit_m.any_snoop ALL_PF_RFO & L3_HIT_M & ANY_SNOOP ocr.all_pf_rfo.l3_hit_m.snoop_miss ALL_PF_RFO & L3_HIT_M & SNOOP_MISS ocr.pf_l2_data_rd.supplier_none.hitm_other_core Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & SUPPLIER_NONE & HITM_OTHER_CORE ocr.all_pf_data_rd.supplier_none.hit_other_core_no_fwd ALL_PF_DATA_RD & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWD ocr.demand_code_rd.l3_hit.any_snoop Counts all demand code reads DEMAND_CODE_RD & L3_HIT & ANY_SNOOP ocr.all_pf_data_rd.l3_hit_f.hit_other_core_fwd ALL_PF_DATA_RD & L3_HIT_F & HIT_OTHER_CORE_FWD ocr.all_rfo.l3_hit_e.snoop_miss ALL_RFO & L3_HIT_E & SNOOP_MISS ocr.demand_data_rd.l3_hit_m.hit_other_core_no_fwd Counts demand data reads DEMAND_DATA_RD & L3_HIT_M & HIT_OTHER_CORE_NO_FWD ocr.pf_l2_data_rd.l3_hit.hit_other_core_fwd Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT & HIT_OTHER_CORE_FWD ocr.pf_l3_rfo.l3_hit_s.hit_other_core_fwd Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_S & HIT_OTHER_CORE_FWD ocr.pf_l3_data_rd.l3_hit.no_snoop_needed Counts all prefetch (that bring data to LLC only) data reads hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores ocr.pf_l3_data_rd.l3_hit_m.hitm_other_core Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_M & HITM_OTHER_CORE ocr.pf_l2_data_rd.l3_hit_e.hitm_other_core Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_E & HITM_OTHER_CORE ocr.all_pf_rfo.supplier_none.no_snoop_needed ALL_PF_RFO & SUPPLIER_NONE & NO_SNOOP_NEEDED ocr.all_rfo.l3_hit_s.hit_other_core_fwd ALL_RFO & L3_HIT_S & HIT_OTHER_CORE_FWD ocr.all_pf_rfo.supplier_none.hit_other_core_no_fwd ALL_PF_RFO & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWD period=200003,umask=0x18,event=0x28 ocr.pf_l2_rfo.l3_hit_m.hit_other_core_fwd Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_M & HIT_OTHER_CORE_FWD ocr.demand_code_rd.l3_hit_f.hit_other_core_no_fwd Counts all demand code reads DEMAND_CODE_RD & L3_HIT_F & HIT_OTHER_CORE_NO_FWD ocr.pf_l3_data_rd.supplier_none.snoop_none ocr.pf_l2_rfo.l3_hit_m.hitm_other_core Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_M & HITM_OTHER_CORE ocr.demand_data_rd.pmm_hit_local_pmm.snoop_none Counts demand data reads DEMAND_DATA_RD & PMM_HIT_LOCAL_PMM & SNOOP_NONE ocr.demand_code_rd.l3_hit_e.no_snoop_needed Counts all demand code reads DEMAND_CODE_RD & L3_HIT_E & NO_SNOOP_NEEDED ocr.pf_l3_rfo.l3_hit_e.any_snoop Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_E & ANY_SNOOP ocr.all_pf_data_rd.l3_hit_s.snoop_none ALL_PF_DATA_RD & L3_HIT_S & SNOOP_NONE ocr.pf_l2_rfo.l3_hit_s.hit_other_core_no_fwd Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_S & HIT_OTHER_CORE_NO_FWD ocr.all_rfo.l3_hit_e.any_snoop ALL_RFO & L3_HIT_E & ANY_SNOOP ocr.all_pf_rfo.l3_hit_s.hit_other_core_no_fwd ALL_PF_RFO & L3_HIT_S & HIT_OTHER_CORE_NO_FWD ocr.all_data_rd.pmm_hit_local_pmm.snoop_not_needed ALL_DATA_RD & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDED ocr.pf_l3_data_rd.l3_hit_e.no_snoop_needed Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_E & NO_SNOOP_NEEDED ocr.demand_rfo.l3_hit_f.any_snoop Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_F & ANY_SNOOP ocr.all_pf_rfo.l3_hit.snoop_none ALL_PF_RFO & L3_HIT & SNOOP_NONE period=203,umask=0x1,event=0xcb ocr.pf_l3_data_rd.l3_hit_f.snoop_miss ocr.pf_l2_rfo.supplier_none.snoop_miss ocr.pf_l3_data_rd.l3_hit.snoop_hit_with_fwd ocr.pf_l2_rfo.l3_hit.hitm_other_core Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT & HITM_OTHER_CORE ocr.other.l3_hit_s.hitm_other_core Counts any other requests OTHER & L3_HIT_S & HITM_OTHER_CORE ocr.pf_l3_data_rd.l3_hit_s.no_snoop_needed Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_S & NO_SNOOP_NEEDED ocr.demand_data_rd.l3_hit_m.snoop_none ocr.demand_rfo.l3_hit.snoop_none Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT & SNOOP_NONE ocr.all_data_rd.l3_hit_m.hit_other_core_no_fwd ALL_DATA_RD & L3_HIT_M & HIT_OTHER_CORE_NO_FWD ocr.all_pf_rfo.supplier_none.hit_other_core_fwd ALL_PF_RFO & SUPPLIER_NONE & HIT_OTHER_CORE_FWD ocr.all_pf_data_rd.l3_hit_s.no_snoop_needed ALL_PF_DATA_RD & L3_HIT_S & NO_SNOOP_NEEDED ocr.demand_rfo.any_response ocr.demand_code_rd.l3_hit_m.hitm_other_core Counts all demand code reads DEMAND_CODE_RD & L3_HIT_M & HITM_OTHER_CORE ocr.demand_code_rd.supplier_none.no_snoop_needed Counts all demand code reads DEMAND_CODE_RD & SUPPLIER_NONE & NO_SNOOP_NEEDED ocr.demand_data_rd.l3_hit_s.snoop_none ocr.demand_rfo.supplier_none.hit_other_core_no_fwd Counts all demand data writes (RFOs) DEMAND_RFO & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWD ocr.demand_code_rd.l3_hit_s.hit_other_core_fwd Counts all demand code reads DEMAND_CODE_RD & L3_HIT_S & HIT_OTHER_CORE_FWD ocr.other.l3_hit_f.hit_other_core_no_fwd Counts any other requests OTHER & L3_HIT_F & HIT_OTHER_CORE_NO_FWD ocr.pf_l3_rfo.any_response ocr.all_data_rd.l3_hit_e.snoop_miss ALL_DATA_RD & L3_HIT_E & SNOOP_MISS ocr.all_pf_data_rd.l3_hit_e.hit_other_core_no_fwd ALL_PF_DATA_RD & L3_HIT_E & HIT_OTHER_CORE_NO_FWD ocr.pf_l3_rfo.l3_hit_m.no_snoop_needed Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_M & NO_SNOOP_NEEDED ocr.demand_data_rd.l3_hit_s.any_snoop Counts demand data reads DEMAND_DATA_RD & L3_HIT_S & ANY_SNOOP ocr.all_data_rd.l3_hit.snoop_miss ALL_DATA_RD & L3_HIT & SNOOP_MISS ocr.other.l3_hit_m.hit_other_core_no_fwd Counts any other requests OTHER & L3_HIT_M & HIT_OTHER_CORE_NO_FWD ocr.pf_l2_data_rd.l3_hit.any_snoop Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT & ANY_SNOOP ocr.other.l3_hit_f.snoop_miss ocr.all_pf_data_rd.l3_hit.snoop_none ALL_PF_DATA_RD & L3_HIT & SNOOP_NONE ocr.all_pf_rfo.supplier_none.any_snoop ALL_PF_RFO & SUPPLIER_NONE & ANY_SNOOP ocr.pf_l2_data_rd.l3_hit.no_snoop_needed Counts prefetch (that bring data to L2) data reads hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores ocr.pf_l1d_and_sw.l3_hit_f.snoop_none ocr.pf_l2_rfo.l3_hit_e.hit_other_core_fwd Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_E & HIT_OTHER_CORE_FWD ocr.all_data_rd.l3_hit_f.hit_other_core_fwd ALL_DATA_RD & L3_HIT_F & HIT_OTHER_CORE_FWD ocr.pf_l1d_and_sw.l3_hit_s.hitm_other_core Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_S & HITM_OTHER_CORE ocr.pf_l2_data_rd.supplier_none.snoop_none ocr.demand_code_rd.l3_hit_m.snoop_none ocr.demand_code_rd.l3_hit_e.hit_other_core_no_fwd Counts all demand code reads DEMAND_CODE_RD & L3_HIT_E & HIT_OTHER_CORE_NO_FWD ocr.pf_l3_rfo.l3_hit_e.hit_other_core_no_fwd Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_E & HIT_OTHER_CORE_NO_FWD ocr.pf_l2_data_rd.l3_hit_m.hitm_other_core Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_M & HITM_OTHER_CORE ocr.demand_data_rd.supplier_none.snoop_miss ocr.demand_data_rd.l3_hit_e.hit_other_core_no_fwd Counts demand data reads DEMAND_DATA_RD & L3_HIT_E & HIT_OTHER_CORE_NO_FWD ocr.all_reads.l3_hit_f.hit_other_core_no_fwd ALL_READS & L3_HIT_F & HIT_OTHER_CORE_NO_FWD ocr.all_rfo.l3_hit_e.hitm_other_core ALL_RFO & L3_HIT_E & HITM_OTHER_CORE ocr.pf_l2_rfo.l3_hit.snoop_hit_with_fwd ocr.demand_rfo.l3_hit_f.hit_other_core_no_fwd Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_F & HIT_OTHER_CORE_NO_FWD ocr.pf_l2_rfo.l3_hit_e.snoop_miss ocr.pf_l1d_and_sw.supplier_none.snoop_none ocr.all_data_rd.supplier_none.no_snoop_needed ALL_DATA_RD & SUPPLIER_NONE & NO_SNOOP_NEEDED ocr.pf_l3_rfo.l3_hit_s.any_snoop Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_S & ANY_SNOOP ocr.all_pf_rfo.l3_hit_f.any_snoop ALL_PF_RFO & L3_HIT_F & ANY_SNOOP ocr.pf_l1d_and_sw.l3_hit.no_snoop_needed Counts L1 data cache hardware prefetch requests and software prefetch requests hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores ocr.pf_l3_data_rd.l3_hit_m.hit_other_core_no_fwd Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_M & HIT_OTHER_CORE_NO_FWD ocr.pf_l2_data_rd.l3_hit_f.hitm_other_core Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_F & HITM_OTHER_CORE ocr.pf_l2_rfo.l3_hit_m.no_snoop_needed Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_M & NO_SNOOP_NEEDED ocr.other.l3_hit.hitm_other_core Counts any other requests OTHER & L3_HIT & HITM_OTHER_CORE ocr.pf_l3_rfo.l3_hit_m.hit_other_core_fwd Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_M & HIT_OTHER_CORE_FWD ocr.pf_l3_rfo.l3_hit_s.snoop_miss ocr.pf_l1d_and_sw.l3_hit_e.hit_other_core_no_fwd Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_E & HIT_OTHER_CORE_NO_FWD ocr.demand_data_rd.l3_hit_f.hitm_other_core Counts demand data reads DEMAND_DATA_RD & L3_HIT_F & HITM_OTHER_CORE period=2000003,umask=0x1,event=0x32 ocr.demand_code_rd.l3_hit_f.no_snoop_needed Counts all demand code reads DEMAND_CODE_RD & L3_HIT_F & NO_SNOOP_NEEDED ocr.demand_code_rd.l3_hit_m.hit_other_core_fwd Counts all demand code reads DEMAND_CODE_RD & L3_HIT_M & HIT_OTHER_CORE_FWD ocr.all_pf_rfo.l3_hit_s.snoop_none ALL_PF_RFO & L3_HIT_S & SNOOP_NONE ocr.demand_code_rd.l3_hit_s.snoop_none ocr.pf_l1d_and_sw.l3_hit_m.no_snoop_needed Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_M & NO_SNOOP_NEEDED ocr.pf_l1d_and_sw.l3_hit.hit_other_core_fwd Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT & HIT_OTHER_CORE_FWD ocr.pf_l1d_and_sw.l3_hit_f.snoop_miss ocr.all_rfo.l3_hit_e.snoop_none ALL_RFO & L3_HIT_E & SNOOP_NONE ocr.pf_l2_rfo.l3_hit_s.any_snoop Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_S & ANY_SNOOP ocr.pf_l2_rfo.l3_hit_s.no_snoop_needed Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_S & NO_SNOOP_NEEDED ocr.all_rfo.l3_hit_f.snoop_none ALL_RFO & L3_HIT_F & SNOOP_NONE ocr.pf_l3_data_rd.l3_hit.hit_other_core_fwd Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT & HIT_OTHER_CORE_FWD ocr.demand_data_rd.l3_hit_m.no_snoop_needed Counts demand data reads DEMAND_DATA_RD & L3_HIT_M & NO_SNOOP_NEEDED ocr.pf_l2_data_rd.l3_hit_s.hit_other_core_fwd Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_S & HIT_OTHER_CORE_FWD ocr.all_data_rd.supplier_none.hitm_other_core ALL_DATA_RD & SUPPLIER_NONE & HITM_OTHER_CORE ocr.all_pf_data_rd.l3_hit_e.hit_other_core_fwd ALL_PF_DATA_RD & L3_HIT_E & HIT_OTHER_CORE_FWD ocr.other.l3_hit_f.no_snoop_needed Counts any other requests OTHER & L3_HIT_F & NO_SNOOP_NEEDED ocr.all_reads.l3_hit_s.any_snoop ALL_READS & L3_HIT_S & ANY_SNOOP ocr.demand_rfo.l3_hit_e.snoop_miss ocr.pf_l2_data_rd.supplier_none.hit_other_core_fwd Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & SUPPLIER_NONE & HIT_OTHER_CORE_FWD ocr.pf_l3_data_rd.l3_hit.hit_other_core_no_fwd Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT & HIT_OTHER_CORE_NO_FWD ocr.pf_l3_rfo.l3_hit_f.snoop_none ocr.pf_l3_data_rd.l3_hit_e.hit_other_core_fwd Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_E & HIT_OTHER_CORE_FWD ocr.all_rfo.pmm_hit_local_pmm.snoop_not_needed ALL_RFO & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDED ocr.pf_l3_rfo.l3_hit_e.hit_other_core_fwd Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_E & HIT_OTHER_CORE_FWD ocr.pf_l3_data_rd.l3_hit_m.any_snoop Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_M & ANY_SNOOP ocr.all_pf_rfo.pmm_hit_local_pmm.snoop_not_needed ALL_PF_RFO & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDED ocr.all_data_rd.supplier_none.hit_other_core_fwd ALL_DATA_RD & SUPPLIER_NONE & HIT_OTHER_CORE_FWD ocr.pf_l1d_and_sw.l3_hit_e.hit_other_core_fwd Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_E & HIT_OTHER_CORE_FWD ocr.pf_l2_data_rd.l3_hit_f.hit_other_core_no_fwd Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_F & HIT_OTHER_CORE_NO_FWD ocr.all_reads.l3_hit_s.snoop_miss ALL_READS & L3_HIT_S & SNOOP_MISS period=100007,umask=0x40,event=0xc4 Far branch instructions retired Spec update: SKL091 (Precise event) This event counts far branch instructions retired Spec update: SKL091 (Precise event) cmask=4,period=2000003,umask=0x4,event=0xa3 period=2000003,umask=0x20,event=0xe cmask=10,inv=1,period=2000003,umask=0x2,event=0xc2 period=2000003,event=0x3c cmask=1,inv=1,period=2000003,umask=0x2,event=0xc2 cmask=1,inv=1,period=2000003,umask=0x2,event=0xb1 any=1,period=2000003,umask=0x1,event=0xd cmask=4,period=2000003,umask=0x1,event=0xa8 any=1,period=25003,umask=0x1,event=0x3c period=100007,umask=0x2,event=0xc4 This event counts both direct and indirect near call instructions retired Spec update: SKL091 (Precise event) cmask=1,period=2000003,umask=0x1,event=0x14 period=25003,umask=0x2,event=0x3c period=400009,umask=0x20,event=0xc5 period=2000003,umask=0x20,event=0xcc period=400009,umask=0x1,event=0xc4 This event counts conditional branch instructions retired Spec update: SKL091 (Precise event) period=2000003,umask=0x80,event=0xd cmask=1,period=2000003,umask=0x1,event=0xb1 cmask=1,inv=1,period=2000003,umask=0x1,event=0xb1 period=2000003,umask=0x10,event=0xa6 cmask=5,period=2000003,umask=0x5,event=0xa3 period=400009,umask=0x4,event=0xc5 cmask=2,period=2000003,umask=0x1,event=0xb1 period=25003,umask=0x1,event=0x3c period=400009,event=0xc4 period=2000003,umask=0x1,event=0xa1 period=2000003,umask=0x2,event=0xa1 period=2000003,umask=0x4,event=0xa1 period=2000003,umask=0x8,event=0xa1 period=2000003,umask=0x10,event=0xa1 period=2000003,umask=0x20,event=0xa1 period=2000003,umask=0x40,event=0xa1 period=2000003,umask=0x80,event=0xa1 period=2000003,umask=0x8,event=0xa6 cmask=1,edge=1,inv=1,period=2000003,umask=0x1,event=0x5e cmask=1,inv=1,period=2000003,umask=0x1,event=0xe period=2000003,umask=0x1,event=0xa8 period=2000003,umask=0x1,event=0x87 period=400009,umask=0x20,event=0xc4 This event counts taken branch instructions retired Spec update: SKL091 (Precise event) period=2000003,umask=0x1,event=0xe period=2000003,umask=0x1,event=0xa2 cmask=20,period=2000003,umask=0x14,event=0xa3 period=2000003,umask=0x1,event=0xa6 period=2000003,umask=0x8,event=0xa2 period=400009,umask=0x10,event=0xc4 Not taken branch instructions retired Spec update: SKL091 This event counts not taken branch instructions retired Spec update: SKL091 cmask=12,period=2000003,umask=0xc,event=0xa3 period=2000003,umask=0x4,event=0xa6 period=2000003,umask=0x10,event=0xb1 period=100003,umask=0x1,event=0x4c period=400009,umask=0x2,event=0xc5 Counts both taken and not taken retired mispredicted direct and indirect near calls, including both register and memory indirect (Precise event) period=2000003,umask=0x1,event=0xb1 cmask=3,period=2000003,umask=0x1,event=0xb1 cmask=1,period=2000003,umask=0x1,event=0xa8 period=2000003,umask=0x1,event=0xd cmask=8,period=2000003,umask=0x8,event=0xa3 period=2000003,umask=0x1,event=0xc0 br_inst_retired.cond_ntaken cmask=3,period=2000003,umask=0x2,event=0xb1 cmask=1,period=2000003,umask=0x2,event=0xb1 cmask=4,period=2000003,umask=0x2,event=0xb1 period=100003,umask=0x3f,event=0xc1 period=2000003,umask=0x40,event=0xa6 cmask=16,period=2000003,umask=0x10,event=0xa3 period=2000003,umask=0x40,event=0xcc cmask=4,period=2000003,umask=0x1,event=0xb1 period=2000003,umask=0x1,event=0x59 period=2000003,umask=0x2,event=0xc2 period=2000003,umask=0x2,event=0xe Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to Mixing Intel AVX and Intel SSE Code section of the Optimization Guide period=100007,umask=0x8,event=0xc4 This event counts return instructions retired Spec update: SKL091 (Precise event) cmask=2,period=2000003,umask=0x2,event=0xb1 period=400009,umask=0x1,event=0xc5 cmask=10,inv=1,period=2000003,umask=0x1,event=0xc0 period=100003,umask=0x1,event=0x7 cmask=1,edge=1,period=100003,umask=0x1,event=0xc3 period=100003,umask=0x1,event=0xe6 period=100003,umask=0x2,event=0x3 Loads blocked due to overlapping with a preceding store that cannot be forwarded Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide period=2000003,umask=0x3,event=0 period=400009,event=0xc5 period=100003,umask=0x8,event=0x3 period=100003,umask=0x4,event=0xc3 any=1,period=2000003,event=0x3c period=2000003,umask=0x1,event=0x5e cmask=1,edge=1,period=100007,event=0x3c period=400009,umask=0x4,event=0xc4 period=2000003,umask=0x2,event=0xa6 period=2000003,umask=0x2,event=0xb1 cmask=1,period=2000003,umask=0x1,event=0xa3 Cycles where DRAM ranks are in power down (CKE) mode+C37. Unit: uncore_imc unc_m_pmm_rpq_inserts event=0xe3 Write requests allocated in the PMM Write Pending Queue for Intel Optane DC persistent memory. Unit: uncore_imc unc_m_pmm_wpq_inserts event=0xe7 unc_m_pmm_bandwidth.read Intel Optane DC persistent memory bandwidth read (MB/sec). Derived from unc_m_pmm_rpq_inserts. Unit: uncore_imc 6.103515625E-5MB/sec unc_m_pmm_bandwidth.write Intel Optane DC persistent memory bandwidth write (MB/sec). Derived from unc_m_pmm_wpq_inserts. Unit: uncore_imc unc_m_pmm_bandwidth.total Intel Optane DC persistent memory bandwidth total (MB/sec). Derived from unc_m_pmm_rpq_inserts. Unit: uncore_imc unc_m_pmm_rpq_inserts + unc_m_pmm_wpq_inserts UNC_M_PMM_BANDWIDTH.TOTAL unc_m_pmm_rpq_occupancy.all umask=0x1,event=0xe0 Read Pending Queue Occupancy of all read requests for Intel Optane DC persistent memory. Unit: uncore_imc unc_m_pmm_read_latency Intel Optane DC persistent memory read latency (ns). Derived from unc_m_pmm_rpq_occupancy.all. Unit: uncore_imc 6000000000ns unc_m_pmm_rpq_occupancy.all / unc_m_pmm_rpq_inserts / unc_m_clockticks UNC_M_PMM_READ_LATENCY All DRAM Read CAS Commands issued (does not include underfills). Unit: uncore_imc unc_m_cas_count.wr_wmm umask=0x4,event=0x4 DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode. Unit: uncore_imc Counts the total number or DRAM Write CAS commands issued on this channel while in Write-Major-Mode unc_m_pmm_cmd1.all umask=0x1,event=0xea All commands for Intel Optane DC persistent memory. Unit: uncore_imc All commands for Intel Optane DC persistent memory unc_m_pmm_cmd1.rd umask=0x2,event=0xea Regular reads(RPQ) commands for Intel Optane DC persistent memory. Unit: uncore_imc All Reads - RPQ or Ufill unc_m_pmm_cmd1.ufill_rd umask=0x8,event=0xea Underfill read commands for Intel Optane DC persistent memory. Unit: uncore_imc Underfill reads unc_m_pmm_cmd1.wr umask=0x4,event=0xea Write commands for Intel Optane DC persistent memory. Unit: uncore_imc Writes unc_m_pmm_wpq_occupancy.all umask=0x1,event=0xe4 Write Pending Queue Occupancy of all write requests for Intel Optane DC persistent memory. Unit: uncore_imc Write Pending Queue Occupancy of all write requests for Intel Optane DC persistent memory unc_m_tagchk.hit umask=0x1,event=0xd3 All hits to Near Memory(DRAM cache) in Memory Mode. Unit: uncore_imc Tag Check; Hit unc_m_tagchk.miss_clean umask=0x2,event=0xd3 All Clean line misses to Near Memory(DRAM cache) in Memory Mode. Unit: uncore_imc Tag Check; Clean unc_m_tagchk.miss_dirty umask=0x4,event=0xd3 All dirty line misses to Near Memory(DRAM cache) in Memory Mode. Unit: uncore_imc Tag Check; Dirty Counts the number of entries in the Write Pending Queue (WPQ) at each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule writes out to the memory controller and to track the requests. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC (memory controller). They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the 'not posted' filter, we can track how long writes spent in the iMC before completions were sent to the HA. The 'posted' filter, on the other hand, provides information about how much queueing is actually happenning in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts. Is there a filter of sorts??? umask=0xf,event=0x2 unc_iio_data_req_of_cpu.mem_write.part0 + unc_iio_data_req_of_cpu.mem_write.part1 + unc_iio_data_req_of_cpu.mem_write.part2 + unc_iio_data_req_of_cpu.mem_write.part3 unc_cha_fast_asserted.horz umask=0x02,event=0xa5 FaST wire asserted; Horizontal. Unit: uncore_cha Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across unc_cha_llc_victims.total_e umask=0x02,event=0x37 Lines Victimized; Lines in E state. Unit: uncore_cha Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.total_f umask=0x08,event=0x37 Lines Victimized; Lines in F State. Unit: uncore_cha unc_cha_llc_victims.total_m umask=0x01,event=0x37 Lines Victimized; Lines in M state. Unit: uncore_cha unc_cha_llc_victims.total_s umask=0x04,event=0x37 Lines Victimized; Lines in S State. Unit: uncore_cha unc_cha_rxc_inserts.irq umask=0x01,event=0x13 Ingress (from CMS) Allocations; IRQ. Unit: uncore_cha Counts number of allocations per cycle into the specified Ingress queue unc_cha_rxc_irq1_reject.pa_match umask=0x80,event=0x19 Ingress (from CMS) Request Queue Rejects; PhyAddr Match. Unit: uncore_cha Ingress (from CMS) Request Queue Rejects; PhyAddr Match unc_cha_rxc_occupancy.irq umask=0x01,event=0x11 Ingress (from CMS) Occupancy; IRQ. Unit: uncore_cha Counts number of entries in the specified Ingress queue in each cycle unc_cha_sf_eviction.e_state umask=0x02,event=0x3d Snoop filter capacity evictions for E-state entries. Unit: uncore_cha Counts snoop filter capacity evictions for entries tracking exclusive lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline unc_cha_sf_eviction.m_state umask=0x01,event=0x3d Snoop filter capacity evictions for M-state entries. Unit: uncore_cha Counts snoop filter capacity evictions for entries tracking modified lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline unc_cha_sf_eviction.s_state umask=0x04,event=0x3d Snoop filter capacity evictions for S-state entries. Unit: uncore_cha Counts snoop filter capacity evictions for entries tracking shared lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline Counts when a transaction with the opcode type Rsp*WB Snoop Response was received which indicates which indicates the data was written back to it's home. This is returned when a non-RFO request hits a cacheline in the Modified state. The Cache can either downgrade the cacheline to a S (Shared) or I (Invalid) state depending on how the system has been configured. This reponse will also be sent when a cache requests E (Exclusive) ownership of a cache line without receiving data, because the cache must acquire ownership Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part0. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus Write request of 4 bytes made to IIO Part2 by the CPU. Unit: uncore_iio Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part2 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus Write request of 4 bytes made to IIO Part3 by the CPU. Unit: uncore_iio Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part3 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.peer_read.part0 fc_mask=0x07,ch_mask=0x01,umask=0x08,event=0xc0 Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0. Unit: uncore_iio Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part0. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.peer_read.part1 fc_mask=0x07,ch_mask=0x02,umask=0x08,event=0xc0 Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part1. Unit: uncore_iio Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part1. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.peer_read.part2 fc_mask=0x07,ch_mask=0x04,umask=0x08,event=0xc0 Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part2. Unit: uncore_iio Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part2. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.peer_read.part3 fc_mask=0x07,ch_mask=0x08,umask=0x08,event=0xc0 Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part3. Unit: uncore_iio Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part3. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.peer_write.part0 fc_mask=0x07,ch_mask=0x01,umask=0x02,event=0xc0 Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit. Unit: uncore_iio Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part0 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.peer_write.part1 fc_mask=0x07,ch_mask=0x02,umask=0x02,event=0xc0 Peer to peer write request of 4 bytes made to IIO Part1 by a different IIO unit. Unit: uncore_iio Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part1 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.peer_write.part2 fc_mask=0x07,ch_mask=0x04,umask=0x02,event=0xc0 Peer to peer write request of 4 bytes made to IIO Part2 by a different IIO unit. Unit: uncore_iio Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part2 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.peer_write.part3 fc_mask=0x07,ch_mask=0x08,umask=0x02,event=0xc0 Peer to peer write request of 4 bytes made to IIO Part3 by a different IIO unit. Unit: uncore_iio Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part3 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.peer_read.part0 fc_mask=0x07,ch_mask=0x01,umask=0x08,event=0x83 Peer to peer read request for 4 bytes made by IIO Part0 to an IIO target. Unit: uncore_iio Counts every peer to peer read request for 4 bytes of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.peer_read.part1 fc_mask=0x07,ch_mask=0x02,umask=0x08,event=0x83 Peer to peer read request for 4 bytes made by IIO Part1 to an IIO target. Unit: uncore_iio Counts every peer to peer read request for 4 bytes of data made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.peer_read.part2 fc_mask=0x07,ch_mask=0x04,umask=0x08,event=0x83 Peer to peer read request for 4 bytes made by IIO Part2 to an IIO target. Unit: uncore_iio Counts every peer to peer read request for 4 bytes of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.peer_read.part3 fc_mask=0x07,ch_mask=0x08,umask=0x08,event=0x83 Peer to peer read request for 4 bytes made by IIO Part3 to an IIO target. Unit: uncore_iio Counts every peer to peer read request for 4 bytes of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.peer_write.part0 fc_mask=0x07,ch_mask=0x01,umask=0x02,event=0x83 Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target. Unit: uncore_iio Counts every peer to peer write request of 4 bytes of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.peer_write.part1 fc_mask=0x07,ch_mask=0x02,umask=0x02,event=0x83 Counts every peer to peer write request of 4 bytes of data made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.peer_write.part2 fc_mask=0x07,ch_mask=0x04,umask=0x02,event=0x83 Counts every peer to peer write request of 4 bytes of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.peer_write.part3 fc_mask=0x07,ch_mask=0x08,umask=0x02,event=0x83 Counts every peer to peer write request of 4 bytes of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part0. In the general case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus Write request of up to a 64 byte transaction is made to IIO Part2 by the CPU. Unit: uncore_iio Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part2 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus Write request of up to a 64 byte transaction is made to IIO Part3 by the CPU. Unit: uncore_iio Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part3 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.peer_read.part0 fc_mask=0x07,ch_mask=0x01,umask=0x08,event=0xc1 Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part0. Unit: uncore_iio Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part0. Does not include requests made by the same IIO unit. In the general case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.peer_read.part1 fc_mask=0x07,ch_mask=0x02,umask=0x08,event=0xc1 Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part1. Unit: uncore_iio Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part1. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.peer_read.part2 fc_mask=0x07,ch_mask=0x04,umask=0x08,event=0xc1 Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part2. Unit: uncore_iio Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part2. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.peer_read.part3 fc_mask=0x07,ch_mask=0x08,umask=0x08,event=0xc1 Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part3. Unit: uncore_iio Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part3. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.peer_write.part0 fc_mask=0x07,ch_mask=0x01,umask=0x02,event=0xc1 Peer to peer write request of up to a 64 byte transaction is made to IIO Part0 by a different IIO unit. Unit: uncore_iio Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part0 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.peer_write.part1 fc_mask=0x07,ch_mask=0x02,umask=0x02,event=0xc1 Peer to peer write request of up to a 64 byte transaction is made to IIO Part1 by a different IIO unit. Unit: uncore_iio Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part1 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.peer_write.part2 fc_mask=0x07,ch_mask=0x04,umask=0x02,event=0xc1 Peer to peer write request of up to a 64 byte transaction is made to IIO Part2 by a different IIO unit. Unit: uncore_iio Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part2 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.peer_write.part3 fc_mask=0x07,ch_mask=0x08,umask=0x02,event=0xc1 Peer to peer write request of up to a 64 byte transaction is made to IIO Part3 by a different IIO unit. Unit: uncore_iio Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part3 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.peer_read.part0 fc_mask=0x07,ch_mask=0x01,umask=0x08,event=0x84 Peer to peer read request of up to a 64 byte transaction is made by IIO Part0 to an IIO target. Unit: uncore_iio Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.peer_read.part1 fc_mask=0x07,ch_mask=0x02,umask=0x08,event=0x84 Peer to peer read request of up to a 64 byte transaction is made by IIO Part1 to an IIO target. Unit: uncore_iio Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.peer_read.part2 fc_mask=0x07,ch_mask=0x04,umask=0x08,event=0x84 Peer to peer read request of up to a 64 byte transaction is made by IIO Part2 to an IIO target. Unit: uncore_iio Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.peer_read.part3 fc_mask=0x07,ch_mask=0x08,umask=0x08,event=0x84 Peer to peer read request of up to a 64 byte transaction is made by IIO Part3 to an IIO target. Unit: uncore_iio Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.peer_write.part0 fc_mask=0x07,ch_mask=0x01,umask=0x02,event=0x84 Peer to peer write request of up to a 64 byte transaction is made by IIO Part0 to an IIO target. Unit: uncore_iio Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.peer_write.part1 fc_mask=0x07,ch_mask=0x02,umask=0x02,event=0x84 Peer to peer write request of up to a 64 byte transaction is made by IIO Part1 to an IIO target. Unit: uncore_iio Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part1 to the MMIO space of an IIO target.In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.peer_write.part2 fc_mask=0x07,ch_mask=0x04,umask=0x02,event=0x84 Peer to peer write request of up to a 64 byte transaction is made by IIO Part2 to an IIO target. Unit: uncore_iio Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.peer_write.part3 fc_mask=0x07,ch_mask=0x08,umask=0x02,event=0x84 Peer to peer write request of up to a 64 byte transaction is made by IIO Part3 to an IIO target. Unit: uncore_iio Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus Multi-socket cacheline Directory lookups (cacheline found in A state). Unit: uncore_m2m Multi-socket cacheline Directory lookup (cacheline found in I state). Unit: uncore_m2m Multi-socket cacheline Directory lookup (cacheline found in S state). Unit: uncore_m2m Multi-socket cacheline Directory update from/to Any state. Unit: uncore_m2m unc_m2m_imc_reads.to_pmm umask=0x8,event=0x37 Read requests to Intel Optane DC persistent memory issued to the iMC from M2M. Unit: uncore_m2m M2M Reads Issued to iMC; All, regardless of priority unc_m2m_imc_writes.ni umask=0x80,event=0x38 M2M Writes Issued to iMC; All, regardless of priority. Unit: uncore_m2m M2M Writes Issued to iMC; All, regardless of priority unc_m2m_imc_writes.to_pmm umask=0x20,event=0x38 Write requests to Intel Optane DC persistent memory issued to the iMC from M2M. Unit: uncore_m2m Counts when the M2M (Mesh to Memory) recieves a prefetch request and inserts it into its outstanding prefetch queue. Explanatory Side Note: the prefect queue is made from CAM: Content Addressable Memory Counts when the a new entry is Received(RxC) and then added to the AD (Address Ring) Ingress Queue from the CMS (Common Mesh Stop). This is generally used for reads, and unc_m2m_rxc_ad_occupancy event=0x2 AD Ingress (from CMS) Occupancy. Unit: uncore_m2m AD Ingress (from CMS) Occupancy unc_m2m_rxc_bl_inserts BL Ingress (from CMS) Allocations. Unit: uncore_m2m BL Ingress (from CMS) Allocations unc_m2m_rxc_bl_occupancy BL Ingress (from CMS) Occupancy. Unit: uncore_m2m BL Ingress (from CMS) Occupancy unc_m2m_tag_hit.nm_rd_hit_dirty umask=0x02,event=0x2c Dirty line read hits(Regular and RFO) to Near Memory(DRAM cache) in Memory Mode. Unit: uncore_m2m Tag Hit; Read Hit from NearMem, Dirty Line unc_m2m_tag_hit.nm_ufill_hit_clean umask=0x04,event=0x2c Clean line underfill read hits to Near Memory(DRAM cache) in Memory Mode. Unit: uncore_m2m Tag Hit; Underfill Rd Hit from NearMem, Clean Line unc_m2m_tag_hit.nm_ufill_hit_dirty umask=0x08,event=0x2c Dirty line underfill read hits to Near Memory(DRAM cache) in Memory Mode. Unit: uncore_m2m Tag Hit; Underfill Rd Hit from NearMem, Dirty Line unc_m2m_txc_ad_inserts event=0x9 AD Egress (to CMS) Allocations. Unit: uncore_m2m AD Egress (to CMS) Allocations unc_m2m_txc_ad_occupancy AD Egress (to CMS) Occupancy. Unit: uncore_m2m AD Egress (to CMS) Occupancy unc_m2m_txc_bl_inserts.all umask=0x03,event=0x15 BL Egress (to CMS) Allocations; All. Unit: uncore_m2m BL Egress (to CMS) Allocations; All unc_m2m_txc_bl_occupancy.all umask=0x03,event=0x16 BL Egress (to CMS) Occupancy; All. Unit: uncore_m2m BL Egress (to CMS) Occupancy; All Counts incoming FLITs (FLow control unITs) which bypassed the slot0 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency Counts incoming FLITs (FLow control unITs) which bypassed the slot1 RxQ buffer (Receive Queue) and passed directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency FLITs received which bypassed the Slot0 Recieve Buffer. Unit: uncore_upi ll Counts incoming FLITs (FLow control unITs) whcih bypassed the slot2 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency unc_upi_txl_flits.data Valid Flits Sent; Data. Unit: uncore_upi ll Shows legal flit time (hides impact of L0p and L0c).; Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting. period=100003,umask=0x4,event=0x49 period=100003,umask=0x10,event=0x85 period=100003,umask=0xe,event=0x85 period=100003,umask=0x1,event=0x8 period=100007,umask=0x20,event=0xbd cmask=1,period=100003,umask=0x10,event=0x8 period=100003,umask=0x8,event=0x49 period=100003,umask=0x1,event=0x49 period=100007,umask=0x1,event=0xae period=2000003,umask=0x10,event=0x49 period=2000003,umask=0x2,event=0x8 period=2000003,umask=0x4,event=0x8 period=2000003,umask=0x10,event=0x8 period=2000003,umask=0x10,event=0x4f cmask=1,period=100003,umask=0x10,event=0x49 period=100003,umask=0x1,event=0x85 period=100003,umask=0x20,event=0x49 period=100003,umask=0xe,event=0x8 period=100003,umask=0x2,event=0x49 period=100003,umask=0x2,event=0x85 period=100003,umask=0x8,event=0x85 period=100003,umask=0x20,event=0x85 period=2000003,umask=0x8,event=0x8 period=100003,umask=0x4,event=0x85 period=100003,umask=0xe,event=0x49 cmask=1,period=100003,umask=0x10,event=0x85 period=2000003,umask=0x20,event=0x8 period=100007,umask=0x1,event=0xbd Counts demand requests that miss L2 cache l2_rqsts.swpf_miss umask=0x28,period=200003,event=0x24 SW prefetch requests that miss L2 cache Counts Software prefetch requests that miss the L2 cache. This event accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache l2_rqsts.swpf_hit umask=0xc8,period=200003,event=0x24 SW prefetch requests that hit L2 cache Counts Software prefetch requests that hit the L2 cache. This event accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions Counts demand requests to L2 cache Number of L1D misses that are outstanding Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailablability Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses l1d_pend_miss.fb_full_periods umask=0x2,period=2000003,cmask=1,edge=1,event=0x48 Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailablability Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses l1d_pend_miss.l2_stall umask=0x4,period=2000003,event=0x48 Number of cycles a demand request has waited due to L1D due to lack of L2 resources Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses Counts the number of cache lines replaced in L1 data cache Counts retired load instructions that true miss the STLB Supports address when precise (Precise event) Counts retired store instructions that true miss the STLB Supports address when precise (Precise event) Counts retired load instructions with locked access Supports address when precise (Precise event) Counts all retired load instructions. This event accounts for SW prefetch instructions for loads Supports address when precise (Precise event) Counts all retired store instructions. This event account for SW prefetch instructions and PREFETCHW instruction for stores Supports address when precise (Precise event) Counts retired load instructions with L2 cache hits as data sources Supports address when precise (Precise event) Counts retired load instructions missed L2 cache as data sources Supports address when precise (Precise event) Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1 Supports address when precise (Precise event) Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache Supports address when precise (Precise event) Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache Supports address when precise (Precise event) Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache Supports address when precise (Precise event) Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache Supports address when precise (Precise event) Retired load instructions whose data sources were HitM responses from shared L3 Supports address when precise (Precise event) Counts retired load instructions whose data sources were HitM responses from shared L3 Supports address when precise (Precise event) Retired load instructions whose data sources were hits in L3 without snoops required Supports address when precise (Precise event) Counts retired load instructions whose data sources were hits in L3 without snoops required Supports address when precise (Precise event) sq_misc.sq_full umask=0x4,period=100003,event=0xf4 Cycles the thread is active and superQ cannot take any more entries Counts the cycles for which the thread is active and the superQ cannot take any more entries assists.fp umask=0x2,period=100003,cmask=1,event=0xc1 Counts all microcode FP assists Counts all microcode Floating Point assists Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT14 RCP14 RANGE DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element Counts number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 RANGE FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 RANGE FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 RANGE FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 RANGE FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB) idq.mite_cycles_ok umask=0x4,period=2000003,cmask=5,event=0x79 Cycles MITE is delivering optimal number of Uops Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB) idq.mite_cycles_any Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB) Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path idq.dsb_cycles_ok umask=0x8,period=2000003,cmask=5,event=0x79 Cycles DSB is delivering optimal number of Uops idq.dsb_cycles_any Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path umask=0x30,period=2000003,cmask=1,edge=1,event=0x79 Number of switches from DSB or MITE to the MS Uops delivered to IDQ while MS is busy idq.ms_cycles_any Cycles when uops are being delivered to IDQ while MS is busy Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity Counts instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses Counts instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss Uops not delivered by IDQ when backend of the machine is not stalled Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle umask=0x1,period=2000003,cmask=5,event=0x9c Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle DSB-to-MITE switch true penalty cycles Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE Retired Instructions who experienced DSB miss (Precise event) Counts retired Instructions who experienced Instruction L1 Cache true miss (Precise event) Counts retired Instructions who experienced Instruction L2 Cache true miss (Precise event) umask=0x1,period=100007,event=0xc6,frontend=0x500206 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall (Precise event) umask=0x1,period=100007,event=0xc6,frontend=0x500406 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall (Precise event) umask=0x1,period=100007,event=0xc6,frontend=0x500806 umask=0x1,period=100007,event=0xc6,frontend=0x501006 umask=0x1,period=100007,event=0xc6,frontend=0x502006 umask=0x1,period=100007,event=0xc6,frontend=0x504006 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall (Precise event) umask=0x1,period=100007,event=0xc6,frontend=0x508006 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall (Precise event) umask=0x1,period=100007,event=0xc6,frontend=0x510006 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall (Precise event) umask=0x1,period=100007,event=0xc6,frontend=0x520006 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall (Precise event) Counts the number of times a TSX line had a cache conflict Speculatively counts the number TSX Aborts due to a data capacity limitation for transactional writes Speculatively counts the number Transactional Synchronization Extensions (TSX) Aborts due to a data capacity limitation for transactional writes umask=0x4,period=100003,event=0x54 Counts the number of times a TSX Abort was triggered due to a non-release/commit store to lock Counts the number of times a TSX Abort was triggered due to commit but Lock Buffer not empty Counts the number of times a TSX Abort was triggered due to release/commit but data and address mismatch Counts the number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer Counts the number of times we could not allocate Lock Buffer Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region Counts Unfriendly TSX abort triggered by a vzeroupper instruction Number of times an instruction execution caused the transactional nest count supported to be exceeded Counts Unfriendly TSX abort triggered by a nest count that is too deep Number of machine clears due to memory ordering conflicts Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture Counts the number of times we entered an HLE region. Does not count nested transactions Number of times an HLE execution successfully committed Supports address when precise Counts the number of times HLE commit succeeded Supports address when precise Number of times an HLE execution aborted due to any reasons (multiple categories may count as one) Counts the number of times HLE abort was triggered Counts the number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts) Counts the number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.) Counts the number of times an HLE execution aborted due to unfriendly events (such as interrupts) Counts the number of times we entered an RTM region. Does not count nested transactions Counts the number of times RTM commit succeeded Number of times an RTM execution aborted Supports address when precise Counts the number of times RTM abort was triggered Supports address when precise Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts) Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions Counts the number of times an RTM execution aborted due to incompatible memory type Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt) topdown.slots umask=0x4,period=10000003,event=0 Counts the number of available slots for an unhalted logical processor Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the Top-down Microarchitecture Analysis method. This event is counted on a designated fixed counter (Fixed Counter 3) and is an architectural event Counts Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes Counts Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture). This includes high current AVX 512-bit instructions Counts the number of PREFETCHNTA instructions executed Counts the number of PREFETCHT0 instructions executed Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed Counts the number of PREFETCHW instructions executed topdown.slots_p umask=0x1,period=10000003,event=0xa4 Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core topdown.backend_bound_slots umask=0x2,period=10000003,event=0xa4 Issue slots where no uops were being issued due to lack of back end resources assists.any umask=0x7,period=100003,event=0xc1 Number of occurrences where a microcode assist is invoked by hardware Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists Number of instructions retired. Fixed Counter - architectural event Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter umask=0x1,period=2000003,event=0 Precise instruction retired event with a reduced effect of PEBS shadow in IP distribution (Must be precise) A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled. Use on Fixed Counter 0 (Must be precise) Counts the number of times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when: a. preceding store conflicts with the load (incomplete overlap),b. store forwarding is impossible due to u-arch limitations, c. preceding lock RMW operations are not forwarded, d. store has the no-forward bit set (uncacheable/page-split/masked stores), e. all-blocking stores are used (mostly, fences and port I/O), and others. The most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events. See the table of not supported store forwards in the Optimization Guide Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use Counts the number of times a load got blocked due to false dependencies in MOB due to partial compare on address Core cycles the allocator was stalled due to recovery from earlier clear event for this thread Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event int_misc.all_recovery_cycles Cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall Counts cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path Uops that RAT issues to RS Cycles when RAT does not issue Uops to RS for the thread umask=0x9,period=2000003,cmask=1,event=0x14 Cycles when divide unit is busy executing divide or square root operations Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations umask=0x1,period=25003,event=0x3c Counts core crystal clock cycles when the thread is unhalted umask=0x2,period=25003,event=0x3c Counts Core crystal clock cycles when current thread is unhalted and the other thread is halted load_hit_prefetch.swpf Counts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into stravation periods (e.g. branch mispredictions or i-cache misses) inv=1,umask=0x1,period=2000003,cmask=1,edge=1,event=0x5e Counts end of periods where the Reservation Station (RS) was empty Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events) uops_dispatched.port_0 Number of uops executed on port 0 uops_dispatched.port_1 Number of uops executed on port 1 uops_dispatched.port_2_3 Number of uops executed on port 2 and 3 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 2 and 3 uops_dispatched.port_4_9 Number of uops executed on port 4 and 9 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 5 and 9 uops_dispatched.port_5 Number of uops executed on port 5 uops_dispatched.port_6 Number of uops executed on port 6 uops_dispatched.port_7_8 Number of uops executed on port 7 and 8 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 7 and 8 resource_stalls.scoreboard Counts cycles where the pipeline is stalled due to serializing operations umask=0x40,period=2000003,cmask=2,event=0xa6 Cycles where the Store Buffer was full and no loads caused an execution stall Counts cycles where the Store Buffer was full and no loads caused an execution stall umask=0x80,period=2000003,event=0xa6 Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector) lsd.cycles_ok umask=0x1,period=2000003,cmask=5,event=0xa8 Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector) uops_executed.cycles_ge_1 uops_executed.cycles_ge_2 uops_executed.cycles_ge_3 uops_executed.cycles_ge_4 Counts the number of uops executed from any thread Counts cycles when at least 1 micro-op is executed from any thread on physical core Counts cycles when at least 2 micro-ops are executed from any thread on physical core Counts cycles when at least 3 micro-ops are executed from any thread on physical core Counts cycles when at least 4 micro-ops are executed from any thread on physical core Number of instructions retired. General Counter - architectural event Counts the number of cycles using always true condition (uops_ret &lt; 16) applied to non PEBS uops retired event uops_retired.slots Counts the retirement slots used each cycle umask=0x1,period=100003,cmask=1,edge=1,event=0xc3 Counts the number of machine clears (nukes) of any type All branch instructions retired (Precise event) Counts all branch instructions retired (Precise event) br_inst_retired.cond_taken Taken conditional branch instructions retired (Precise event) Counts taken conditional branch instructions retired (Precise event) Counts both direct and indirect near call instructions retired (Precise event) Counts return instructions retired (Precise event) Not taken branch instructions retired (Precise event) Counts not taken branch instructions retired (Precise event) br_inst_retired.cond umask=0x11,period=400009,event=0xc4 Counts conditional branch instructions retired (Precise event) Counts taken branch instructions retired (Precise event) Far branch instructions retired (Precise event) Counts far branch instructions retired (Precise event) br_inst_retired.indirect umask=0x80,period=100003,event=0xc4 All indirect branch instructions retired (excluding RETs. TSX aborts are considered indirect branch) (Precise event) Counts all indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch) (Precise event) All mispredicted branch instructions retired Supports address when precise (Precise event) Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path Supports address when precise (Precise event) br_misp_retired.cond_taken number of branch instructions retired that were mispredicted and taken. Non PEBS Supports address when precise (Precise event) Counts taken conditional mispredicted branch instructions retired Supports address when precise (Precise event) br_misp_retired.cond umask=0x11,period=400009,event=0xc5 Mispredicted conditional branch instructions retired Supports address when precise (Precise event) Counts mispredicted conditional branch instructions retired Supports address when precise (Precise event) Number of near branch instructions retired that were mispredicted and taken Supports address when precise (Precise event) Counts number of near branch instructions retired that were mispredicted and taken Supports address when precise (Precise event) br_misp_retired.indirect umask=0x80,period=100003,event=0xc5 All miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch) Supports address when precise (Precise event) Counts all miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch) Supports address when precise (Precise event) misc_retired.lbr_inserts misc_retired.pause_inst Number of retired PAUSE instructions Counts number of retired PAUSE instructions (that do not end up with a VMExit to the VMM; TSX aborted Instructions may be counted) cpu_clk_unhalted.distributed umask=0x2,period=2000003,event=0xec Cycle counts are evenly distributed between active threads in the Core This event distributes cycle counts between active hyperthreads, i.e., those in C0. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If all other hyperthreads are inactive (or disabled or do not exist), all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread Page walks completed due to a demand data load to a 4K page Page walks completed due to a demand data load to a 2M/4M page Number of page walks outstanding for a demand load in the PMH each cycle Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle Cycles when at least one PMH is busy with a page walk for a demand load Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load Page walks completed due to a demand data store to a 4K page Page walks completed due to a demand data store to a 2M/4M page Number of page walks outstanding for a store in the PMH each cycle Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle Cycles when at least one PMH is busy with a page walk for a store Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB) Counts code misses in all ITLB (Instruction TLB) levels that caused a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault Counts completed page walks (2M and 4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault Number of page walks outstanding for an outstanding code request in the PMH each cycle Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB) Counts memory requests originating from the core that miss in the last level cache. If the platform has an L3 cache, last level cache is the L3, otherwise it is the L2 Counts cacheable memory requests that miss in the the Last Level Cache. Requests include Demand Loads, Reads for Ownership(RFO), Instruction fetches and L1 HW prefetches. If the platform has an L3 cache, last level cache is the L3, otherwise it is the L2 Counts memory requests originating from the core that reference a cache line in the last level cache. If the platform has an L3 cache, last level cache is the L3, otherwise it is the L2 Counts cacheable memory requests that access the Last Level Cache. Requests include Demand Loads, Reads for Ownership(RFO), Instruction fetches and L1 HW prefetches. If the platform has an L3 cache, last level cache is the L3, otherwise it is the L2 Counts the number of load uops retired Supports address when precise (Precise event) Counts the number of load uops retired. This event is Precise Event capable Supports address when precise (Precise event) Counts the number of store uops retired Supports address when precise (Precise event) Counts the number of store uops retired. This event is Precise Event capable Supports address when precise (Precise event) Counts the number of load uops retired that hit the level 1 data cache Supports address when precise (Precise event) Counts the number of load uops retired that hit in the level 2 cache Supports address when precise (Precise event) umask=0x4,period=200003,event=0xd1 Counts the number of load uops retired that miss in the level 3 cache (Precise event) Counts the number of load uops retired that miss in the level 1 data cache Supports address when precise (Precise event) Counts the number of load uops retired that miss in the level 2 cache Supports address when precise (Precise event) Counts requests to the Instruction Cache (ICache) for one or more bytes in a cache line and they do not hit in the ICache (miss) Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is not in the ICache (miss). The event strives to count on a cache line basis, so that multiple accesses which miss in a single cache line count as one ICACHE.MISS. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is not in the ICache Counts requests to the Instruction Cache (ICache) for one or more bytes cache Line Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line. The event strives to count on a cache line basis, so that multiple fetches to a single cache line count as one ICACHE.ACCESS. Specifically, the event counts when accesses from straight line code crosses the cache line boundary, or when a branch target is to a new line ocr.demand_data_rd.l3_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x000000003F04000001 Counts demand data reads that was not supplied by the L3 cache ocr.demand_rfo.l3_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x000000003F04000002 Counts all demand reads for ownership (RFO) requests and software based prefetches for exclusive ownership (PREFETCHW) that was not supplied by the L3 cache umask=0x1,period=100003,event=0xb7,offcore_rsp=0x000000000000010001 Counts demand data reads that have any response type umask=0x1,period=100003,event=0xb7,offcore_rsp=0x000000000000010002 Counts all demand reads for ownership (RFO) requests and software based prefetches for exclusive ownership (PREFETCHW) that have any response type Counts the number of instructions retired. (Fixed event) (Precise event) Counts the number of instructions that retire. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0 (Precise event) Counts the number of unhalted core clock cycles. (Fixed event) Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1 Counts the number of unhalted reference clock cycles at TSC frequency. (Fixed event) Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time. This event is not affected by core frequency changes and at a fixed frequency. This event uses fixed counter 2 Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses a programmable general purpose performance counter Counts the number of unhalted reference clock cycles at TSC frequency Counts reference cycles (at TSC frequency) when core is not halted. This event uses a programmable general purpose perfmon counter Counts the number of instructions retired (Precise event) Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The event continues counting during hardware interrupts, traps, and inside interrupt handlers. This is an architectural performance event. This event uses a Programmable general purpose perfmon counter. *This event is Precise Event capable: The EventingRIP field in the PEBS record is precise to the address of the instruction which caused the event (Precise event) machine_clears.any period=20003,event=0xc3 Counts all machine clears due to, but not limited to memory ordering, memory disambiguation, SMC, page faults and FP assist period=200003,event=0xc4 Counts the number of branch instructions retired for all branch types (Precise event) Counts branch instructions retired for all branch types. This event is Precise Event capable. This is an architectural event (Precise event) period=200003,event=0xc5 Counts mispredicted branch instructions retired for all branch types. This event is Precise Event capable. This is an architectural event (Precise event) cycles_div_busy.any period=2000003,event=0xcd Counts cycles the floating point divider or integer divider or both are busy. Does not imply a stall waiting for either divider umask=0x0f,event=0x4 umask=0x30,event=0x4 umask=0x04,event=0x2 umask=0x08,event=0x2 unc_m_pre_count.all umask=0x1c,event=0x2 Precharge due to read on page miss, write on page miss or PGT. Unit: uncore_imc unc_m_pre_count.pgt umask=0x10,event=0x2 DRAM Precharge commands. : Precharge due to page table. Unit: uncore_imc DRAM Precharge commands. : Precharge due to page table : Counts the number of DRAM Precharge commands sent on this channel umask=0xC001FE01,event=0x35,config1=0x40e33 umask=0xC001FE01,event=0x35,config1=0x40040e33 umask=0xC001FE01,event=0x35,config1=0x40041e33 umask=0xC001FE01,event=0x35,config1=0x41833 umask=0xC001FE01,event=0x35,config1=0x41a33 unc_iio_data_req_of_cpu.mem_read.part0 +unc_iio_data_req_of_cpu.mem_read.part1 +unc_iio_data_req_of_cpu.mem_read.part2 +unc_iio_data_req_of_cpu.mem_read.part3 unc_cha_tor_inserts.ia_miss_crd umask=0xC80FFE01,event=0x35 TOR Inserts; CRd misses from local IA. Unit: uncore_cha TOR Inserts; Code read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_crd_pref umask=0xC88FFE01,event=0x35 TOR Inserts; CRd Pref misses from local IA. Unit: uncore_cha TOR Inserts; Code read prefetch from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_drd_opt umask=0xC827FE01,event=0x35 TOR Inserts; DRd Opt misses from local IA. Unit: uncore_cha TOR Inserts; Data read opt from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_drd_opt_pref umask=0xC8A7FE01,event=0x35 TOR Inserts; DRd Opt Pref misses from local IA. Unit: uncore_cha TOR Inserts; Data read opt prefetch from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_rfo umask=0xC807FE01,event=0x35 TOR Inserts; RFO misses from local IA. Unit: uncore_cha TOR Inserts; Read for ownership from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_rfo_pref umask=0xC887FE01,event=0x35 TOR Inserts; RFO pref misses from local IA. Unit: uncore_cha TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_wcil umask=0xC86FFE01,event=0x35 TOR Inserts; WCiL misses from local IA. Unit: uncore_cha TOR Inserts; Data read from local IA that misses in the snoop filter unc_cha_tor_inserts.ia_miss_wcilf umask=0xC867FE01,event=0x35 TOR Inserts; WCiLF misses from local IA. Unit: uncore_cha Clockticks of the integrated IO (IIO) traffic controller. Unit: uncore_iio Clockticks of the integrated IO (IIO) traffic controller unc_iio_data_req_of_cpu.mem_read.part4 fc_mask=0x07,ch_mask=0x10,umask=0x04,event=0x83 Data requested of the CPU : Card reading from DRAM. Unit: uncore_iio Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.mem_read.part5 fc_mask=0x07,ch_mask=0x20,umask=0x04,event=0x83 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.mem_read.part6 fc_mask=0x07,ch_mask=0x40,umask=0x04,event=0x83 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.mem_read.part7 fc_mask=0x07,ch_mask=0x80,umask=0x04,event=0x83 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_iio_data_req_of_cpu.mem_write.part4 fc_mask=0x07,ch_mask=0x10,umask=0x01,event=0x83 Data requested of the CPU : Card writing to DRAM. Unit: uncore_iio Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.mem_write.part5 fc_mask=0x07,ch_mask=0x20,umask=0x01,event=0x83 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.mem_write.part6 fc_mask=0x07,ch_mask=0x40,umask=0x01,event=0x83 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.mem_write.part7 fc_mask=0x07,ch_mask=0x80,umask=0x01,event=0x83 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 unc_i_clockticks Clockticks of the IO coherency tracker (IRP). Unit: uncore_irp Clockticks of the IO coherency tracker (IRP) uncore_irp unc_m2m_clockticks Clockticks of the mesh to memory (M2M). Unit: uncore_m2m Clockticks of the mesh to memory (M2M) unc_m2p_clockticks Clockticks of the mesh to PCI (M2P). Unit: uncore_m2pcie Clockticks of the mesh to PCI (M2P) uncore_m2pcie unc_u_clockticks event=0xff Clockticks in the UBOX using a dedicated 48-bit Fixed Counter. Unit: uncore_ubox Clockticks in the UBOX using a dedicated 48-bit Fixed Counter uncore_ubox Clockticks of the power control unit (PCU). Unit: uncore_pcu Clockticks of the power control unit (PCU) itlb.fills Counts the number of times there was an ITLB miss and a new translation was filled into the ITLB Counts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) and new translation was filled into the ITLB. The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLB bp_l1_btb_correct event=0x8a L1 BTB Correction branch bp_l2_btb_correct event=0x8b L2 BTB Correction bp_dyn_ind_pred event=0x8e Dynamic Indirect Predictions Indirect Branch Prediction for potential multi-target branch (speculative) bp_de_redirect event=0x91 Decoder Overrides Existing Branch Prediction (speculative) ic_fw32 The number of 32B fetch windows transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheable fill responses) ic_fw32_miss The number of 32B fetch windows tried to read the L1 IC and missed in the full tag ic_cache_fill_l2 event=0x82 The number of 64 byte instruction cache line was fulfilled from the L2 cache ic_cache_fill_sys event=0x83 The number of 64 byte instruction cache line fulfilled from system memory or another cache bp_l1_tlb_miss_l2_hit event=0x84 The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB bp_l1_tlb_miss_l2_miss The number of instruction fetches that miss in both the L1 and L2 TLBs bp_snp_re_sync The number of pipeline restarts caused by invalidating probes that hit on the instruction stream currently being executed. This would happen if the active instruction stream was being modified by another processor in an MP system - typically a highly unlikely event ic_fetch_stall.ic_stall_any umask=0x4,event=0x87 Instruction Pipe Stall. IC pipe was stalled during this clock cycle for any reason (nothing valid in pipe ICM1) ic_fetch_stall.ic_stall_dq_empty umask=0x2,event=0x87 Instruction Pipe Stall. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to DQ empty ic_fetch_stall.ic_stall_back_pressure umask=0x1,event=0x87 Instruction Pipe Stall. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure ic_cache_inval.l2_invalidating_probe umask=0x2,event=0x8c IC line invalidated due to L2 invalidating probe (external or LS). The number of instruction cache lines invalidated. A non-SMC event is CMC (cross modifying code), either from the other thread of the core or another core ic_cache_inval.fill_invalidated umask=0x1,event=0x8c IC line invalidated due to overwriting fill response. The number of instruction cache lines invalidated. A non-SMC event is CMC (cross modifying code), either from the other thread of the core or another core bp_tlb_rel event=0x99 The number of ITLB reload requests l2_request_g1.rd_blk_l umask=0x80,event=0x60 All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including hardware and software prefetch) l2_request_g1.rd_blk_x umask=0x40,event=0x60 All L2 Cache Requests (Breakdown 1 - Common). Data cache stores l2_request_g1.ls_rd_blk_c_s umask=0x20,event=0x60 All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads l2_request_g1.cacheable_ic_read umask=0x10,event=0x60 All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads l2_request_g1.change_to_x umask=0x8,event=0x60 All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Request change to writable, check L2 for current state l2_request_g1.prefetch_l2_cmd umask=0x4,event=0x60 All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd l2_request_g1.l2_hw_pf umask=0x2,event=0x60 All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2 pipeline, hit or miss. Types of PF and L2 hit/miss broken out in a separate perfmon event l2_request_g1.group2 umask=0x1,event=0x60 Miscellaneous events covered in more detail by l2_request_g2 (PMCx061) l2_request_g2.group1 umask=0x80,event=0x61 Miscellaneous events covered in more detail by l2_request_g1 (PMCx060) l2_request_g2.ls_rd_sized umask=0x40,event=0x61 All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized l2_request_g2.ls_rd_sized_nc umask=0x20,event=0x61 All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheable l2_request_g2.ic_rd_sized umask=0x10,event=0x61 All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized l2_request_g2.ic_rd_sized_nc umask=0x8,event=0x61 All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized non-cacheable l2_request_g2.smc_inval umask=0x4,event=0x61 All L2 Cache Requests (Breakdown 2 - Rare). Self-modifying code invalidates l2_request_g2.bus_locks_originator umask=0x2,event=0x61 All L2 Cache Requests (Breakdown 2 - Rare). Bus locks l2_request_g2.bus_locks_responses umask=0x1,event=0x61 All L2 Cache Requests (Breakdown 2 - Rare). Bus lock response l2_latency.l2_cycles_waiting_on_fills umask=0x1,event=0x62 Total cycles spent waiting for L2 fills to complete from L3 or memory, divided by four. Event counts are for both threads. To calculate average latency, the number of fills from both threads must be used l2_wcb_req.wcb_write umask=0x40,event=0x63 LS to L2 WCB write requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) write requests l2_wcb_req.wcb_close umask=0x20,event=0x63 LS to L2 WCB close requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) close requests l2_wcb_req.zero_byte_store umask=0x4,event=0x63 LS to L2 WCB zero byte store requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) zero byte store requests l2_wcb_req.cl_zero umask=0x1,event=0x63 LS to L2 WCB cache line zeroing requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) cache line zeroing requests l2_cache_req_stat.ls_rd_blk_cs umask=0x80,event=0x64 Core to L2 cacheable request access status (not including L2 Prefetch). Data cache shared read hit in L2 l2_cache_req_stat.ls_rd_blk_l_hit_x umask=0x40,event=0x64 Core to L2 cacheable request access status (not including L2 Prefetch). Data cache read hit in L2 l2_cache_req_stat.ls_rd_blk_l_hit_s umask=0x20,event=0x64 Core to L2 cacheable request access status (not including L2 Prefetch). Data cache read hit on shared line in L2 l2_cache_req_stat.ls_rd_blk_x umask=0x10,event=0x64 Core to L2 cacheable request access status (not including L2 Prefetch). Data cache store or state change hit in L2 l2_cache_req_stat.ls_rd_blk_c umask=0x8,event=0x64 Core to L2 cacheable request access status (not including L2 Prefetch). Data cache request miss in L2 (all types) l2_cache_req_stat.ic_fill_hit_x umask=0x4,event=0x64 Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache hit modifiable line in L2 l2_cache_req_stat.ic_fill_hit_s umask=0x2,event=0x64 Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache hit clean line in L2 l2_cache_req_stat.ic_fill_miss umask=0x1,event=0x64 Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request miss in L2 l2_fill_pending.l2_fill_busy umask=0x1,event=0x6d Cycles with fill pending from L2. Total cycles spent with one or more fill requests in flight from L2 l3_request_g1.caching_l3_cache_accesses umask=0x80,event=0x1 Caching: L3 cache accesses. Unit: uncore_l3pmc uncore_l3pmc l3_lookup_state.all_l3_req_typs umask=0xff,event=0x4 All L3 Request Types. Unit: uncore_l3pmc l3_comb_clstr_state.other_l3_miss_typs umask=0xfe,event=0x6 Other L3 Miss Request Types. Unit: uncore_l3pmc l3_comb_clstr_state.request_miss umask=0x01,event=0x6 L3 cache misses. Unit: uncore_l3pmc xi_sys_fill_latency umask=0x00,event=0x90 L3 Cache Miss Latency. Total cycles for all transactions divided by 16. Ignores SliceMask and ThreadMask. Unit: uncore_l3pmc xi_ccx_sdp_req1.all_l3_miss_req_typs umask=0x3f,event=0x9a All L3 Miss Request Types. Ignores SliceMask and ThreadMask. Unit: uncore_l3pmc ex_ret_instr Retired Instructions ex_ret_cops event=0xc1 Retired Uops The number of uOps retired. This includes all processor activity (instructions, exceptions, interrupts, microcode assists, etc.). The number of events logged per cycle can vary from 0 to 4 ex_ret_brn event=0xc2 Retired Branch Instructions The number of branch instructions retired. This includes all types of architectural control flow changes, including exceptions and interrupts ex_ret_brn_misp event=0xc3 Retired Branch Instructions Mispredicted The number of branch instructions retired, of any type, that were not correctly predicted. This includes those for which prediction is not attempted (far control transfers, exceptions and interrupts) ex_ret_brn_tkn event=0xc4 Retired Taken Branch Instructions The number of taken branches that were retired. This includes all types of architectural control flow changes, including exceptions and interrupts ex_ret_brn_tkn_misp event=0xc5 Retired Taken Branch Instructions Mispredicted The number of retired taken branch instructions that were mispredicted ex_ret_brn_far event=0xc6 Retired Far Control Transfers The number of far control transfers retired including far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts. Far control transfers are not subject to branch prediction ex_ret_brn_resync event=0xc7 Retired Branch Resyncs The number of resync branches. These reflect pipeline restarts due to certain microcode assists and events such as writes to the active instruction stream, among other things. Each occurrence reflects a restart penalty similar to a branch mispredict. This is relatively rare ex_ret_near_ret event=0xc8 Retired Near Returns The number of near return instructions (RET or RET Iw) retired ex_ret_near_ret_mispred event=0xc9 Retired Near Returns Mispredicted The number of near returns retired that were not correctly predicted by the return address predictor. Each such mispredict incurs the same penalty as a mispredicted conditional branch instruction ex_ret_brn_ind_misp event=0xca Retired Indirect Branch Instructions Mispredicted ex_ret_mmx_fp_instr.sse_instr umask=0x4,event=0xcb SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX) The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX) ex_ret_mmx_fp_instr.mmx_instr umask=0x2,event=0xcb MMX instructions The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. MMX instructions ex_ret_mmx_fp_instr.x87_instr umask=0x1,event=0xcb x87 instructions The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. x87 instructions ex_ret_cond event=0xd1 Retired Conditional Branch Instructions ex_div_busy event=0xd3 Div Cycles Busy count ex_div_count event=0xd4 Div Op Count ex_tagged_ibs_ops.ibs_count_rollover umask=0x4,event=0x1cf Tagged IBS Ops. Number of times an op could not be tagged by IBS because of a previous tagged op that has not retired ex_tagged_ibs_ops.ibs_tagged_ops_ret umask=0x2,event=0x1cf Tagged IBS Ops. Number of Ops tagged by IBS that retired ex_tagged_ibs_ops.ibs_tagged_ops umask=0x1,event=0x1cf Tagged IBS Ops. Number of Ops tagged by IBS ex_ret_fus_brnch_inst event=0x1d0 The number of fused retired branch instructions retired per cycle. The number of events logged per cycle can vary from 0 to 3 df_ccm_reqa.node0.anydram umask=0x0F,event=0x8b Data Fabric CCM Performance Monitor Event DF CCM Request Any DRAM transaction data fabric df_ccm_reqa.node1.anydram umask=0x2F,event=0x8b df_ccm_reqa.node2.anydram umask=0x4F,event=0x8b df_ccm_reqa.node3.anydram umask=0x6F,event=0x8b df_ccm_reqa.node4.anydram umask=0x8F,event=0x8b df_ccm_reqa.node5.anydram umask=0xAF,event=0x8b df_ccm_reqa.node6.anydram umask=0xCF,event=0x8b df_ccm_reqa.node7.anydram umask=0xEF,event=0x8b df_ccm_reqa.node0.wrsizedfullzero umask=0x0E,event=0x8b Data Fabric CCM Performance Monitor Event DF CCM Request Ordered WrSizedFullZero df_ccm_reqa.node1.wrsizedfullzero umask=0x2E,event=0x8b df_ccm_reqa.node2.wrsizedfullzero umask=0x4E,event=0x8b df_ccm_reqa.node3.wrsizedfullzero umask=0x6E,event=0x8e df_ccm_reqa.node4.wrsizedfullzero umask=0x8E,event=0x8b df_ccm_reqa.node5.wrsizedfullzero umask=0xAE,event=0x8b df_ccm_reqa.node6.wrsizedfullzero umask=0xCE,event=0x8b df_ccm_reqa.node7.wrsizedfullzero umask=0xEE,event=0x8b df_ccm_reqa.node0.wrsizedfullnc umask=0x0D,event=0x8b Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullnc df_ccm_reqa.node1.wrsizedfullnc umask=0x2D,event=0x8a df_ccm_reqa.node2.wrsizedfullnc umask=0x4D,event=0x8b df_ccm_reqa.node3.wrsizedfullnc umask=0x6D,event=0x8b df_ccm_reqa.node4.wrsizedfullnc umask=0x8D,event=0x8b df_ccm_reqa.node5.wrsizedfullnc umask=0xAD,event=0x8b df_ccm_reqa.node6.wrsizedfullnc umask=0xCD,event=0x8b df_ccm_reqa.node7.wrsizedfullnc umask=0xED,event=0x8b df_ccm_reqa.node0.wrsized umask=0x0C,event=0x8b Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsized df_ccm_reqa.node1.wrsized umask=0x2C,event=0x8b df_ccm_reqa.node2.wrsized umask=0x4C,event=0x8b df_ccm_reqa.node3.wrsized umask=0x6C,event=0x8b df_ccm_reqa.node4.wrsized umask=0x8C,event=0x8b df_ccm_reqa.node5.wrsized umask=0xAC,event=0x8b df_ccm_reqa.node6.wrsized umask=0xCC,event=0x8b df_ccm_reqa.node7.wrsized umask=0xEC,event=0x8b umask=0x0B,event=0x8b Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullzero umask=0x2B,event=0x8b umask=0x4B,event=0x8b umask=0x6B,event=0x8b umask=0x8B,event=0x8b umask=0xAB,event=0x8b umask=0xCB,event=0x8b umask=0xEB,event=0x8b umask=0x0A,event=0x8b umask=0x2A,event=0x8b umask=0x4A,event=0x8b umask=0x6A,event=0x8b umask=0x8A,event=0x8b umask=0xAA,event=0x8b umask=0xCA,event=0x8b umask=0xEA,event=0x8b umask=0x09,event=0x8b umask=0x29,event=0x8b umask=0x49,event=0x8b umask=0x69,event=0x8b umask=0x89,event=0x8b umask=0xA9,event=0x8b umask=0xC9,event=0x8b umask=0xE9,event=0x8b df_ccm_reqa.node0.rdsizednc umask=0x08,event=0x8b Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdsizednc df_ccm_reqa.node1.rdsizednc umask=0x28,event=0x8b df_ccm_reqa.node2.rdsizednc umask=0x48,event=0x8b df_ccm_reqa.node3.rdsizednc umask=0x68,event=0x8b df_ccm_reqa.node4.rdsizednc umask=0x88,event=0x8b df_ccm_reqa.node5.rdsizednc umask=0xA8,event=0x8b df_ccm_reqa.node6.rdsizednc umask=0xC8,event=0x8b df_ccm_reqa.node7.rdsizednc umask=0xE8,event=0x8b df_ccm_reqa.node0.rdsized umask=0x07,event=0x8b Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdsized df_ccm_reqa.node1.rdsized umask=0x27,event=0x8b df_ccm_reqa.node2.rdsized umask=0x47,event=0x8b df_ccm_reqa.node3.rdsized umask=0x67,event=0x8b df_ccm_reqa.node4.rdsized umask=0x87,event=0x8b df_ccm_reqa.node5.rdsized umask=0xA7,event=0x8b df_ccm_reqa.node6.rdsized umask=0xC7,event=0x8b df_ccm_reqa.node7.rdsized umask=0xE7,event=0x8b df_ccm_reqa.node0.specdramrd umask=0x06,event=0x8b Data Fabric CCM Performance Monitor Event DF CCM Request Ordered specdramrd df_ccm_reqa.node1.specdramrd umask=0x26,event=0x8b df_ccm_reqa.node2.specdramrd umask=0x46,event=0x8b df_ccm_reqa.node3.specdramrd umask=0x66,event=0x8b df_ccm_reqa.node4.specdramrd umask=0x86,event=0x8b df_ccm_reqa.node5.specdramrd umask=0xA6,event=0x8b df_ccm_reqa.node6.specdramrd umask=0xC6,event=0x8b df_ccm_reqa.node7.specdramrd umask=0xE6,event=0x8b df_ccm_reqa.node0.anyrdblk umask=0x05,event=0x8b Data Fabric CCM Performance Monitor Event DF CCM Request Ordered anyrdblk df_ccm_reqa.node1.anyrdblk umask=0x25,event=0x8b df_ccm_reqa.node2.anyrdblk umask=0x45,event=0x8b df_ccm_reqa.node3.anyrdblk umask=0x65,event=0x8b df_ccm_reqa.node4.anyrdblk umask=0x85,event=0x8b df_ccm_reqa.node5.anyrdblk umask=0xA5,event=0x8b df_ccm_reqa.node6.anyrdblk umask=0xC5,event=0x8b df_ccm_reqa.node7.anyrdblk umask=0xE5,event=0x8b df_ccm_reqa.node0.rdvlkc umask=0x04,event=0x8b Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdvlkc df_ccm_reqa.node1.rdvlkc umask=0x24,event=0x8b df_ccm_reqa.node2.rdvlkc umask=0x44,event=0x8b df_ccm_reqa.node3.rdvlkc umask=0x64,event=0x8b df_ccm_reqa.node4.rdvlkc umask=0x84,event=0x8b df_ccm_reqa.node5.rdvlkc umask=0xA4,event=0x8b df_ccm_reqa.node6.rdvlkc umask=0xC4,event=0x8b df_ccm_reqa.node7.rdvlkc umask=0xE4,event=0x8b df_ccm_reqa.node0.rdvlkx umask=0x03,event=0x8b Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdvlkx df_ccm_reqa.node1.rdvlkx umask=0x23,event=0x8b df_ccm_reqa.node2.rdvlkx umask=0x43,event=0x8b df_ccm_reqa.node3.rdvlkx umask=0x63,event=0x8b df_ccm_reqa.node4.rdvlkx umask=0x83,event=0x8b df_ccm_reqa.node5.rdvlkx umask=0xA3,event=0x8b df_ccm_reqa.node6.rdvlkx umask=0xC3,event=0x8b df_ccm_reqa.node7.rdvlkx umask=0xE3,event=0x8b df_ccm_reqa.node0.rdvlks umask=0x02,event=0x8b Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdvlks df_ccm_reqa.node1.rdvlks umask=0x22,event=0x8b df_ccm_reqa.node2.rdvlks umask=0x42,event=0x8b df_ccm_reqa.node3.rdvlks umask=0x62,event=0x8b df_ccm_reqa.node4.rdvlks umask=0x82,event=0x8b df_ccm_reqa.node5.rdvlks umask=0xA2,event=0x8b df_ccm_reqa.node6.rdvlks umask=0xC2,event=0x8b df_ccm_reqa.node7.rdvlks umask=0xE2,event=0x8b df_ccm_reqa.node0.rdvlkl umask=0x01,event=0x8b Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdvlkl df_ccm_reqa.node1.rdvlkl umask=0x21,event=0x8b df_ccm_reqa.node2.rdvlkl umask=0x41,event=0x8b df_ccm_reqa.node3.rdvlkl umask=0x61,event=0x8b df_ccm_reqa.node4.rdvlkl umask=0x81,event=0x8b df_ccm_reqa.node5.rdvlkl umask=0xA1,event=0x8b df_ccm_reqa.node6.rdvlkl umask=0xC1,event=0x8b df_ccm_reqa.node7.rdvlkl umask=0xE1,event=0x8b df_ccm_reqb.node0.chgtox umask=0x0E,event=0x8c Data Fabric CCM Performance Monitor Event DF CCM Request Ordered chgtox df_ccm_reqb.node1.chgtox umask=0x2E,event=0x8c df_ccm_reqb.node2.chgtox umask=0x4E,event=0x8c df_ccm_reqb.node3.chgtox df_ccm_reqb.node4.chgtox umask=0x8E,event=0x8c df_ccm_reqb.node5.chgtox umask=0xAE,event=0x8c df_ccm_reqb.node6.chgtox umask=0xCE,event=0x8c df_ccm_reqb.node7.chgtox umask=0xEE,event=0x8c df_ccm_reqb.node0.vicblkfull. umask=0x0D,event=0x8c Data Fabric CCM Performance Monitor Event DF CCM Request Ordered vicblkfull df_ccm_reqb.node1.vicblkfull. df_ccm_reqb.node2.vicblkfull. umask=0x4D,event=0x8c df_ccm_reqb.node3.vicblkfull. umask=0x6D,event=0x8c df_ccm_reqb.node4.vicblkfull. umask=0x8D,event=0x8c df_ccm_reqb.node5.vicblkfull. umask=0xAD,event=0x8c df_ccm_reqb.node6.vicblkfull. umask=0xCD,event=0x8c df_ccm_reqb.node7.vicblkfull. umask=0xED,event=0x8c df_ccm_reqb.node0.wbinvblkall umask=0x0C,event=0x8c Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wbinvblkall df_ccm_reqb.node1.wbinvblkall umask=0x2C,event=0x8c df_ccm_reqb.node2.wbinvblkall umask=0x4C,event=0x8c df_ccm_reqb.node3.wbinvblkall umask=0x6C,event=0x8c df_ccm_reqb.node4.wbinvblkall umask=0x8C,event=0x8c df_ccm_reqb.node5.wbinvblkall umask=0xAC,event=0x8c df_ccm_reqb.node6.wbinvblkall umask=0xCC,event=0x8c df_ccm_reqb.node7.wbinvblkall umask=0xEC,event=0x8c df_ccm_reqb.node0.vicblkfullzero umask=0x0B,event=0x8c Data Fabric CCM Performance Monitor Event DF CCM Request Ordered vicblkfullzero df_ccm_reqb.node1.vicblkfullzero umask=0x2B,event=0x8c df_ccm_reqb.node2.vicblkfullzero umask=0x4B,event=0x8c df_ccm_reqb.node3.vicblkfullzero umask=0x6B,event=0x8c df_ccm_reqb.node4.vicblkfullzero umask=0x8B,event=0x8c df_ccm_reqb.node5.vicblkfullzero umask=0xAB,event=0x8c df_ccm_reqb.node6.vicblkfullzero umask=0xCB,event=0x8c df_ccm_reqb.node7.vicblkfullzero umask=0xEB,event=0x8c umask=0x0A,event=0x8c umask=0x2A,event=0x8c umask=0x4A,event=0x8c umask=0x6A,event=0x8c umask=0x8A,event=0x8c umask=0xAA,event=0x8c umask=0xCA,event=0x8c umask=0xEA,event=0x8c df_ccm_reqb.node0.vicblkcln umask=0x09,event=0x8c Data Fabric CCM Performance Monitor Event DF CCM Request Ordered vicblkcln df_ccm_reqb.node1.vicblkcln umask=0x29,event=0x8c df_ccm_reqb.node2.vicblkcln umask=0x49,event=0x8c df_ccm_reqb.node3.vicblkcln umask=0x69,event=0x8c df_ccm_reqb.node4.vicblkcln umask=0x89,event=0x8c df_ccm_reqb.node5.vicblkcln umask=0xA9,event=0x8c df_ccm_reqb.node6.vicblkcln umask=0xC9,event=0x8c df_ccm_reqb.node7.vicblkcln umask=0xE9,event=0x8c df_ccm_reqb.node0.anyiorequest. umask=0x07,event=0x8c Data Fabric CCM Performance Monitor Event DF CCM Request Ordered anyiorequest df_ccm_reqb.node1.anyiorequest. umask=0x27,event=0x8c df_ccm_reqb.node2.anyiorequest. umask=0x47,event=0x8c df_ccm_reqb.node3.anyiorequest. umask=0x67,event=0x8c df_ccm_reqb.node4.anyiorequest. umask=0x87,event=0x8c df_ccm_reqb.node5.anyiorequest. umask=0xA7,event=0x8c df_ccm_reqb.node6.anyiorequest. umask=0xC7,event=0x8c df_ccm_reqb.node7.anyiorequest. umask=0xE7,event=0x8c df_ccm_reqb.node0.anywrsized umask=0x06,event=0x8c Data Fabric CCM Performance Monitor Event DF CCM Request Ordered anywrsized df_ccm_reqb.node1.anywrsized umask=0x26,event=0x8c df_ccm_reqb.node2.anywrsized umask=0x46,event=0x8c df_ccm_reqb.node3.anywrsized umask=0x66,event=0x8c df_ccm_reqb.node4.anywrsized umask=0x86,event=0x8c df_ccm_reqb.node5.anywrsized umask=0xA6,event=0x8c df_ccm_reqb.node6.anywrsized umask=0xC6,event=0x8c df_ccm_reqb.node7.anywrsized umask=0xE6,event=0x8c df_ccm_reqb.node0.wrsizedfullnc umask=0x05,event=0x8c df_ccm_reqb.node1.wrsizedfullnc umask=0x25,event=0x8c df_ccm_reqb.node2.wrsizedfullnc umask=0x45,event=0x8c df_ccm_reqb.node3.wrsizedfullnc umask=0x65,event=0x8c df_ccm_reqb.node4.wrsizedfullnc umask=0x85,event=0x8c df_ccm_reqb.node5.wrsizedfullnc umask=0xA5,event=0x8c df_ccm_reqb.node6.wrsizedfullnc umask=0xC5,event=0x8c df_ccm_reqb.node7.wrsizedfullnc umask=0xE5,event=0x8c df_ccm_reqb.node0.wrsizednc umask=0x04,event=0x8c Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizednc df_ccm_reqb.node1.wrsizednc umask=0x24,event=0x8c df_ccm_reqb.node2.wrsizednc umask=0x44,event=0x8c df_ccm_reqb.node3.wrsizednc umask=0x64,event=0x8c df_ccm_reqb.node4.wrsizednc umask=0x84,event=0x8c df_ccm_reqb.node5.wrsizednc umask=0xA4,event=0x8c df_ccm_reqb.node6.wrsizednc umask=0xC4,event=0x8c df_ccm_reqb.node7.wrsizednc umask=0xE4,event=0x8c df_ccm_reqb.node0.wrsizedfullncposted umask=0x03,event=0x8c Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullncposted df_ccm_reqb.node1.wrsizedfullncposted umask=0x23,event=0x8c df_ccm_reqb.node2.wrsizedfullncposted umask=0x43,event=0x8c df_ccm_reqb.node3.wrsizedfullncposted umask=0x63,event=0x8c df_ccm_reqb.node4.wrsizedfullncposted umask=0x83,event=0x8c df_ccm_reqb.node5.wrsizedfullncposted umask=0xA3,event=0x8c df_ccm_reqb.node6.wrsizedfullncposted umask=0xC3,event=0x8c df_ccm_reqb.node7.wrsizedfullncposted umask=0xE3,event=0x8c df_ccm_reqb.node0.wrsizedncposted umask=0x02,event=0x8c Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedncposted df_ccm_reqb.node1.wrsizedncposted umask=0x22,event=0x8c df_ccm_reqb.node2.wrsizedncposted umask=0x42,event=0x8c df_ccm_reqb.node3.wrsizedncposted umask=0x62,event=0x8c df_ccm_reqb.node4.wrsizedncposted umask=0x82,event=0x8c df_ccm_reqb.node5.wrsizedncposted umask=0xA2,event=0x8c df_ccm_reqb.node6.wrsizedncposted umask=0xC2,event=0x8c df_ccm_reqb.node7.wrsizedncposted umask=0xE2,event=0x8c df_ccm_reqb.node0.rdsized umask=0x01,event=0x8c df_ccm_reqb.node1.rdsized umask=0x21,event=0x8c df_ccm_reqb.node2.rdsized umask=0x41,event=0x8c df_ccm_reqb.node3.rdsized umask=0x61,event=0x8c df_ccm_reqb.node4.rdsized umask=0x81,event=0x8c df_ccm_reqb.node5.rdsized umask=0xA1,event=0x8c df_ccm_reqb.node6.rdsized umask=0xC1,event=0x8c df_ccm_reqb.node7.rdsized umask=0xE1,event=0x8c df_ccm_reqc.apicaccess umask=0x01,event=0x8d Data Fabric CCM Performance Monitor Event DF CCM Request Type C (PIE Requests)APIC access df_ccm_reqc.apicucodeaccess umask=0x02,event=0x8d Data Fabric CCM Performance Monitor Event DF CCM Request Type C (PIE Requests)APIC ucode access df_ccm_reqc.fasttprwrite umask=0x03,event=0x8d Data Fabric CCM Performance Monitor Event DF CCM Request Type C (PIE Requests)Fast TPR write df_ccm_reqc.anybuslockrequest umask=0x04,event=0x8d Data Fabric CCM Performance Monitor Event DF CCM Request Type C (PIE Requests)APIC access Any Bus Lock request df_ioms_reqa.node0.masterabort umask=0x0C,event=0x108 Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) masterabort df_ioms_reqa.node1.masterabort umask=0x2C,event=0x108 df_ioms_reqa.node2.masterabort umask=0x4C,event=0x108 df_ioms_reqa.node3.masterabort umask=0x6C,event=0x108 df_ioms_reqa.node4.masterabort umask=0x8C,event=0x108 df_ioms_reqa.node5.masterabort umask=0xAC,event=0x108 df_ioms_reqa.node6.masterabort umask=0xCC,event=0x108 df_ioms_reqa.node7.masterabort umask=0xEC,event=0x108 df_ioms_reqa.node0.ios_resp umask=0x0B,event=0x108 Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) ios_resp df_ioms_reqa.node1.ios_resp umask=0x2B,event=0x108 df_ioms_reqa.node2.ios_resp umask=0x4B,event=0x108 df_ioms_reqa.node3.ios_resp umask=0x6B,event=0x108 df_ioms_reqa.node4.ios_resp umask=0x8B,event=0x108 df_ioms_reqa.node5.ios_resp umask=0xAB,event=0x108 df_ioms_reqa.node6.ios_resp umask=0xCB,event=0x108 df_ioms_reqa.node7.ios_resp umask=0xEB,event=0x108 df_ioms_reqa.node0.flush umask=0x0A,event=0x108 Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) flush df_ioms_reqa.node1.flush umask=0x2A,event=0x108 df_ioms_reqa.node2.flush umask=0x4A,event=0x108 df_ioms_reqa.node3.flush umask=0x6A,event=0x108 df_ioms_reqa.node4.flush umask=0x8A,event=0x108 df_ioms_reqa.node5.flush umask=0xAA,event=0x108 df_ioms_reqa.node6.flush umask=0xCA,event=0x108 df_ioms_reqa.node7.flush umask=0xEA,event=0x108 df_ioms_reqa.node0.fence umask=0x09,event=0x108 Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) fence df_ioms_reqa.node1.fence umask=0x29,event=0x108 df_ioms_reqa.node2.fence umask=0x49,event=0x108 df_ioms_reqa.node3.fence umask=0x69,event=0x108 df_ioms_reqa.node4.fence umask=0x89,event=0x108 df_ioms_reqa.node5.fence umask=0xA9,event=0x108 df_ioms_reqa.node6.fence umask=0xC9,event=0x108 df_ioms_reqa.node7.fence umask=0xE9,event=0x108 df_ioms_reqa.node0.anydramtransaction umask=0x08,event=0x108 Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anydramtransaction df_ioms_reqa.node1.anydramtransaction umask=0x28,event=0x108 df_ioms_reqa.node2.anydramtransaction umask=0x48,event=0x108 df_ioms_reqa.node3.anydramtransaction umask=0x68,event=0x108 df_ioms_reqa.node4.anydramtransaction umask=0x88,event=0x108 df_ioms_reqa.node5.anydramtransaction umask=0xA8,event=0x108 df_ioms_reqa.node6.anydramtransaction umask=0xC8,event=0x108 df_ioms_reqa.node7.anydramtransaction umask=0xE8,event=0x108 df_ioms_reqa.node0.anyatomic umask=0x07,event=0x108 Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anyatomic df_ioms_reqa.node1.anyatomic umask=0x27,event=0x108 df_ioms_reqa.node2.anyatomic umask=0x47,event=0x108 df_ioms_reqa.node3.anyatomic umask=0x67,event=0x108 df_ioms_reqa.node4.anyatomic umask=0x87,event=0x108 df_ioms_reqa.node5.anyatomic umask=0xA7,event=0x108 df_ioms_reqa.node6.anyatomic umask=0xC7,event=0x108 df_ioms_reqa.node7.anyatomic umask=0xE7,event=0x108 df_ioms_reqa.node0.anywrsized=64b umask=0x06,event=0x108 Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized=64b df_ioms_reqa.node1.anywrsized=64b umask=0x26,event=0x108 df_ioms_reqa.node2.anywrsized=64b umask=0x46,event=0x108 df_ioms_reqa.node3.anywrsized=64b umask=0x66,event=0x108 df_ioms_reqa.node4.anywrsized=64b umask=0x86,event=0x108 df_ioms_reqa.node5.anywrsized=64b umask=0xA6,event=0x108 df_ioms_reqa.node6.anywrsized=64b umask=0xC6,event=0x108 df_ioms_reqa.node7.anywrsized=64b umask=0xE6,event=0x108 df_ioms_reqa.node0.anywrsized>32band<64b umask=0x05,event=0x108 Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized>32band<64b df_ioms_reqa.node1.anywrsized>32band<64b umask=0x25,event=0x108 df_ioms_reqa.node2.anywrsized>32band<64b umask=0x45,event=0x108 df_ioms_reqa.node3.anywrsized>32band<64b umask=0x65,event=0x108 df_ioms_reqa.node4.anywrsized>32band<64b umask=0x85,event=0x108 df_ioms_reqa.node5.anywrsized>32band<64b umask=0xA5,event=0x108 df_ioms_reqa.node6.anywrsized>32band<64b umask=0xC5,event=0x108 df_ioms_reqa.node7.anywrsized>32band<64b umask=0xE5,event=0x108 df_ioms_reqa.node0.anywrsized=32b umask=0x04,event=0x108 Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized=32b df_ioms_reqa.node1.anywrsized=32b umask=0x24,event=0x108 df_ioms_reqa.node2.anywrsized=32b umask=0x44,event=0x108 df_ioms_reqa.node3.anywrsized=32b umask=0x64,event=0x108 df_ioms_reqa.node4.anywrsized=32b umask=0x84,event=0x108 df_ioms_reqa.node5.anywrsized=32b umask=0xA4,event=0x108 df_ioms_reqa.node6.anywrsized=32b umask=0xC4,event=0x108 df_ioms_reqa.node7.anywrsized=32b umask=0xE4,event=0x108 df_ioms_reqa.node0.anywrsized<32b umask=0x03,event=0x108 Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized<32b df_ioms_reqa.node1.anywrsized<32b umask=0x23,event=0x108 df_ioms_reqa.node2.anywrsized<32b umask=0x43,event=0x108 df_ioms_reqa.node3.anywrsized<32b umask=0x63,event=0x108 df_ioms_reqa.node4.anywrsized<32b umask=0x83,event=0x108 df_ioms_reqa.node5.anywrsized<32b umask=0xA3,event=0x108 df_ioms_reqa.node6.anywrsized<32b umask=0xC3,event=0x108 df_ioms_reqa.node7.anywrsized<32b umask=0xE3,event=0x108 df_ioms_reqa.node0.anyrdsized umask=0x02,event=0x108 Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anyrdsized df_ioms_reqa.node1.anyrdsized umask=0x22,event=0x108 df_ioms_reqa.node2.anyrdsized umask=0x42,event=0x108 df_ioms_reqa.node3.anyrdsized umask=0x62,event=0x108 df_ioms_reqa.node4.anyrdsized umask=0x82,event=0x108 df_ioms_reqa.node5.anyrdsized umask=0xA2,event=0x108 df_ioms_reqa.node6.anyrdsized umask=0xC2,event=0x108 df_ioms_reqa.node7.anyrdsized umask=0xE2,event=0x108 df_ioms_reqa.node0.largeread umask=0x01,event=0x108 Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) largeread df_ioms_reqa.node1.largeread umask=0x21,event=0x108 df_ioms_reqa.node2.largeread umask=0x41,event=0x108 df_ioms_reqa.node3.largeread umask=0x61,event=0x108 df_ioms_reqa.node4.largeread umask=0x81,event=0x108 df_ioms_reqa.node5.largeread umask=0xA1,event=0x108 df_ioms_reqa.node6.largeread umask=0xC1,event=0x108 df_ioms_reqa.node7.largeread umask=0xE1,event=0x108 df_ioms_reqb.node0.pieiorequest umask=0x0F,event=0x109 Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Any DRAM transaction df_ioms_reqb.node1.pieiorequest umask=0x2F,event=0x109 df_ioms_reqb.node2.pieiorequest umask=0x4F,event=0x109 df_ioms_reqb.node3.pieiorequest umask=0x6F,event=0x109 df_ioms_reqb.node4.pieiorequest umask=0x8F,event=0x109 df_ioms_reqb.node5.pieiorequest umask=0xAF,event=0x109 df_ioms_reqb.node6.pieiorequest umask=0xCF,event=0x109 df_ioms_reqb.node7.pieiorequest umask=0xEF,event=0x109 df_ioms_reqb.node0.piesystemmanagement umask=0x0E,event=0x109 Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered piesystemmanagement df_ioms_reqb.node1.piesystemmanagement umask=0x2E,event=0x109 df_ioms_reqb.node2.piesystemmanagement umask=0x4E,event=0x109 df_ioms_reqb.node3.piesystemmanagement umask=0x6E,event=0x109 df_ioms_reqb.node4.piesystemmanagement umask=0x8E,event=0x109 df_ioms_reqb.node5.piesystemmanagement umask=0xAE,event=0x109 df_ioms_reqb.node6.piesystemmanagement umask=0xCE,event=0x109 df_ioms_reqb.node7.piesystemmanagement umask=0xEE,event=0x109 df_ioms_reqb.node0.pieinterrupt umask=0x0D,event=0x109 Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered pieinterrupt df_ioms_reqb.node1.pieinterrupt umask=0x2D,event=0x109 df_ioms_reqb.node2.pieinterrupt umask=0x4D,event=0x109 df_ioms_reqb.node3.pieinterrupt umask=0x6D,event=0x109 df_ioms_reqb.node4.pieinterrupt umask=0x8D,event=0x109 df_ioms_reqb.node5.pieinterrupt umask=0xAD,event=0x109 df_ioms_reqb.node6.pieinterrupt umask=0xCD,event=0x109 df_ioms_reqb.node7.pieinterrupt umask=0xED,event=0x109 df_ioms_reqb.node0.anyiotransaction umask=0x0C,event=0x109 Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered anyiotransaction df_ioms_reqb.node1.anyiotransaction umask=0x2C,event=0x109 df_ioms_reqb.node2.anyiotransaction umask=0x4C,event=0x109 df_ioms_reqb.node3.anyiotransaction umask=0x6C,event=0x109 df_ioms_reqb.node4.anyiotransaction umask=0x8C,event=0x109 df_ioms_reqb.node5.anyiotransaction umask=0xAC,event=0x109 df_ioms_reqb.node6.anyiotransaction umask=0xCC,event=0x109 df_ioms_reqb.node7.anyiotransaction umask=0xEC,event=0x109 df_ioms_reqb.node0.ioanyatomic umask=0x0B,event=0x109 Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanyatomic df_ioms_reqb.node1.ioanyatomic umask=0x2B,event=0x109 df_ioms_reqb.node2.ioanyatomic umask=0x4B,event=0x109 df_ioms_reqb.node3.ioanyatomic umask=0x6B,event=0x109 df_ioms_reqb.node4.ioanyatomic umask=0x8B,event=0x109 df_ioms_reqb.node5.ioanyatomic umask=0xAB,event=0x109 df_ioms_reqb.node6.ioanyatomic umask=0xCB,event=0x109 df_ioms_reqb.node7.ioanyatomic umask=0xEB,event=0x109 df_ioms_reqb.node0.ioanynon-postedwrsized=64b umask=0x0A,event=0x109 Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized=64b df_ioms_reqb.node1.ioanynon-postedwrsized=64b umask=0x2A,event=0x109 df_ioms_reqb.node2.ioanynon-postedwrsized=64b umask=0x4A,event=0x109 df_ioms_reqb.node3.ioanynon-postedwrsized=64b umask=0x6A,event=0x109 df_ioms_reqb.node4.ioanynon-postedwrsized=64b umask=0x8A,event=0x109 df_ioms_reqb.node5.ioanynon-postedwrsized=64b umask=0xAA,event=0x109 df_ioms_reqb.node6.ioanynon-postedwrsized=64b umask=0xCA,event=0x109 df_ioms_reqb.node7.ioanynon-postedwrsized=64b umask=0xEA,event=0x109 df_ioms_reqb.node0.ioanynon-postedwrsized>32band<64b umask=0x09,event=0x109 Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized>32band<64b df_ioms_reqb.node1.ioanynon-postedwrsized>32band<64b umask=0x29,event=0x109 df_ioms_reqb.node2.ioanynon-postedwrsized>32band<64b umask=0x49,event=0x109 df_ioms_reqb.node3.ioanynon-postedwrsized>32band<64b umask=0x69,event=0x109 df_ioms_reqb.node4.ioanynon-postedwrsized>32band<64b umask=0x89,event=0x109 df_ioms_reqb.node5.ioanynon-postedwrsized>32band<64b umask=0xA9,event=0x109 df_ioms_reqb.node6.ioanynon-postedwrsized>32band<64b umask=0xC9,event=0x109 df_ioms_reqb.node7.ioanynon-postedwrsized>32band<64b umask=0xE9,event=0x109 df_ioms_reqb.node0.ioanynon-postedwrsized=32b umask=0x08,event=0x109 Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized=32b df_ioms_reqb.node1.ioanynon-postedwrsized=32b umask=0x28,event=0x109 df_ioms_reqb.node2.ioanynon-postedwrsized=32b umask=0x48,event=0x109 df_ioms_reqb.node3.ioanynon-postedwrsized=32b umask=0x68,event=0x109 df_ioms_reqb.node4.ioanynon-postedwrsized=32b umask=0x88,event=0x109 df_ioms_reqb.node5.ioanynon-postedwrsized=32b umask=0xA8,event=0x109 df_ioms_reqb.node6.ioanynon-postedwrsized=32b umask=0xC8,event=0x109 df_ioms_reqb.node7.ioanynon-postedwrsized=32b umask=0xE8,event=0x109 df_ioms_reqb.node0.ioanynon-postedwrsized<32b umask=0x07,event=0x109 Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized<32b df_ioms_reqb.node1.ioanynon-postedwrsized<32b umask=0x27,event=0x109 df_ioms_reqb.node2.ioanynon-postedwrsized<32b umask=0x47,event=0x109 df_ioms_reqb.node3.ioanynon-postedwrsized<32b umask=0x67,event=0x109 df_ioms_reqb.node4.ioanynon-postedwrsized<32b umask=0x87,event=0x109 df_ioms_reqb.node5.ioanynon-postedwrsized<32b umask=0xA7,event=0x109 df_ioms_reqb.node6.ioanynon-postedwrsized<32b umask=0xC7,event=0x109 df_ioms_reqb.node7.ioanynon-postedwrsized<32b umask=0xE7,event=0x109 df_ioms_reqb.node0.ioanypostedwrsized=64b umask=0x06,event=0x109 Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized=64b df_ioms_reqb.node1.ioanypostedwrsized=64b umask=0x26,event=0x109 df_ioms_reqb.node2.ioanypostedwrsized=64b umask=0x46,event=0x109 df_ioms_reqb.node3.ioanypostedwrsized=64b umask=0x66,event=0x109 df_ioms_reqb.node4.ioanypostedwrsized=64b umask=0x86,event=0x109 df_ioms_reqb.node5.ioanypostedwrsized=64b umask=0xA6,event=0x109 df_ioms_reqb.node6.ioanypostedwrsized=64b umask=0xC6,event=0x109 df_ioms_reqb.node7.ioanypostedwrsized=64b umask=0xE6,event=0x109 df_ioms_reqb.node0.ioanypostedwrsized>32band<64b umask=0x05,event=0x109 Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized>32band<64b df_ioms_reqb.node1.ioanypostedwrsized>32band<64b umask=0x25,event=0x109 df_ioms_reqb.node2.ioanypostedwrsized>32band<64b umask=0x45,event=0x109 df_ioms_reqb.node3.ioanypostedwrsized>32band<64b umask=0x65,event=0x109 df_ioms_reqb.node4.ioanypostedwrsized>32band<64b umask=0x85,event=0x109 df_ioms_reqb.node5.ioanypostedwrsized>32band<64b umask=0xA5,event=0x109 df_ioms_reqb.node6.ioanypostedwrsized>32band<64b umask=0xC5,event=0x109 df_ioms_reqb.node7.ioanypostedwrsized>32band<64b umask=0xE5,event=0x109 df_ioms_reqb.node0.ioanypostedwrsized=32 umask=0x04,event=0x109 Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized=32 df_ioms_reqb.node1.ioanypostedwrsized=32 umask=0x24,event=0x109 df_ioms_reqb.node2.ioanypostedwrsized=32 umask=0x44,event=0x109 df_ioms_reqb.node3.ioanypostedwrsized=32 umask=0x64,event=0x109 df_ioms_reqb.node4.ioanypostedwrsized=32 umask=0x84,event=0x109 df_ioms_reqb.node5.ioanypostedwrsized=32 umask=0xA4,event=0x109 df_ioms_reqb.node6.ioanypostedwrsized=32 umask=0xC4,event=0x109 df_ioms_reqb.node7.ioanypostedwrsized=32 umask=0xE4,event=0x109 df_ioms_reqb.node0.ioanypostedwrsized<32 umask=0x03,event=0x109 Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized<32 df_ioms_reqb.node1.ioanypostedwrsized<32 umask=0x23,event=0x109 df_ioms_reqb.node2.ioanypostedwrsized<32 umask=0x43,event=0x109 df_ioms_reqb.node3.ioanypostedwrsized<32 umask=0x63,event=0x109 df_ioms_reqb.node4.ioanypostedwrsized<32 umask=0x83,event=0x109 df_ioms_reqb.node5.ioanypostedwrsized<32 umask=0xA3,event=0x109 df_ioms_reqb.node6.ioanypostedwrsized<32 umask=0xC3,event=0x109 df_ioms_reqb.node7.ioanypostedwrsized<32 umask=0xE3,event=0x109 df_ioms_reqb.node0.ioanyrdsized umask=0x02,event=0x109 Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanyrdsized df_ioms_reqb.node1.ioanyrdsized umask=0x22,event=0x109 df_ioms_reqb.node2.ioanyrdsized umask=0x42,event=0x109 df_ioms_reqb.node3.ioanyrdsized umask=0x62,event=0x109 df_ioms_reqb.node4.ioanyrdsized umask=0x82,event=0x109 df_ioms_reqb.node5.ioanyrdsized umask=0xA2,event=0x109 df_ioms_reqb.node6.ioanyrdsized umask=0xC2,event=0x109 df_ioms_reqb.node7.ioanyrdsized umask=0xE2,event=0x109 df_ioms_reqb.node0.iolargeread umask=0x01,event=0x109 Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered iolargeread df_ioms_reqb.node1.iolargeread umask=0x21,event=0x109 df_ioms_reqb.node2.iolargeread umask=0x41,event=0x109 df_ioms_reqb.node3.iolargeread umask=0x61,event=0x109 df_ioms_reqb.node4.iolargeread umask=0x81,event=0x109 df_ioms_reqb.node5.iolargeread umask=0xA1,event=0x109 df_ioms_reqb.node6.iolargeread umask=0xC1,event=0x109 df_ioms_reqb.node7.iolargeread umask=0xE1,event=0x109 fpu_pipe_assignment.dual umask=0xf0,event=0 Total number multi-pipe uOps assigned to all pipes The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to all pipes fpu_pipe_assignment.dual3 umask=0x80,event=0 Total number multi-pipe uOps assigned to pipe 3 The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to pipe 3 fpu_pipe_assignment.dual2 umask=0x40,event=0 Total number multi-pipe uOps assigned to pipe 2 The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to pipe 2 fpu_pipe_assignment.dual1 umask=0x20,event=0 Total number multi-pipe uOps assigned to pipe 1 The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to pipe 1 fpu_pipe_assignment.dual0 umask=0x10,event=0 Total number multi-pipe uOps assigned to pipe 0 The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to pipe 0 fpu_pipe_assignment.total umask=0xf,event=0 Total number uOps assigned to all fpu pipes The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to all pipes fpu_pipe_assignment.total3 umask=0x8,event=0 Total number of fp uOps on pipe 3 The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one-cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 3 fpu_pipe_assignment.total2 Total number of fp uOps on pipe 2 The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 2 fpu_pipe_assignment.total1 Total number of fp uOps on pipe 1 The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 1 fpu_pipe_assignment.total0 umask=0x1,event=0 Total number of fp uOps on pipe 0 The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 0 fp_sched_empty This is a speculative event. The number of cycles in which the FPU scheduler is empty. Note that some Ops like FP loads bypass the scheduler fp_retx87_fp_ops.all umask=0x7,event=0x2 All Ops The number of x87 floating-point Ops that have retired. The number of events logged per cycle can vary from 0 to 8 fp_retx87_fp_ops.div_sqr_r_ops Divide and square root Ops The number of x87 floating-point Ops that have retired. The number of events logged per cycle can vary from 0 to 8. Divide and square root Ops fp_retx87_fp_ops.mul_ops umask=0x2,event=0x2 Multiply Ops The number of x87 floating-point Ops that have retired. The number of events logged per cycle can vary from 0 to 8. Multiply Ops fp_retx87_fp_ops.add_sub_ops Add/subtract Ops The number of x87 floating-point Ops that have retired. The number of events logged per cycle can vary from 0 to 8. Add/subtract Ops fp_ret_sse_avx_ops.all umask=0xff,event=0x3 All FLOPS This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15 fp_ret_sse_avx_ops.dp_mult_add_flops umask=0x80,event=0x3 Double precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Double precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS fp_ret_sse_avx_ops.dp_div_flops umask=0x40,event=0x3 Double precision divide/square root FLOPS This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Double precision divide/square root FLOPS fp_ret_sse_avx_ops.dp_mult_flops umask=0x20,event=0x3 Double precision multiply FLOPS This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Double precision multiply FLOPS fp_ret_sse_avx_ops.dp_add_sub_flops umask=0x10,event=0x3 Double precision add/subtract FLOPS This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Double precision add/subtract FLOPS fp_ret_sse_avx_ops.sp_mult_add_flops umask=0x8,event=0x3 Single precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Single precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS fp_ret_sse_avx_ops.sp_div_flops umask=0x4,event=0x3 Single-precision divide/square root FLOPS This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Single-precision divide/square root FLOPS fp_ret_sse_avx_ops.sp_mult_flops umask=0x2,event=0x3 Single-precision multiply FLOPS This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Single-precision multiply FLOPS fp_ret_sse_avx_ops.sp_add_sub_flops umask=0x1,event=0x3 Single-precision add/subtract FLOPS This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Single-precision add/subtract FLOPS fp_num_mov_elim_scal_op.optimized umask=0x8,event=0x4 Number of Scalar Ops optimized This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes. Number of Scalar Ops optimized fp_num_mov_elim_scal_op.opt_potential Number of Ops that are candidates for optimization (have Z-bit either set or pass) This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes. Number of Ops that are candidates for optimization (have Z-bit either set or pass) fp_num_mov_elim_scal_op.sse_mov_ops_elim Number of SSE Move Ops eliminated This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes. Number of SSE Move Ops eliminated fp_num_mov_elim_scal_op.sse_mov_ops Number of SSE Move Ops This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes. Number of SSE Move Ops fp_retired_ser_ops.x87_ctrl_ret umask=0x8,event=0x5 x87 control word mispredict traps due to mispredictions in RC or PC, or changes in mask bits The number of serializing Ops retired. x87 control word mispredict traps due to mispredictions in RC or PC, or changes in mask bits fp_retired_ser_ops.x87_bot_ret umask=0x4,event=0x5 x87 bottom-executing uOps retired The number of serializing Ops retired. x87 bottom-executing uOps retired fp_retired_ser_ops.sse_ctrl_ret umask=0x2,event=0x5 SSE control word mispredict traps due to mispredictions in RC, FTZ or DAZ, or changes in mask bits The number of serializing Ops retired. SSE control word mispredict traps due to mispredictions in RC, FTZ or DAZ, or changes in mask bits fp_retired_ser_ops.sse_bot_ret umask=0x1,event=0x5 SSE bottom-executing uOps retired The number of serializing Ops retired. SSE bottom-executing uOps retired l3_request_g1.t0.s0.wrsizednc l3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x02,event=0x1 L3 Cache Performance Monitor Counters L3 Cache Accesses l3cache l3_request_g1.t1.s0.wrsizednc l3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x02,event=0x1 L3 Cache Performance Monitor Counters L3 Cache Accesses l3_request_g1.t2.s0.wrsizednc l3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x02,event=0x1 l3_request_g1.t3.s0.wrsizednc l3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x02,event=0x1 l3_request_g1.t4.s0.wrsizednc l3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x02,event=0x1 l3_request_g1.t5.s0.wrsizednc l3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x02,event=0x1 l3_request_g1.t6.s0.wrsizednc l3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x02,event=0x1 l3_request_g1.t7.s0.wrsizednc l3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x02,event=0x1 l3_request_g1.t0.s1.wrsizednc l3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x02,event=0x1 l3_request_g1.t1.s1.wrsizednc l3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x02,event=0x1 l3_request_g1.t2.s1.wrsizednc l3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x02,event=0x1 l3_request_g1.t3.s1.wrsizednc l3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x02,event=0x1 l3_request_g1.t4.s1.wrsizednc l3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x02,event=0x1 l3_request_g1.t5.s1.wrsizednc l3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x02,event=0x1 l3_request_g1.t6.s1.wrsizednc l3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x02,event=0x1 l3_request_g1.t7.s1.wrsizednc l3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x02,event=0x1 l3_request_g1.t0.s2.wrsizednc l3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x02,event=0x1 l3_request_g1.t1.s2.wrsizednc l3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x02,event=0x1 l3_request_g1.t2.s2.wrsizednc l3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x02,event=0x1 l3_request_g1.t3.s2.wrsizednc l3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x02,event=0x1 l3_request_g1.t4.s2.wrsizednc l3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x02,event=0x1 l3_request_g1.t5.s2.wrsizednc l3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x02,event=0x1 l3_request_g1.t6.s2.wrsizednc l3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x02,event=0x1 l3_request_g1.t7.s2.wrsizednc l3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x02,event=0x1 l3_request_g1.t0.s3.wrsizednc l3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x02,event=0x1 l3_request_g1.t1.s3.wrsizednc l3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x02,event=0x1 l3_request_g1.t2.s3.wrsizednc l3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x02,event=0x1 l3_request_g1.t3.s3.wrsizednc l3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x02,event=0x1 l3_request_g1.t4.s3.wrsizednc l3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x02,event=0x1 l3_request_g1.t5.s3.wrsizednc l3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x02,event=0x1 l3_request_g1.t6.s3.wrsizednc l3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x02,event=0x1 l3_request_g1.t7.s3.wrsizednc l3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x02,event=0x1 l3_request_g1.t0.s0.wrsized l3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x04,event=0x1 l3_request_g1.t1.s0.wrsized l3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x04,event=0x1 l3_request_g1.t2.s0.wrsized l3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x04,event=0x1 l3_request_g1.t3.s0.wrsized l3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x04,event=0x1 l3_request_g1.t4.s0.wrsized l3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x04,event=0x1 l3_request_g1.t5.s0.wrsized l3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x04,event=0x1 l3_request_g1.t6.s0.wrsized l3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x04,event=0x1 l3_request_g1.t7.s0.wrsized l3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x04,event=0x1 l3_request_g1.t0.s1.wrsized l3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x04,event=0x1 l3_request_g1.t1.s1.wrsized l3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x04,event=0x1 l3_request_g1.t2.s1.wrsized l3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x04,event=0x1 l3_request_g1.t3.s1.wrsized l3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x04,event=0x1 l3_request_g1.t4.s1.wrsized l3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x04,event=0x1 l3_request_g1.t5.s1.wrsized l3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x04,event=0x1 l3_request_g1.t6.s1.wrsized l3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x04,event=0x1 l3_request_g1.t7.s1.wrsized l3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x04,event=0x1 l3_request_g1.t0.s2.wrsized l3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x04,event=0x1 l3_request_g1.t1.s2.wrsized l3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x04,event=0x1 l3_request_g1.t2.s2.wrsized l3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x04,event=0x1 l3_request_g1.t3.s2.wrsized l3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x04,event=0x1 l3_request_g1.t4.s2.wrsized l3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x04,event=0x1 l3_request_g1.t5.s2.wrsized l3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x04,event=0x1 l3_request_g1.t6.s2.wrsized l3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x04,event=0x1 l3_request_g1.t7.s2.wrsized l3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x04,event=0x1 l3_request_g1.t0.s3.wrsized l3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x04,event=0x1 l3_request_g1.t1.s3.wrsized l3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x04,event=0x1 l3_request_g1.t2.s3.wrsized l3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x04,event=0x1 l3_request_g1.t3.s3.wrsized l3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x04,event=0x1 l3_request_g1.t4.s3.wrsized l3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x04,event=0x1 l3_request_g1.t5.s3.wrsized l3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x04,event=0x1 l3_request_g1.t6.s3.wrsized l3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x04,event=0x1 l3_request_g1.t7.s3.wrsized l3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x04,event=0x1 l3_request_g1.t0.s0.rdsizednc l3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x20,event=0x1 l3_request_g1.t1.s0.rdsizednc l3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x20,event=0x1 l3_request_g1.t2.s0.rdsizednc l3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x20,event=0x1 l3_request_g1.t3.s0.rdsizednc l3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x20,event=0x1 l3_request_g1.t4.s0.rdsizednc l3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x20,event=0x1 l3_request_g1.t5.s0.rdsizednc l3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x20,event=0x1 l3_request_g1.t6.s0.rdsizednc l3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x20,event=0x1 l3_request_g1.t7.s0.rdsizednc l3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x20,event=0x1 l3_request_g1.t0.s1.rdsizednc l3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x20,event=0x1 l3_request_g1.t1.s1.rdsizednc l3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x20,event=0x1 l3_request_g1.t2.s1.rdsizednc l3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x20,event=0x1 l3_request_g1.t3.s1.rdsizednc l3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x20,event=0x1 l3_request_g1.t4.s1.rdsizednc l3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x20,event=0x1 l3_request_g1.t5.s1.rdsizednc l3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x20,event=0x1 l3_request_g1.t6.s1.rdsizednc l3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x20,event=0x1 l3_request_g1.t7.s1.rdsizednc l3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x20,event=0x1 l3_request_g1.t0.s2.rdsizednc l3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x20,event=0x1 l3_request_g1.t1.s2.rdsizednc l3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x20,event=0x1 l3_request_g1.t2.s2.rdsizednc l3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x20,event=0x1 l3_request_g1.t3.s2.rdsizednc l3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x20,event=0x1 l3_request_g1.t4.s2.rdsizednc l3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x20,event=0x1 l3_request_g1.t5.s2.rdsizednc l3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x20,event=0x1 l3_request_g1.t6.s2.rdsizednc l3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x20,event=0x1 l3_request_g1.t7.s2.rdsizednc l3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x20,event=0x1 l3_request_g1.t0.s3.rdsizednc l3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x20,event=0x1 l3_request_g1.t1.s3.rdsizednc l3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x20,event=0x1 l3_request_g1.t2.s3.rdsizednc l3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x20,event=0x1 l3_request_g1.t3.s3.rdsizednc l3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x20,event=0x1 l3_request_g1.t4.s3.rdsizednc l3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x20,event=0x1 l3_request_g1.t5.s3.rdsizednc l3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x20,event=0x1 l3_request_g1.t6.s3.rdsizednc l3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x20,event=0x1 l3_request_g1.t7.s3.rdsizednc l3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x20,event=0x1 l3_request_g1.t0.s0.rdsized l3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x40,event=0x1 l3_request_g1.t1.s0.rdsized l3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x40,event=0x1 l3_request_g1.t2.s0.rdsized l3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x40,event=0x1 l3_request_g1.t3.s0.rdsized l3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x40,event=0x1 l3_request_g1.t4.s0.rdsized l3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x40,event=0x1 l3_request_g1.t5.s0.rdsized l3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x40,event=0x1 l3_request_g1.t6.s0.rdsized l3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x40,event=0x1 l3_request_g1.t7.s0.rdsized l3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x40,event=0x1 l3_request_g1.t0.s1.rdsized l3_request_g1.t1.s1.rdsized l3_request_g1.t2.s1.rdsized l3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x40,event=0x1 l3_request_g1.t3.s1.rdsized l3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x40,event=0x1 l3_request_g1.t4.s1.rdsized l3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x40,event=0x1 l3_request_g1.t5.s1.rdsized l3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x40,event=0x1 l3_request_g1.t6.s1.rdsized l3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x40,event=0x1 l3_request_g1.t7.s1.rdsized l3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x40,event=0x1 l3_request_g1.t0.s2.rdsized l3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x40,event=0x1 l3_request_g1.t1.s2.rdsized l3_request_g1.t2.s2.rdsized l3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x40,event=0x1 l3_request_g1.t3.s2.rdsized l3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x40,event=0x1 l3_request_g1.t4.s2.rdsized l3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x40,event=0x1 l3_request_g1.t5.s2.rdsized l3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x40,event=0x1 l3_request_g1.t6.s2.rdsized l3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x40,event=0x1 l3_request_g1.t7.s2.rdsized l3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x40,event=0x1 l3_request_g1.t0.s3.rdsized l3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x40,event=0x1 l3_request_g1.t1.s3.rdsized l3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x40,event=0x1 l3_request_g1.t2.s3.rdsized l3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x40,event=0x1 l3_request_g1.t3.s3.rdsized l3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x40,event=0x1 l3_request_g1.t4.s3.rdsized l3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x40,event=0x1 l3_request_g1.t5.s3.rdsized l3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x40,event=0x1 l3_request_g1.t6.s3.rdsized l3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x40,event=0x1 l3_request_g1.t7.s3.rdsized l3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x40,event=0x1 l3_request_g1.t0.s0.caching l3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x80,event=0x1 l3_request_g1.t1.s0.caching l3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x80,event=0x1 l3_request_g1.t2.s0.caching l3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x80,event=0x1 l3_request_g1.t3.s0.caching l3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x80,event=0x1 l3_request_g1.t4.s0.caching l3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x80,event=0x1 l3_request_g1.t5.s0.caching l3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x80,event=0x1 l3_request_g1.t6.s0.caching l3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x80,event=0x1 l3_request_g1.t7.s0.caching l3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x80,event=0x1 l3_request_g1.t0.s1.caching l3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x80,event=0x1 l3_request_g1.t1.s1.caching l3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x80,event=0x1 l3_request_g1.t2.s1.caching l3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x80,event=0x1 l3_request_g1.t3.s1.caching l3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x80,event=0x1 l3_request_g1.t4.s1.caching l3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x80,event=0x1 l3_request_g1.t5.s1.caching l3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x80,event=0x1 l3_request_g1.t6.s1.caching l3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x80,event=0x1 l3_request_g1.t7.s1.caching l3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x80,event=0x1 l3_request_g1.t0.s2.caching l3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x80,event=0x1 l3_request_g1.t1.s2.caching l3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x80,event=0x1 l3_request_g1.t2.s2.caching l3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x80,event=0x1 l3_request_g1.t3.s2.caching l3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x80,event=0x1 l3_request_g1.t4.s2.caching l3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x80,event=0x1 l3_request_g1.t5.s2.caching l3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x80,event=0x1 l3_request_g1.t6.s2.caching l3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x80,event=0x1 l3_request_g1.t7.s2.caching l3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x80,event=0x1 l3_request_g1.t0.s3.caching l3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x80,event=0x1 l3_request_g1.t1.s3.caching l3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x80,event=0x1 l3_request_g1.t2.s3.caching l3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x80,event=0x1 l3_request_g1.t3.s3.caching l3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x80,event=0x1 l3_request_g1.t4.s3.caching l3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x80,event=0x1 l3_request_g1.t5.s3.caching l3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x80,event=0x1 l3_request_g1.t6.s3.caching l3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x80,event=0x1 l3_request_g1.t7.s3.caching l3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x80,event=0x1 l3fillvicreq.t0.s0.vicblk l3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x01,event=0x3 L3 Cache Performance Monitor Counters L3 cache access types l3fillvicreq.t1.s0.vicblk l3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x01,event=0x3 l3fillvicreq.t2.s0.vicblk l3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x01,event=0x3 l3fillvicreq.t3.s0.vicblk l3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x01,event=0x3 l3fillvicreq.t4.s0.vicblk l3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x01,event=0x3 l3fillvicreq.t5.s0.vicblk l3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x01,event=0x3 l3fillvicreq.t6.s0.vicblk l3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x01,event=0x3 l3fillvicreq.t7.s0.vicblk l3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x01,event=0x3 l3fillvicreq.t0.s1.vicblk l3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x01,event=0x3 l3fillvicreq.t1.s1.vicblk l3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x01,event=0x3 l3fillvicreq.t2.s1.vicblk l3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x01,event=0x3 l3fillvicreq.t3.s1.vicblk l3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x01,event=0x3 l3fillvicreq.t4.s1.vicblk l3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x01,event=0x3 l3fillvicreq.t5.s1.vicblk l3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x01,event=0x3 l3fillvicreq.t6.s1.vicblk l3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x01,event=0x3 l3fillvicreq.t7.s1.vicblk l3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x01,event=0x3 l3fillvicreq.t0.s2.vicblk l3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x01,event=0x3 l3fillvicreq.t1.s2.vicblk l3fillvicreq.t2.s2.vicblk l3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x01,event=0x3 l3fillvicreq.t3.s2.vicblk l3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x01,event=0x3 l3fillvicreq.t4.s2.vicblk l3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x01,event=0x3 l3fillvicreq.t5.s2.vicblk l3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x01,event=0x3 l3fillvicreq.t6.s2.vicblk l3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x01,event=0x3 l3fillvicreq.t7.s2.vicblk l3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x01,event=0x3 l3fillvicreq.t0.s3.vicblk l3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x01,event=0x3 l3fillvicreq.t1.s3.vicblk l3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x01,event=0x3 l3fillvicreq.t2.s3.vicblk l3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x01,event=0x3 l3fillvicreq.t3.s3.vicblk l3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x01,event=0x3 l3fillvicreq.t4.s3.vicblk l3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x01,event=0x3 l3fillvicreq.t5.s3.vicblk l3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x01,event=0x3 l3fillvicreq.t6.s3.vicblk l3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x01,event=0x3 l3fillvicreq.t7.s3.vicblk l3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x01,event=0x3 l3fillvicreq.t0.s0.chgtox l3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x02,event=0x3 l3fillvicreq.t1.s0.chgtox l3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x02,event=0x3 l3fillvicreq.t2.s0.chgtox l3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x02,event=0x3 l3fillvicreq.t3.s0.chgtox l3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x02,event=0x3 l3fillvicreq.t4.s0.chgtox l3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x02,event=0x3 l3fillvicreq.t5.s0.chgtox l3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x02,event=0x3 l3fillvicreq.t6.s0.chgtox l3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x02,event=0x3 l3fillvicreq.t7.s0.chgtox l3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x02,event=0x3 l3fillvicreq.t0.s1.chgtox l3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x02,event=0x3 l3fillvicreq.t1.s1.chgtox l3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x02,event=0x3 l3fillvicreq.t2.s1.chgtox l3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x02,event=0x3 l3fillvicreq.t3.s1.chgtox l3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x02,event=0x3 l3fillvicreq.t4.s1.chgtox l3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x02,event=0x3 l3fillvicreq.t5.s1.chgtox l3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x02,event=0x3 l3fillvicreq.t6.s1.chgtox l3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x02,event=0x3 l3fillvicreq.t7.s1.chgtox l3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x02,event=0x3 l3fillvicreq.t0.s2.chgtox l3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x02,event=0x3 l3fillvicreq.t1.s2.chgtox l3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x02,event=0x3 l3fillvicreq.t2.s2.chgtox l3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x02,event=0x3 l3fillvicreq.t3.s2.chgtox l3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x02,event=0x3 l3fillvicreq.t4.s2.chgtox l3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x02,event=0x3 l3fillvicreq.t5.s2.chgtox l3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x02,event=0x3 l3fillvicreq.t6.s2.chgtox l3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x02,event=0x3 l3fillvicreq.t7.s2.chgtox l3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x02,event=0x3 l3fillvicreq.t0.s3.chgtox l3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x02,event=0x3 l3fillvicreq.t1.s3.chgtox l3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x02,event=0x3 l3fillvicreq.t2.s3.chgtox l3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x02,event=0x3 l3fillvicreq.t3.s3.chgtox l3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x02,event=0x3 l3fillvicreq.t4.s3.chgtox l3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x02,event=0x3 l3fillvicreq.t5.s3.chgtox l3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x02,event=0x3 l3fillvicreq.t6.s3.chgtox l3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x02,event=0x3 l3fillvicreq.t7.s3.chgtox l3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x02,event=0x3 l3fillvicreq.t0.s0.rdblkc_s_vic l3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x04,event=0x3 l3fillvicreq.t1.s0.rdblkc_s_vic l3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x04,event=0x3 l3fillvicreq.t2.s0.rdblkc_s_vic l3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x04,event=0x3 l3fillvicreq.t3.s0.rdblkc_s_vic l3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x04,event=0x3 l3fillvicreq.t4.s0.rdblkc_s_vic l3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x04,event=0x3 l3fillvicreq.t5.s0.rdblkc_s_vic l3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x04,event=0x3 l3fillvicreq.t6.s0.rdblkc_s_vic l3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x04,event=0x3 l3fillvicreq.t7.s0.rdblkc_s_vic l3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x04,event=0x3 l3fillvicreq.t0.s1.rdblkc_s_vic l3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x04,event=0x3 l3fillvicreq.t1.s1.rdblkc_s_vic l3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x04,event=0x3 l3fillvicreq.t2.s1.rdblkc_s_vic l3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x04,event=0x3 l3fillvicreq.t3.s1.rdblkc_s_vic l3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x04,event=0x3 l3fillvicreq.t4.s1.rdblkc_s_vic l3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x04,event=0x3 l3fillvicreq.t5.s1.rdblkc_s_vic l3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x04,event=0x3 l3fillvicreq.t6.s1.rdblkc_s_vic l3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x04,event=0x3 l3fillvicreq.t7.s1.rdblkc_s_vic l3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x04,event=0x3 l3fillvicreq.t0.s2.rdblkc_s_vic l3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x04,event=0x3 l3fillvicreq.t1.s2.rdblkc_s_vic l3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x04,event=0x3 l3fillvicreq.t2.s2.rdblkc_s_vic l3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x04,event=0x3 l3fillvicreq.t3.s2.rdblkc_s_vic l3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x04,event=0x3 l3fillvicreq.t4.s2.rdblkc_s_vic l3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x04,event=0x3 l3fillvicreq.t5.s2.rdblkc_s_vic l3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x04,event=0x3 l3fillvicreq.t6.s2.rdblkc_s_vic l3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x04,event=0x3 l3fillvicreq.t7.s2.rdblkc_s_vic l3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x04,event=0x3 l3fillvicreq.t0.s3.rdblkc_s_vic l3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x04,event=0x3 l3fillvicreq.t1.s3.rdblkc_s_vic l3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x04,event=0x3 l3fillvicreq.t2.s3.rdblkc_s_vic l3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x04,event=0x3 l3fillvicreq.t3.s3.rdblkc_s_vic l3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x04,event=0x3 l3fillvicreq.t4.s3.rdblkc_s_vic l3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x04,event=0x3 l3fillvicreq.t5.s3.rdblkc_s_vic l3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x04,event=0x3 l3fillvicreq.t6.s3.rdblkc_s_vic l3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x04,event=0x3 l3fillvicreq.t7.s3.rdblkc_s_vic l3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x04,event=0x3 l3fillvicreq.t0.s0.rdblkc_s l3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x08,event=0x3 l3fillvicreq.t1.s0.rdblkc_s l3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x08,event=0x3 l3fillvicreq.t2.s0.rdblkc_s l3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x08,event=0x3 l3fillvicreq.t3.s0.rdblkc_s l3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x08,event=0x3 l3fillvicreq.t4.s0.rdblkc_s l3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x08,event=0x3 l3fillvicreq.t5.s0.rdblkc_s l3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x08,event=0x3 l3fillvicreq.t6.s0.rdblkc_s l3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x08,event=0x3 l3fillvicreq.t7.s0.rdblkc_s l3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x08,event=0x3 l3fillvicreq.t0.s1.rdblkc_s l3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x08,event=0x3 l3fillvicreq.t1.s1.rdblkc_s l3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x08,event=0x3 l3fillvicreq.t2.s1.rdblkc_s l3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x08,event=0x3 l3fillvicreq.t3.s1.rdblkc_s l3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x08,event=0x3 l3fillvicreq.t4.s1.rdblkc_s l3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x08,event=0x3 l3fillvicreq.t5.s1.rdblkc_s l3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x08,event=0x3 l3fillvicreq.t6.s1.rdblkc_s l3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x08,event=0x3 l3fillvicreq.t7.s1.rdblkc_s l3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x08,event=0x3 l3fillvicreq.t0.s2.rdblkc_s l3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x08,event=0x3 l3fillvicreq.t1.s2.rdblkc_s l3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x08,event=0x3 l3fillvicreq.t2.s2.rdblkc_s l3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x08,event=0x3 l3fillvicreq.t3.s2.rdblkc_s l3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x08,event=0x3 l3fillvicreq.t4.s2.rdblkc_s l3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x08,event=0x3 l3fillvicreq.t5.s2.rdblkc_s l3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x08,event=0x3 l3fillvicreq.t6.s2.rdblkc_s l3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x08,event=0x3 l3fillvicreq.t7.s2.rdblkc_s l3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x08,event=0x3 l3fillvicreq.t0.s3.rdblkc_s l3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x08,event=0x3 l3fillvicreq.t1.s3.rdblkc_s l3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x08,event=0x3 l3fillvicreq.t2.s3.rdblkc_s l3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x08,event=0x3 l3fillvicreq.t3.s3.rdblkc_s l3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x08,event=0x3 l3fillvicreq.t4.s3.rdblkc_s l3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x08,event=0x3 l3fillvicreq.t5.s3.rdblkc_s l3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x08,event=0x3 l3fillvicreq.t6.s3.rdblkc_s l3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x08,event=0x3 l3fillvicreq.t7.s3.rdblkc_s l3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x08,event=0x3 l3fillvicreq.t0.s0.rdblkx_vic l3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x10,event=0x3 l3fillvicreq.t1.s0.rdblkx_vic l3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x10,event=0x3 l3fillvicreq.t2.s0.rdblkx_vic l3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x10,event=0x3 l3fillvicreq.t3.s0.rdblkx_vic l3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x10,event=0x3 l3fillvicreq.t4.s0.rdblkx_vic l3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x10,event=0x3 l3fillvicreq.t5.s0.rdblkx_vic l3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x10,event=0x3 l3fillvicreq.t6.s0.rdblkx_vic l3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x10,event=0x3 l3fillvicreq.t7.s0.rdblkx_vic l3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x10,event=0x3 l3fillvicreq.t0.s1.rdblkx_vic l3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x10,event=0x3 l3fillvicreq.t1.s1.rdblkx_vic l3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x10,event=0x3 l3fillvicreq.t2.s1.rdblkx_vic l3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x10,event=0x3 l3fillvicreq.t3.s1.rdblkx_vic l3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x10,event=0x3 l3fillvicreq.t4.s1.rdblkx_vic l3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x10,event=0x3 l3fillvicreq.t5.s1.rdblkx_vic l3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x10,event=0x3 l3fillvicreq.t6.s1.rdblkx_vic l3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x10,event=0x3 l3fillvicreq.t7.s1.rdblkx_vic l3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x10,event=0x3 l3fillvicreq.t0.s2.rdblkx_vic l3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x10,event=0x3 l3fillvicreq.t1.s2.rdblkx_vic l3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x10,event=0x3 l3fillvicreq.t2.s2.rdblkx_vic l3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x10,event=0x3 l3fillvicreq.t3.s2.rdblkx_vic l3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x10,event=0x3 l3fillvicreq.t4.s2.rdblkx_vic l3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x10,event=0x3 l3fillvicreq.t5.s2.rdblkx_vic l3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x10,event=0x3 l3fillvicreq.t6.s2.rdblkx_vic l3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x10,event=0x3 l3fillvicreq.t7.s2.rdblkx_vic l3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x10,event=0x3 l3fillvicreq.t0.s3.rdblkx_vic l3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x10,event=0x3 l3fillvicreq.t1.s3.rdblkx_vic l3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x10,event=0x3 l3fillvicreq.t2.s3.rdblkx_vic l3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x10,event=0x3 l3fillvicreq.t3.s3.rdblkx_vic l3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x10,event=0x3 l3fillvicreq.t4.s3.rdblkx_vic l3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x10,event=0x3 l3fillvicreq.t5.s3.rdblkx_vic l3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x10,event=0x3 l3fillvicreq.t6.s3.rdblkx_vic l3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x10,event=0x3 l3fillvicreq.t7.s3.rdblkx_vic l3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x10,event=0x3 l3fillvicreq.t0.s0.rdblkx l3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x20,event=0x3 l3fillvicreq.t1.s0.rdblkx l3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x20,event=0x3 l3fillvicreq.t2.s0.rdblkx l3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x20,event=0x3 l3fillvicreq.t3.s0.rdblkx l3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x20,event=0x3 l3fillvicreq.t4.s0.rdblkx l3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x20,event=0x3 l3fillvicreq.t5.s0.rdblkx l3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x20,event=0x3 l3fillvicreq.t6.s0.rdblkx l3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x20,event=0x3 l3fillvicreq.t7.s0.rdblkx l3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x20,event=0x3 l3fillvicreq.t0.s1.rdblkx l3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x20,event=0x3 l3fillvicreq.t1.s1.rdblkx l3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x20,event=0x3 l3fillvicreq.t2.s1.rdblkx l3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x20,event=0x3 l3fillvicreq.t3.s1.rdblkx l3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x20,event=0x3 l3fillvicreq.t4.s1.rdblkx l3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x20,event=0x3 l3fillvicreq.t5.s1.rdblkx l3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x20,event=0x3 l3fillvicreq.t6.s1.rdblkx l3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x20,event=0x3 l3fillvicreq.t7.s1.rdblkx l3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x20,event=0x3 l3fillvicreq.t0.s2.rdblkx l3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x20,event=0x3 l3fillvicreq.t1.s2.rdblkx l3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x20,event=0x3 l3fillvicreq.t2.s2.rdblkx l3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x20,event=0x3 l3fillvicreq.t3.s2.rdblkx l3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x20,event=0x3 l3fillvicreq.t4.s2.rdblkx l3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x20,event=0x3 l3fillvicreq.t5.s2.rdblkx l3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x20,event=0x3 l3fillvicreq.t6.s2.rdblkx l3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x20,event=0x3 l3fillvicreq.t7.s2.rdblkx l3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x20,event=0x3 l3fillvicreq.t0.s3.rdblkx l3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x20,event=0x3 l3fillvicreq.t1.s3.rdblkx l3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x20,event=0x3 l3fillvicreq.t2.s3.rdblkx l3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x20,event=0x3 l3fillvicreq.t3.s3.rdblkx l3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x20,event=0x3 l3fillvicreq.t4.s3.rdblkx l3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x20,event=0x3 l3fillvicreq.t5.s3.rdblkx l3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x20,event=0x3 l3fillvicreq.t6.s3.rdblkx l3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x20,event=0x3 l3fillvicreq.t7.s3.rdblkx l3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x20,event=0x3 l3fillvicreq.t0.s0.rdblkl_vic l3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x40,event=0x3 l3fillvicreq.t1.s0.rdblkl_vic l3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x40,event=0x3 l3fillvicreq.t2.s0.rdblkl_vic l3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x40,event=0x3 l3fillvicreq.t3.s0.rdblkl_vic l3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x40,event=0x3 l3fillvicreq.t4.s0.rdblkl_vic l3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x40,event=0x3 l3fillvicreq.t5.s0.rdblkl_vic l3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x40,event=0x3 l3fillvicreq.t6.s0.rdblkl_vic l3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x40,event=0x3 l3fillvicreq.t7.s0.rdblkl_vic l3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x40,event=0x3 l3fillvicreq.t0.s1.rdblkl_vic l3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x40,event=0x3 l3fillvicreq.t1.s1.rdblkl_vic l3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x40,event=0x3 l3fillvicreq.t2.s1.rdblkl_vic l3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x40,event=0x3 l3fillvicreq.t3.s1.rdblkl_vic l3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x40,event=0x3 l3fillvicreq.t4.s1.rdblkl_vic l3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x40,event=0x3 l3fillvicreq.t5.s1.rdblkl_vic l3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x40,event=0x3 l3fillvicreq.t6.s1.rdblkl_vic l3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x40,event=0x3 l3fillvicreq.t7.s1.rdblkl_vic l3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x40,event=0x3 l3fillvicreq.t0.s2.rdblkl_vic l3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x40,event=0x3 l3fillvicreq.t1.s2.rdblkl_vic l3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x40,event=0x3 l3fillvicreq.t2.s2.rdblkl_vic l3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x40,event=0x3 l3fillvicreq.t3.s2.rdblkl_vic l3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x40,event=0x3 l3fillvicreq.t4.s2.rdblkl_vic l3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x40,event=0x3 l3fillvicreq.t5.s2.rdblkl_vic l3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x40,event=0x3 l3fillvicreq.t6.s2.rdblkl_vic l3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x40,event=0x3 l3fillvicreq.t7.s2.rdblkl_vic l3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x40,event=0x3 l3fillvicreq.t0.s3.rdblkl_vic l3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x40,event=0x3 l3fillvicreq.t1.s3.rdblkl_vic l3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x40,event=0x3 l3fillvicreq.t2.s3.rdblkl_vic l3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x40,event=0x3 l3fillvicreq.t3.s3.rdblkl_vic l3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x40,event=0x3 l3fillvicreq.t4.s3.rdblkl_vic l3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x40,event=0x3 l3fillvicreq.t5.s3.rdblkl_vic l3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x40,event=0x3 l3fillvicreq.t6.s3.rdblkl_vic l3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x40,event=0x3 l3fillvicreq.t7.s3.rdblkl_vic l3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x40,event=0x3 l3fillvicreq.t0.s0.rdblkl l3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x80,event=0x3 l3fillvicreq.t1.s0.rdblkl l3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x80,event=0x3 l3fillvicreq.t2.s0.rdblkl l3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x80,event=0x3 l3fillvicreq.t3.s0.rdblkl l3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x80,event=0x3 l3fillvicreq.t4.s0.rdblkl l3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x80,event=0x3 l3fillvicreq.t5.s0.rdblkl l3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x80,event=0x3 l3fillvicreq.t6.s0.rdblkl l3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x80,event=0x3 l3fillvicreq.t7.s0.rdblkl l3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x80,event=0x3 l3fillvicreq.t0.s1.rdblkl l3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x80,event=0x3 l3fillvicreq.t1.s1.rdblkl l3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x80,event=0x3 l3fillvicreq.t2.s1.rdblkl l3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x80,event=0x3 l3fillvicreq.t3.s1.rdblkl l3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x80,event=0x3 l3fillvicreq.t4.s1.rdblkl l3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x80,event=0x3 l3fillvicreq.t5.s1.rdblkl l3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x80,event=0x3 l3fillvicreq.t6.s1.rdblkl l3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x80,event=0x3 l3fillvicreq.t7.s1.rdblkl l3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x80,event=0x3 l3fillvicreq.t0.s2.rdblkl l3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x80,event=0x3 l3fillvicreq.t1.s2.rdblkl l3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x80,event=0x3 l3fillvicreq.t2.s2.rdblkl l3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x80,event=0x3 l3fillvicreq.t3.s2.rdblkl l3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x80,event=0x3 l3fillvicreq.t4.s2.rdblkl l3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x80,event=0x3 l3fillvicreq.t5.s2.rdblkl l3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x80,event=0x3 l3fillvicreq.t6.s2.rdblkl l3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x80,event=0x3 l3fillvicreq.t7.s2.rdblkl l3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x80,event=0x3 l3fillvicreq.t0.s3.rdblkl l3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x80,event=0x3 l3fillvicreq.t1.s3.rdblkl l3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x80,event=0x3 l3fillvicreq.t2.s3.rdblkl l3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x80,event=0x3 l3fillvicreq.t3.s3.rdblkl l3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x80,event=0x3 l3fillvicreq.t4.s3.rdblkl l3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x80,event=0x3 l3fillvicreq.t5.s3.rdblkl l3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x80,event=0x3 l3fillvicreq.t6.s3.rdblkl l3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x80,event=0x3 l3fillvicreq.t7.s3.rdblkl l3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x80,event=0x3 l3combclstrstate L3 Cache Performance Monitor Counters RequestMiss: L3 miss l3victimstate.t0.s0.nol3victimline l3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x01,event=0x9 L3 Cache Performance Monitor Counters L3 Victim State l3victimstate.t1.s0.nol3victimline l3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x01,event=0x9 l3victimstate.t2.s0.nol3victimline l3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x01,event=0x9 l3victimstate.t3.s0.nol3victimline l3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x01,event=0x9 l3victimstate.t4.s0.nol3victimline l3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x01,event=0x9 l3victimstate.t5.s0.nol3victimline l3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x01,event=0x9 l3victimstate.t6.s0.nol3victimline l3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x01,event=0x9 l3victimstate.t7.s0.nol3victimline l3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x01,event=0x9 l3victimstate.t0.s1.nol3victimline l3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x01,event=0x9 l3victimstate.t1.s1.nol3victimline l3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x01,event=0x9 l3victimstate.t2.s1.nol3victimline l3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x01,event=0x9 l3victimstate.t3.s1.nol3victimline l3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x01,event=0x9 l3victimstate.t4.s1.nol3victimline l3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x01,event=0x9 l3victimstate.t5.s1.nol3victimline l3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x01,event=0x9 l3victimstate.t6.s1.nol3victimline l3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x01,event=0x9 l3victimstate.t7.s1.nol3victimline l3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x01,event=0x9 l3victimstate.t0.s2.nol3victimline l3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x01,event=0x9 l3victimstate.t1.s2.nol3victimline l3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x01,event=0x9 l3victimstate.t2.s2.nol3victimline l3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x01,event=0x9 l3victimstate.t3.s2.nol3victimline l3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x01,event=0x9 l3victimstate.t4.s2.nol3victimline l3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x01,event=0x9 l3victimstate.t5.s2.nol3victimline l3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x01,event=0x9 l3victimstate.t6.s2.nol3victimline l3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x01,event=0x9 l3victimstate.t7.s2.nol3victimline l3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x01,event=0x9 l3victimstate.t0.s3.nol3victimline l3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x01,event=0x9 l3victimstate.t1.s3.nol3victimline l3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x01,event=0x9 l3victimstate.t2.s3.nol3victimline l3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x01,event=0x9 l3victimstate.t3.s3.nol3victimline l3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x01,event=0x9 l3victimstate.t4.s3.nol3victimline l3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x01,event=0x9 l3victimstate.t5.s3.nol3victimline l3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x01,event=0x9 l3victimstate.t6.s3.nol3victimline l3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x01,event=0x9 l3victimstate.t7.s3.nol3victimline l3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x01,event=0x9 l3victimstate.t0.s0.none_nol3victimline l3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x02,event=0x9 l3victimstate.t1.s0.none_nol3victimline l3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x02,event=0x9 l3victimstate.t2.s0.none_nol3victimline l3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x02,event=0x9 l3victimstate.t3.s0.none_nol3victimline l3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x02,event=0x9 l3victimstate.t4.s0.none_nol3victimline l3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x02,event=0x9 l3victimstate.t5.s0.none_nol3victimline l3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x02,event=0x9 l3victimstate.t6.s0.none_nol3victimline l3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x02,event=0x9 l3victimstate.t7.s0.none_nol3victimline l3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x02,event=0x9 l3victimstate.t0.s1.none_nol3victimline l3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x02,event=0x9 l3victimstate.t1.s1.none_nol3victimline l3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x02,event=0x9 l3victimstate.t2.s1.none_nol3victimline l3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x02,event=0x9 l3victimstate.t3.s1.none_nol3victimline l3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x02,event=0x9 l3victimstate.t4.s1.none_nol3victimline l3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x02,event=0x9 l3victimstate.t5.s1.none_nol3victimline l3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x02,event=0x9 l3victimstate.t6.s1.none_nol3victimline l3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x02,event=0x9 l3victimstate.t7.s1.none_nol3victimline l3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x02,event=0x9 l3victimstate.t0.s2.none_nol3victimline l3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x02,event=0x9 l3victimstate.t1.s2.none_nol3victimline l3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x02,event=0x9 l3victimstate.t2.s2.none_nol3victimline l3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x02,event=0x9 l3victimstate.t3.s2.none_nol3victimline l3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x02,event=0x9 l3victimstate.t4.s2.none_nol3victimline l3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x02,event=0x9 l3victimstate.t5.s2.none_nol3victimline l3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x02,event=0x9 l3victimstate.t6.s2.none_nol3victimline l3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x02,event=0x9 l3victimstate.t7.s2.none_nol3victimline l3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x02,event=0x9 l3victimstate.t0.s3.none_nol3victimline l3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x02,event=0x9 l3victimstate.t1.s3.none_nol3victimline l3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x02,event=0x9 l3victimstate.t2.s3.none_nol3victimline l3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x02,event=0x9 l3victimstate.t3.s3.none_nol3victimline l3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x02,event=0x9 l3victimstate.t4.s3.none_nol3victimline l3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x02,event=0x9 l3victimstate.t5.s3.none_nol3victimline l3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x02,event=0x9 l3victimstate.t6.s3.none_nol3victimline l3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x02,event=0x9 l3victimstate.t7.s3.none_nol3victimline l3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x02,event=0x9 l3victimstate.t0.s0.f_s l3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x04,event=0x9 l3victimstate.t1.s0.f_s l3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x04,event=0x9 l3victimstate.t2.s0.f_s l3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x04,event=0x9 l3victimstate.t3.s0.f_s l3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x04,event=0x9 l3victimstate.t4.s0.f_s l3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x04,event=0x9 l3victimstate.t5.s0.f_s l3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x04,event=0x9 l3victimstate.t6.s0.f_s l3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x04,event=0x9 l3victimstate.t7.s0.f_s l3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x04,event=0x9 l3victimstate.t0.s1.f_s l3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x04,event=0x9 l3victimstate.t1.s1.f_s l3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x04,event=0x9 l3victimstate.t2.s1.f_s l3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x04,event=0x9 l3victimstate.t3.s1.f_s l3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x04,event=0x9 l3victimstate.t4.s1.f_s l3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x04,event=0x9 l3victimstate.t5.s1.f_s l3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x04,event=0x9 l3victimstate.t6.s1.f_s l3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x04,event=0x9 l3victimstate.t7.s1.f_s l3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x04,event=0x9 l3victimstate.t0.s2.f_s l3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x04,event=0x9 l3victimstate.t1.s2.f_s l3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x04,event=0x9 l3victimstate.t2.s2.f_s l3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x04,event=0x9 l3victimstate.t3.s2.f_s l3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x04,event=0x9 l3victimstate.t4.s2.f_s l3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x04,event=0x9 l3victimstate.t5.s2.f_s l3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x04,event=0x9 l3victimstate.t6.s2.f_s l3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x04,event=0x9 l3victimstate.t7.s2.f_s l3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x04,event=0x9 l3victimstate.t0.s3.f_s l3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x04,event=0x9 l3victimstate.t1.s3.f_s l3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x04,event=0x9 l3victimstate.t2.s3.f_s l3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x04,event=0x9 l3victimstate.t3.s3.f_s l3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x04,event=0x9 l3victimstate.t4.s3.f_s l3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x04,event=0x9 l3victimstate.t5.s3.f_s l3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x04,event=0x9 l3victimstate.t6.s3.f_s l3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x04,event=0x9 l3victimstate.t7.s3.f_s l3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x04,event=0x9 l3victimstate.t0.s0.o l3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x08,event=0x9 l3victimstate.t1.s0.o l3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x08,event=0x9 l3victimstate.t2.s0.o l3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x08,event=0x9 l3victimstate.t3.s0.o l3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x08,event=0x9 l3victimstate.t4.s0.o l3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x08,event=0x9 l3victimstate.t5.s0.o l3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x08,event=0x9 l3victimstate.t6.s0.o l3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x08,event=0x9 l3victimstate.t7.s0.o l3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x08,event=0x9 l3victimstate.t0.s1.o l3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x08,event=0x9 l3victimstate.t1.s1.o l3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x08,event=0x9 l3victimstate.t2.s1.o l3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x08,event=0x9 l3victimstate.t3.s1.o l3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x08,event=0x9 l3victimstate.t4.s1.o l3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x08,event=0x9 l3victimstate.t5.s1.o l3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x08,event=0x9 l3victimstate.t6.s1.o l3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x08,event=0x9 l3victimstate.t7.s1.o l3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x08,event=0x9 l3victimstate.t0.s2.o l3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x08,event=0x9 l3victimstate.t1.s2.o l3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x08,event=0x9 l3victimstate.t2.s2.o l3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x08,event=0x9 l3victimstate.t3.s2.o l3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x08,event=0x9 l3victimstate.t4.s2.o l3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x08,event=0x9 l3victimstate.t5.s2.o l3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x08,event=0x9 l3victimstate.t6.s2.o l3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x08,event=0x9 l3victimstate.t7.s2.o l3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x08,event=0x9 l3victimstate.t0.s3.o l3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x08,event=0x9 l3victimstate.t1.s3.o l3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x08,event=0x9 l3victimstate.t2.s3.o l3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x08,event=0x9 l3victimstate.t3.s3.o l3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x08,event=0x9 l3victimstate.t4.s3.o l3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x08,event=0x9 l3victimstate.t5.s3.o l3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x08,event=0x9 l3victimstate.t6.s3.o l3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x08,event=0x9 l3victimstate.t7.s3.o l3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x08,event=0x9 l3victimstate.t0.s0.e_fe l3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x10,event=0x9 l3victimstate.t1.s0.e_fe l3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x10,event=0x9 l3victimstate.t2.s0.e_fe l3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x10,event=0x9 l3victimstate.t3.s0.e_fe l3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x10,event=0x9 l3victimstate.t4.s0.e_fe l3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x10,event=0x9 l3victimstate.t5.s0.e_fe l3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x10,event=0x9 l3victimstate.t6.s0.e_fe l3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x10,event=0x9 l3victimstate.t7.s0.e_fe l3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x10,event=0x9 l3victimstate.t0.s1.e_fe l3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x10,event=0x9 l3victimstate.t1.s1.e_fe l3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x10,event=0x9 l3victimstate.t2.s1.e_fe l3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x10,event=0x9 l3victimstate.t3.s1.e_fe l3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x10,event=0x9 l3victimstate.t4.s1.e_fe l3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x10,event=0x9 l3victimstate.t5.s1.e_fe l3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x10,event=0x9 l3victimstate.t6.s1.e_fe l3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x10,event=0x9 l3victimstate.t7.s1.e_fe l3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x10,event=0x9 l3victimstate.t0.s2.e_fe l3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x10,event=0x9 l3victimstate.t1.s2.e_fe l3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x10,event=0x9 l3victimstate.t2.s2.e_fe l3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x10,event=0x9 l3victimstate.t3.s2.e_fe l3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x10,event=0x9 l3victimstate.t4.s2.e_fe l3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x10,event=0x9 l3victimstate.t5.s2.e_fe l3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x10,event=0x9 l3victimstate.t6.s2.e_fe l3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x10,event=0x9 l3victimstate.t7.s2.e_fe l3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x10,event=0x9 l3victimstate.t0.s3.e_fe l3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x10,event=0x9 l3victimstate.t1.s3.e_fe l3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x10,event=0x9 l3victimstate.t2.s3.e_fe l3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x10,event=0x9 l3victimstate.t3.s3.e_fe l3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x10,event=0x9 l3victimstate.t4.s3.e_fe l3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x10,event=0x9 l3victimstate.t5.s3.e_fe l3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x10,event=0x9 l3victimstate.t6.s3.e_fe l3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x10,event=0x9 l3victimstate.t7.s3.e_fe l3_thread_mask=0x80,l3_slice_mask=0x08,event=0x9 l3victimstate.t0.s0.m l3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x20,event=0x9 l3victimstate.t1.s0.m l3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x20,event=0x9 l3victimstate.t2.s0.m l3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x20,event=0x9 l3victimstate.t3.s0.m l3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x20,event=0x9 l3victimstate.t4.s0.m l3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x20,event=0x9 l3victimstate.t5.s0.m l3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x20,event=0x9 l3victimstate.t6.s0.m l3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x20,event=0x9 l3victimstate.t7.s0.m l3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x20,event=0x9 l3victimstate.t0.s1.m l3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x20,event=0x9 l3victimstate.t1.s1.m l3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x20,event=0x9 l3victimstate.t2.s1.m l3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x20,event=0x9 l3victimstate.t3.s1.m l3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x20,event=0x9 l3victimstate.t4.s1.m l3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x20,event=0x9 l3victimstate.t5.s1.m l3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x20,event=0x9 l3victimstate.t6.s1.m l3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x20,event=0x9 l3victimstate.t7.s1.m l3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x20,event=0x9 l3victimstate.t0.s2.m l3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x20,event=0x9 l3victimstate.t1.s2.m l3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x20,event=0x9 l3victimstate.t2.s2.m l3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x20,event=0x9 l3victimstate.t3.s2.m l3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x20,event=0x9 l3victimstate.t4.s2.m l3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x20,event=0x9 l3victimstate.t5.s2.m l3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x20,event=0x9 l3victimstate.t6.s2.m l3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x20,event=0x9 l3victimstate.t7.s2.m l3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x20,event=0x9 l3victimstate.t0.s3.m l3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x20,event=0x9 l3victimstate.t1.s3.m l3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x20,event=0x9 l3victimstate.t2.s3.m l3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x20,event=0x9 l3victimstate.t3.s3.m l3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x20,event=0x9 l3victimstate.t4.s3.m l3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x20,event=0x9 l3victimstate.t5.s3.m l3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x20,event=0x9 l3victimstate.t6.s3.m l3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x20,event=0x9 l3victimstate.t7.s3.m l3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x20,event=0x9 l3victimstate.t0.s0.d l3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x40,event=0x9 l3victimstate.t1.s0.d l3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x40,event=0x9 l3victimstate.t2.s0.d l3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x40,event=0x9 l3victimstate.t3.s0.d l3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x40,event=0x9 l3victimstate.t4.s0.d l3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x40,event=0x9 l3victimstate.t5.s0.d l3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x40,event=0x9 l3victimstate.t6.s0.d l3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x40,event=0x9 l3victimstate.t7.s0.d l3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x40,event=0x9 l3victimstate.t0.s1.d l3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x40,event=0x9 l3victimstate.t1.s1.d l3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x40,event=0x9 l3victimstate.t2.s1.d l3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x40,event=0x9 l3victimstate.t3.s1.d l3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x40,event=0x9 l3victimstate.t4.s1.d l3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x40,event=0x9 l3victimstate.t5.s1.d l3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x40,event=0x9 l3victimstate.t6.s1.d l3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x40,event=0x9 l3victimstate.t7.s1.d l3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x40,event=0x9 l3victimstate.t0.s2.d l3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x40,event=0x9 l3victimstate.t1.s2.d l3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x40,event=0x9 l3victimstate.t2.s2.d l3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x40,event=0x9 l3victimstate.t3.s2.d l3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x40,event=0x9 l3victimstate.t4.s2.d l3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x40,event=0x9 l3victimstate.t5.s2.d l3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x40,event=0x9 l3victimstate.t6.s2.d l3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x40,event=0x9 l3victimstate.t7.s2.d l3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x40,event=0x9 l3victimstate.t0.s3.d l3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x40,event=0x9 l3victimstate.t1.s3.d l3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x40,event=0x9 l3victimstate.t2.s3.d l3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x40,event=0x9 l3victimstate.t3.s3.d l3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x40,event=0x9 l3victimstate.t4.s3.d l3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x40,event=0x9 l3victimstate.t5.s3.d l3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x40,event=0x9 l3victimstate.t6.s3.d l3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x40,event=0x9 l3victimstate.t7.s3.d l3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x40,event=0x9 l3victimstate.t0.s0.od l3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x80,event=0x9 l3victimstate.t1.s0.od l3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x80,event=0x9 l3victimstate.t2.s0.od l3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x80,event=0x9 l3victimstate.t3.s0.od l3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x80,event=0x9 l3victimstate.t4.s0.od l3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x80,event=0x9 l3victimstate.t5.s0.od l3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x80,event=0x9 l3victimstate.t6.s0.od l3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x80,event=0x9 l3victimstate.t7.s0.od l3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x80,event=0x9 l3victimstate.t0.s1.od l3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x80,event=0x9 l3victimstate.t1.s1.od l3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x80,event=0x9 l3victimstate.t2.s1.od l3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x80,event=0x9 l3victimstate.t3.s1.od l3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x80,event=0x9 l3victimstate.t4.s1.od l3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x80,event=0x9 l3victimstate.t5.s1.od l3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x80,event=0x9 l3victimstate.t6.s1.od l3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x80,event=0x9 l3victimstate.t7.s1.od l3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x80,event=0x9 l3victimstate.t0.s2.od l3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x80,event=0x9 l3victimstate.t1.s2.od l3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x80,event=0x9 l3victimstate.t2.s2.od l3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x80,event=0x9 l3victimstate.t3.s2.od l3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x80,event=0x9 l3victimstate.t4.s2.od l3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x80,event=0x9 l3victimstate.t5.s2.od l3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x80,event=0x9 l3victimstate.t6.s2.od l3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x80,event=0x9 l3victimstate.t7.s2.od l3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x80,event=0x9 l3victimstate.t0.s3.od l3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x80,event=0x9 l3victimstate.t1.s3.od l3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x80,event=0x9 l3victimstate.t2.s3.od l3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x80,event=0x9 l3victimstate.t3.s3.od l3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x80,event=0x9 l3victimstate.t4.s3.od l3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x80,event=0x9 l3victimstate.t5.s3.od l3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x80,event=0x9 l3victimstate.t6.s3.od l3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x80,event=0x9 l3victimstate.t7.s3.od l3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x80,event=0x9 ls_locks.bus_lock umask=0x1,event=0x25 Bus lock when a locked operations crosses a cache boundary or is done on an uncacheable memory type ls_dispatch.ld_st_dispatch umask=0x4,event=0x29 Counts the number of operations dispatched to the LS unit. Unit Masks ADDed. Load-op-Stores ls_dispatch.store_dispatch umask=0x2,event=0x29 Counts the number of stores dispatched to the LS unit. Unit Masks ADDed ls_dispatch.ld_dispatch umask=0x1,event=0x29 Counts the number of loads dispatched to the LS unit. Unit Masks ADDed ls_stlf event=0x35 Number of STLF hits ls_dc_accesses event=0x40 The number of accesses to the data cache for load and store references. This may include certain microcode scratchpad accesses, although these are generally rare. Each increment represents an eight-byte access, although the instruction may only be accessing a portion of that. This event is a speculative event ls_mab_alloc.dc_prefetcher umask=0x8,event=0x41 LS MAB allocates by type - DC prefetcher ls_mab_alloc.stores umask=0x2,event=0x41 LS MAB allocates by type - stores ls_mab_alloc.loads umask=0x01,event=0x41 LS MAB allocates by type - loads ls_l1_d_tlb_miss.all umask=0xff,event=0x45 L1 DTLB Miss or Reload off all sizes ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss umask=0x80,event=0x45 L1 DTLB Miss of a page of 1G size ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss umask=0x40,event=0x45 L1 DTLB Miss of a page of 2M size ls_l1_d_tlb_miss.tlb_reload_32k_l2_miss umask=0x20,event=0x45 L1 DTLB Miss of a page of 32K size ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss umask=0x10,event=0x45 L1 DTLB Miss of a page of 4K size ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit umask=0x8,event=0x45 L1 DTLB Reload of a page of 1G size ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit umask=0x4,event=0x45 L1 DTLB Reload of a page of 2M size ls_l1_d_tlb_miss.tlb_reload_32k_l2_hit umask=0x2,event=0x45 L1 DTLB Reload of a page of 32K size ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit umask=0x1,event=0x45 L1 DTLB Reload of a page of 4K size ls_tablewalker.iside umask=0xc,event=0x46 Total Page Table Walks on I-side ls_tablewalker.ic_type1 umask=0x8,event=0x46 Total Page Table Walks IC Type 1 ls_tablewalker.ic_type0 umask=0x4,event=0x46 Total Page Table Walks IC Type 0 ls_tablewalker.dside umask=0x3,event=0x46 Total Page Table Walks on D-side ls_tablewalker.dc_type1 umask=0x2,event=0x46 Total Page Table Walks DC Type 1 ls_tablewalker.dc_type0 umask=0x1,event=0x46 Total Page Table Walks DC Type 0 ls_misal_accesses event=0x47 Misaligned loads ls_pref_instr_disp.prefetch_nta umask=0x4,event=0x4b Software Prefetch Instructions (PREFETCHNTA instruction) Dispatched ls_pref_instr_disp.store_prefetch_w umask=0x2,event=0x4b Software Prefetch Instructions (3DNow PREFETCHW instruction) Dispatched ls_pref_instr_disp.load_prefetch_w umask=0x1,event=0x4b Software Prefetch Instructions Dispatched. Prefetch, Prefetch_T0_T1_T2 ls_inef_sw_pref.mab_mch_cnt umask=0x2,event=0x52 The number of software prefetches that did not fetch data outside of the processor core. Software PREFETCH instruction saw a match on an already-allocated miss request buffer ls_inef_sw_pref.data_pipe_sw_pf_dc_hit umask=0x1,event=0x52 The number of software prefetches that did not fetch data outside of the processor core. Software PREFETCH instruction saw a DC hit ls_not_halted_cyc event=0x76 Cycles not in Halt ic_oc_mode_switch.oc_ic_mode_switch umask=0x2,event=0x28a OC Mode Switch. OC to IC mode switch ic_oc_mode_switch.ic_oc_mode_switch umask=0x1,event=0x28a OC Mode Switch. IC to OC mode switch de_dis_dispatch_token_stalls0.retire_token_stall umask=0x40,event=0xaf Cycles where a dispatch group is valid but does not get dispatched due to a token stall. RETIRE Tokens unavailable de_dis_dispatch_token_stalls0.agsq_token_stall umask=0x20,event=0xaf Cycles where a dispatch group is valid but does not get dispatched due to a token stall. AGSQ Tokens unavailable de_dis_dispatch_token_stalls0.alu_token_stall umask=0x10,event=0xaf Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALU tokens total unavailable de_dis_dispatch_token_stalls0.alsq3_0_token_stall umask=0x8,event=0xaf Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 3_0 Tokens unavailable de_dis_dispatch_token_stalls0.alsq3_token_stall umask=0x4,event=0xaf Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 3 Tokens unavailable de_dis_dispatch_token_stalls0.alsq2_token_stall umask=0x2,event=0xaf Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 2 Tokens unavailable de_dis_dispatch_token_stalls0.alsq1_token_stall umask=0x1,event=0xaf Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 1 Tokens unavailable L1 Branch Prediction Overrides Existing Prediction (speculative) L2 Branch Prediction Overrides Existing Prediction (speculative) bp_l1_tlb_fetch_hit umask=0xFF,event=0x94 The number of instruction fetches that hit in the L1 ITLB bp_l1_tlb_fetch_hit.if1g umask=0x4,event=0x94 The number of instruction fetches that hit in the L1 ITLB. Instruction fetches to a 1GB page bp_l1_tlb_fetch_hit.if2m umask=0x2,event=0x94 The number of instruction fetches that hit in the L1 ITLB. Instruction fetches to a 2MB page bp_l1_tlb_fetch_hit.if4k umask=0x1,event=0x94 The number of instruction fetches that hit in the L1 ITLB. Instruction fetches to a 4KB page l2_pf_hit_l2 umask=0xff,event=0x70 L2 prefetch hit in L2 l2_pf_miss_l2_hit_l3 umask=0xff,event=0x71 L2 prefetcher hits in L3. Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit the L3 l2_pf_miss_l2_l3 umask=0xff,event=0x72 L2 prefetcher misses in L3. All L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches bp_l1_tlb_miss_l2_tlb_miss umask=0xff,event=0x85 bp_l1_tlb_miss_l2_tlb_miss.if1g umask=0x4,event=0x85 The number of instruction fetches that miss in both the L1 and L2 TLBs. Instruction fetches to a 1GB page bp_l1_tlb_miss_l2_tlb_miss.if2m umask=0x2,event=0x85 The number of instruction fetches that miss in both the L1 and L2 TLBs. Instruction fetches to a 2MB page bp_l1_tlb_miss_l2_tlb_miss.if4k umask=0x1,event=0x85 The number of instruction fetches that miss in both the L1 and L2 TLBs. Instruction fetches to a 4KB page The number of micro-ops retired. This count includes all processor activity (instructions, exceptions, interrupts, microcode assists, etc.). The number of events logged per cycle can vary from 0 to 8 ex_ret_cond_misp event=0xd2 Retired Conditional Branch Instructions Mispredicted Retired Fused Instructions. The number of fuse-branch instructions retired per cycle. The number of events logged per cycle can vary from 0-8 Total number of fp uOps Total number of fp uOps. The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS Total number uOps assigned to pipe 3 Total number uOps assigned to pipe 2 Total number uOps assigned to pipe 1 All FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15 fp_ret_sse_avx_ops.mac_flops Multiply-add FLOPS. Multiply-add counts as 2 FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15 fp_ret_sse_avx_ops.div_flops Divide/square root FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15 fp_ret_sse_avx_ops.mult_flops Multiply FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15 fp_ret_sse_avx_ops.add_sub_flops Add/subtract FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15 Number of Scalar Ops optimized. This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes Number of Ops that are candidates for optimization (have Z-bit either set or pass). This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes Number of SSE Move Ops eliminated. This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes Number of SSE Move Ops. This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes SSE bottom-executing uOps retired. The number of serializing Ops retired x87 bottom-executing uOps retired. The number of serializing Ops retired x87 control word mispredict traps due to mispredictions in RC or PC, or changes in mask bits. The number of serializing Ops retired fp_disp_faults.ymm_spill_fault umask=0x8,event=0xe Floating Point Dispatch Faults. YMM spill fault fp_disp_faults.ymm_fill_fault umask=0x4,event=0xe Floating Point Dispatch Faults. YMM fill fault fp_disp_faults.xmm_fill_fault umask=0x2,event=0xe Floating Point Dispatch Faults. XMM fill fault fp_disp_faults.x87_fill_fault umask=0x1,event=0xe Floating Point Dispatch Faults. x87 fill fault ls_bad_status2.stli_other umask=0x2,event=0x24 Non-forwardable conflict; used to reduce STLI's via software. All reasons. Store To Load Interlock (STLI) are loads that were unable to complete because of a possible match with an older store, and the older store could not do STLF for some reason Store-to-load conflicts: A load was unable to complete due to a non-forwardable conflict with an older store. Most commonly, a load's address range partially but not completely overlaps with an uncompleted older store. Software can avoid this problem by using same-size and same-alignment loads and stores when accessing the same data. Vector/SIMD code is particularly susceptible to this problem; software should construct wide vector stores by manipulating vector elements in registers using shuffle/blend/swap instructions prior to storing to memory, instead of using narrow element-by-element stores ls_locks.spec_lock_hi_spec umask=0x8,event=0x25 Retired lock instructions. High speculative cacheable lock speculation succeeded ls_locks.spec_lock_lo_spec umask=0x4,event=0x25 Retired lock instructions. Low speculative cacheable lock speculation succeeded ls_locks.non_spec_lock umask=0x2,event=0x25 Retired lock instructions. Non-speculative lock succeeded Retired lock instructions. Bus lock when a locked operations crosses a cache boundary or is done on an uncacheable memory type. Comparable to legacy bus lock ls_ret_cl_flush Number of retired CLFLUSH instructions ls_ret_cpuid Number of retired CPUID instructions Dispatch of a single op that performs a load from and store to the same memory address. Number of single ops that do load/store to an address Number of stores dispatched. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed Number of loads dispatched. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed ls_smi_rx event=0x2b Number of SMIs received ls_int_taken event=0x2c Number of interrupts taken ls_rdtsc event=0x2d Number of reads of the TSC (RDTSC instructions). The count is speculative ls_st_commit_cancel2.st_commit_cancel_wcb_full event=0x37 A non-cacheable store and the non-cacheable commit buffer is full Number of accesses to the dcache for load/store references LS MAB Allocates by Type. DC prefetcher LS MAB Allocates by Type. Stores umask=0x1,event=0x41 LS MAB Allocates by Type. Loads ls_refills_from_sys.ls_mabresp_rmt_dram umask=0x40,event=0x43 Demand Data Cache Fills by Data Source. DRAM or IO from different die ls_refills_from_sys.ls_mabresp_rmt_cache umask=0x10,event=0x43 Demand Data Cache Fills by Data Source. Hit in cache; Remote CCX and the address's Home Node is on a different die ls_refills_from_sys.ls_mabresp_lcl_dram umask=0x8,event=0x43 Demand Data Cache Fills by Data Source. DRAM or IO from this thread's die ls_refills_from_sys.ls_mabresp_lcl_cache umask=0x2,event=0x43 Demand Data Cache Fills by Data Source. Hit in cache; local CCX (not Local L2), or Remote CCX and the address's Home Node is on this thread's die ls_refills_from_sys.ls_mabresp_lcl_l2 umask=0x1,event=0x43 Demand Data Cache Fills by Data Source. Local L2 hit All L1 DTLB Misses or Reloads L1 DTLB Miss. DTLB reload to a 1G page that miss in the L2 TLB L1 DTLB Miss. DTLB reload to a 2M page that miss in the L2 TLB ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss L1 DTLB Miss. DTLB reload coalesced page miss L1 DTLB Miss. DTLB reload to a 4K page that miss the L2 TLB L1 DTLB Miss. DTLB reload to a 1G page that hit in the L2 TLB L1 DTLB Miss. DTLB reload to a 2M page that hit in the L2 TLB ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit L1 DTLB Miss. DTLB reload hit a coalesced page L1 DTLB Miss. DTLB reload to a 4K page that hit in the L2 TLB ls_pref_instr_disp umask=0xff,event=0x4b Software Prefetch Instructions Dispatched (Speculative) Software Prefetch Instructions Dispatched (Speculative). PrefetchNTA instruction. See docAPM3 PREFETCHlevel ls_pref_instr_disp.prefetch_w Software Prefetch Instructions Dispatched (Speculative). See docAPM3 PREFETCHW ls_pref_instr_disp.prefetch Software Prefetch Instructions Dispatched (Speculative). Prefetch_T0_T1_T2. PrefetchT0, T1 and T2 instructions. See docAPM3 PREFETCHlevel ls_sw_pf_dc_fill.ls_mabresp_rmt_dram umask=0x40,event=0x59 Software Prefetch Data Cache Fills by Data Source. From DRAM (home node remote) ls_sw_pf_dc_fill.ls_mabresp_rmt_cache umask=0x10,event=0x59 Software Prefetch Data Cache Fills by Data Source. From another cache (home node remote) ls_sw_pf_dc_fill.ls_mabresp_lcl_dram umask=0x8,event=0x59 Software Prefetch Data Cache Fills by Data Source. DRAM or IO from this thread's die. From DRAM (home node local) ls_sw_pf_dc_fill.ls_mabresp_lcl_cache umask=0x2,event=0x59 Software Prefetch Data Cache Fills by Data Source. From another cache (home node local) ls_sw_pf_dc_fill.ls_mabresp_lcl_l2 umask=0x1,event=0x59 Software Prefetch Data Cache Fills by Data Source. Local L2 hit ls_hw_pf_dc_fill.ls_mabresp_rmt_dram umask=0x40,event=0x5a Hardware Prefetch Data Cache Fills by Data Source. From DRAM (home node remote) ls_hw_pf_dc_fill.ls_mabresp_rmt_cache umask=0x10,event=0x5a Hardware Prefetch Data Cache Fills by Data Source. From another cache (home node remote) ls_hw_pf_dc_fill.ls_mabresp_lcl_dram umask=0x8,event=0x5a Hardware Prefetch Data Cache Fills by Data Source. From DRAM (home node local) ls_hw_pf_dc_fill.ls_mabresp_lcl_cache umask=0x2,event=0x5a Hardware Prefetch Data Cache Fills by Data Source. From another cache (home node local) ls_hw_pf_dc_fill.ls_mabresp_lcl_l2 umask=0x1,event=0x5a Hardware Prefetch Data Cache Fills by Data Source. Local L2 hit ls_tlb_flush event=0x78 All TLB Flushes de_dis_uop_queue_empty_di0 event=0xa9 Cycles where the Micro-Op Queue is empty de_dis_uops_from_decoder umask=0xff,event=0xaa Ops dispatched from either the decoders, OpCache or both de_dis_uops_from_decoder.opcache_dispatched umask=0x2,event=0xaa Count of dispatched Ops from OpCache de_dis_uops_from_decoder.decoder_dispatched umask=0x1,event=0xaa Count of dispatched Ops from Decoder de_dis_dispatch_token_stalls1.fp_misc_rsrc_stall umask=0x80,event=0xae Cycles where a dispatch group is valid but does not get dispatched due to a token stall. FP Miscellaneous resource unavailable. Applies to the recovery of mispredicts with FP ops de_dis_dispatch_token_stalls1.fp_sch_rsrc_stall umask=0x40,event=0xae Cycles where a dispatch group is valid but does not get dispatched due to a token stall. FP scheduler resource stall. Applies to ops that use the FP scheduler de_dis_dispatch_token_stalls1.fp_reg_file_rsrc_stall umask=0x20,event=0xae Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Floating point register file resource stall. Applies to all FP ops that have a destination register de_dis_dispatch_token_stalls1.taken_branch_buffer_rsrc_stall umask=0x10,event=0xae Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Taken branch buffer resource stall de_dis_dispatch_token_stalls1.int_sched_misc_token_stall umask=0x8,event=0xae Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Integer Scheduler miscellaneous resource stall de_dis_dispatch_token_stalls1.store_queue_token_stall umask=0x4,event=0xae Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Store queue resource stall. Applies to all ops with store semantics de_dis_dispatch_token_stalls1.load_queue_token_stall umask=0x2,event=0xae Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Load queue resource stall. Applies to all ops with load semantics de_dis_dispatch_token_stalls1.int_phy_reg_file_token_stall umask=0x1,event=0xae Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Integer Physical Register File resource stall. Applies to all ops that have an integer destination register de_dis_dispatch_token_stalls0.sc_agu_dispatch_stall Cycles where a dispatch group is valid but does not get dispatched due to a token stall. SC AGU dispatch stall Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ3_0_TokenStall 0N 0N B B B B B u u
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.L.str.6487 .L.str.15487 .L.str.5487 .L.str.14487 .L.str.4487 .L.str.13487 .L.str.3487 .L.str.12487 .L.str.2487 .L.str.11487 .L.str.1487 .L.str.10487 .L.str.487 .L.str.19387 .L.str.9387 .L.str.18387 .L.str.8387 .L.str.17387 .L.str.7387 .L.str.16387 .L.str.6387 .L.str.15387 .L.str.5387 .L.str.14387 .L.str.4387 .L.str.13387 .L.str.3387 .L.str.12387 .L.str.2387 .L.str.11387 .L.str.1387 .L.str.10387 .L.str.387 .L.str.19287 .L.str.9287 .L.str.18287 .L.str.8287 .L.str.17287 .L.str.7287 .L.str.16287 .L.str.6287 .L.str.15287 .L.str.5287 .L.str.14287 .L.str.4287 .L.str.13287 .L.str.3287 .L.str.12287 .L.str.2287 .L.str.11287 .L.str.1287 .L.str.10287 .L.str.287 .L.str.19187 .L.str.9187 .L.str.18187 .L.str.8187 .L.str.17187 .L.str.7187 .L.str.16187 .L.str.6187 .L.str.15187 .L.str.5187 .L.str.14187 .L.str.4187 .L.str.13187 .L.str.3187 .L.str.12187 .L.str.2187 .L.str.11187 .L.str.1187 .L.str.10187 .L.str.187 .L.str.19087 .L.str.9087 .L.str.18087 .L.str.8087 .L.str.17087 .L.str.7087 .L.str.16087 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.L.str.5677 .L.str.14677 .L.str.4677 .L.str.13677 .L.str.3677 .L.str.12677 .L.str.2677 .L.str.11677 .L.str.1677 .L.str.10677 .L.str.677 .L.str.19577 .L.str.9577 .L.str.18577 .L.str.8577 .L.str.17577 .L.str.7577 .L.str.16577 .L.str.6577 .L.str.15577 .L.str.5577 .L.str.14577 .L.str.4577 .L.str.13577 .L.str.3577 .L.str.12577 .L.str.2577 .L.str.11577 .L.str.1577 .L.str.10577 .L.str.577 .L.str.19477 .L.str.9477 .L.str.18477 .L.str.8477 .L.str.17477 .L.str.7477 .L.str.16477 .L.str.6477 .L.str.15477 .L.str.5477 .L.str.14477 .L.str.4477 .L.str.13477 .L.str.3477 .L.str.12477 .L.str.2477 .L.str.11477 .L.str.1477 .L.str.10477 .L.str.477 .L.str.19377 .L.str.9377 .L.str.18377 .L.str.8377 .L.str.17377 .L.str.7377 .L.str.16377 .L.str.6377 .L.str.15377 .L.str.5377 .L.str.14377 .L.str.4377 .L.str.13377 .L.str.3377 .L.str.12377 .L.str.2377 .L.str.11377 .L.str.1377 .L.str.10377 .L.str.377 .L.str.19277 .L.str.9277 .L.str.18277 .L.str.8277 .L.str.17277 .L.str.7277 .L.str.16277 .L.str.6277 .L.str.15277 .L.str.5277 .L.str.14277 .L.str.4277 .L.str.13277 .L.str.3277 .L.str.12277 .L.str.2277 .L.str.11277 .L.str.1277 .L.str.10277 .L.str.277 .L.str.19177 .L.str.9177 .L.str.18177 .L.str.8177 .L.str.17177 .L.str.7177 .L.str.16177 .L.str.6177 .L.str.15177 .L.str.5177 .L.str.14177 .L.str.4177 .L.str.13177 .L.str.3177 .L.str.12177 .L.str.2177 .L.str.11177 .L.str.1177 .L.str.10177 .L.str.177 .L.str.19077 .L.str.9077 .L.str.18077 .L.str.8077 .L.str.17077 .L.str.7077 .L.str.16077 .L.str.6077 .L.str.15077 .L.str.5077 .L.str.14077 .L.str.4077 .L.str.13077 .L.str.3077 .L.str.12077 .L.str.2077 .L.str.11077 .L.str.1077 .L.str.10077 .L.str.77 .L.str.9967 .L.str.18967 .L.str.8967 .L.str.17967 .L.str.7967 .L.str.16967 .L.str.6967 .L.str.15967 .L.str.5967 .L.str.14967 .L.str.4967 .L.str.13967 .L.str.3967 .L.str.12967 .L.str.2967 .L.str.11967 .L.str.1967 .L.str.10967 .L.str.967 .L.str.19867 .L.str.9867 .L.str.18867 .L.str.8867 .L.str.17867 .L.str.7867 .L.str.16867 .L.str.6867 .L.str.15867 .L.str.5867 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.L.str.13801 .L.str.3801 .L.str.12801 .L.str.2801 .L.str.11801 .L.str.1801 .L.str.10801 .L.str.801 .L.str.19701 .L.str.9701 .L.str.18701 .L.str.8701 .L.str.17701 .L.str.7701 .L.str.16701 .L.str.6701 .L.str.15701 .L.str.5701 .L.str.14701 .L.str.4701 .L.str.13701 .L.str.3701 .L.str.12701 .L.str.2701 .L.str.11701 .L.str.1701 .L.str.10701 .L.str.701 .L.str.19601 .L.str.9601 .L.str.18601 .L.str.8601 .L.str.17601 .L.str.7601 .L.str.16601 .L.str.6601 .L.str.15601 .L.str.5601 .L.str.14601 .L.str.4601 .L.str.13601 .L.str.3601 .L.str.12601 .L.str.2601 .L.str.11601 .L.str.1601 .L.str.10601 .L.str.601 .L.str.19501 .L.str.9501 .L.str.18501 .L.str.8501 .L.str.17501 .L.str.7501 .L.str.16501 .L.str.6501 .L.str.15501 .L.str.5501 .L.str.14501 .L.str.4501 .L.str.13501 .L.str.3501 .L.str.12501 .L.str.2501 .L.str.11501 .L.str.1501 .L.str.10501 .L.str.501 .L.str.19401 .L.str.9401 .L.str.18401 .L.str.8401 .L.str.17401 .L.str.7401 .L.str.16401 .L.str.6401 .L.str.15401 .L.str.5401 .L.str.14401 .L.str.4401 .L.str.13401 .L.str.3401 .L.str.12401 .L.str.2401 .L.str.11401 .L.str.1401 .L.str.10401 .L.str.401 .L.str.19301 .L.str.9301 .L.str.18301 .L.str.8301 .L.str.17301 .L.str.7301 .L.str.16301 .L.str.6301 .L.str.15301 .L.str.5301 .L.str.14301 .L.str.4301 .L.str.13301 .L.str.3301 .L.str.12301 .L.str.2301 .L.str.11301 .L.str.1301 .L.str.10301 .L.str.301 .L.str.19201 .L.str.9201 .L.str.18201 .L.str.8201 .L.str.17201 .L.str.7201 .L.str.16201 .L.str.6201 .L.str.15201 .L.str.5201 .L.str.14201 .L.str.4201 .L.str.13201 .L.str.3201 .L.str.12201 .L.str.2201 .L.str.11201 .L.str.1201 .L.str.10201 .L.str.201 .L.str.19101 .L.str.9101 .L.str.18101 .L.str.8101 .L.str.17101 .L.str.7101 .L.str.16101 .L.str.6101 .L.str.15101 .L.str.5101 .L.str.14101 .L.str.4101 .L.str.13101 .L.str.3101 .L.str.12101 .L.str.2101 .L.str.11101 .L.str.1101 .L.str.10101 .L.str.101 .L.str.19001 .L.str.9001 .L.str.18001 .L.str.8001 .L.str.17001 .L.str.7001 .L.str.16001 .L.str.6001 .L.str.15001 .L.str.5001 .L.str.14001 .L.str.4001 .L.str.13001 .L.str.3001 .L.str.12001 .L.str.2001 .L.str.11001 .L.str.1001 .L.str.10001 .L.str.1 .rodata.str1.1 .L.str.9990 .L.str.18990 .L.str.8990 .L.str.17990 .L.str.7990 .L.str.16990 .L.str.6990 .L.str.15990 .L.str.5990 .L.str.14990 .L.str.4990 .L.str.13990 .L.str.3990 .L.str.12990 .L.str.2990 .L.str.11990 .L.str.1990 .L.str.10990 .L.str.990 .L.str.9890 .L.str.18890 .L.str.8890 .L.str.17890 .L.str.7890 .L.str.16890 .L.str.6890 .L.str.15890 .L.str.5890 .L.str.14890 .L.str.4890 .L.str.13890 .L.str.3890 .L.str.12890 .L.str.2890 .L.str.11890 .L.str.1890 .L.str.10890 .L.str.890 .L.str.19790 .L.str.9790 .L.str.18790 .L.str.8790 .L.str.17790 .L.str.7790 .L.str.16790 .L.str.6790 .L.str.15790 .L.str.5790 .L.str.14790 .L.str.4790 .L.str.13790 .L.str.3790 .L.str.12790 .L.str.2790 .L.str.11790 .L.str.1790 .L.str.10790 .L.str.790 .L.str.19690 .L.str.9690 .L.str.18690 .L.str.8690 .L.str.17690 .L.str.7690 .L.str.16690 .L.str.6690 .L.str.15690 .L.str.5690 .L.str.14690 .L.str.4690 .L.str.13690 .L.str.3690 .L.str.12690 .L.str.2690 .L.str.11690 .L.str.1690 .L.str.10690 .L.str.690 .L.str.19590 .L.str.9590 .L.str.18590 .L.str.8590 .L.str.17590 .L.str.7590 .L.str.16590 .L.str.6590 .L.str.15590 .L.str.5590 .L.str.14590 .L.str.4590 .L.str.13590 .L.str.3590 .L.str.12590 .L.str.2590 .L.str.11590 .L.str.1590 .L.str.10590 .L.str.590 .L.str.19490 .L.str.9490 .L.str.18490 .L.str.8490 .L.str.17490 .L.str.7490 .L.str.16490 .L.str.6490 .L.str.15490 .L.str.5490 .L.str.14490 .L.str.4490 .L.str.13490 .L.str.3490 .L.str.12490 .L.str.2490 .L.str.11490 .L.str.1490 .L.str.10490 .L.str.490 .L.str.19390 .L.str.9390 .L.str.18390 .L.str.8390 .L.str.17390 .L.str.7390 .L.str.16390 .L.str.6390 .L.str.15390 .L.str.5390 .L.str.14390 .L.str.4390 .L.str.13390 .L.str.3390 .L.str.12390 .L.str.2390 .L.str.11390 .L.str.1390 .L.str.10390 .L.str.390 .L.str.19290 .L.str.9290 .L.str.18290 .L.str.8290 .L.str.17290 .L.str.7290 .L.str.16290 .L.str.6290 .L.str.15290 .L.str.5290 .L.str.14290 .L.str.4290 .L.str.13290 .L.str.3290 .L.str.12290 .L.str.2290 .L.str.11290 .L.str.1290 .L.str.10290 .L.str.290 .L.str.19190 .L.str.9190 .L.str.18190 .L.str.8190 .L.str.17190 .L.str.7190 .L.str.16190 .L.str.6190 .L.str.15190 .L.str.5190 .L.str.14190 .L.str.4190 .L.str.13190 .L.str.3190 .L.str.12190 .L.str.2190 .L.str.11190 .L.str.1190 .L.str.10190 .L.str.190 .L.str.19090 .L.str.9090 .L.str.18090 .L.str.8090 .L.str.17090 .L.str.7090 .L.str.16090 .L.str.6090 .L.str.15090 .L.str.5090 .L.str.14090 .L.str.4090 .L.str.13090 .L.str.3090 .L.str.12090 .L.str.2090 .L.str.11090 .L.str.1090 .L.str.10090 .L.str.90 .L.str.9980 .L.str.18980 .L.str.8980 .L.str.17980 .L.str.7980 .L.str.16980 .L.str.6980 .L.str.15980 .L.str.5980 .L.str.14980 .L.str.4980 .L.str.13980 .L.str.3980 .L.str.12980 .L.str.2980 .L.str.11980 .L.str.1980 .L.str.10980 .L.str.980 .L.str.9880 .L.str.18880 .L.str.8880 .L.str.17880 .L.str.7880 .L.str.16880 .L.str.6880 .L.str.15880 .L.str.5880 .L.str.14880 .L.str.4880 .L.str.13880 .L.str.3880 .L.str.12880 .L.str.2880 .L.str.11880 .L.str.1880 .L.str.10880 .L.str.880 .L.str.19780 .L.str.9780 .L.str.18780 .L.str.8780 .L.str.17780 .L.str.7780 .L.str.16780 .L.str.6780 .L.str.15780 .L.str.5780 .L.str.14780 .L.str.4780 .L.str.13780 .L.str.3780 .L.str.12780 .L.str.2780 .L.str.11780 .L.str.1780 .L.str.10780 .L.str.780 .L.str.19680 .L.str.9680 .L.str.18680 .L.str.8680 .L.str.17680 .L.str.7680 .L.str.16680 .L.str.6680 .L.str.15680 .L.str.5680 .L.str.14680 .L.str.4680 .L.str.13680 .L.str.3680 .L.str.12680 .L.str.2680 .L.str.11680 .L.str.1680 .L.str.10680 .L.str.680 .L.str.19580 .L.str.9580 .L.str.18580 .L.str.8580 .L.str.17580 .L.str.7580 .L.str.16580 .L.str.6580 .L.str.15580 .L.str.5580 .L.str.14580 .L.str.4580 .L.str.13580 .L.str.3580 .L.str.12580 .L.str.2580 .L.str.11580 .L.str.1580 .L.str.10580 .L.str.580 .L.str.19480 .L.str.9480 .L.str.18480 .L.str.8480 .L.str.17480 .L.str.7480 .L.str.16480 .L.str.6480 .L.str.15480 .L.str.5480 .L.str.14480 .L.str.4480 .L.str.13480 .L.str.3480 .L.str.12480 .L.str.2480 .L.str.11480 .L.str.1480 .L.str.10480 .L.str.480 .L.str.19380 .L.str.9380 .L.str.18380 .L.str.8380 .L.str.17380 .L.str.7380 .L.str.16380 .L.str.6380 .L.str.15380 .L.str.5380 .L.str.14380 .L.str.4380 .L.str.13380 .L.str.3380 .L.str.12380 .L.str.2380 .L.str.11380 .L.str.1380 .L.str.10380 .L.str.380 .L.str.19280 .L.str.9280 .L.str.18280 .L.str.8280 .L.str.17280 .L.str.7280 .L.str.16280 .L.str.6280 .L.str.15280 .L.str.5280 .L.str.14280 .L.str.4280 .L.str.13280 .L.str.3280 .L.str.12280 .L.str.2280 .L.str.11280 .L.str.1280 .L.str.10280 .L.str.280 .L.str.19180 .L.str.9180 .L.str.18180 .L.str.8180 .L.str.17180 .L.str.7180 .L.str.16180 .L.str.6180 .L.str.15180 .L.str.5180 .L.str.14180 .L.str.4180 .L.str.13180 .L.str.3180 .L.str.12180 .L.str.2180 .L.str.11180 .L.str.1180 .L.str.10180 .L.str.180 .L.str.19080 .L.str.9080 .L.str.18080 .L.str.8080 .L.str.17080 .L.str.7080 .L.str.16080 .L.str.6080 .L.str.15080 .L.str.5080 .L.str.14080 .L.str.4080 .L.str.13080 .L.str.3080 .L.str.12080 .L.str.2080 .L.str.11080 .L.str.1080 .L.str.10080 .L.str.80 .L.str.9970 .L.str.18970 .L.str.8970 .L.str.17970 .L.str.7970 .L.str.16970 .L.str.6970 .L.str.15970 .L.str.5970 .L.str.14970 .L.str.4970 .L.str.13970 .L.str.3970 .L.str.12970 .L.str.2970 .L.str.11970 .L.str.1970 .L.str.10970 .L.str.970 .L.str.19870 .L.str.9870 .L.str.18870 .L.str.8870 .L.str.17870 .L.str.7870 .L.str.16870 .L.str.6870 .L.str.15870 .L.str.5870 .L.str.14870 .L.str.4870 .L.str.13870 .L.str.3870 .L.str.12870 .L.str.2870 .L.str.11870 .L.str.1870 .L.str.10870 .L.str.870 .L.str.19770 .L.str.9770 .L.str.18770 .L.str.8770 .L.str.17770 .L.str.7770 .L.str.16770 .L.str.6770 .L.str.15770 .L.str.5770 .L.str.14770 .L.str.4770 .L.str.13770 .L.str.3770 .L.str.12770 .L.str.2770 .L.str.11770 .L.str.1770 .L.str.10770 .L.str.770 .L.str.19670 .L.str.9670 .L.str.18670 .L.str.8670 .L.str.17670 .L.str.7670 .L.str.16670 .L.str.6670 .L.str.15670 .L.str.5670 .L.str.14670 .L.str.4670 .L.str.13670 .L.str.3670 .L.str.12670 .L.str.2670 .L.str.11670 .L.str.1670 .L.str.10670 .L.str.670 .L.str.19570 .L.str.9570 .L.str.18570 .L.str.8570 .L.str.17570 .L.str.7570 .L.str.16570 .L.str.6570 .L.str.15570 .L.str.5570 .L.str.14570 .L.str.4570 .L.str.13570 .L.str.3570 .L.str.12570 .L.str.2570 .L.str.11570 .L.str.1570 .L.str.10570 .L.str.570 .L.str.19470 .L.str.9470 .L.str.18470 .L.str.8470 .L.str.17470 .L.str.7470 .L.str.16470 .L.str.6470 .L.str.15470 .L.str.5470 .L.str.14470 .L.str.4470 .L.str.13470 .L.str.3470 .L.str.12470 .L.str.2470 .L.str.11470 .L.str.1470 .L.str.10470 .L.str.470 .L.str.19370 .L.str.9370 .L.str.18370 .L.str.8370 .L.str.17370 .L.str.7370 .L.str.16370 .L.str.6370 .L.str.15370 .L.str.5370 .L.str.14370 .L.str.4370 .L.str.13370 .L.str.3370 .L.str.12370 .L.str.2370 .L.str.11370 .L.str.1370 .L.str.10370 .L.str.370 .L.str.19270 .L.str.9270 .L.str.18270 .L.str.8270 .L.str.17270 .L.str.7270 .L.str.16270 .L.str.6270 .L.str.15270 .L.str.5270 .L.str.14270 .L.str.4270 .L.str.13270 .L.str.3270 .L.str.12270 .L.str.2270 .L.str.11270 .L.str.1270 .L.str.10270 .L.str.270 .L.str.19170 .L.str.9170 .L.str.18170 .L.str.8170 .L.str.17170 .L.str.7170 .L.str.16170 .L.str.6170 .L.str.15170 .L.str.5170 .L.str.14170 .L.str.4170 .L.str.13170 .L.str.3170 .L.str.12170 .L.str.2170 .L.str.11170 .L.str.1170 .L.str.10170 .L.str.170 .L.str.19070 .L.str.9070 .L.str.18070 .L.str.8070 .L.str.17070 .L.str.7070 .L.str.16070 .L.str.6070 .L.str.15070 .L.str.5070 .L.str.14070 .L.str.4070 .L.str.13070 .L.str.3070 .L.str.12070 .L.str.2070 .L.str.11070 .L.str.1070 .L.str.10070 .L.str.70 .L.str.9960 .L.str.18960 .L.str.8960 .L.str.17960 .L.str.7960 .L.str.16960 .L.str.6960 .L.str.15960 .L.str.5960 .L.str.14960 .L.str.4960 .L.str.13960 .L.str.3960 .L.str.12960 .L.str.2960 .L.str.11960 .L.str.1960 .L.str.10960 .L.str.960 .L.str.19860 .L.str.9860 .L.str.18860 .L.str.8860 .L.str.17860 .L.str.7860 .L.str.16860 .L.str.6860 .L.str.15860 .L.str.5860 .L.str.14860 .L.str.4860 .L.str.13860 .L.str.3860 .L.str.12860 .L.str.2860 .L.str.11860 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.L.str.8700 .L.str.17700 .L.str.7700 .L.str.16700 .L.str.6700 .L.str.15700 .L.str.5700 .L.str.14700 .L.str.4700 .L.str.13700 .L.str.3700 .L.str.12700 .L.str.2700 .L.str.11700 .L.str.1700 .L.str.10700 .L.str.700 .L.str.19600 .L.str.9600 .L.str.18600 .L.str.8600 .L.str.17600 .L.str.7600 .L.str.16600 .L.str.6600 .L.str.15600 .L.str.5600 .L.str.14600 .L.str.4600 .L.str.13600 .L.str.3600 .L.str.12600 .L.str.2600 .L.str.11600 .L.str.1600 .L.str.10600 .L.str.600 .L.str.19500 .L.str.9500 .L.str.18500 .L.str.8500 .L.str.17500 .L.str.7500 .L.str.16500 .L.str.6500 .L.str.15500 .L.str.5500 .L.str.14500 .L.str.4500 .L.str.13500 .L.str.3500 .L.str.12500 .L.str.2500 .L.str.11500 .L.str.1500 .L.str.10500 .L.str.500 .L.str.19400 .L.str.9400 .L.str.18400 .L.str.8400 .L.str.17400 .L.str.7400 .L.str.16400 .L.str.6400 .L.str.15400 .L.str.5400 .L.str.14400 .L.str.4400 .L.str.13400 .L.str.3400 .L.str.12400 .L.str.2400 .L.str.11400 .L.str.1400 .L.str.10400 .L.str.400 .L.str.19300 .L.str.9300 .L.str.18300 .L.str.8300 .L.str.17300 .L.str.7300 .L.str.16300 .L.str.6300 .L.str.15300 .L.str.5300 .L.str.14300 .L.str.4300 .L.str.13300 .L.str.3300 .L.str.12300 .L.str.2300 .L.str.11300 .L.str.1300 .L.str.10300 .L.str.300 .L.str.19200 .L.str.9200 .L.str.18200 .L.str.8200 .L.str.17200 .L.str.7200 .L.str.16200 .L.str.6200 .L.str.15200 .L.str.5200 .L.str.14200 .L.str.4200 .L.str.13200 .L.str.3200 .L.str.12200 .L.str.2200 .L.str.11200 .L.str.1200 .L.str.10200 .L.str.200 .L.str.19100 .L.str.9100 .L.str.18100 .L.str.8100 .L.str.17100 .L.str.7100 .L.str.16100 .L.str.6100 .L.str.15100 .L.str.5100 .L.str.14100 .L.str.4100 .L.str.13100 .L.str.3100 .L.str.12100 .L.str.2100 .L.str.11100 .L.str.1100 .L.str.10100 .L.str.100 .L.str.19000 .L.str.9000 .L.str.18000 .L.str.8000 .L.str.17000 .L.str.7000 .L.str.16000 .L.str.6000 .L.str.15000 .L.str.5000 .L.str.14000 .L.str.4000 .L.str.13000 .L.str.3000 .L.str.12000 .L.str.2000 .L.str.11000 .L.str.1000 .L.str.10000 n+ s 4 &g 2 4 * ` G
# e P _ + x 0 V 0 d Q x x ` t Lo + N M
Zerion Mini Shell 1.0