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Mini Shell
Mini Shell
| Direktori : /usr/lib32/ |
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| Current File : //usr/lib32/libpmc.so.5 |
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" (" ," 0" P" X" \" `" d" " " " " " " " " " " " " " " " " " " $" @" H" L" P" T" p" x" |" " " " " " " " " " " " " " " " " 0" 8" <" @" `" h" l" p" t" " " " " " " " " " " " " " " " (" ," 0" P" X" \" `" d" " " " " " " " " " " " " " " " " " @" H" L" P" p" x" |" " " " " " " " " " " " " " " 0" 8" <" @" D" `" h" l" p" t" " " " " " " " " " " " " " " " " (" ," 0" 4" P" X" \" `" d" " " " " " " " " " " " " " " " " " " " $" @" H" L" P" T" p" x" |" " " " " " " " " " " " " " " " 0" 8" <" @" `" h" l" p" " " " " " " " " " " " " " (" ," 0" 4" P" X" \" `" d" " " " " " " " " " " " " " " " " " " " @" H" L" P" T" p" x" |" " " " " " " " " " " " " " " " " " 0" 8" <" @" D" `" h" l" p" t" " " " " " " " " " " " " " " " " (" ," 0" P" X" \" `" " " " " " " " " " " " " " " " " $" @" H" L" P" T" p" x" |" " " " " " " " " " " " " " " " " 0" 8" <" @" D" `" h" l" p" t" " " " " " " " " " " " " " " " " (" ," 0" 4" P" X" \" `" d" " " " " " " " " " " " " " " " " " " " $" @" H" L" P" T" p" x" |" " " " " " " " " " " " " " " " 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,/$ 0/$ P/$ X/$ \/$ `/$ /$ /$ /$ /$ /$ /$ /$ /$ /$ /$ /$ /$ 0$ 0$ 0$ 0$ @0$ H0$ L0$ P0$ p0$ x0$ |0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 1$ 1$ 1$ 1$ 01$ 81$ <1$ @1$ `1$ h1$ l1$ p1$ 1$ 1$ 1$ 1$ 1$ 1$ 1$ 1$ 1$ 1$ 1$ 2$ 2$ (2$ ,2$ 02$ P2$ X2$ \2$ `2$ 2$ 2$ 2$ 2$ 2$ 2$ 2$ 2$ 2$ 2$ 2$ 2$ 3$ 3$ 3$ 3$ @3$ H3$ L3$ P3$ p3$ x3$ |3$ 3$ 3$ 3$ 3$ 3$ 3$ 3$ 3$ 3$ 4$ 4$ 4$ 4$ 04$ 84$ <4$ @4$ `4$ h4$ l4$ p4$ 4$ 4$ 4$ 4$ 4$ 4$ 4$ 4$ 4$ 4$ 4$ 5$ 5$ (5$ ,5$ 05$ P5$ X5$ \5$ `5$ 5$ 5$ 5$ 5$ 5$ 5$ 5$ 5$ 5$ 5$ 5$ 5$ 6$ 6$ 6$ 6$ @6$ H6$ L6$ P6$ p6$ x6$ |6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 6$ 7$ 7$ 7$ 7$ 07$ 87$ <7$ @7$ `7$ h7$ l7$ p7$ 7$ 7$ 7$ 7$ 7$ 7$ 7$ 7$ 7$ 7$ 7$ 8$ 8$ (8$ ,8$ 08$ P8$ X8$ \8$ `8$ 8$ 8$ 8$ 8$ 8$ 8$ 8$ 8$ 8$ 8$ 8$ 8$ 9$ 9$ 9$ 9$ @9$ H9$ L9$ P9$ p9$ x9$ |9$ 9$ 9$ 9$ 9$ 9$ 9$ 9$ 9$ 9$ :$ :$ :$ :$ 0:$ 8:$ <:$ @:$ `:$ h:$ l:$ p:$ :$ :$ :$ :$ :$ :$ :$ :$ :$ :$ :$ ;$ ;$ (;$ ,;$ 0;$ P;$ X;$ \;$ `;$ ;$ ;$ ;$ ;$ ;$ ;$ ;$ ;$ <$ <$ <$ <$ @<$ H<$ L<$ P<$ p<$ x<$ |<$ <$ <$ <$ <$ <$ <$ <$ <$ <$ =$ =$ =$ =$ 0=$ 8=$ <=$ @=$ `=$ h=$ l=$ p=$ =$ =$ =$ =$ =$ =$ =$ =$ =$ =$ =$ >$ >$ (>$ ,>$ 0>$ P>$ X>$ \>$ `>$ >$ >$ >$ >$ >$ >$ >$ >$ >$ >$ >$ >$ ?$ ?$ ?$ ?$ @?$ H?$ L?$ P?$ p?$ x?$ |?$ ?$ ?$ ?$ ?$ ?$ ?$ ?$ ?$ ?$ @$ @$ @$ @$ 0@$ 8@$ <@$ @@$ `@$ h@$ l@$ p@$ @$ @$ @$ @$ @$ @$ @$ @$ @$ @$ @$ A$ A$ (A$ ,A$ 0A$ PA$ XA$ \A$ `A$ A$ A$ A$ A$ A$ A$ A$ A$ A$ A$ A$ A$ B$ B$ B$ B$ @B$ HB$ LB$ PB$ pB$ xB$ |B$ B$ B$ B$ B$ B$ B$ B$ B$ B$ C$ C$ C$ C$ 0C$ 8C$ <C$ @C$ `C$ hC$ lC$ pC$ C$ C$ C$ C$ C$ C$ C$ C$ C$ C$ C$ D$ D$ (D$ ,D$ 0D$ PD$ XD$ \D$ `D$ D$ D$ D$ D$ D$ D$ D$ D$ D$ D$ D$ D$ E$ E$ E$ E$ @E$ HE$ LE$ PE$ pE$ xE$ |E$ E$ E$ E$ E$ E$ E$ E$ E$ E$ F$ F$ F$ F$ 0F$ 8F$ <F$ @F$ `F$ hF$ lF$ pF$ F$ F$ F$ F$ F$ F$ F$ F$ F$ F$ F$ G$ G$ (G$ ,G$ 0G$ PG$ XG$ \G$ `G$ G$ G$ G$ G$ G$ G$ G$ G$ G$ G$ G$ G$ H$ H$ H$ H$ @H$ HH$ LH$ PH$ pH$ xH$ |H$ H$ H$ H$ H$ H$ H$ H$ H$ H$ I$ I$ I$ I$ 0I$ 8I$ <I$ @I$ `I$ hI$ lI$ pI$ I$ I$ I$ I$ I$ I$ I$ I$ I$ I$ I$ J$ J$ (J$ ,J$ 0J$ PJ$ XJ$ \J$ `J$ J$ J$ J$ J$ J$ J$ J$ J$ J$ J$ J$ J$ K$ K$ K$ K$ @K$ HK$ LK$ PK$ pK$ xK$ |K$ K$ K$ K$ K$ K$ K$ K$ K$ K$ L$ L$ L$ L$ 0L$ 8L$ <L$ @L$ `L$ hL$ lL$ pL$ L$ L$ L$ L$ L$ L$ L$ L$ L$ L$ L$ M$ M$ (M$ ,M$ 0M$ PM$ XM$ \M$ `M$ M$ M$ M$ M$ M$ M$ M$ M$ M$ M$ M$ M$ N$ N$ N$ N$ @N$ HN$ LN$ PN$ pN$ xN$ |N$ N$ N$ N$ N$ N$ N$ N$ N$ N$ O$ O$ O$ O$ 0O$ 8O$ <O$ @O$ `O$ hO$ lO$ pO$ O$ O$ O$ O$ O$ O$ O$ O$ O$ O$ O$ P$ P$ (P$ ,P$ 0P$ PP$ XP$ \P$ `P$ P$ P$ P$ P$ P$ P$ P$ P$ P$ P$ P$ P$ Q$ Q$ Q$ Q$ @Q$ HQ$ LQ$ PQ$ pQ$ xQ$ |Q$ Q$ Q$ Q$ Q$ Q$ Q$ Q$ Q$ Q$ R$ R$ R$ R$ 0R$ 8R$ <R$ @R$ `R$ hR$ lR$ pR$ R$ R$ R$ R$ R$ R$ R$ R$ R$ R$ R$ S$ S$ (S$ ,S$ 0S$ PS$ XS$ \S$ `S$ S$ S$ S$ S$ S$ S$ S$ S$ S$ S$ S$ S$ T$ T$ T$ T$ @T$ HT$ LT$ PT$ pT$ xT$ |T$ T$ T$ T$ T$ T$ T$ T$ T$ T$ U$ U$ U$ U$ 0U$ 8U$ <U$ @U$ `U$ hU$ lU$ pU$ U$ U$ U$ U$ U$ U$ U$ U$ U$ U$ U$ V$ V$ (V$ ,V$ 0V$ PV$ XV$ \V$ `V$ V$ V$ V$ V$ V$ V$ V$ V$ V$ V$ V$ V$ W$ W$ W$ W$ @W$ HW$ LW$ PW$ pW$ xW$ |W$ W$ W$ W$ W$ W$ W$ W$ W$ W$ X$ X$ X$ X$ 0X$ 8X$ <X$ @X$ `X$ hX$ lX$ pX$ X$ X$ X$ X$ X$ X$ X$ X$ X$ X$ X$ Y$ Y$ (Y$ ,Y$ 0Y$ PY$ XY$ \Y$ `Y$ Y$ Y$ Y$ Y$ Y$ Y$ Y$ Y$ Y$ Y$ Y$ Y$ Z$ Z$ Z$ Z$ @Z$ HZ$ LZ$ PZ$ pZ$ xZ$ |Z$ Z$ Z$ Z$ Z$ Z$ Z$ Z$ Z$ Z$ [$ [$ [$ [$ 0[$ 8[$ <[$ @[$ `[$ h[$ l[$ p[$ [$ [$ [$ [$ [$ [$ [$ [$ [$ [$ [$ \$ \$ (\$ ,\$ 0\$ P\$ X\$ \\$ `\$ \$ \$ \$ \$ \$ \$ \$ \$ \$ \$ \$ \$ ]$ ]$ ]$ ]$ @]$ H]$ L]$ P]$ p]$ x]$ |]$ ]$ ]$ ]$ ]$ ]$ ]$ ]$ ]$ ]$ ^$ ^$ ^$ ^$ 0^$ 8^$ <^$ @^$ `^$ h^$ l^$ p^$ ^$ ^$ ^$ ^$ ^$ ^$ ^$ ^$ ^$ ^$ ^$ _$ _$ (_$ ,_$ 0_$ P_$ X_$ \_$ `_$ _$ _$ _$ _$ _$ _$ _$ _$ _$ _$ _$ _$ `$ `$ `$ `$ @`$ H`$ L`$ P`$ p`$ x`$ |`$ `$ `$ `$ `$ `$ `$ `$ `$ `$ a$ a$ a$ a$ 0a$ 8a$ <a$ @a$ `a$ ha$ la$ pa$ a$ a$ a$ a$ a$ a$ a$ a$ a$ a$ a$ b$ b$ (b$ ,b$ 0b$ Pb$ Xb$ \b$ `b$ b$ b$ b$ b$ b$ b$ b$ b$ b$ b$ b$ b$ c$ c$ c$ c$ @c$ Hc$ Lc$ Pc$ pc$ xc$ |c$ c$ c$ c$ c$ c$ c$ c$ c$ c$ d$ d$ d$ d$ 0d$ 8d$ <d$ @d$ `d$ hd$ ld$ pd$ d$ d$ d$ d$ d$ d$ d$ d$ d$ d$ d$ e$ e$ (e$ ,e$ 0e$ Pe$ Xe$ \e$ `e$ e$ e$ e$ e$ e$ e$ e$ e$ e$ e$ e$ e$ f$ f$ f$ f$ @f$ Hf$ Lf$ Pf$ pf$ xf$ |f$ f$ f$ f$ f$ f$ f$ f$ f$ f$ g$ g$ g$ g$ 0g$ 8g$ <g$ @g$ `g$ hg$ lg$ pg$ g$ g$ g$ g$ g$ g$ g$ g$ g$ g$ g$ h$ h$ (h$ ,h$ 0h$ Ph$ Xh$ \h$ `h$ h$ h$ h$ h$ h$ h$ h$ h$ h$ h$ h$ h$ i$ i$ i$ i$ @i$ Hi$ Li$ Pi$ pi$ xi$ |i$ i$ i$ i$ i$ i$ i$ i$ i$ i$ j$ j$ j$ j$ 0j$ 8j$ <j$ @j$ `j$ hj$ lj$ pj$ j$ j$ j$ j$ j$ j$ j$ j$ j$ j$ j$ k$ k$ (k$ ,k$ 0k$ Pk$ Xk$ \k$ `k$ k$ k$ k$ k$ k$ k$ k$ k$ k$ k$ k$ k$ l$ l$ l$ l$ @l$ Hl$ Ll$ Pl$ pl$ xl$ |l$ l$ l$ l$ l$ l$ l$ l$ l$ l$ m$ m$ m$ m$ 0m$ 8m$ <m$ @m$ `m$ hm$ lm$ pm$ m$ m$ m$ m$ m$ m$ m$ m$ m$ m$ m$ n$ n$ (n$ ,n$ 0n$ Pn$ Xn$ \n$ `n$ n$ n$ n$ n$ n$ n$ n$ n$ n$ n$ n$ n$ o$ o$ o$ o$ @o$ Ho$ Lo$ Po$ po$ xo$ |o$ o$ o$ o$ o$ o$ o$ o$ o$ o$ p$ p$ p$ p$ 0p$ 8p$ <p$ @p$ `p$ hp$ lp$ pp$ p$ p$ p$ p$ p$ p$ p$ p$ p$ p$ p$ q$ q$ (q$ ,q$ 0q$ Pq$ Xq$ \q$ `q$ q$ q$ q$ q$ q$ q$ q$ q$ q$ q$ q$ q$ r$ r$ r$ r$ @r$ Hr$ Lr$ Pr$ pr$ xr$ |r$ r$ r$ r$ r$ r$ r$ r$ r$ r$ s$ s$ s$ s$ 0s$ 8s$ <s$ @s$ `s$ hs$ ls$ ps$ s$ s$ s$ s$ s$ s$ s$ s$ s$ s$ s$ t$ t$ (t$ ,t$ 0t$ Pt$ Xt$ \t$ `t$ t$ t$ t$ t$ t$ t$ t$ t$ t$ t$ t$ t$ u$ u$ u$ u$ @u$ Hu$ Lu$ Pu$ pu$ xu$ |u$ u$ u$ u$ u$ u$ u$ u$ u$ u$ v$ v$ v$ v$ 0v$ 8v$ <v$ @v$ `v$ hv$ lv$ pv$ v$ v$ v$ v$ v$ v$ v$ v$ v$ v$ v$ w$ w$ (w$ ,w$ 0w$ Pw$ Xw$ \w$ `w$ w$ w$ w$ w$ w$ w$ w$ w$ w$ w$ w$ w$ x$ x$ x$ x$ @x$ Hx$ Lx$ Px$ px$ xx$ |x$ x$ x$ x$ x$ x$ x$ x$ x$ x$ y$ y$ y$ y$ 0y$ 8y$ <y$ @y$ `y$ hy$ ly$ py$ y$ y$ y$ y$ y$ y$ y$ y$ y$ y$ y$ z$ z$ (z$ ,z$ 0z$ Pz$ Xz$ \z$ `z$ z$ z$ z$ z$ z$ z$ z$ z$ z$ z$ z$ z$ {$ {$ {$ {$ @{$ H{$ L{$ P{$ p{$ x{$ |{$ {$ {$ {$ {$ {$ {$ {$ {$ {$ |$ |$ |$ |$ 0|$ 8|$ <|$ @|$ `|$ h|$ l|$ p|$ |$ |$ |$ |$ |$ |$ |$ |$ |$ |$ |$ }$ }$ (}$ ,}$ 0}$ P}$ X}$ \}$ `}$ }$ }$ }$ }$ }$ }$ }$ }$ }$ }$ }$ }$ ~$ ~$ ~$ ~$ @~$ H~$ L~$ P~$ p~$ x~$ |~$ ~$ ~$ ~$ ~$ ~$ ~$ ~$ ~$ ~$ $ $ $ $ 0$ 8$ <$ @$ `$ h$ l$ p$ $ $ $ $ $ $ $ $ $ $ $ $ $ ($ ,$ 0$ P$ X$ \$ `$ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ @$ H$ L$ P$ p$ x$ |$ $ $ $ $ $ Ё$ $ ܁$ $ $ $ $ $ 0$ 8$ <$ @$ `$ h$ l$ p$ $ $ $ $ $ Ȃ$ ̂$ Ђ$ $ $ $ $ $ ($ ,$ 0$ P$ X$ \$ `$ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ @$ H$ L$ P$ p$ x$ |$ $ $ $ $ $ Є$ $ ܄$ $ $ $ $ $ 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,^% 0^% 4^% P^% X^% \^% `^% d^% ^% ^% ^% ^% ^% ^% ^% ^% ^% ^% ^% ^% ^% ^% ^% _% _% _% _% $_% @_% H_% L_% P_% T_% p_% x_% |_% _% _% _% _% _% _% _% _% _% _% _% _% `% `% `% `% `% 0`% 8`% <`% @`% D`% ``% h`% l`% p`% t`% `% `% `% `% `% `% `% `% `% `% `% `% `% a% a% a% (a% ,a% 0a% 4a% Pa% Xa% \a% `a% da% a% a% a% a% a% a% a% a% a% a% a% a% a% a% a% b% b% b% b% @b% Hb% Lb% Pb% Tb% pb% xb% |b% b% b% b% b% b% b% b% b% b% b% b% c% c% c% c% c% 0c% 8c% <c% @c% Dc% `c% hc% lc% pc% tc% c% c% c% c% c% c% c% c% c% c% c% c% c% d% d% d% (d% ,d% 0d% 4d% Pd% Xd% \d% `d% dd% d% d% d% d% d% d% d% d% d% d% d% d% d% d% d% e% e% e% e% $e% @e% He% Le% Pe% Te% pe% xe% |e% e% e% e% e% e% e% e% e% e% e% e% e% f% f% f% f% f% 0f% 8f% <f% @f% Df% `f% hf% lf% pf% tf% f% f% f% f% f% f% f% f% f% f% f% f% f% g% g% g% (g% ,g% 0g% 4g% Pg% Xg% \g% `g% dg% g% g% g% g% g% g% g% g% g% g% g% g% g% g% g% h% h% h% h% $h% @h% Hh% Lh% Ph% Th% ph% xh% |h% h% h% h% h% h% h% h% h% h% h% h% h% i% i% i% i% i% 0i% 8i% <i% @i% Di% `i% hi% li% pi% ti% i% i% i% i% i% i% i% i% i% i% i% i% i% j% j% j% (j% ,j% 0j% 4j% Pj% Xj% \j% `j% dj% j% j% j% j% j% j% j% j% j% j% j% j% j% j% j% k% k% k% k% $k% @k% Hk% Lk% Pk% Tk% pk% xk% |k% k% k% k% k% k% k% k% k% k% k% k% k% l% l% l% l% l% 0l% 8l% <l% @l% Dl% `l% hl% ll% pl% tl% l% l% l% l% l% l% l% l% l% l% l% l% l% m% m% m% (m% ,m% 0m% 4m% Pm% Xm% \m% `m% dm% m% m% m% m% m% m% m% m% m% m% m% m% m% m% n% n% n% n% $n% @n% Hn% Ln% Pn% Tn% pn% xn% |n% n% n% n% n% n% n% n% n% n% n% n% n% o% o% o% o% o% 0o% 8o% <o% @o% Do% `o% ho% lo% po% to% o% o% o% o% o% o% o% o% o% o% o% o% o% p% p% p% (p% ,p% 0p% 4p% Pp% Xp% \p% `p% dp% p% p% p% p% p% p% p% p% p% p% p% p% p% p% p% q% q% q% q% $q% @q% Hq% Lq% Pq% Tq% pq% xq% |q% q% q% q% q% q% q% q% q% q% q% q% q% r% r% r% r% r% 0r% 8r% <r% @r% Dr% `r% hr% lr% pr% tr% r% r% r% r% r% r% r% r% r% r% r% r% r% s% s% s% (s% ,s% 0s% 4s% Ps% Xs% \s% `s% ds% s% s% s% s% s% s% s% s% s% s% s% s% s% s% s% t% t% t% t% $t% @t% Ht% Lt% Pt% Tt% pt% xt% |t% t% t% t% t% t% t% t% t% t% t% t% u% u% u% u% u% 0u% 8u% <u% @u% Du% `u% hu% lu% pu% tu% u% u% u% u% u% u% u% u% u% u% u% u% u% v% v% v% (v% ,v% 0v% 4v% Pv% Xv% \v% `v% dv% v% v% v% v% v% v% v% v% v% v% v% v% v% v% v% w% w% w% w% $w% @w% Hw% Lw% Pw% pw% xw% |w% w% w% w% w% w% w% w% w% w% w% w% w% x% x% x% x% x% 0x% 8x% <x% @x% Dx% `x% hx% lx% px% x% x% x% x% x% x% x% x% x% x% x% x% x% y% y% y% (y% ,y% 0y% 4y% Py% Xy% \y% `y% dy% y% y% y% y% y% y% y% y% y% y% y% y% y% y% y% z% z% z% z% $z% @z% Hz% Lz% Pz% Tz% pz% xz% |z% z% z% z% z% z% z% z% z% z% z% z% z% {% {% {% {% {% 0{% 8{% <{% @{% D{% `{% h{% l{% p{% t{% {% {% {% {% {% {% {% {% {% {% {% {% {% |% |% |% (|% ,|% 0|% 4|% P|% X|% \|% `|% d|% |% |% |% |% |% |% |% |% |% |% |% |% |% |% |% }% }% }% }% $}% @}% H}% L}% P}% T}% p}% x}% |}% }% }% }% }% }% }% }% }% }% }% }% }% ~% ~% ~% ~% ~% 0~% 8~% <~% @~% D~% `~% h~% l~% p~% t~% ~% ~% ~% ~% ~% ~% ~% ~% ~% ~% ~% ~% ~% % % % (% ,% 0% 4% P% X% \% `% d% % % % % % % % % % % % % % % % % % % % $% @% H% L% P% T% p% x% |% % % % % % % % Ѐ% % ܀% % % % % % % % 0% 8% <% @% D% `% h% l% p% t% % % % % % % ȁ% ́% Ё% % % % % % % (% ,% 0% 4% P% X% \% `% d% % % % % % % % % % Ă% % % % % % % % % $% @% H% L% P% T% p% x% |% % % % % % % % Ѓ% % ܃% % % % % % % % 0% 8% <% @% D% `% h% l% p% t% % % % % % % Ȅ% ̄% Є% Ԅ% % % % % % % (% ,% 0% 4% P% X% \% `% d% % % % % % % % % % ą% % % % % % % % % % $% @% H% L% P% T% p% x% |% % % % % % % % І% ؆% ܆% % % % % % % % 0% 8% <% @% D% `% h% l% p% t% % % % % % % ȇ% ̇% Ї% ԇ% % % % % % % (% ,% 0% 4% P% X% \% `% d% % % % % % % % % % Ĉ% % % % % % % % % % $% @% H% L% P% T% p% x% |% % % % % % % % Љ% ؉% ܉% % % % % % % % 0% 8% <% @% D% `% h% l% p% t% % % % % % % Ȋ% ̊% Њ% Ԋ% % % % % % % (% ,% 0% 4% P% X% \% `% d% % % % % % % % % % ċ% % % % % % % % % % $% @% H% L% P% T% p% x% |% % % % % % % % Ќ% ،% ܌% % % % % % % % 0% 8% <% @% D% `% h% l% p% t% % % % % % % ȍ% ̍% Ѝ% ԍ% % % % % % (% ,% 0% 4% P% X% \% `% d% % % % % % % % % % Ď% % % % % % % % % % $% @% H% L% P% T% p% x% |% % % % % % % % Џ% ؏% % % % % % % % % 0% 8% <% @% D% `% h% l% p% t% % % % % % % Ȑ% ̐% А% Ԑ% % % % % % % (% ,% 0% 4% P% X% \% `% d% % % % % % % % % % đ% % % % % % % % % % $% @% H% L% P% T% p% x% |% % % % % % % % В% ؒ% ܒ% % % % % % % % 0% 8% <% @% D% `% h% l% p% t% % % % % % % ȓ% ̓% Г% ԓ% % % % % % % (% ,% 0% 4% P% X% \% `% d% % % % % % % % % % Ĕ% % % % % % % % % % $% @% H% L% P% T% p% x% |% % % % % % % % Е% ؕ% ܕ% % % % % % % % 0% 8% <% @% D% `% h% l% p% t% % % % % % % Ȗ% ̖% Ж% Ԗ% % % % % % % (% ,% 0% 4% P% X% \% `% d% % % % % % % % % % ė% % % % % % % % % % $% @% H% L% P% T% p% x% |% % % % % % % % И% ؘ% ܘ% % % % % % % % 0% 8% <% @% D% `% h% l% p% t% % % % % % % ș% ̙% Й% ԙ% % % % % % % (% ,% 0% 4% P% X% \% `% d% % % % % % % % % % Ě% % % % % % % % % % $% @% H% L% P% T% p% x% |% % % % % % % % Л% ؛% ܛ% % % % % % % % 0% 8% <% @% D% `% h% l% p% t% % % % % % % Ȝ% ̜% М% Ԝ% % % % % % % (% ,% 0% 4% P% X% \% `% d% % % % % % % % % % ĝ% % % % % % % % % % $% @% H% L% P% T% p% x% |% % % % % % % % О% ؞% ܞ% % % % % % % % 0% 8% <% @% D% `% h% l% p% t% % % % % % % ȟ% ̟% П% ԟ% % % % % % % (% ,% 0% 4% P% X% \% `% d% % % % % % % % % % Ġ% % % % % % % % % % $% @% H% L% P% T% p% x% |% % % % % % % % С% ء% ܡ% % % % % % % % 0% 8% <% @% D% `% h% l% p% t% % % % % % % Ȣ% ̢% Т% Ԣ% % % % % % % (% ,% 0% 4% P% X% \% `% d% % % % % % % % % % ģ% % % % % % % % % % $% @% H% L% P% T% p% x% |% % % % % % % % Ф% ؤ% ܤ% % % % % % % % 0% 8% <% @% D% `% h% l% p% t% % % % % % % ȥ% ̥% Х% ԥ% % % % % % % (% ,% 0% 4% P% X% \% `% d% % % % % % % % % % Ħ% % % % % % % % % % $% @% H% L% P% T% p% x% |% % % % % % % % Ч% ا% ܧ% % % % % % % % 0% 8% <% @% D% `% h% l% p% t% % % % % % % Ȩ% ̨% Ш% Ԩ% % % % % % % (% ,% 0% 4% \% `% d% t% x% |% % % % % % % % % ĩ% ԩ% ة% ܩ% % % % % % % % % $% 4% 8% <% L% P% T% d% h% l% |% % % % % % % % % Ī% Ȫ% ̪% ܪ% % % % % % % $% (% ,% <% @% T% X% \% l% p% % % % % % % % % ̫% Ы% % % % % % % % % ,% 0% D% H% L% \% `% t% x% |% % % % % % % % Ԭ% ج% ܬ% % % % % % % % 4% 8% <% L% P% d% h% l% |% % % % % % % ĭ% ȭ% ̭% ܭ% % % % % % % $% (% ,% <% @% T% X% \% l% p% % % % % % % % % ̮% Ю% % % % % % % % % ,% 0% D% H% L% \% `% t% x% |% % % % % % % % ԯ% د% ܯ% % % % % % % % 4% 8% <% L% P% d% h% l% |% % % % % % % İ% Ȱ% ̰% ܰ% % % % % % % $% (% ,% <% @% T% X% \% l% p% % % % % % % % % ̱% б% % % % % % % % % ,% 0% D% H% L% \% `% t% x% |% % % % % % % % Բ% ز% ܲ% % % % % % % % 4% 8% <% L% P% d% h% l% |% % % % % % % ij% ȳ% ̳% ܳ% % % % % % % $% (% ,% <% @% T% X% \% l% p% % % % % % % % % ̴% д% % % % % % % % % ,% 0% D% H% L% \% `% t% x% |% % % % % % % % Ե% ص% ܵ% % % % % % % % % @% H% L% P% p% x% |% % % % % % ж% ض% ܶ% % % % % % % 0% 8% <% @% `% h% l% p% % % % % % % ȷ% ̷% з% % % % % % % (% ,% 0% P% X% \% `% % % % % % % % % % % % % % % % % % % @% H% L% P% T% p% x% |% % % % % % % % й% ع% ܹ% % % % % % % % 0% 8% <% @% D% `% h% l% p% t% % % % % % % Ⱥ% ̺% к% Ժ% % % % % % (% ,% 0% P% X% \% `% d% % % % % % % % % % % % % % % % % % @% H% L% P% p% x% |% % % % % % % % м% ؼ% ܼ% % % % % % % 0% 8% <% @% D% `% h% l% p% t% % % % % % % Ƚ% ̽% н% Խ% % % % % % % (% ,% 0% 4% P% X% \% `% d% % % % % % % % % ľ% % % % % % % % % % @% H% L% P% T% p% x% |% % % % % % % % п% ؿ% ܿ% % % % % % % % 0% 8% <% @% D% `% h% l% p% t% % % % % % % % % % % % % % % % % (% ,% 0% 4% P% X% \% `% d% % % % % % % % % % % % % % % % % % % % $% @% H% L% P% T% p% x% |% % % % % % % % % % % % % % % % % % 0% 8% <% @% D% `% h% l% p% t% % % % % % % % % % % % % % % % % (% ,% 0% 4% P% X% \% `% d% % % % % % % % % % % % % % % % % % % % $% @% H% L% P% T% p% x% |% % % % % % % % % % % % % % % % % % 0% 8% <% @% D% `% h% l% p% t% % % % % % % % % % % % % % % % % (% ,% 0% 4% P% X% \% `% d% % % % % % % % % % % % % % % % % % % % $% @% H% L% P% T% p% x% |% % % % % % % % % % % % % % % % % % 0% 8% <% @% D% `% h% l% p% t% % % % % % % % % % % % % % % % % (% ,% 0% 4% P% X% \% `% d% % % % % % % % % % % % % % % % % % % % $% @% H% L% P% T% p% x% |% % % % % % % % % % % % % % % % % % 0% 8% <% @% D% `% h% l% p% % % % % % % % % % % % % % % % % (% ,% 0% 4% P% X% \% `% d% % % % % % % % % % % % % % % % % % % % $% @% H% L% P% T% p% x% |% % % % % % % % % % % % % % % % % % 0% 8% <% @% D% `% h% l% p% t% % % % % % % % % % % % % % % % % (% ,% 0% 4% P% X% \% `% d% % % % % % % % % % % % % % % % % % % $% @% H% L% P% T% p% x% |% % % % % % % % % % % % % % % % % % 0% 8% <% @% D% `% h% l% p% t% % % % % % % % % % % % % % % % % (% ,% 0% 4% P% X% \% `% d% % % % % % % % % % % % % % % % % % % % $% @% H% L% P% T% p% x% |% % % % % % % % % % % % % % % % % % 0% 8% <% @% D% `% h% l% p% t% % % % % % % % % % % % % % % % % (% ,% 0% 4% P% X% \% `% d% % % % % % % % % % % % % % % % % % % % $% @% H% L% P% T% p% x% |% % % % % % % % % % % % % % % % % % 0% 8% <% @% D% `% h% l% p% t% % % % % % % % % % % % % % % % % (% ,% 0% 4% P% X% \% `% d% % % % % % % % % % % % % % % % % % % % $% @% H% L% P% T% p% x% |% % % % % % % % % % % % % % % % % % 0% 8% <% @% D% `% h% l% p% t% % % % % % % % % % % % % % % % % (% ,% 0% 4% P% X% \% `% d% % % % % % % % % % % % % % % % % % % % $% @% H% L% P% T% p% x% |% % % % % % % % % % % % % % % % % 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"*2:BJRZbjr LS_BUFFER2_FULL LS_RETIRED_CPUID_INSTRUCTIONS DC_L1_DTLB_MISS_AND_L2_DTLB_MISS BU_FILL_INTO_L2 FR_DISPATCH_STALL_FOR_SEGMENT_LOAD L1_DCACHE_ACCESS MEM_READ BRANCH_DIR_MISPREDICT ISSUE_IS_EMPTY L2D_CACHE_WB EXC_FIQ L2CACHEMASTER_READ_RSP_FLIT LOAD_MISS LOAD_COMPLETED LDQ_QUARTER_TO_HALF LDQ_GT_HALF DDQ1_FULL_DR_STALLS JMIS DIDNA MTVSCR_INSTR_COMPLETED MFVSCR_SYNC_CYCLES LSU_LOAD_HIT_LINE_ALIAS_VS_CSQ0 LSU_RA_LATCH_STALL L1_DATA_STORE_MISS L1_INSTR_CACHE_RELOADS SECOND_SPECULATION_BUFFER_ACTIVE CANCELLED_L1_INSTR_CACHE_MISSES GPR_ISSUE_QUEUE_STALLED L3_TOUCH_HITS L1_INSTR_MISS CYCLES_BRANCH_ISSUE_STALLED PART2_MISALIGNED_CACHE_ACCESS STASH_L2_HITS L2_CACHE_CLEAN_UPDATES DVT7_DETECTED cycles multiply-pipe-excluding-junk-ops cs victim-from-l2 sse-reclass-microfaults rdmodwr ARMV7 INTEL_CORE2 PPC_7450 perpkg: %s
inst-retired.any_p offcore_rsp {"type": "userdata" {"type": "callchain" %s, "pmcid": "0x%08x", "event": "%d", "flags": "0x%08x", "evname": "%s"}
v4 GenuineIntel-6-7A AuthenticAMD-23-[[:xdigit:]]+ Demand requests that miss L2 cache umask=0x41,period=200003,event=0x24 This event counts core-originated cacheable demand requests that refer to the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU l1d_pend_miss.pending_cycles_any Cycles a demand request was blocked due to Fill Buffers inavailability Retired store uops that split across a cacheline boundary. (Precise Event - PEBS) Supports address when precise (Precise event) umask=0x10,period=50021,event=0xd1 l2_trans.l2_wb Number of SSE/AVX computational scalar double precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element Number of X87 assists due to input value fp_assist.simd_output idq.ms_dsb_cycles Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy idq_uops_not_delivered.cycles_fe_was_ok inv=1,umask=0x1,cmask=1,period=2000003,event=0x9c Number of times a TSX Abort was triggered due to release/commit but data and address mismatch umask=0x40,period=2000003,event=0xc8 rtm_retired.aborted_misc1 umask=0x1,period=100007,event=0xcd,ldlat=0x20 This event counts loads with latency value being above 512 Spec update: BDM100, BDM35 (Must be precise) cpu_clk_unhalted.thread_any int_misc.recovery_cycles This event counts taken speculative and retired macro-conditional branch instructions excluding calls and indirect branches Taken speculative and retired indirect branches with return mnemonic umask=0x84,period=200003,event=0x89 uops_executed_port.port_3_core umask=0x8,any=1,period=2000003,event=0xa1 uops_executed_port.port_6 cycle_activity.cycles_l2_miss cycle_activity.cycles_l1d_pending Number of Uops delivered by the LSD umask=0x1,cmask=1,period=2000003,event=0xa8 inv=1,umask=0x2,period=2000003,event=0xb1 Number of instructions retired. General Counter - architectural event Spec update: BDM61 inv=1,umask=0x1,cmask=1,period=2000003,event=0xc2 umask=0x1,period=400009,event=0xc5 umask=0x8,period=100007,event=0xc5 LLC prefetch misses for code reads. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox unc_h_snoop_resp.rspifwd Pre-charges due to page misses. Unit: uncore_imc dtlb_load_misses.walk_completed_4k umask=0x10,period=2000003,event=0x8 Cycle count for an Extended Page table walk itlb_misses.walk_completed_2m_4m Core misses that miss the DTLB and hit the STLB (4K) Operations that miss the first ITLB level but hit the second and do not cause any page walks Number of ITLB page walker hits in the L3 + XSNP Spec update: BDM69, BDM98 tlb_flush.stlb_any Frontend_Bound_SMT uops_retired.retire_slots / (4 * cycles) inst_retired.any / cycles L2_Cache_Fill_BW L2MPKI_All umask=0x1,period=2000003,cmask=1,event=0x60 Counts demand data reads offcore_response.demand_data_rd.supplier_none.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020001 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020001 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010002 offcore_response.pf_l2_data_rd.supplier_none.snoop_not_needed offcore_response.pf_l2_data_rd.l3_hit.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020020 offcore_response.pf_l2_rfo.l3_hit.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0020 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0020 offcore_response.all_pf_data_rd.supplier_none.snoop_hitm offcore_response.all_pf_data_rd.l3_hit.snoop_none offcore_response.all_pf_data_rd.l3_hit.any_snoop offcore_response.all_pf_code_rd.supplier_none.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020091 offcore_response.all_data_rd.supplier_none.snoop_hit_no_fwd umask=0x18,period=2000003,cmask=4,event=0x79 inv=1,umask=0x1,period=2000003,cmask=1,event=0x9c umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000001 offcore_response.demand_data_rd.l3_miss_local_dram.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000001 offcore_response.corewb.l3_miss_local_dram.snoop_not_needed offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000040 offcore_response.pf_l2_code_rd.l3_miss.snoop_not_needed offcore_response.pf_l3_data_rd.l3_hit.snoop_non_dram offcore_response.pf_l3_code_rd.supplier_none.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC008000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000090 offcore_response.all_data_rd.l3_miss_local_dram.snoop_non_dram offcore_response.all_data_rd.l3_miss.snoop_hit_no_fwd offcore_response.all_rfo.l3_miss_local_dram.snoop_hit_no_fwd umask=0x3,any=1,period=2000003,cmask=1,event=0xd umask=0x2,period=2000003,cmask=3,event=0xb1 unc_cbo_xsnp_response.miss_xcore umask=0x18,event=0x34 unc_cbo_cache_lookup.any_mesi DRAM_Read_Latency This event counts retired load uops which data sources were hits in the mid-level (L2) cache Supports address when precise. Spec update: BDM35 (Precise event) offcore_response.all_reads.llc_miss.remote_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x103FC00002 Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache Conditional branch instructions retired (Precise event) qpi_data_bandwidth_tx umask=0x74,period=200000,event=0x29 l2_reject_busq.self.any.i_state umask=0x58,period=200000,event=0x30 l2_no_req.self l1d_cache.all_cache_ref SIMD packed shift micro-ops retired misalign_mem_ref.ld_split umask=0x9,period=200000,event=0x5 misalign_mem_ref.st_split prefetch.prefetcht0 Number of segment register loads External snoops umask=0x1,period=2000000,event=0x12 cpu_clk_unhalted.core_p br_inst_retired.pred_taken br_inst_retired.any1 umask=0x3,period=200000,event=0xc Load uops retired that split a cache-line (Precise event capable) Supports address when precise (Must be precise) offcore_response.any_rfo.l2_miss.any Counts reads for ownership (RFO) requests (demand & prefetch) that hit the L2 cache Counts any data writes to uncacheable write combining (USWC) memory region that miss the L2 cache umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000044000 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600002000 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000042000 offcore_response.full_streaming_stores.l2_miss.any Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000040010 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600000008 offcore_response.corewb.l2_miss.hitm_other_core offcore_response.demand_rfo.outstanding Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0. You cannot collect a PEBs record for this event Counts a load blocked from using a store forward because of an address/size mismatch, only one of the loads blocked from each store will be counted (Must be precise) Counts uops issued by the front end and allocated into the back end of the machine. This event counts uops that retire as well as uops that were speculatively executed but didn't retire. The sort of speculative uops that might be counted includes, but is not limited to those uops issued in the shadow of a miss-predicted branch, those uops that are inserted during an assist (such as for a denormal floating point result), and (previously allocated) uops that might be canceled during a machine clear machine_clears.fp_assist br_inst_retired.jcc Counts near indirect CALL branch instructions retired (Must be precise) Counts near relative CALL branch instructions retired (Must be precise) Counts mispredicted near RET branch instructions retired, where the return address taken was not what the processor predicted (Must be precise) cycles_div_busy.idiv Counts core cycles the integer divide unit is busy Counts the number of demand and L1 prefetcher requests rejected by the L2Q due to a full or nearly full condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to insure fairness between cores, or to delay a core's dirty eviction when the address conflicts with incoming external snoops Counts demand cacheable data reads of full cache lines hit the L2 cache Counts demand cacheable data reads of full cache lines outstanding, per cycle, from the time of the L2 miss to when any response is received Counts the number of writeback transactions caused by L1 or L2 cache evictions hit the L2 cache Counts bus lock and split lock requests hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes true miss for the L2 cache with a snoop miss in the other processor module Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cache line reads generated by hardware L1 data cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts any data writes to uncacheable write combining (USWC) memory region outstanding, per cycle, from the time of the L2 miss to when any response is received Counts data reads generated by L1 or L2 prefetchers miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data reads (demand & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts machine clears due to memory ordering issues. This occurs when a snoop request happens and the machine is uncertain if memory ordering will be preserved - as another core is in the process of modifying the data Page walk completed due to a demand load to a 4K page dtlb_load_misses.walk_completed_1gb Counts cycles DSB is delivered four uops. Set Cmask = 4 Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled Spec update: HSD135 Randomly selected loads with latency value being above 512 Spec update: HSD76, HSD25, HSM26 (Must be precise) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC007F7 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00100 Unhalted core cycles when the thread is not in ring 0 Cycles which a uop is dispatched on port 5 in this thread Cycles with pending L1 cache miss loads Cycles where at least 4 uops were executed per-thread Spec update: HSD144, HSD30, HSM31 Cycles at least 3 micro-op is executed from any thread on physical core Spec update: HSD30, HSM31 Number of front end re-steers due to BPU misprediction Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size dtlb_load_misses.pde_cache_miss This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB store misses Misses in ITLB that causes a page walk of any page size Misses in all ITLB levels that cause completed page walks Counts the number of ITLB flushes, includes 4k/2M/4M pages Number of ITLB page walker loads that hit in the L1+FB umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0600400002 FP operations retired. X87 FP operations that have no exceptions: Counts also flows that have several X87 or flows that use X87 uops in the exception handling Requests from the L2 hardware prefetchers that hit L2 cache l2_store_lock_rqsts.hit_m Not rejected writebacks that missed LLC Counts cycles MITE is delivered at least one uops. Set Cmask = 1 Instruction cache, streaming buffer and victim cache misses Loads with latency value being above 16 (Must be precise) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400001 Cycles which a Uop is dispatched on port 0 Cycles while L2 cache miss load* is outstanding Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution (Must be precise) umask=0x04,event=0x34 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0090 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3fffc203f7 Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from local dram offcore_response.pf_l2_data_rd.llc_miss.any_dram txl0p_power_cycles % event=0x7 event=0xc,filter_band1=20 Counts the number of cycles that the uncore was running at a frequency greater than or equal to 3Ghz. Derived from unc_p_freq_band2_cycles. Unit: uncore_pcu Counts the number of cycles that the uncore transitioned to a frequency greater than or equal to 3Ghz. Derived from unc_p_freq_band2_cycles. Unit: uncore_pcu This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K) (Precise event) umask=0x4,period=200003,event=0x27 l1d_blocks.bank_conflict_cycles inv=1,umask=0x1,period=2000003,cmask=4,event=0x9c umask=0xa,period=2000003,event=0xac All (macro) branch instructions retired. (Precise Event - PEBS) (Must be precise) Memory page activates. Unit: uncore_imc umask=0xc,event=0x4 unc_m_rpq_occupancy Counts the loads retired that get the data from the other core in the same tile in M state Supports address when precise (Precise event) umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010070 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x08000832f7 Counts Demand code reads and prefetch code read requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080022 Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state offcore_response.bus_locks.l2_hit_near_tile_m Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state offcore_response.bus_locks.l2_hit_near_tile_e_f offcore_response.partial_writes.l2_hit_near_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080100 offcore_response.demand_data_rd.l2_hit_near_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002000200 Counts any Prefetch requests that accounts for responses which hit its own tile's L2 with data in M state Counts Demand code reads and prefetch code read requests that accounts for responses which hit its own tile's L2 with data in E state offcore_response.partial_reads.l2_hit_this_tile_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010002000 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800400044 Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from DRAM Local offcore_response.uc_code_reads.ddr_far Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from DRAM Far offcore_response.pf_l2_rfo.mcdram Counts Bus locks and split lock requests that accounts for responses from MCDRAM (local and far) umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181800080 offcore_response.any_request.ddr offcore_response.any_read.ddr Counts the number of branch instructions retired (Precise event) Counts the number of near indirect CALL branch instructions retired (Precise event) This event counts the number of packed vector SSE, AVX, AVX2, and AVX-512 micro-ops retired (floating point, integer and store) except for loads (memory-to-register mov-type micro-ops), packed byte and word multiplies Counts all nukes Counts the number of unhalted core clock cycles l1d_wb_l2.m_state umask=0x8,period=100000,event=0x28 L1 writebacks to L2 in M state L2 data prefetches in M state l2_lines_in.any umask=0xf,period=100000,event=0xf2 L2 modified lines evicted by a prefetch request umask=0x30,period=200000,event=0x24 L2 instruction fetches umask=0x4,period=200000,event=0xf0 umask=0x8,period=100000,event=0x27 mem_inst_retired.stores umask=0x40,period=200000,event=0xcb umask=0x10,period=2000000,event=0xf4 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4744 offcore_response.any_rfo.io_csr_mmio Offcore writebacks to the IO, CSR, MMIO unit offcore_response.corewb.llc_hit_no_other_core offcore_response.data_ifetch.any_location umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4777 offcore_response.data_in.any_location Offcore data reads, RFO's and prefetches satisfied by the LLC and HIT in a sibling core offcore_response.data_in.llc_hit_other_core_hitm umask=0x1,period=100000,event=0xb7,offcore_rsp=0x203 Offcore demand data requests that HIT in a remote cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x702 Offcore demand RFO requests that HIT in a remote cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x8030 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x230 offcore_response.pf_data.remote_cache_dram Offcore prefetch data reads satisfied by the LLC or local DRAM Offcore prefetch code reads satisfied by the LLC or local DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3840 Offcore prefetch RFO requests satisfied by a remote cache Computational floating-point operations executed offcore_response.any_rfo.local_dram Offcore prefetch data requests satisfied by a remote DRAM Offcore prefetch RFO requests satisfied by the local DRAM l1i.cycles_stalled umask=0x20,period=2000,event=0x89 umask=0x40,period=20000,event=0x89 Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter) ssex_uops_retired.scalar_double inv=1,umask=0x1,period=2000000,cmask=1,event=0xd1 uops_executed.core_stall_count_no_port5 Cycles Uops are being retired (Precise event) Counts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches from L1 and L2. It does not include all accesses to the L3 Spec update: SKL057 Counts duration of L1D miss outstanding in cycles umask=0x80,period=100003,event=0xb0 Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0108000 offcore_response.other.l3_hit_e.snoop_hitm offcore_response.other.l3_hit_m.snoop_hitm offcore_response.demand_code_rd.l3_hit_s.spl_hit offcore_response.demand_code_rd.l3_hit_e.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080040004 offcore_response.demand_code_rd.l3_hit_m.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040020004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000040001 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080040001 Counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ Cycles with less than 2 uops delivered by the front-end umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C408000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC4008000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFC400004 offcore_response.demand_rfo.l4_hit_local_l4.snoop_non_dram umask=0x40,period=2000003,event=0xa6 A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled Spec update: SKL091, SKL044 (Must be precise) umask=0x1,period=100003,event=0xe6 min( 1 , uops_issued.any / ( (uops_retired.retire_slots / inst_retired.any) * 64 * ( icache_64b.iftag_hit + icache_64b.iftag_miss ) / 4.1 ) ) arb@event\=0x80\,umask\=0x2@ / arb@event\=0x80\,umask\=0x2\,thresh\=1@ Counts demand data loads that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB) Counts the number of request from the L2 that were not accepted into the XQ offcore_response.any_code_rd.l2_miss.hit_other_core_no_fwd Counts any code reads (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Counts any code reads (demand & prefetch) that have any response type umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400000040 offcore_response.demand_rfo.l2_miss.snoop_miss This event counts every cycle when a I-side (walks due to an instruction fetch) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0040 Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores umask=0x1,period=2000000,event=0x60 REQUEST = ANY_DATA read and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HIT REQUEST = ANY_REQUEST and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = ANY RFO and RESPONSE = IO_CSR_MMIO REQUEST = CORE_WB and RESPONSE = IO_CSR_MMIO REQUEST = DEMAND_DATA and RESPONSE = REMOTE_CACHE_HITM REQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_CACHE umask=0x1,period=100000,event=0xb7,offcore_rsp=0xff04 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f80 REQUEST = OTHER and RESPONSE = ANY_LOCATION REQUEST = PF_DATA and RESPONSE = IO_CSR_MMIO REQUEST = ANY_DATA read and RESPONSE = ANY_DRAM AND REMOTE_FWD umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3044 offcore_response.corewb.other_local_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0xf870 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5808 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2704 Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines can be either in modified state or clean state. Modified lines may either be written back to L3 or directly written to memory and not allocated in L3. Clean lines may either be allocated in L3 or dropped umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010490 offcore_response.all_data_rd.l3_hit.no_snoop_needed offcore_response.demand_data_rd.l3_hit.snoop_hit_with_fwd offcore_response.demand_data_rd.l3_miss.remote_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063FC00001 offcore_response.demand_code_rd.l3_miss.remote_hitm offcore_response.pf_l2_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0604000020 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063FC00080 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0604000100 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063B800400 umask=0x40,period=200003,event=0x28 DRAM Underfill Read CAS Commands issued. Unit: uncore_imc PCI Express bandwidth reading at IIO, part 1. Unit: uncore_iio umask=0x01,event=0x5f umask=0x04,event=0x5c Counts when a a transaction with the opcode type RspSFwd Snoop Response was received which indicates a remote caching agent forwarded the data but held on to its current copy. This is common for data and code reads that hit in a remote socket in E (Exclusive) or F (Forward) state Rsp*Fwd*WB Snoop Responses Received. Unit: uncore_cha unc_iio_clockticks Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.mem_read.part1 umask=0x2,event=0x2e unc_m2m_imc_writes.partial event=0x21 Protocol header and credit FLITs received from any slot. Unit: uncore_upi ll Counts protocol header and credit FLITs (80 bit FLow control unITs) received from any of the 3 UPI slots on this UPI unit This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD period=50021,umask=0x4,event=0xd1 offcore_response.pf_l3_data_rd.l3_hit_m.snoop_none This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0400 offcore_response.all_pf_data_rd.pmm_hit_local_pmm.snoop_not_needed This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP offcore_response.all_rfo.supplier_none.no_snoop_needed offcore_response.demand_data_rd.l3_hit_m.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000028000 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100002 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400002 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_MISS This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200001 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0002 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED offcore_response.demand_code_rd.l3_hit.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0004 offcore_response.pf_l2_data_rd.pmm_hit_local_pmm.snoop_not_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100490 offcore_response.all_reads.l3_hit.no_snoop_needed This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100080 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100004 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080020 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040491 offcore_response.demand_rfo.supplier_none.hitm_other_core cmask=1,period=2000003,umask=0x1,event=0x48 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0120 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01000807F7 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE offcore_response.pf_l3_data_rd.l3_hit_m.hit_other_core_fwd offcore_response.pf_l3_rfo.l3_hit_m.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020001 This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040080 offcore_response.pf_l2_data_rd.l3_hit_e.no_snoop_needed offcore_response.demand_data_rd.l3_hit_s.hit_other_core_fwd This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100004 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE offcore_response.demand_rfo.l3_hit_e.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200490 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0491 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100122 PMM_Read_BW Retired instructions that are fetched after an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall (Precise event) period=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800491 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000490 ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.any_snoop ocr.pf_l3_data_rd.l3_miss_local_dram.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000002 offcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.snoop_none This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000080 ALL_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS ocr.all_reads.l3_miss_local_dram.any_snoop This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP ocr.demand_rfo.l3_miss_local_dram.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404008000 ocr.demand_data_rd.l3_miss_local_dram.snoop_miss This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.any_snoop ocr.demand_rfo.l3_miss_local_dram.snoop_miss offcore_response.all_pf_rfo.l3_miss.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000001 ocr.pf_l2_rfo.l3_miss.no_snoop_needed ALL_PF_RFO & L3_MISS_LOCAL_DRAM & NO_SNOOP_NEEDED offcore_response.all_pf_data_rd.l3_miss.hit_other_core_fwd period=2000003,umask=0x80,event=0xc9 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000490 ALL_PF_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000100 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000080 This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000010 ocr.demand_data_rd.l3_miss.remote_hitm period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00120 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD cmask=2,period=2000003,umask=0x2,event=0xa3 Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS & HIT_OTHER_CORE_NO_FWD ALL_RFO & L3_MISS_LOCAL_DRAM & ANY_SNOOP Counts demand data reads DEMAND_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_FWD offcore_response.all_reads.l3_miss_local_dram.hit_other_core_no_fwd ocr.all_rfo.l3_miss_remote_hop1_dram.snoop_none Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_FWD ALL_DATA_RD & L3_MISS & HIT_OTHER_CORE_FWD Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS & ANY_SNOOP Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS_REMOTE_HOP1_DRAM & HITM_OTHER_CORE ocr.all_rfo.supplier_none.snoop_miss ocr.demand_rfo.l3_hit_s.snoop_none ocr.other.pmm_hit_local_pmm.any_snoop ocr.demand_data_rd.l3_hit_f.snoop_miss ocr.other.l3_hit.snoop_miss ocr.other.l3_hit_e.hit_other_core_fwd ocr.all_pf_data_rd.supplier_none.hit_other_core_fwd ocr.all_reads.l3_hit_e.any_snoop ALL_PF_DATA_RD & SUPPLIER_NONE & SNOOP_NONE ocr.demand_code_rd.l3_hit_m.hit_other_core_no_fwd ocr.demand_data_rd.l3_hit_f.snoop_none Counts all demand code reads DEMAND_CODE_RD & L3_HIT_F & ANY_SNOOP ocr.pf_l3_rfo.l3_hit_f.hitm_other_core Counts demand data reads DEMAND_DATA_RD & L3_HIT_M & ANY_SNOOP ocr.other.pmm_hit_local_pmm.snoop_none Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_M & ANY_SNOOP Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_M & HITM_OTHER_CORE Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & PMM_HIT_LOCAL_PMM & SNOOP_NONE ocr.pf_l3_rfo.l3_hit_e.snoop_none ocr.all_reads.supplier_none.no_snoop_needed Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_S & HIT_OTHER_CORE_NO_FWD ocr.demand_rfo.l3_hit_s.any_snoop ocr.all_pf_rfo.l3_hit.snoop_hit_with_fwd ocr.pf_l2_data_rd.l3_hit_m.snoop_miss ocr.demand_code_rd.l3_hit_f.snoop_none ocr.pf_l3_rfo.l3_hit_s.hit_other_core_fwd ocr.pf_l3_rfo.l3_hit_e.any_snoop ocr.pf_l2_rfo.supplier_none.snoop_miss Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT & HITM_OTHER_CORE ALL_PF_RFO & SUPPLIER_NONE & HIT_OTHER_CORE_FWD ocr.other.l3_hit_f.hit_other_core_no_fwd Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_E & HIT_OTHER_CORE_NO_FWD ocr.pf_l2_rfo.l3_hit_m.no_snoop_needed cmask=1,inv=1,period=2000003,umask=0x2,event=0xb1 period=2000003,umask=0x40,event=0xa6 Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to Mixing Intel AVX and Intel SSE Code section of the Optimization Guide event=0xe3 Ingress (from CMS) Allocations; IRQ. Unit: uncore_cha Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0. Unit: uncore_iio unc_iio_data_req_by_cpu.peer_write.part2 Counts every peer to peer read request for 4 bytes of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus Counts every peer to peer write request of 4 bytes of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part2. Unit: uncore_iio Peer to peer write request of up to a 64 byte transaction is made by IIO Part2 to an IIO target. Unit: uncore_iio unc_m2m_imc_reads.to_pmm BL Ingress (from CMS) Allocations. Unit: uncore_m2m period=2000003,umask=0x10,event=0x49 Counts Software prefetch requests that miss the L2 cache. This event accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions umask=0x2,period=2000003,cmask=1,edge=1,event=0x48 Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 RANGE FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element idq.mite_cycles_any umask=0x1,period=100007,event=0xc6,frontend=0x500206 Counts Unfriendly TSX abort triggered by a nest count that is too deep Number of times an HLE execution successfully committed Supports address when precise inv=1,umask=0x1,period=2000003,cmask=1,edge=1,event=0x5e uops_dispatched.port_0 Counts the number of uops executed from any thread All mispredicted branch instructions retired Supports address when precise (Precise event) Number of near branch instructions retired that were mispredicted and taken Supports address when precise (Precise event) umask=0x2,period=2000003,event=0xec Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB) Counts cacheable memory requests that access the Last Level Cache. Requests include Demand Loads, Reads for Ownership(RFO), Instruction fetches and L1 HW prefetches. If the platform has an L3 cache, last level cache is the L3, otherwise it is the L2 Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1 TOR Inserts; Data read opt prefetch from local IA that misses in the snoop filter umask=0xC887FE01,event=0x35 event=0x91 Decoder Overrides Existing Branch Prediction (speculative) umask=0x10,event=0x60 All L2 Cache Requests (Breakdown 2 - Rare). Bus lock response umask=0x4,event=0x63 umask=0x20,event=0x64 event=0x1d0 umask=0x2E,event=0x8b umask=0x4E,event=0x8b df_ccm_reqa.node5.wrsizedfullzero umask=0x2A,event=0x8b umask=0x45,event=0x8b umask=0xCC,event=0x8c umask=0xAB,event=0x8c umask=0xCB,event=0x8c umask=0xE9,event=0x8c umask=0x67,event=0x8c df_ccm_reqb.node2.wrsizedncposted umask=0x02,event=0x8d umask=0xCC,event=0x108 umask=0x0B,event=0x108 df_ioms_reqa.node3.ios_resp df_ioms_reqa.node7.ios_resp umask=0xC8,event=0x108 df_ioms_reqa.node4.anyatomic df_ioms_reqa.node5.anywrsized>32band<64b umask=0x82,event=0x108 df_ioms_reqa.node6.largeread df_ioms_reqb.node7.pieiorequest umask=0xAC,event=0x109 df_ioms_reqb.node3.ioanynon-postedwrsized>32band<64b umask=0xC9,event=0x109 umask=0xE9,event=0x109 df_ioms_reqb.node2.ioanynon-postedwrsized=32b umask=0x81,event=0x109 umask=0xE1,event=0x109 umask=0x4,event=0x3 l3_request_g1.t3.s0.wrsizednc l3_request_g1.t3.s1.wrsizednc l3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x02,event=0x1 l3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x02,event=0x1 l3_request_g1.t0.s2.wrsized l3_request_g1.t7.s3.wrsized l3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x20,event=0x1 l3_request_g1.t0.s2.rdsizednc l3_request_g1.t4.s2.rdsized l3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x40,event=0x1 l3_request_g1.t6.s2.rdsized l3_request_g1.t3.s0.caching l3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x80,event=0x1 l3fillvicreq.t2.s2.vicblk l3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x01,event=0x3 l3fillvicreq.t3.s1.chgtox l3fillvicreq.t3.s0.rdblkc_s_vic l3fillvicreq.t0.s1.rdblkc_s_vic l3fillvicreq.t2.s2.rdblkc_s_vic l3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x04,event=0x3 l3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x04,event=0x3 l3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x08,event=0x3 l3fillvicreq.t7.s3.rdblkc_s l3fillvicreq.t1.s1.rdblkx_vic l3fillvicreq.t1.s0.rdblkl_vic l3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x40,event=0x3 l3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x40,event=0x3 l3fillvicreq.t0.s3.rdblkl_vic l3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x80,event=0x3 l3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x80,event=0x3 l3fillvicreq.t6.s1.rdblkl l3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x80,event=0x3 l3fillvicreq.t4.s3.rdblkl l3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x80,event=0x3 l3victimstate.t0.s0.none_nol3victimline l3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x04,event=0x9 l3victimstate.t5.s3.f_s l3victimstate.t2.s0.o l3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x40,event=0x9 l3victimstate.t6.s1.d l3victimstate.t4.s2.d l3victimstate.t3.s0.od umask=0x8,event=0x41 L1 DTLB Miss of a page of 4K size ls_inef_sw_pref.mab_mch_cnt Floating Point Dispatch Faults. YMM spill fault umask=0x40,event=0x43 Demand Data Cache Fills by Data Source. DRAM or IO from different die Demand Data Cache Fills by Data Source. DRAM or IO from this thread's die ls_refills_from_sys.ls_mabresp_lcl_cache ls_hw_pf_dc_fill.ls_mabresp_rmt_dram de_dis_dispatch_token_stalls0.sc_agu_dispatch_stall CPU_CLK_UNHALTED_REF FR_NUMBER_OF_BREAKPOINTS_FOR_DR3 PMNC_SW_INCR MEM_WRITE SOFTWARE_JAVA_BYTECODE DMB L1D_TLB_REFILL BR_MIS_PRED BUS_ACCESS_NORMAL STALL_FRONTEND L1D_CACHE_REFILL_INNER L2CACHE_READ_HIT TAGCACHE_WRITE_HIT TAGCACHEMASTER_READ_REQ JTLB_DMISS STORE_COND_COMPLETED REQUEST_LATENCY ICACHE_MISSES AGEN_NO_ISSUES_CYCLES WBB_OVER_50_FULL FPU_INSNS ALU_DSP_SATURATION_INSNS SISSUE II ITLB MTVRSAVE_INSTR_COMPLETED LSU_INSTR_COMPLETED VR_STALLS MISPREDICTED_BRANCHES L3_INSTR_CACHE_MISSES MARKED_STORE_COMPLETED FXU0_IDLE_FXU1_BUSY PMC0_OVERFLOW FPU_DENORM_INPUT_CYCLES add-pipe-excluding-junk-ops ic-fill page-hit %s: %s
pmu: %s
LONGEST_LAT_CACHE.MISS %s, "tid": "%d"}
GenuineIntel-6-56 inst_retired.any / cpu_clk_unhalted.thread Average CPU Utilization C3 residency percent per core C6_Core_Residency (cstate_core@c7\-residency@ / msr@tsc@) * 100 This event counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted RFO requests to L2 cache umask=0x42,period=100003,event=0xd0 umask=0x7,period=100003,event=0xf1 umask=0x15,period=2000006,event=0xc7 fp_arith_inst_retired.single umask=0x3c,period=2000004,event=0xc7 This event counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end. It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty umask=0x10,period=2000003,event=0x79 Cycles MITE is delivering 4 Uops This event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit) Cycles with less than 3 uops delivered by the front end Number of times we entered an HLE region
does not count nested transactions Number of times HLE abort was triggered (PEBS) (Precise event) Number of times an HLE execution aborted due to HLE-unfriendly instructions cpl_cycles.ring0_trans This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events umask=0x3,period=2000003,event=0 Not software-prefetch load dispatches that hit FB allocated for hardware prefetch This event counts taken speculative and retired indirect branches excluding calls and return branches br_inst_exec.taken_indirect_near_call umask=0xd0,period=200003,event=0x88 br_misp_exec.all_branches uops_executed_port.port_3 uops_executed_port.port_4_core Cycles stalled due to re-order buffer full umask=0x5,cmask=5,period=2000003,event=0xa3 cycle_activity.stalls_mem_any cycle_activity.stalls_l1d_pending uops_retired.retire_slots This is a precise version (that is, uses PEBS) of the event that counts the number of retirement slots used (Precise event) br_misp_retired.conditional This event counts cases of saving new LBR records by hardware. This assumes proper enabling of LBRs and takes into account LBR filtering done by the LBR_SELECT register MMIO writes. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox llc_misses.data_llc_prefetch llc_references.code_llc_prefetch llc_references.streaming_partial umask=0x1,event=0x35,filter_opc=0x19e PCIe read current. Derived from unc_c_tor_inserts.opcode. Unit: uncore_cbox unc_h_requests.writes Pre-charge for writes. Unit: uncore_imc dtlb_store_misses.walk_duration ept.walk_cycles umask=0x10,period=2000003,event=0x4f page_walker_loads.itlb_l2 umask=0x22,period=2000003,event=0xbc ( uops_issued.any - uops_retired.retire_slots + 4 * (( int_misc.recovery_cycles_any / 2 )) ) / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) ))) This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. SMT version; use when SMT is enabled and measuring per logical CPU inst_retired.any / br_inst_retired.near_taken Branches;Fetch_BW;PGO Rough Estimation of fraction of fetched lines bytes that were likely (includes speculatively fetches) consumed by program instructions Instructions per Load (lower number means higher occurance rate) inst_retired.any / br_misp_retired.all_branches 64 * l1d.replacement / 1000000000 / duration_time L2 cache misses per kilo instruction for all request types (including speculative) 1000 * l2_rqsts.miss / inst_retired.any L2HPKI_All umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020001 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0010 offcore_response.pf_l2_data_rd.l3_hit.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0010 offcore_response.pf_l2_data_rd.l3_hit.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020020 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0020 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0040 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0040 offcore_response.pf_l3_data_rd.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0100 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200028000 offcore_response.all_pf_data_rd.l3_hit.snoop_hitm offcore_response.all_data_rd.supplier_none.snoop_none Number of transitions from legacy SSE to AVX-256 when penalty applicable (Precise Event) Spec update: BDM30 SSE* FP micro-code assist when output value is invalid. (Precise Event) umask=0x18,period=2000003,cmask=1,event=0x79 Counts randomly selected loads with latency value being above 32 Spec update: BDM100, BDM35 (Must be precise) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0001 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000004 offcore_response.corewb.l3_miss_local_dram.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000010 offcore_response.pf_l2_data_rd.l3_miss.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000040 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000040 offcore_response.pf_l3_code_rd.l3_miss.snoop_hit_no_fwd offcore_response.all_pf_code_rd.l3_hit.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000240 offcore_response.all_data_rd.l3_miss_local_dram.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000091 Number of cycles using always true condition applied to PEBS uops retired event (Precise event) This is a precise version (that is, uses PEBS) of the event that counts far branch instructions retired Spec update: BDW98 umask=0x44,event=0x22 L3 Lookup read request that access cache and found line in M-state Socket actual clocks when any core is active on that socket This event counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault Supports address when precise (Precise event) Retired load uops with locked access Supports address when precise. Spec update: BDM35 (Precise event) This event counts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting excludes unknown and UC data source Supports address when precise (Precise event) l2_ifetch.self.e_state l2_ld.self.any.mesi umask=0x48,period=200000,event=0x2b umask=0x4f,period=200000,event=0x2d l2_reject_busq.self.demand.s_state umask=0x83,period=2000000,event=0x40 l1d_cache.replm umask=0x0,period=2000000,event=0xcf prefetch.prefetcht2 bus_request_outstanding.all_agents Number of Bus Not Ready signals asserted bus_drdy_clocks.all_agents umask=0x20,period=200000,event=0x62 umask=0x40,period=200000,event=0x64 umask=0xe0,period=200000,event=0x67 bus_trans_pwr.all_agents bus_trans_burst.self bus_hit_drv.all_agents cpu_clk_unhalted.ref br_inst_type_retired.cond_taken br_inst_retired.pred_not_taken br_inst_retired.taken L0 DTLB misses due to store operations Load uops retired that hit L2 (Precise event capable) Supports address when precise (Must be precise) Counts load uops retired that miss the L1 data cache Supports address when precise (Must be precise) offcore_response.any_read.l2_miss.snoop_miss_or_no_snoop_needed umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400000022 Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required offcore_response.any_request.l2_miss.hit_other_core_no_fwd offcore_response.any_request.l2_miss.snoop_miss_or_no_snoop_needed Counts requests to the uncore subsystem that true miss for the L2 cache with a snoop miss in the other processor module Counts partial cache line data writes to uncacheable write combining (USWC) memory region that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l1_data_rd.l2_miss.snoop_miss_or_no_snoop_needed offcore_response.sw_prefetch.l2_miss.hit_other_core_no_fwd Counts data cache lines requests by software prefetch instructions that hit the L2 cache offcore_response.pf_l2_rfo.l2_miss.any umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000000020 Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that are outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_data_rd.l2_miss.any Counts hardware interrupts received by the processor Cycles hardware interrupts are masked Counts branch instructions retired for all branch types. This is an architectural performance event (Must be precise) br_inst_retired.rel_call Counts core cycles if either divide unit is busy Counts demand cacheable data reads of full cache lines miss the L2 cache with a snoop hit in the other processor module, data forwarding is required umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010010 Counts data cacheline reads generated by hardware L2 cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cache lines requests by software prefetch instructions outstanding, per cycle, from the time of the L2 miss to when any response is received Counts any data writes to uncacheable write combining (USWC) memory region hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) machine_clears.page_fault dtlb_store_misses.walk_completed_1gb Counts once per cycle for each page walk only while traversing the Extended Page Table (EPT), and does not count during the rest of the translation. The EPT is used for translating Guest-Physical Addresses to Physical Addresses for Virtual Machine Monitors (VMMs). Average cycles per walk can be calculated by dividing the count by number of walks Counts all L2 HW prefetcher requests that missed L2 This event counts when new data lines are brought into the L1 Data cache, which cause other lines to be evicted from the cache Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore Spec update: HSD62, HSD61 Demand Data Read requests sent to uncore Spec update: HSD78 hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded offcore_response.all_reads.l3_hit.hit_other_core_no_fwd offcore_response.pf_l2_code_rd.l3_hit.any_response offcore_response.demand_data_rd.l3_hit.hitm_other_core Counts demand data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded ( itlb_misses.walk_duration + dtlb_load_misses.walk_duration + dtlb_store_misses.walk_duration ) / (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00091 This event counts the number of uops issued by the Front-end of the pipeline to the Back-end. This event is counted at the allocation stage and will count both retired and non-retired uops Cycles per core when uops are executed in port 4 Cycles with pending L2 cache miss loads Spec update: HSD78 Cycles with pending L2 miss loads. Set Cmask=2 to count cycle Spec update: HSD78 Number of loads missed L2 Mispredicted branch instructions at retirement Unit: uncore_cbox L3 Lookup external snoop request that access cache and found line in M-state umask=0x46,event=0x34 Retired load uops misses in L1 cache as data sources Supports address when precise. Spec update: HSM30 (Precise event) Retired load uops which data sources were hits in L3 without snoops required Supports address when precise. Spec update: HSD74, HSD29, HSD25, HSM26, HSM30 (Precise event) umask=0x4,period=100003,event=0xd3 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00004 inv=1,umask=0x1,any=1,cmask=1,period=2000003,event=0xc2 l2_lines_out.pf_clean fp_comp_ops_exe.x87 Number of DSB to MITE switches ivb metrics 1000 * mem_load_uops_retired.llc_miss / inst_retired.any umask=0x3,edge=1,period=2000003,cmask=1,event=0xd LLC lookup request that access cache and found line in I-state umask=0x06,event=0x34 Misses in all TLB levels that caused page walk completed of any size by demand loads Counts demand data reads that hit in the LLC and sibling core snoop returned a clean response unc_q_txl_flits_g0.data Read requests to memory controller. Derived from unc_m_cas_count.rd. Unit: uncore_imc (unc_p_freq_band0_cycles / unc_p_clockticks) * 100. Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. (filter_band2=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Unit: uncore_pcu unc_p_freq_band0_transitions (unc_p_freq_ge_2000mhz_cycles / unc_p_clockticks) * 100. event=0xd,filter_band2=30 Counts the number of times that the uncore transitioned to a frequency greater than or equal to 1.2Ghz. Derived from unc_p_freq_band0_cycles. Unit: uncore_pcu This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K) (Precise event) Retired load uops which data sources were data hits in LLC without snoops required Number of AVX-256 Computational FP double precision uops issued this cycle partial_rat_stalls.flags_merge_uop br_misp_retired.not_taken Uops dispatched per thread umask=0x1,period=100007,event=0xb7,offcore_rsp=0x00000132f7 offcore_response.any_data_rd.l2_hit_near_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000088000 Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state Counts L2 code HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0 Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002001000 offcore_response.any_data_rd.l2_hit_this_tile_s umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000004 offcore_response.uc_code_reads.l2_hit_this_tile_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010001000 Counts Demand code reads and prefetch code read requests that accounts for responses which hit its own tile's L2 with data in F state offcore_response.pf_l2_code_rd.l2_hit_near_tile offcore_response.partial_reads.l2_hit_near_tile offcore_response.partial_writes.l2_hit_far_tile Counts the number of times the machine clears due to memory ordering hazards offcore_response.any_pf_l2.ddr_far Counts any Prefetch requests that accounts for data responses from DRAM Far Counts any request that accounts for data responses from DRAM Far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080808000 Counts L1 data HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far offcore_response.pf_software.mcdram_far offcore_response.bus_locks.ddr_near offcore_response.pf_l2_code_rd.ddr_near umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400020 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180600400 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180608000 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180600022 offcore_response.any_code_rd.mcdram offcore_response.pf_l2_rfo.ddr l1d_all_ref.any L1 data cacheable reads and writes l1d_cache_ld.e_state umask=0x10,period=200000,event=0x26 L2 lines allocated in the S state All L2 misses umask=0x1,period=100000,event=0x27 L2 demand store RFOs in M state mem_uncore_retired.other_core_l2_hitm Cacheable loads delayed with L1D block code mem_inst_retired.latency_above_threshold_256 umask=0x10,period=200,event=0xb,ldlat=0x200 Offcore data reads satisfied by the IO, CSR, MMIO unit All offcore RFO requests offcore_response.any_rfo.remote_cache_hitm offcore_response.corewb.local_cache Offcore writebacks that HITM in a remote cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x277 offcore_response.data_ifetch.llc_hit_other_core_hitm Offcore code or data read requests satisfied by the LLC offcore_response.data_ifetch.remote_cache Offcore code or data read requests satisfied by a remote cache Offcore code or data read requests that HITM in a remote cache offcore_response.demand_data.local_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x101 offcore_response.other.any_cache_dram offcore_response.other.io_csr_mmio offcore_response.pf_data.io_csr_mmio Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4710 offcore_response.pf_ifetch.local_cache Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4770 Transitions from Floating Point to MMX instructions simd_int_64.packed_shift umask=0x1,period=100000,event=0xb7,offcore_rsp=0x40FF offcore_response.any_request.remote_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x6008 Offcore code or data read requests satisfied by any DRAM Offcore code or data read requests satisfied by a remote DRAM Offcore demand data requests satisfied by the local DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0x6002 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x6010 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4040 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4020 umask=0x1,period=2000000,event=0x6c umask=0x1,period=2000000,event=0xf6 BACLEAR asserted, regardless of cause umask=0x10,period=2000,event=0x89 cpu_clk_unhalted.ref_p Length Change Prefix stall cycles FPU control word write stall cycles Cycles Uops executed on ports 0-4 (core count) Uops executed on port 0 Uops executed on port 3 (core count) Counts L2 cache hits when fetching instructions, code reads Counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS mem_inst_retired.lock_loads mem_inst_retired.split_stores Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source Supports address when precise (Precise event) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000088000 offcore_response.demand_code_rd.l3_hit_s.any_snoop offcore_response.demand_code_rd.l3_hit_m.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080040002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00801C0001 offcore_response.demand_data_rd.l3_hit_e.snoop_miss offcore_response.demand_data_rd.l3_hit_m.snoop_hitm offcore_response.demand_data_rd.l3_hit_m.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100040001 umask=0x1,period=100007,event=0xc6,frontend=0x410006 offcore_requests.l3_miss_demand_data_rd Counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:a. memory disambiguation,b. external snoop, orc. cross SMT-HW-thread snoop (stores) hitting load buffer Spec update: SKL089 Number of times HLE abort was triggered. (PEBS) (Precise event) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20001C8000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C400002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C400001 Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events cpu_clk_unhalted.ring0_trans Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty inv=1,umask=0x2,period=2000003,cmask=1,event=0xb1 offcore_response.any_code_rd.l2_miss.any Counts any code reads (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache Counts demand and DCU prefetch instruction cacheline that are are outstanding, per cycle, from the time of the L2 miss to when any response is received This event counts the number of instructions that retire execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers This event counts the number of instructions that retire. For instructions that consist of multiple micro-ops, this event counts exactly once, as the last micro-op of the instruction retires. The event continues counting while instructions retire, including during interrupt service routines caused by hardware interrupts, faults or traps. Background: Modern microprocessors employ extensive pipelining and speculative techniques. Since sometimes an instruction is started but never completed, the notion of "retirement" is introduced. A retired instruction is one that commits its states. Or stated differently, an instruction might be abandoned at some point. No instruction is truly finished until it retires. This counter measures the number of completed instructions. The fixed event is INST_RETIRED.ANY and the programmable event is INST_RETIRED.ANY_P Retired store uops that miss the STLB. (Precise Event - PEBS) (Precise event) This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a non-modified state. (Precise Event - PEBS) (Precise event) Retired load uops which data sources were hits in LLC without snoops required. (Precise Event - PEBS) (Precise event) offcore_response.all_pf_code_rd.llc_hit.no_snoop_needed Counts prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean response Counts all prefetch RFOs that hit in the LLC umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0122 offcore_response.pf_l2_rfo.llc_hit.snoop_miss Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded offcore_response.pf_llc_code_rd.llc_hit.no_snoop_needed Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops sent to sibling cores return clean response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0100 REQUEST = PF_LLC_DATA_RD and RESPONSE = ANY_RESPONSE Counts all demand & prefetch RFOs that miss the LLC and the data returned from dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400010 Cycles offcore reads busy Cycles offcore demand code read busy REQUEST = ANY_DATA read and RESPONSE = ANY_CACHE_DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0x10ff umask=0x1,period=100000,event=0xb7,offcore_rsp=0xff22 REQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM REQUEST = DEMAND_DATA and RESPONSE = ANY_LOCATION REQUEST = DEMAND_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5004 REQUEST = PF_DATA and RESPONSE = LLC_HIT_NO_OTHER_CORE umask=0x1,period=100000,event=0xb7,offcore_rsp=0x750 REQUEST = PF_RFO and RESPONSE = LOCAL_CACHE umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5070 REQUEST = DEMAND_DATA and RESPONSE = ANY_LLC_MISS offcore_response.demand_ifetch.any_dram_and_remote_fwd REQUEST = PF_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD dtlb_load_misses.large_walk_completed offcore_response.demand_code_rd.l3_miss.remote_hit_forward umask=0x1,period=100003,event=0xb7,offcore_rsp=0x103FC00010 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBC000020 offcore_response.all_pf_data_rd.l3_miss.remote_hitm core_snoop_response.rsp_ihitfse Streaming stores (full cache line). Derived from unc_cha_tor_inserts.ia_miss. Unit: uncore_cha LLC_MISSES.PCIE_WRITE fc_mask=0x07,ch_mask=0x04,umask=0x01,event=0x83 CHA to iMC Full Line Writes Issued; Full Line Non-ISOCH. Unit: uncore_cha Counts when a normal (Non-Isochronous) full line write is issued from the CHA to the any of the memory controller channels Counts when a transaction with the opcode type RspI Snoop Response was received which indicates the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO: the Read for Ownership issued before a write hits non-modified data) RspSFwd Snoop Responses Received. Unit: uncore_cha Read request for 4 bytes made by the CPU to IIO Part0. Unit: uncore_iio Read request for 4 bytes made by the CPU to IIO Part3. Unit: uncore_iio Write request of 4 bytes made to IIO Part0 by the CPU. Unit: uncore_iio Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus fc_mask=0x07,ch_mask=0x02,umask=0x01,event=0xc1 fc_mask=0x07,ch_mask=0x08,umask=0x04,event=0x84 Counts every write request of up to a 64 byte transaction of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_m2m_directory_lookup.state_i unc_m2m_directory_update.a2s Prefecth requests that got turn into a demand request. Unit: uncore_m2m Data Response packets that go direct to core. Unit: uncore_upi ll Counts incoming FLITs (FLow control unITs) which bypassed the slot1 RxQ buffer (Receive Queue) and passed directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) received from any of the 3 Intel Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unit This event is deprecated. Refer to new event OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080080 offcore_response.pf_l2_rfo.l3_hit_m.hit_other_core_fwd This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100400 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200020 offcore_response.all_data_rd.l3_hit_m.snoop_miss offcore_response.all_pf_rfo.l3_hit_f.hitm_other_core offcore_response.all_reads.l3_hit_s.snoop_miss offcore_response.pf_l3_data_rd.pmm_hit_local_pmm.snoop_none This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE period=100003,umask=0x1,event=0xb7 offcore_response.pf_l2_rfo.l3_hit_f.snoop_miss offcore_response.pf_l3_data_rd.l3_hit_m.snoop_miss This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400400 offcore_response.pf_l1d_and_sw.l3_hit_m.snoop_miss This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE offcore_response.pf_l2_data_rd.l3_hit_m.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200080 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0100 offcore_response.pf_l3_rfo.supplier_none.hitm_other_core offcore_response.pf_l2_data_rd.l3_hit_e.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080010 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400108000 offcore_response.demand_data_rd.l3_hit_f.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080010 offcore_response.pf_l2_rfo.l3_hit_s.hit_other_core_fwd offcore_response.all_pf_data_rd.l3_hit_f.hit_other_core_no_fwd offcore_response.all_reads.l3_hit_e.hitm_other_core This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED offcore_response.pf_l1d_and_sw.l3_hit_e.hitm_other_core This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200004 offcore_response.all_data_rd.l3_hit_s.hitm_other_core offcore_response.all_data_rd.l3_hit_e.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01000407F7 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080120 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040100 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100491 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_NONE This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD offcore_response.all_reads.l3_hit_f.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020020 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0080 period=100007,umask=0x21,event=0xd0 offcore_response.pf_l3_rfo.l3_hit_e.hitm_other_core offcore_response.all_data_rd.supplier_none.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_MISS offcore_response.pf_l2_data_rd.l3_hit_e.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080010 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400120 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020001 offcore_response.pf_l2_rfo.l3_hit_m.no_snoop_needed offcore_response.pf_l3_data_rd.l3_hit_m.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080010 This event is deprecated. Refer to new event OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP offcore_response.demand_data_rd.l3_hit_f.hitm_other_core This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C07F7 offcore_response.demand_code_rd.l3_hit_f.hit_other_core_fwd offcore_response.all_pf_data_rd.l3_hit_s.any_snoop offcore_response.all_pf_rfo.l3_hit_f.any_snoop This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0490 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04000807F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.ANY_SNOOP This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD Retired instructions that are fetched after an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall (Precise event) period=100007,umask=0x1,event=0xc6,frontend=0x400806 ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed offcore_response.demand_rfo.l3_miss.no_snoop_needed ocr.all_reads.l3_miss_remote_hop1_dram.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000490 offcore_response.pf_l2_data_rd.l3_miss_local_dram.no_snoop_needed ocr.other.l3_miss_remote_hop1_dram.no_snoop_needed offcore_response.all_pf_rfo.l3_miss_local_dram.hitm_other_core ALL_DATA_RD & L3_MISS & ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000010 ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd offcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.snoop_miss ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000100 ocr.demand_rfo.l3_miss.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS_LOCAL_DRAM & HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED ocr.all_data_rd.l3_miss_local_dram.snoop_none This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD ocr.demand_rfo.l3_miss_remote_hop1_dram.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000001 ocr.all_rfo.l3_miss.snoop_miss This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE offcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed ocr.demand_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD ocr.pf_l2_rfo.l3_miss.any_snoop offcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.snoop_miss ocr.pf_l2_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd offcore_response.pf_l2_rfo.l3_miss.no_snoop_needed This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00120 offcore_response.other.l3_miss.remote_hit_forward Counts all demand code reads DEMAND_CODE_RD & L3_MISS & HIT_OTHER_CORE_NO_FWD ALL_PF_RFO & L3_MISS_LOCAL_DRAM & SNOOP_NONE ocr.demand_code_rd.l3_miss.remote_hitm Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS_REMOTE_HOP1_DRAM & ANY_SNOOP ALL_PF_RFO & L3_MISS & REMOTE_HITM ocr.all_reads.l3_miss_local_dram.snoop_none ALL_DATA_RD & L3_HIT & SNOOP_HIT_WITH_FWD ocr.all_reads.l3_hit_m.hit_other_core_fwd ocr.demand_data_rd.l3_hit_s.no_snoop_needed ocr.all_data_rd.l3_hit_s.hitm_other_core ocr.pf_l1d_and_sw.pmm_hit_local_pmm.snoop_none ocr.demand_data_rd.supplier_none.no_snoop_needed ocr.all_rfo.l3_hit_m.any_snoop ocr.demand_code_rd.l3_hit_e.snoop_miss ocr.pf_l2_data_rd.pmm_hit_local_pmm.snoop_none ocr.pf_l2_rfo.supplier_none.snoop_none Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_F & HIT_OTHER_CORE_FWD ALL_RFO & L3_HIT_E & HIT_OTHER_CORE_NO_FWD Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_M & ANY_SNOOP ocr.pf_l2_rfo.l3_hit_e.any_snoop ocr.all_pf_rfo.l3_hit.no_snoop_needed ocr.demand_rfo.l3_hit_s.no_snoop_needed ocr.pf_l1d_and_sw.l3_hit_f.hit_other_core_fwd Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & PMM_HIT_LOCAL_PMM & ANY_SNOOP ALL_READS & L3_HIT_F & HITM_OTHER_CORE ocr.other.l3_hit_s.snoop_miss Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & PMM_HIT_LOCAL_PMM & ANY_SNOOP period=2000003,umask=0x4,event=0x32 ALL_DATA_RD & L3_HIT_M & HIT_OTHER_CORE_FWD ocr.all_reads.pmm_hit_local_pmm.snoop_none Counts demand data reads DEMAND_DATA_RD & L3_HIT & HITM_OTHER_CORE ocr.all_reads.l3_hit_e.hit_other_core_no_fwd period=2000003,umask=0x2,event=0x32 ALL_READS & L3_HIT_M & SNOOP_NONE ocr.demand_code_rd.supplier_none.any_snoop Counts any other requests OTHER & L3_HIT_F & ANY_SNOOP ocr.all_rfo.l3_hit_m.no_snoop_needed Counts all demand data writes (RFOs) DEMAND_RFO & PMM_HIT_LOCAL_PMM & ANY_SNOOP ocr.pf_l1d_and_sw.l3_hit.snoop_miss ocr.pf_l3_data_rd.l3_hit_s.snoop_miss Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & SUPPLIER_NONE & NO_SNOOP_NEEDED ocr.demand_code_rd.supplier_none.no_snoop_needed ALL_READS & L3_HIT_F & HIT_OTHER_CORE_NO_FWD Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_F & HIT_OTHER_CORE_NO_FWD ocr.pf_l3_rfo.l3_hit_f.snoop_none Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_M & ANY_SNOOP ALL_PF_RFO & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDED cmask=12,period=2000003,umask=0xc,event=0xa3 period=2000003,umask=0x4,event=0xa6 cmask=1,period=2000003,umask=0x2,event=0xb1 cmask=1,edge=1,period=100003,umask=0x1,event=0xc3 period=2000003,umask=0x2,event=0xb1 cmask=1,period=2000003,umask=0x1,event=0xa3 unc_m_pmm_rpq_occupancy.all umask=0x4,event=0xd3 umask=0x02,event=0x37 Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part3 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus fc_mask=0x07,ch_mask=0x02,umask=0x02,event=0x83 Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part0. Does not include requests made by the same IIO unit. In the general case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus fc_mask=0x07,ch_mask=0x02,umask=0x02,event=0xc1 Peer to peer read request of up to a 64 byte transaction is made by IIO Part0 to an IIO target. Unit: uncore_iio M2M Reads Issued to iMC; All, regardless of priority unc_m2m_tag_hit.nm_ufill_hit_dirty Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache Supports address when precise (Precise event) Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB) Speculatively counts the number Transactional Synchronization Extensions (TSX) Aborts due to a data capacity limitation for transactional writes Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt) Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the Top-down Microarchitecture Analysis method. This event is counted on a designated fixed counter (Fixed Counter 3) and is an architectural event Counts the number of PREFETCHW instructions executed Uops that RAT issues to RS umask=0x1,period=2000003,cmask=5,event=0xa8 Counts cycles when at least 1 micro-op is executed from any thread on physical core Counts requests to the Instruction Cache (ICache) for one or more bytes in a cache line and they do not hit in the ICache (miss) unc_m_pre_count.pgt Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 Counts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) and new translation was filled into the ITLB. The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLB umask=0x20,event=0x60 l2_request_g1.cacheable_ic_read umask=0x8,event=0x61 LS to L2 WCB close requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) close requests l2_fill_pending.l2_fill_busy Retired Near Returns df_ccm_reqa.node7.anydram umask=0x0D,event=0x8b umask=0x4C,event=0x8b umask=0xAC,event=0x8b umask=0xEB,event=0x8b umask=0x49,event=0x8b df_ccm_reqa.node0.specdramrd df_ccm_reqa.node0.rdvlkc Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdvlkc df_ccm_reqa.node7.rdvlkc umask=0x62,event=0x8b umask=0xC2,event=0x8b df_ccm_reqa.node6.rdvlkl umask=0x0D,event=0x8c df_ccm_reqb.node7.anyiorequest. umask=0x45,event=0x8c umask=0x23,event=0x8c umask=0x03,event=0x8d df_ccm_reqc.anybuslockrequest umask=0x6C,event=0x108 umask=0xCB,event=0x108 df_ioms_reqa.node0.fence df_ioms_reqa.node6.fence Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized<32b df_ioms_reqb.node0.pieinterrupt umask=0x4D,event=0x109 umask=0xAB,event=0x109 umask=0x28,event=0x109 umask=0xA7,event=0x109 df_ioms_reqb.node4.ioanypostedwrsized=64b Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized>32band<64b df_ioms_reqb.node0.iolargeread umask=0x61,event=0x109 Total number uOps assigned to all fpu pipes umask=0x7,event=0x2 fp_retx87_fp_ops.add_sub_ops umask=0xff,event=0x3 Number of Ops that are candidates for optimization (have Z-bit either set or pass) l3_request_g1.t6.s1.wrsizednc l3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x02,event=0x1 l3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x02,event=0x1 l3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x04,event=0x1 l3_request_g1.t4.s3.wrsized l3_request_g1.t6.s2.rdsizednc l3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x40,event=0x1 l3_request_g1.t6.s0.caching l3_request_g1.t5.s1.caching l3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x80,event=0x1 l3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x01,event=0x3 l3fillvicreq.t2.s3.vicblk l3fillvicreq.t4.s0.chgtox l3fillvicreq.t6.s1.chgtox l3fillvicreq.t1.s3.chgtox l3fillvicreq.t0.s3.rdblkc_s_vic l3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x10,event=0x3 l3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x10,event=0x3 l3fillvicreq.t4.s3.rdblkx_vic l3fillvicreq.t1.s1.rdblkl_vic l3fillvicreq.t5.s2.rdblkl_vic l3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x80,event=0x3 l3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x80,event=0x3 l3fillvicreq.t3.s3.rdblkl l3combclstrstate l3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x01,event=0x9 l3victimstate.t2.s1.nol3victimline l3victimstate.t4.s0.none_nol3victimline l3victimstate.t7.s1.none_nol3victimline l3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x02,event=0x9 l3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x04,event=0x9 l3victimstate.t6.s1.f_s l3victimstate.t5.s0.o l3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x08,event=0x9 l3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x10,event=0x9 l3victimstate.t1.s1.e_fe l3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x10,event=0x9 l3victimstate.t6.s0.m l3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x20,event=0x9 l3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x20,event=0x9 l3victimstate.t2.s3.m l3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x80,event=0x9 l3victimstate.t7.s0.od l3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x80,event=0x9 umask=0x01,event=0x41 umask=0x4,event=0x46 Total Page Table Walks DC Type 1 Software Prefetch Instructions (3DNow PREFETCHW instruction) Dispatched The number of software prefetches that did not fetch data outside of the processor core. Software PREFETCH instruction saw a DC hit bp_l1_tlb_fetch_hit.if2m l2_pf_miss_l2_l3 umask=0x4,event=0x85 Software Prefetch Instructions Dispatched (Speculative). See docAPM3 PREFETCHW ls_sw_pf_dc_fill.ls_mabresp_rmt_cache umask=0x10,event=0x5a Ops dispatched from either the decoders, OpCache or both DC_L1_DTLB_MISS_AND_L2_DTLB_HIT FR_RETIRED_NEAR_RETURNS_MISPREDICTED INSTR_SPEC L2_CACHE_MISS INSTR_CACHE_DEPENDENT_STALL MAIN_TLB_MISS_STALL PLE_CACHE_LINE_REQ_SKIPPED L1D_CACHE_REFILL L2D_CACHE_REFILL RC_ST_SPEC MEM_BYTE_WRITE MDU_STALL_CYCLES PDTRACE_BACK_STALLS IODQ_FULL_DR_STALLS ALU_NO_ISSUES_CYCLES BRANCH_LIKELY_INSNS SYSTEM_EVENT_6 LDQ_25_50_FULL ISSUE WDAT BADDL2 LMLDS LMSTS DTLB BRANCH_LINK_STAC_PREDICTED EIEIO_INSTR_COMPLETED L1_DATA_CACHE_LOAD_MISS_CYCLES_OVER_THRESHOLD LSU_MISALIGN_STORE_COMPLETED ITLB_NON_SPECULATIVE_MISSES TLBIE_SNOOPS STORE_MERGE_GATHER DST_STREAM_3_CACHE_LINE_FETCHES PREFETCH_ENGINE_COLLISION_VS_LOAD_STORE_INSTR_FETCH GCT_EMPTY_BY_SRQ_FULL REJECT_COMPLETION_STALL L3_INSTR_MISS TOTAL_TRANSLATED ADDRESS_COLLISION_CYCLES BIU_MASTER_INSTR_SIDE_REQUESTS CYCLES_COMPLETION_STALLED_NEXUS_FIFO_FULL nonpostwrszbyte INTEL_CL INTEL_CORE INTEL_BROADWELL RESOURCE_STALLS_ANY {"type": "dropnotify"}
{"type": "thr_exit" %s, "pmcid": "0x%08x", "event": "0x%08x", "flags": "0x%08x", "rate": "%jd"}
GenuineIntel-6-35 uops_retired.retire_slots / inst_retired.any cpu_clk_unhalted.thread / cpu_clk_unhalted.ref_tsc C3_Core_Residency umask=0x27,period=200003,event=0x24 umask=0xe2,period=200003,event=0x24 Demand RFO requests including regular RFOs, locks, ItoM Offcore requests buffer cannot take more entries for this thread core umask=0x8,period=100003,event=0xc1 fp_arith_inst_retired.scalar_single umask=0x4,period=2000003,event=0xc7 Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ? This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB) Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer idq.mite_all_uops Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty umask=0x10,period=2000003,event=0x5d rtm_retired.commit umask=0x1,period=100003,event=0xcd,ldlat=0x4 This event counts loads with latency value being above eight Spec update: BDM100, BDM35 (Must be precise) pipeline Cases when loads get true Block-on-Store blocking code preventing store forwarding This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues This event counts taken speculative and retired direct near calls umask=0xc1,period=200003,event=0x88 umask=0x81,period=200003,event=0x89 umask=0x3,period=2000003,event=0xa0 umask=0x1,any=1,period=2000003,event=0xa1 Cycles while memory subsystem has an outstanding load umask=0x6,cmask=6,period=2000003,event=0xa3 cycle_activity.stalls_l1d_miss uops_executed.cycles_ge_3_uops_exec Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution Spec update: BDM11, BDM55 (Must be precise) umask=0x4,period=100003,event=0xc3 This is a precise version (that is, uses PEBS) of the event that counts return instructions retired (Precise event) llc_misses.rfo_llc_prefetch write requests to local home agent. Unit: uncore_ha unc_m_dclockticks This is an occupancy event that tracks the number of cores that are in C3. It can be used by itself to get the average number of cores in C0, with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details. Unit: uncore_pcu This event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G) Spec update: BDM69 This event counts load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault Spec update: BDM69 This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. SMT version; use when SMT is enabled and measuring per logical CPU inst_retired.any / mem_uops_retired.all_stores Branch_Misprediction_Cost L2MPKI L2 cache hits per kilo instruction for all request types (including speculative) ( (( 1 * ( fp_arith_inst_retired.scalar_single + fp_arith_inst_retired.scalar_double ) + 2 * fp_arith_inst_retired.128b_packed_double + 4 * ( fp_arith_inst_retired.128b_packed_single + fp_arith_inst_retired.256b_packed_double ) + 8 * fp_arith_inst_retired.256b_packed_single )) / 1000000000 ) / duration_time offcore_response.demand_code_rd.supplier_none.snoop_hit_no_fwd offcore_response.pf_l2_rfo.l3_hit.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010200 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020200 offcore_response.pf_l3_code_rd.l3_hit.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C8000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0120 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020091 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020091 Number of transitions from AVX-256 to legacy SSE when penalty applicable (Precise Event) Spec update: BDM30 This is a precise version (that is, uses PEBS) of the event that counts any input SSE* floating-point (FP) assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention umask=0x30,edge=1,period=2000003,cmask=1,event=0x79 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000001 offcore_response.corewb.l3_miss_local_dram.snoop_hit_no_fwd offcore_response.pf_l2_data_rd.l3_miss.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020080 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0200 offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_none offcore_response.all_data_rd.l3_miss_local_dram.snoop_hitm offcore_response.all_rfo.l3_miss.snoop_miss umask=0x1,period=2000003,cmask=4,event=0xa8 umask=0x1,period=2000003,cmask=1,event=0xa8 unc_cbo_xsnp_response.hitm_xcore umask=0x11,event=0x34 L3 Lookup write request that access cache and found line in M-state unc_cbo_cache_lookup.read_es umask=0x01,cmask=1,event=0x80 DRAM_Parallel_Reads Miss in last-level (L3) cache. Excludes Unknown data-source Supports address when precise. Spec update: BDM100, BDE70 (Precise event) This event counts retired load uops which data sources were load uops missed L1 but hit a fill buffer due to a preceding miss to the same cache line with the data not ready.
Note: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load Supports address when precise (Precise event) offcore_response.all_reads.llc_miss.remote_hitm offcore_response.all_code_rd.llc_miss.local_dram l2_lines_in.self.any umask=0x40,period=200000,event=0x25 umask=0x70,period=200000,event=0x26 umask=0x44,period=200000,event=0x2a l2_lock.self.s_state l2_data_rqsts.self.i_state l2_data_rqsts.self.mesi All read requests from L1 instruction and data caches L2 cache requests umask=0x5f,period=200000,event=0x2e umask=0x1,period=2000000,event=0xc7 simd_comp_inst_retired.scalar_double umask=0x1,period=200000,event=0x80 Partial write bus transaction umask=0x40,period=200000,event=0x6f reissue.any.ar div.ar All indirect branches that have a return mnemonic Periods no micro-ops retired Retired taken branch instructions umask=0x81,period=200000,event=0x3 umask=0x4,period=200000,event=0xcb Counts memory requests originating from the core that miss in the L2 cache Counts memory requests originating from the core that reference a cache line in the L2 cache mem_uops_retired.split Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts reads for ownership (RFO) requests (demand & prefetch) that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) umask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600003091 Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data reads generated by L1 or L2 prefetchers that hit the L2 cache Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that hit the L2 cache umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400000020 Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that hit the L2 cache Counts demand cacheable data reads of full cache lines that are outstanding, per cycle, from the time of the L2 miss to when any response is received umask=0x2,period=200003,event=0xc3 fetch_stall.all Instructions retired (Fixed event) Loads blocked because address has 4k partial address false dependence (Precise event capable) (Must be precise) Retired instructions of near indirect Jmp or call (Precise event capable) (Must be precise) Retired near return instructions (Precise event capable) (Must be precise) umask=0xfe,period=200003,event=0xc4 Counts reads for ownership (RFO) requests generated by L2 prefetcher true miss for the L2 cache with a snoop miss in the other processor module Counts reads for ownership (RFO) requests generated by L2 prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required offcore_response.full_streaming_stores.outstanding Counts any data writes to uncacheable write combining (USWC) memory region true miss for the L2 cache with a snoop miss in the other processor module offcore_response.any_pf_data_rd.any_response umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000003091 Counts the number of times that the machines clears due to a page fault. Covers both I-side and D-side(Loads/Stores) page faults. A page fault occurs when either page is not present, or an access violation Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 1GB pages. The page walks can end with or without a page fault umask=0x8,period=2000003,event=0x85 Number of instruction fetches that hit the L2 cache Demand requests to L2 cache Spec update: HSD78 Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache Spec update: HSD29, HSD25, HSM26, HSM30. Supports address when precise (Precise event) Counts cycles the IDQ is empty Spec update: HSD135 offcore_response.all_reads.l3_miss.local_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100400001 Cycles which a uop is dispatched on port 1 in this thread Execution stalls due to L1 data cache misses Store miss in all TLB levels causes a page walk that completes. (1G) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00001 Retired load uops that miss the STLB. (Precise Event) Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready (Precise event) Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores offcore_response.demand_rfo.llc_hit.no_snoop_needed Counts all demand data reads umask=0x40,period=2000003,event=0x10 umask=0x2,period=2000003,event=0x11 Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss Number of flags-merge uops being allocated umask=0x30,any=1,period=2000003,event=0xa1 umask=0x4,period=100003,event=0x5f offcore_response.pf_l2_data_rd.llc_miss.remote_hit_forward offcore_response.pf_l2_data_rd.llc_miss.remote_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3fffc20080 Streaming stores (partial cache line). Derived from unc_c_tor_inserts.opcode.streaming_partial. Unit: uncore_cbox Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. (filter_band3=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Unit: uncore_pcu This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers. Machine clears can have a significant performance impact if they are happening frequently partial_rat_stalls.slow_lea_window umask=0x8,period=100003,event=0x7 resource_stalls2.all_prf_control umask=0x20,period=2000003,cmask=1,event=0x59 event=0x80 Counts the number of core cycles the fetch stalls because of an icache miss. This is a cummulative count of core cycles the fetch stalled for all icache misses umask=0x4,period=100007,event=0x4 offcore_response.any_pf_l2.outstanding umask=0x1,period=100007,event=0xb7,offcore_rsp=0x10004032f7 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400200 Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010040 offcore_response.pf_l2_rfo.l2_hit_far_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000020020 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400004 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002000100 offcore_response.any_data_rd.l2_hit_this_tile_e umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004003091 Counts Demand cacheable data write requests that accounts for responses which hit its own tile's L2 with data in S state umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800183091 Counts L2 code HW prefetches that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800044 offcore_response.any_data_rd.ddr_near offcore_response.any_request.mcdram_near Counts Software Prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far offcore_response.uc_code_reads.ddr_near Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200001 L2 load hits umask=0x2,period=200000,event=0x24 umask=0xc0,period=200000,event=0x24 All L2 prefetches l2_transactions.prefetch l2_write.rfo.mesi umask=0x2,period=2000000,event=0xb Memory instructions retired above 128 clocks (Precise Event) mem_inst_retired.latency_above_threshold_512 Memory instructions retired above 8 clocks (Precise Event) umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1011 offcore_response.any_request.llc_hit_other_core_hitm Offcore RFO requests satisfied by the IO, CSR, MMIO unit Offcore RFO requests satisfied by a remote cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF08 offcore_response.corewb.remote_cache Offcore writebacks to a remote cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1833 umask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF03 All offcore demand data reads offcore_response.demand_data_rd.llc_hit_no_other_core offcore_response.demand_data_rd.remote_cache_hitm offcore_response.demand_ifetch.any_location Offcore demand code reads satisfied by the LLC and HIT in a sibling core offcore_response.demand_ifetch.remote_cache_hit offcore_response.demand_rfo.llc_hit_other_core_hitm umask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF80 Offcore prefetch data requests that HIT in a remote cache Offcore prefetch code reads that HIT in a remote cache Offcore prefetch RFO requests satisfied by any cache or DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF70 offcore_response.prefetch.llc_hit_no_other_core Offcore prefetch requests satisfied by the LLC and not found in a sibling core offcore_response.prefetch.llc_hit_other_core_hitm Offcore prefetch requests satisfied by the LLC or local DRAM 128 bit SIMD integer logical operations simd_int_64.packed_mpy umask=0x1,period=100000,event=0xb7,offcore_rsp=0x60FF Offcore requests satisfied by a remote DRAM offcore_response.any_rfo.remote_dram Offcore data reads, RFO's and prefetches statisfied by the local DRAM Offcore demand data reads satisfied by a remote DRAM offcore_response.demand_rfo.any_llc_miss Offcore other requests satisfied by any DRAM offcore_response.pf_data_rd.remote_dram l1i.reads umask=0xf,period=2000000,event=0xd2 umask=0x1,period=2000000,event=0xd4 arith.div umask=0x2,period=20000,event=0xc4 br_misp_exec.any Mispredicted indirect non call branches executed ild_stall.any umask=0x1,period=2000000,event=0x1e inst_retired.mmx resource_stalls.load umask=0x2,period=2000000,event=0xa2 DTLB load misses umask=0x10,period=200000,event=0x49 Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore mem_inst_retired.stlb_miss_loads mem_inst_retired.stlb_miss_stores Retired load instructions with L3 cache hits as data sources Supports address when precise (Precise event) mem_load_retired.fb_hit umask=0x1f,period=100003,event=0xf1 Number of cache line split locks sent to uncore umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000108000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0088000 offcore_response.other.l3_hit_e.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000400004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000400001 Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity umask=0x1,period=100007,event=0xc6,frontend=0x200206 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall. Precise Event (Precise event) sw_prefetch_access.prefetchw Demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch exe_activity.bound_on_stores This is a precise version (that is, uses PEBS) of the event that counts not taken branch instructions retired Spec update: SKL091 (Precise event) Load miss in all TLB levels causes a page walk that completes. (All page sizes) Counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific) Counts the number of request that were not accepted into the L2Q because the L2Q is FULL Load uops that split cache line boundary (Precise event) This event counts the number of store ops retired offcore_response.any_code_rd.l2_miss.snoop_miss Counts code reads generated by L2 prefetchers that miss L2 The NO_ALLOC_CYCLES.NOT_DELIVERED event is used to measure front-end inefficiencies, i.e. when front-end of the machine is not delivering micro-ops to the back-end and the back-end is not stalled. This event can be used to identify if the machine is truly front-end bound. When this event occurs, it is an indication that the front-end of the machine is operating at less than its theoretical peak performance. Background: We can think of the processor pipeline as being divided into 2 broader parts: Front-end and Back-end. Front-end is responsible for fetching the instruction, decoding into micro-ops (uops) in machine understandable format and putting them into a micro-op queue to be consumed by back end. The back-end then takes these micro-ops, allocates the required resources. When all resources are ready, micro-ops are executed. If the back-end is not ready to accept micro-ops from the front-end, then we do not want to count these as front-end bottlenecks. However, whenever we have bottlenecks in the back-end, we will have allocation unit stalls and eventually forcing the front-end to wait until the back-end is ready to receive more UOPS. This event counts the cycles only when back-end is requesting more uops and front-end is not able to provide them. Some examples of conditions that cause front-end efficiencies are: Icache misses, ITLB misses, and decoder restrictions that limit the the front-end bandwidth Duration of I-side page-walks in core cycles Counts prefetch code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded Counts prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean response Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded REQUEST = DATA_INTO_CORE and RESPONSE = ANY_RESPONSE offcore_response.pf_ifetch.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10040 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400090 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400122 offcore_response.pf_llc_data_rd.llc_miss.dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1f80400004 This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceeding smaller uncompleted store. See the table of not supported store forwards in the Intel® 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued Offcore RFO requests offcore_requests.demand.rfo umask=0x2,period=2000000,event=0x60 Outstanding offcore demand RFOs Cycles offcore demand RFOs busy REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HITM REQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HIT offcore_response.data_in.local_dram_and_remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0xff01 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5080 REQUEST = PF_DATA and RESPONSE = ANY_CACHE_DRAM REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE REQUEST = ANY_REQUEST and RESPONSE = ANY_DRAM AND REMOTE_FWD REQUEST = ANY RFO and RESPONSE = OTHER_LOCAL_DRAM REQUEST = DATA_IFETCH and RESPONSE = REMOTE_DRAM REQUEST = DATA_IN and RESPONSE = OTHER_LOCAL_DRAM REQUEST = PF_DATA_RD and RESPONSE = OTHER_LOCAL_DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0xf820 REQUEST = PF_IFETCH and RESPONSE = REMOTE_DRAM REQUEST = PREFETCH and RESPONSE = ANY_LLC_MISS snoopq_requests.invalidate umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0491 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x103FC00001 offcore_response.demand_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd offcore_response.demand_code_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063B800004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x103FC00080 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBC000122 core_power.lvl2_turbo_license umask=0x20,period=200003,event=0x28 Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule Write Pending Queue Allocations. Unit: uncore_imc unc_cha_core_snp.core_gtone Counts when a transaction with the opcode type Rsp*WB Snoop Response was received which indicates which indicates the data was written back to it's home. This is returned when a non-RFO request hits a cacheline in the Modified state. The Cache can either downgrade the cacheline to a S (Shared) or I (Invalid) state depending on how the system has been configured. This response will also be sent when a cache requests E (Exclusive) ownership of a cache line without receiving data, because the cache must acquire ownership Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus fc_mask=0x07,ch_mask=0x02,umask=0x01,event=0xc0 unc_iio_txn_req_by_cpu.mem_write.part3 unc_iio_txn_req_of_cpu.mem_write.part2 Counts reads in which direct to core transactions (which would have bypassed the CHA) were overridden event=0x57 Counts cycles when the Intel Ultra Path Interconnect (UPI) is in L1 power mode. L1 is a mode that totally shuts down the UPI link. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another, this event only coutns when both links are shutdown umask=0x10,cmask=1,period=100003,event=0x49 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200100 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020400 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200010 offcore_response.other.l3_hit_m.no_snoop_needed This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD period=200003,umask=0xc4,event=0x24 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040122 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200020 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE offcore_response.pf_l1d_and_sw.l3_hit_f.any_snoop period=2000003,umask=0x2,event=0x48 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020020 This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200002 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0010 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040020 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080001 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD offcore_response.all_pf_data_rd.supplier_none.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0400 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0491 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C8000 offcore_response.demand_code_rd.supplier_none.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040120 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080080 offcore_response.demand_rfo.l3_hit_m.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040004 period=100003,umask=0x4,event=0xb0 This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS offcore_response.demand_data_rd.l3_hit_m.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100100 period=200003,umask=0x22,event=0x24 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020004 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200122 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080001 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200208000 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0001 offcore_response.all_data_rd.l3_hit_f.no_snoop_needed This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020004 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0490 period=2000003,umask=0x2,event=0x60 Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT14 RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element cmask=4,period=2000003,umask=0x1,event=0x9c period=100007,umask=0x1,event=0xc6,frontend=0x400206 ALL_DATA_RD & L3_MISS_REMOTE_DRAM & SNOOP_MISS_OR_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000400 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000100 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000002 offcore_response.all_reads.l3_miss_local_dram.any_snoop offcore_response.pf_l1d_and_sw.l3_miss.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000490 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00100 ocr.all_pf_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE offcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.hitm_other_core ocr.all_rfo.l3_miss_local_dram.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD period=2000003,umask=0x40,event=0xc9 ocr.all_pf_data_rd.l3_miss_local_dram.any_snoop ocr.all_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000001 offcore_response.demand_code_rd.l3_miss.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE ocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.snoop_miss Counts all demand data writes (RFOs) DEMAND_RFO & L3_MISS & HIT_OTHER_CORE_NO_FWD ocr.pf_l3_data_rd.l3_miss.hitm_other_core Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS & ANY_SNOOP ocr.demand_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD ocr.demand_data_rd.l3_miss.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00400 ALL_READS & L3_MISS & REMOTE_HITM ocr.all_data_rd.l3_miss_local_dram.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800004 Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS & REMOTE_HIT_FORWARD offcore_response.pf_l3_data_rd.l3_miss_local_dram.no_snoop_needed ocr.all_rfo.l3_miss_remote_hop1_dram.snoop_miss ALL_RFO & L3_MISS & SNOOP_NONE This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP offcore_response.pf_l2_rfo.l3_miss_local_dram.hit_other_core_fwd offcore_response.demand_code_rd.l3_miss_local_dram.hit_other_core_fwd period=2000003,umask=0x20,event=0xc8 offcore_response.pf_l2_rfo.l3_miss.hitm_other_core offcore_response.all_reads.l3_miss_remote_hop1_dram.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000004 ALL_PF_RFO & L3_MISS_REMOTE_HOP1_DRAM & SNOOP_MISS offcore_response.all_pf_rfo.l3_miss.hit_other_core_fwd This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.SNOOP_NONE offcore_response.all_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd offcore_response.demand_data_rd.l3_miss_remote_hop1_dram.any_snoop offcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.no_snoop_needed ALL_PF_RFO & L3_HIT_S & HITM_OTHER_CORE Counts all demand code reads DEMAND_CODE_RD & L3_HIT_S & HITM_OTHER_CORE ocr.demand_code_rd.l3_hit.hitm_other_core ocr.all_data_rd.l3_hit_e.no_snoop_needed ocr.demand_rfo.l3_hit.snoop_hit_with_fwd ocr.pf_l2_rfo.pmm_hit_local_pmm.snoop_not_needed ocr.demand_data_rd.l3_hit_e.any_snoop ALL_PF_DATA_RD & L3_HIT_M & ANY_SNOOP ocr.demand_code_rd.l3_hit.snoop_none ocr.all_data_rd.l3_hit_e.any_snoop ocr.pf_l1d_and_sw.supplier_none.any_snoop Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_F & NO_SNOOP_NEEDED ocr.all_rfo.supplier_none.hitm_other_core ocr.demand_rfo.supplier_none.snoop_miss ocr.all_data_rd.l3_hit_s.snoop_none ocr.pf_l3_data_rd.l3_hit_m.hit_other_core_fwd ALL_PF_DATA_RD & PMM_HIT_LOCAL_PMM & ANY_SNOOP ocr.all_rfo.l3_hit_f.no_snoop_needed Counts demand data reads DEMAND_DATA_RD & L3_HIT_M & HITM_OTHER_CORE ocr.pf_l3_data_rd.l3_hit_f.no_snoop_needed ALL_READS & L3_HIT_M & HITM_OTHER_CORE Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & SUPPLIER_NONE & HITM_OTHER_CORE Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_E & HITM_OTHER_CORE ocr.demand_code_rd.l3_hit_f.hit_other_core_no_fwd ocr.other.l3_hit_s.hitm_other_core ocr.all_pf_rfo.supplier_none.hit_other_core_fwd ALL_PF_DATA_RD & L3_HIT & SNOOP_NONE ocr.pf_l2_data_rd.l3_hit.no_snoop_needed Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_S & HITM_OTHER_CORE ocr.pf_l2_data_rd.supplier_none.snoop_none Counts demand data reads DEMAND_DATA_RD & L3_HIT_F & HITM_OTHER_CORE Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_F & HIT_OTHER_CORE_NO_FWD any=1,period=2000003,umask=0x1,event=0xd period=400009,umask=0x4,event=0xc5 Counts both taken and not taken retired mispredicted direct and indirect near calls, including both register and memory indirect (Precise event) cmask=2,period=2000003,umask=0x2,event=0xb1 unc_m_cas_count.wr_wmm unc_cha_llc_victims.total_f Counts snoop filter capacity evictions for entries tracking shared lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline Write request of 4 bytes made to IIO Part2 by the CPU. Unit: uncore_iio Counts every peer to peer read request for 4 bytes of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus fc_mask=0x07,ch_mask=0x02,umask=0x08,event=0xc1 unc_iio_txn_req_of_cpu.peer_write.part0 unc_iio_txn_req_of_cpu.peer_write.part2 Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus umask=0x8,event=0x37 event=0x2 Counts incoming FLITs (FLow control unITs) which bypassed the slot0 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency period=100003,umask=0x4,event=0x49 Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailablability Counts number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element Cycles DSB is delivering optimal number of Uops Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture Counts the number of PREFETCHNTA instructions executed Counts the number of times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when: a. preceding store conflicts with the load (incomplete overlap),b. store forwarding is impossible due to u-arch limitations, c. preceding lock RMW operations are not forwarded, d. store has the no-forward bit set (uncacheable/page-split/masked stores), e. all-blocking stores are used (mostly, fences and port I/O), and others. The most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events. See the table of not supported store forwards in the Optimization Guide Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path Counts cycles where the pipeline is stalled due to serializing operations uops_retired.slots Counts all branch instructions retired (Precise event) br_misp_retired.cond_taken Counts the number of load uops retired that miss in the level 2 cache Supports address when precise (Precise event) Counts the number of instructions retired (Precise event) Counts mispredicted branch instructions retired for all branch types. This event is Precise Event capable. This is an architectural event (Precise event) TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter Clockticks of the mesh to memory (M2M). Unit: uncore_m2m event=0x84 All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd umask=0x10,event=0x61 umask=0x10,event=0x64 event=0xc3 df_ccm_reqa.node2.wrsizedfullzero umask=0xEE,event=0x8b umask=0xEC,event=0x8b df_ccm_reqa.node6.rdsized df_ccm_reqa.node5.specdramrd umask=0x23,event=0x8b umask=0x01,event=0x8b df_ccm_reqb.node5.wbinvblkall df_ccm_reqb.node2.vicblkfullzero umask=0x87,event=0x8c df_ccm_reqb.node0.wrsizedfullnc df_ccm_reqb.node0.wrsizednc umask=0xE2,event=0x8c df_ioms_reqa.node3.masterabort umask=0x4A,event=0x108 df_ioms_reqa.node0.anywrsized<32b umask=0x23,event=0x108 umask=0x41,event=0x108 umask=0x4E,event=0x109 umask=0x6E,event=0x109 df_ioms_reqb.node3.anyiotransaction umask=0x2B,event=0x109 umask=0xCA,event=0x109 umask=0x65,event=0x109 umask=0x85,event=0x109 df_ioms_reqb.node1.ioanypostedwrsized<32 umask=0xC3,event=0x109 fpu_pipe_assignment.dual The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to pipe 0 fpu_pipe_assignment.total This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Single-precision add/subtract FLOPS fp_num_mov_elim_scal_op.sse_mov_ops_elim L3 Cache Performance Monitor Counters L3 Cache Accesses l3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x02,event=0x1 l3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x02,event=0x1 l3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x04,event=0x1 l3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x04,event=0x1 l3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x20,event=0x1 l3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x20,event=0x1 l3_request_g1.t2.s3.rdsizednc l3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x40,event=0x1 l3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x80,event=0x1 l3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x80,event=0x1 l3fillvicreq.t0.s0.vicblk l3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x01,event=0x3 l3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x02,event=0x3 l3fillvicreq.t4.s0.rdblkc_s_vic l3fillvicreq.t1.s2.rdblkc_s_vic l3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x08,event=0x3 l3fillvicreq.t2.s0.rdblkc_s l3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x10,event=0x3 l3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x20,event=0x3 l3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x40,event=0x3 l3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x40,event=0x3 l3fillvicreq.t6.s3.rdblkl l3victimstate.t7.s0.nol3victimline l3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x02,event=0x9 l3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x02,event=0x9 l3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x02,event=0x9 l3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x02,event=0x9 l3victimstate.t7.s0.f_s l3victimstate.t0.s2.o l3victimstate.t4.s3.o l3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x08,event=0x9 l3victimstate.t1.s3.e_fe l3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x10,event=0x9 l3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x20,event=0x9 l3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x20,event=0x9 l3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x40,event=0x9 event=0x35 Number of STLF hits The number of accesses to the data cache for load and store references. This may include certain microcode scratchpad accesses, although these are generally rare. Each increment represents an eight-byte access, although the instruction may only be accessing a portion of that. This event is a speculative event umask=0x2,event=0x41 ls_tablewalker.ic_type1 Software Prefetch Instructions Dispatched. Prefetch, Prefetch_T0_T1_T2 umask=0x1,event=0x28a The number of instruction fetches that hit in the L1 ITLB ex_ret_cond_misp fp_ret_sse_avx_ops.add_sub_flops Software Prefetch Instructions Dispatched (Speculative). PrefetchNTA instruction. See docAPM3 PREFETCHlevel umask=0xff,event=0xaa de_dis_dispatch_token_stalls1.int_sched_misc_token_stall Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Store queue resource stall. Applies to all ops with store semantics NB_HT_BUS2_BANDWIDTH STREX_PASSED MEM_ACCESS_LD BR_RETURN_SPEC ISB_SPEC MEM_CAP_READ_TAG_SET INSTR_REFETCH INTEGER_INSNS NT_MUL_DIV_INSNS DSP_BRANCH_INSNS EXCEPTIONS_TAKEN FSB_25_50_FULL IDIDS IOLDS DTLBAD THRESHOLD_VEC_INSTR_QUEUE_ENTRIES_CYCLES DST_INSTR_DISPATCHED VTQ_LINE_FETCH BRANCH_LINK_STACK_MISPREDICTED L3_DATA_CACHE_MISSES LSU_EMPTY DISPATCH_SUCCESS BUS_HIGH UOPS_COMPLETED STORE_UOPS_COMPLETED CYCLES_DECODE_STALLED INSTR_L1_CACHE_LOCKS L2_CACHE_INSTR_HITS SOFT- k8-fr-retired-taken-branches-mispredicted ic-misses K8- usr gs postwrszbyte AMD_K8 INTEL_ATOM mem_load_l3_miss_retired.remote_hitm RESOURCE_STALL %s, "tsc": "%jd" CoreIPC C3_Pkg_Residency This event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types l2_rqsts.all_pf umask=0x1,period=100003,event=0xb0 mem_uops_retired.split_loads This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were hits in the mid-level (L2) cache Supports address when precise. Spec update: BDM35 (Precise event) umask=0x20,period=100007,event=0xd1 umask=0x4,period=100007,event=0xd3 L2 cache accesses when fetching instructions L2 cache lines filling L2 Number of SIMD FP assists due to input values idq_uops_not_delivered.core Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:
a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;
b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions);
c. Instruction Decode Queue (IDQ) delivers four uops umask=0x1,period=2000003,event=0x5 This event counts speculative cache-line split load uops dispatched to the L1 cache This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache Number of times a TSX line had a cache conflict tx_mem.abort_hle_store_to_elided_lock umask=0x10,period=2000003,event=0x54 tx_mem.hle_elision_buffer_full umask=0x4,period=2000003,event=0x5d Number of times we entered an HLE region; does not count nested transactions umask=0x4,period=2000003,event=0xc9 umask=0x20,period=2000003,event=0xc9 rtm_retired.aborted_misc4 This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time move_elimination.int_not_eliminated Taken speculative and retired indirect calls Taken speculative and retired mispredicted macro conditional branches This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1 umask=0x4,any=1,period=2000003,event=0xa1 uops_dispatched_port.port_4 umask=0x20,period=2000003,event=0xa1 Resource-related stall cycles cycle_activity.cycles_no_execute umask=0x2,cmask=4,period=2000003,event=0xb1 umask=0x1,period=2000003,event=0xc3 Return instructions retired. (Precise Event - PEBS) (Precise event) umask=0x20,period=2000003,event=0xcc umask=0x1,event=0x37 umask=0x3,event=0x4 unc_m_pre_count.page_miss uncore power This event counts load misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault Spec update: BDM69 Store misses in all DTLB levels that cause completed page walks (1G) Spec update: BDM69 Store operations that miss the first TLB level but hit the second and do not cause page walks umask=0x1,period=100007,event=0xbd Pipeline;Retire DSB;Fetch_BW Instruction_Type IpS Branches umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0002 offcore_response.corewb.supplier_none.snoop_hitm offcore_response.corewb.supplier_none.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020008 offcore_response.pf_l2_data_rd.supplier_none.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020010 offcore_response.pf_l2_code_rd.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010040 offcore_response.pf_l2_code_rd.l3_hit.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010100 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020120 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0091 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0091 This is a precise version (that is, uses PEBS) of the event that counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid umask=0x1,period=2000003,cmask=4,event=0x9c umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000001 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000001 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000008 offcore_response.corewb.l3_miss_local_dram.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000010 offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_non_dram offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_not_needed offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000200 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C008000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C008000 offcore_response.all_pf_data_rd.l3_miss.snoop_hit_no_fwd offcore_response.all_data_rd.l3_miss.snoop_not_needed offcore_response.all_rfo.supplier_none.snoop_non_dram Cycles no executable uops retired (Precise Event) unc_arb_trk_occupancy.cycles_with_any_request Miss in mid-level (L2) cache. Excludes Unknown data-source Supports address when precise (Precise event) Counts all prefetch (that bring data to LLC only) RFOs hit in the L3 Counts all demand data writes (RFOs) hit in the L3 l2_st.self.s_state umask=0x72,period=200000,event=0x2e l2_rqsts.self.prefetch.e_state l2_rqsts.self.prefetch.i_state l2_rqsts.self.prefetch.mesi L1 Cacheable Data Reads Modified cache lines evicted from the L1 data cache Floating point assists SIMD packed multiply micro-ops retired umask=0x88,period=2000000,event=0xb3 simd_comp_inst_retired.scalar_single umask=0x2,period=200000,event=0x80 umask=0x1,period=2000000,cmask=1,event=0xa9 misalign_mem_ref.rmw_split Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed Streaming SIMD Extensions (SSE) PrefetchT2 instructions executed Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed umask=0x80,period=200000,event=0x6 Memory bus transactions umask=0x40,period=200000,event=0x7f br_missp_type_retired.ind umask=0x2,period=2000000,event=0xdc umask=0x7,period=200000,event=0x8 Counts the number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the intra-die interconnect (IDI) fabric. The XQ may reject transactions from the L2Q (non-cacheable requests), L2 misses and L2 write-back victims Loads retired that came from DRAM (Precise event capable) Supports address when precise (Must be precise) umask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600000022 Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts partial cache line data writes to uncacheable write combining (USWC) memory region that true miss for the L2 cache with a snoop miss in the other processor module Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required offcore_response.full_streaming_stores.l2_miss.hit_other_core_no_fwd Counts bus lock and split lock requests that have any transaction responses from the uncore subsystem Counts data cacheline reads generated by hardware L2 cache prefetcher that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that are outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) umask=0x1,period=203,event=0xcb hw_interrupts.pending_and_masked Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. This event uses fixed counter 2. You cannot collect a PEBs record for this event ld_blocks.utlb_miss Core cycles when core is not halted. This event uses a (_P)rogrammable general purpose performance counter Counts machine clears due to floating point (FP) operations needing assists. For instance, if the result was a floating point denormal, the hardware clears the pipeline and reissues uops to produce the correct IEEE compliant denormal result umask=0xf7,period=200003,event=0xc5 br_misp_retired.ind_call Retired mispredicted conditional branch instructions that were taken (Precise event capable) (Must be precise) itlb.miss Counts uops retired that had a DTLB miss on load, store or either. Note that when two distinct memory operations to the same page miss the DTLB, only one of them will be recorded as a DTLB miss Supports address when precise (Must be precise) umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000010 Counts reads for ownership (RFO) requests generated by L2 prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received Counts bus lock and split lock requests miss the L2 cache with a snoop hit in the other processor module, data forwarding is required umask=0x1,period=100007,event=0xb7,offcore_rsp=0x40000032b7 dtlb_load_misses.walk_pending Page walk completed due to an instruction fetch in a 2M or 4M page itlb_misses.walk_pending Number of instruction fetches that missed the L2 cache Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences Counts all prefetch (that bring data to L2) RFOs hit in the L3 Randomly selected loads with latency value being above 16 Spec update: HSD76, HSD25, HSM26 (Must be precise) miss in the L3 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00200 offcore_response.pf_l2_code_rd.l3_miss.any_response This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store. The penalty for blocked store forwarding is that the load must wait for the store to write its value to the cache before it can be issued umask=0x4,period=2000003,event=0x87 Cycles with pending memory loads Number of instructions retired. General Counter - architectural event Spec update: HSD11, HSD140 Branch instructions at retirement An external snoop hits a non-modified line in some processor core umask=0x48,event=0x34 This event counts cycles when the page miss handler (PMH) is servicing page walks caused by ITLB misses Retired load uops missed L2. Unknown data source excluded Supports address when precise. Spec update: HSD29, HSM30 (Precise event) offcore_response.demand_rfo.llc_hit.hit_other_core_no_fwd Clean L2 cache lines evicted by L2 prefetch umask=0x8,period=100003,event=0xf2 offcore_response.all_rfo.llc_hit.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0001 Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core caches Counts non-temporal stores (( 1 * ( fp_comp_ops_exe.sse_scalar_single + fp_comp_ops_exe.sse_scalar_double ) + 2 * fp_comp_ops_exe.sse_packed_double + 4 * ( fp_comp_ops_exe.sse_packed_single + simd_fp_256.packed_double ) + 8 * simd_fp_256.packed_single )) / cycles Loads with latency value being above 128 (Must be precise) mem_trans_retired.precise_store Counts LLC replacements Cycles per thread when uops are dispatched to port 5 uops_dispatched_port.port_5_core Cycles stalled due to no store buffers available (not including draining form sync) Cycles with pending L2 cache miss loads umask=0x08,event=0x34 umask=0x80,period=100003,event=0x85 offcore_response.pf_l2_data_rd.llc_hit.snoop_miss Counts all demand code reads that miss the LLC llc_references.pcie_ns_read QPI clock ticks. Use to get percentages for QPI cycles events. Unit: uncore_qpi (unc_p_freq_band1_cycles / unc_p_clockticks) * 100. unc_p_freq_band2_transitions event=0xb,filter_band0=12 (unc_p_freq_ge_1200mhz_cycles / unc_p_clockticks) * 100. Retired store uops that miss the STLB (Precise event) Retired load uops with locked access (Precise event) This event counts the number of uops not delivered to the back-end per cycle, per thread, when the back-end was not stalled. In the ideal case 4 uops can be delivered each cycle. The event counts the undelivered uops - so if 3 were delivered in one cycle, the counter would be incremented by 1 for that cycle (4 - 3). If the back-end is stalled, the count for this event is not incremented even when uops were not delivered, because the back-end would not have been able to accept them. This event is used in determining the front-end bound category of the top-down pipeline slots characterization This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events umask=0xa,period=2000003,event=0xa2 umask=0xc,event=0x1 This event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses umask=0x4,period=200003,event=0x86 mem_uops_retired.l2_miss_loads offcore_response.any_read.l2_hit_near_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400200 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080080 offcore_response.pf_l2_rfo.supplier_none offcore_response.demand_code_rd.l2_hit_far_tile_e_f Counts Demand cacheable data writes that accounts for any response offcore_response.pf_software.l2_hit_this_tile_e umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004001000 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x00080032f7 offcore_response.demand_code_rd.l2_hit_this_tile_f offcore_response.demand_rfo.l2_hit_far_tile umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800401000 offcore_response.any_pf_l2.mcdram_near umask=0x1,period=100007,event=0xb7,offcore_rsp=0x01004032f7 Counts L1 data HW prefetches that accounts for data responses from DRAM Far offcore_response.bus_locks.mcdram_near umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200200 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400100 offcore_response.partial_writes.ddr_near umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000080 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180600001 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180600002 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180600020 offcore_response.any_pf_l2.mcdram Counts demand code reads and prefetch code reads that accounts for responses from DDR (local and far) umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181800400 Counts the number of core cycles when no micro-ops are allocated and a RATstall (caused by reservation station full) is asserted recycleq.st_splits Counts any retired store that was pushed into the recycle queue for any reason unc_m_cas_count.rd umask=0x1,period=2000000,event=0x63 l1d.m_evict L1 data cache load locks in M state L1D prefetch load lock accepted in fill buffer L1D hardware prefetch requests triggered l1d_wb_l2.s_state umask=0x10,period=200000,event=0xf0 All L2 demand store RFOs that hit the cache umask=0xf,period=100000,event=0x27 Loads delayed with at-Retirement block code offcore_response.any_data.local_cache offcore_response.any_ifetch.llc_hit_no_other_core Offcore requests satisfied by any cache or DRAM Offcore requests satisfied by a remote cache Offcore request = all data, response = any cache_dram offcore_response.demand_data.llc_hit_other_core_hitm offcore_response.demand_data_rd.llc_hit_other_core_hit offcore_response.demand_data_rd.local_cache_dram offcore_response.demand_ifetch.remote_cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x102 Offcore prefetch data requests satisfied by the LLC or local DRAM Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit umask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF20 Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3820 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1870 umask=0x8,period=200000,event=0xfd macro_insts.fusions_decoded umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4011 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2077 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2033 offcore_response.demand_data_rd.any_llc_miss offcore_response.demand_data_rd.remote_dram Offcore demand code reads satisfied by any DRAM offcore_response.demand_rfo.remote_dram umask=0x1,period=200000,event=0x7 sb_drain.any Thread responded HIT to snoop baclear_force_iq Mispredicted unconditional branches executed br_misp_exec.direct_near_call Any Instruction Length Decoder stall cycles inst_decoded.dec0 machine_clears.mem_order umask=0x4,period=20000,event=0xc3 umask=0x1,period=200000,event=0xc7 SIMD Scalar-Single Uops retired (Precise Event) inv=1,umask=0x40,period=2000000,cmask=1,event=0xb1 Uops executed on port 4 (core count) Cycles Uops are not retiring (Precise Event) dtlb_load_misses.any Counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch.Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type mem_load_l3_hit_retired.xsnp_hit offcore_response.other.l4_hit_local_l4.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040088000 offcore_response.demand_code_rd.l3_hit_e.snoop_miss offcore_response.demand_code_rd.l3_hit_m.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000080002 offcore_response.demand_rfo.l3_hit_m.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400400001 offcore_response.demand_data_rd.l3_hit_s.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040100001 offcore_response.demand_data_rd.l3_hit_m.any_snoop Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ icache_64b.iftag_stall umask=0x1,period=100007,event=0xc6,frontend=0x11 umask=0x1,period=100007,event=0xc6,frontend=0x100206 Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles (Must be precise) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000040004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C400002 offcore_response.demand_rfo.l3_miss_local_dram.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0044000002 offcore_response.demand_data_rd.l3_miss.snoop_non_dram Counts the number of hardware interruptions received by the processor umask=0x1,any=1,period=2000003,event=0xd Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 3 umask=0x2,period=2000003,event=0xa6 Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT ( ((br_misp_retired.all_branches / ( br_misp_retired.all_branches + machine_clears.count )) * (( uops_issued.any - uops_retired.retire_slots + 4 * int_misc.recovery_cycles ) / (4 * cycles))) + (4 * idq_uops_not_delivered.cycles_0_uops_deliv.core / (4 * cycles)) * (( int_misc.clear_resteer_cycles + 9 * baclears.any ) / cycles) / (4 * idq_uops_not_delivered.cycles_0_uops_deliv.core / (4 * cycles)) ) * (4 * cycles) / br_misp_retired.all_branches Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load Stores that miss the DTLB and hit the STLB This event counts the number of retired memory operations with lock semantics. These are either implicit locked instructions such as the XCHG instruction or instructions with an explicit LOCK prefix (0xF0) Any reissued load uops Counts any rfo reads (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache offcore_response.any_request.l2_miss.snoop_miss umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680000100 offcore_response.pf_l2_code_rd.l2_miss.snoop_miss Counts demand and DCU prefetch instruction cacheline that have any response type Counts the number of times a decode restriction reduced the decode throughput due to wrong instruction length prediction Counts the number of taken JCC branch instructions retired (Precise event) NON_RETURN_IND counts the number of near indirect JMP and near indirect CALL branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) umask=0x50,period=200003,event=0xca The BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end. The BACLEARS.COND event counts the number of JCC (Jump on Condtional Code) baclears Duration of D-side page-walks in core cycles This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K). (Precise Event - PEBS) (Precise event) Counts demand & prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0120 COREWB & ANY_RESPONSE umask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0040 offcore_response.pf_llc_rfo.llc_hit.snoop_miss Counts all data/code/rfo references (demand & prefetch) Counts demand data writes (RFOs) that miss the LLC and the data returned from dram offcore_requests.any REQUEST = DATA_IFETCH and RESPONSE = ANY_CACHE_DRAM REQUEST = DATA_IFETCH and RESPONSE = LOCAL_CACHE REQUEST = DEMAND_DATA and RESPONSE = ANY_CACHE_DRAM REQUEST = PF_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT offcore_response.pf_rfo.all_local_dram_and_remote_cache_hit REQUEST = PF_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = PREFETCH and RESPONSE = ANY_LOCATION REQUEST = ANY IFETCH and RESPONSE = REMOTE_DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0xf8ff REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_LLC_MISS umask=0x1,period=100000,event=0xb7,offcore_rsp=0xf810 umask=0x1,period=20000,event=0xc5 DTLB misses casued by low part of address umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2733 umask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF50 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063B800001 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063B800002 unc_m_wpq_inserts PCI Express bandwidth writing at IIO, part 3. Unit: uncore_iio Counts when a a transaction with the opcode type RspCnflct* Snoop Response was received. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent. This triggers conflict resolution hardware. This covers both the opcode RspCnflct and RspCnflctWbI Number of reads in which direct to Intel UPI transactions were overridden. Unit: uncore_m2m unc_m2m_direct2upi_not_taken_dirstate Multi-socket cacheline Directory update from S to A. Unit: uncore_m2m unc_upi_direct_attempts.d2u umask=0x2,event=0x31 unc_upi_txl_flits.non_data period=100003,umask=0x1f,event=0xf1 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0080 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400490 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE period=100003,umask=0x10,event=0xf4 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NONE offcore_response.pf_l2_data_rd.l3_hit_s.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010122 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE This event is deprecated. Refer to new event OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.SNOOP_MISS This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200100 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP offcore_response.pf_l2_data_rd.supplier_none.hit_other_core_fwd offcore_response.all_pf_data_rd.l3_hit_m.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100120 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080491 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE period=100003,umask=0x12,event=0xd0 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080122 offcore_response.pf_l3_data_rd.l3_hit_m.no_snoop_needed offcore_response.demand_code_rd.l3_hit_e.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200400 offcore_response.pf_l3_rfo.l3_hit_s.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04000407F7 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200122 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED period=20011,umask=0x1,event=0xd2 offcore_response.demand_rfo.l3_hit_s.no_snoop_needed This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0001 offcore_response.demand_rfo.l3_hit_f.hitm_other_core This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100408000 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100004 offcore_response.all_reads.l3_hit.any_snoop This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.ANY_SNOOP This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS offcore_response.pf_l1d_and_sw.l3_hit_s.hit_other_core_fwd offcore_response.other.l3_hit_f.snoop_miss This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED offcore_response.all_pf_rfo.supplier_none.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C8000 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020490 offcore_response.pf_l2_rfo.l3_hit_m.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200491 This event is deprecated. Refer to new event OCR.PF_L3_RFO.ANY_RESPONSE period=2000003,umask=0x1,event=0xc7 period=2000003,umask=0x20,event=0x79 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall (Precise event) This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS_LOCAL_DRAM & NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000002 offcore_response.all_pf_data_rd.l3_miss_local_dram.hitm_other_core ocr.pf_l3_rfo.l3_miss_local_dram.hit_other_core_fwd ocr.pf_l3_data_rd.l3_miss_local_dram.no_snoop_needed ocr.pf_l1d_and_sw.l3_miss.remote_hit_forward period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000010 offcore_response.demand_code_rd.l3_miss_local_dram.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD ALL_READS & L3_MISS & HIT_OTHER_CORE_NO_FWD Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS & REMOTE_HIT_FORWARD This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE ocr.other.l3_miss_local_dram.hitm_other_core offcore_response.all_data_rd.l3_miss.hit_other_core_fwd ocr.demand_rfo.l3_miss.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000080 offcore_response.pf_l2_data_rd.l3_miss.hitm_other_core ocr.pf_l1d_and_sw.l3_miss_local_dram.any_snoop ocr.other.l3_miss_local_dram.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000002 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE offcore_response.all_reads.l3_miss.remote_hitm This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.REMOTE_HITM This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP offcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.snoop_none offcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.snoop_none This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000120 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000001 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000490 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810008000 ocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.no_snoop_needed ocr.demand_code_rd.l3_miss_local_dram.snoop_miss_or_no_fwd Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS & ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000491 ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.no_snoop_needed ocr.pf_l2_data_rd.l3_miss_local_dram.hit_other_core_fwd ALL_PF_DATA_RD & L3_MISS & HIT_OTHER_CORE_NO_FWD offcore_response.demand_data_rd.l3_miss_remote_hop1_dram.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000001 ocr.pf_l2_rfo.l3_miss_local_dram.snoop_none This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD Counts any other requests OTHER & L3_MISS & REMOTE_HITM period=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800001 offcore_response.other.l3_miss.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE offcore_response.all_pf_rfo.l3_miss_local_dram.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS ocr.demand_code_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd offcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.any_snoop ALL_PF_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & SNOOP_NONE Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS & REMOTE_HITM offcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hit_other_core_no_fwd offcore_response.pf_l3_rfo.l3_miss_local_dram.hit_other_core_no_fwd Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_M & NO_SNOOP_NEEDED ALL_READS & L3_HIT_M & NO_SNOOP_NEEDED ALL_READS & L3_HIT_F & SNOOP_MISS ALL_PF_DATA_RD & L3_HIT_M & HIT_OTHER_CORE_NO_FWD ocr.demand_data_rd.l3_hit_e.snoop_none Counts demand data reads DEMAND_DATA_RD & L3_HIT_F & ANY_SNOOP ALL_DATA_RD & L3_HIT_F & ANY_SNOOP ocr.all_pf_rfo.l3_hit_m.hit_other_core_fwd ocr.all_rfo.l3_hit_m.hit_other_core_no_fwd ALL_READS & SUPPLIER_NONE & SNOOP_NONE ocr.all_rfo.pmm_hit_local_pmm.snoop_none Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_M & HIT_OTHER_CORE_NO_FWD Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_M & NO_SNOOP_NEEDED Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_S & HITM_OTHER_CORE ocr.all_pf_data_rd.l3_hit.hit_other_core_fwd Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_M & HIT_OTHER_CORE_FWD ocr.pf_l3_rfo.pmm_hit_local_pmm.any_snoop ocr.other.l3_hit_m.no_snoop_needed Counts all demand data writes (RFOs) hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores ALL_READS & PMM_HIT_LOCAL_PMM & SNOOP_NONE ocr.other.supplier_none.hit_other_core_no_fwd ocr.all_pf_data_rd.l3_hit.any_snoop Counts all demand code reads DEMAND_CODE_RD & PMM_HIT_LOCAL_PMM & SNOOP_NONE ALL_PF_RFO & PMM_HIT_LOCAL_PMM & ANY_SNOOP ocr.other.l3_hit.snoop_none Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_S & HITM_OTHER_CORE Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT & ANY_SNOOP ocr.all_pf_rfo.l3_hit_f.hit_other_core_fwd Counts any other requests OTHER & L3_HIT & ANY_SNOOP ocr.demand_data_rd.supplier_none.hit_other_core_fwd ocr.pf_l2_data_rd.l3_hit_m.any_snoop Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_M & ANY_SNOOP Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_F & ANY_SNOOP ocr.other.l3_hit.no_snoop_needed ocr.pf_l3_rfo.l3_hit_s.no_snoop_needed ALL_RFO & SUPPLIER_NONE & ANY_SNOOP ocr.demand_code_rd.l3_hit.any_snoop ocr.pf_l3_rfo.any_response Counts all demand code reads DEMAND_CODE_RD & L3_HIT_E & HIT_OTHER_CORE_NO_FWD ALL_RFO & L3_HIT_F & SNOOP_NONE ALL_READS & L3_HIT_S & ANY_SNOOP cmask=10,inv=1,period=2000003,umask=0x1,event=0xc0 umask=0xf,event=0x2 umask=0x01,event=0x11 fc_mask=0x07,ch_mask=0x01,umask=0x08,event=0x83 unc_iio_txn_req_of_cpu.peer_read.part2 fc_mask=0x07,ch_mask=0x01,umask=0x02,event=0x84 unc_m2m_imc_writes.ni unc_m2m_rxc_bl_inserts BL Egress (to CMS) Occupancy; All Counts demand requests to L2 cache Counts retired load instructions missed L2 cache as data sources Supports address when precise (Precise event) Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE Counts Unfriendly TSX abort triggered by a vzeroupper instruction Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed umask=0x1,period=2000003,event=0 int_misc.all_recovery_cycles Not taken branch instructions retired (Precise event) Counts not taken branch instructions retired (Precise event) Counts taken conditional mispredicted branch instructions retired Supports address when precise (Precise event) Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses a programmable general purpose performance counter unc_cha_tor_inserts.ia_miss_wcil Data requested of the CPU : Card reading from DRAM. Unit: uncore_iio unc_iio_data_req_of_cpu.mem_write.part4 event=0xff ic_fw32_miss bp_snp_re_sync ic_cache_inval.l2_invalidating_probe All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Request change to writable, check L2 for current state l2_request_g2.smc_inval umask=0x1,event=0x61 l2_latency.l2_cycles_waiting_on_fills LS to L2 WCB zero byte store requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) zero byte store requests Retired Branch Resyncs event=0xca ex_ret_mmx_fp_instr.mmx_instr ex_div_busy umask=0x4D,event=0x8b df_ccm_reqa.node7.wrsizedfullnc df_ccm_reqa.node0.rdsized umask=0x86,event=0x8b df_ccm_reqa.node1.anyrdblk Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdvlkx umask=0x42,event=0x8b df_ccm_reqb.node0.chgtox df_ccm_reqb.node0.vicblkfull. umask=0x4D,event=0x8c umask=0xAD,event=0x8c umask=0x8C,event=0x8c df_ioms_reqa.node7.masterabort df_ioms_reqa.node6.flush umask=0xEA,event=0x108 umask=0xA7,event=0x108 df_ioms_reqa.node4.anywrsized=32b df_ioms_reqa.node0.anyrdsized umask=0x01,event=0x108 umask=0x8D,event=0x109 df_ioms_reqb.node0.anyiotransaction umask=0x8B,event=0x109 Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized=32b umask=0xE8,event=0x109 df_ioms_reqb.node6.ioanypostedwrsized=32 df_ioms_reqb.node0.ioanypostedwrsized<32 fpu_pipe_assignment.dual2 umask=0x2,event=0x2 Double precision multiply FLOPS The number of serializing Ops retired. SSE control word mispredict traps due to mispredictions in RC, FTZ or DAZ, or changes in mask bits l3_request_g1.t5.s0.wrsizednc l3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x02,event=0x1 l3_request_g1.t0.s1.wrsized l3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x04,event=0x1 l3_request_g1.t1.s0.rdsizednc l3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x20,event=0x1 l3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x40,event=0x1 l3_request_g1.t2.s2.rdsized l3fillvicreq.t7.s0.vicblk l3fillvicreq.t5.s3.vicblk l3fillvicreq.t4.s1.chgtox l3fillvicreq.t7.s1.chgtox l3fillvicreq.t0.s0.rdblkc_s_vic l3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x04,event=0x3 l3fillvicreq.t2.s3.rdblkc_s_vic l3fillvicreq.t7.s1.rdblkc_s l3fillvicreq.t5.s2.rdblkc_s l3fillvicreq.t4.s3.rdblkc_s l3fillvicreq.t2.s0.rdblkx_vic l3fillvicreq.t6.s2.rdblkx l3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x40,event=0x3 l3fillvicreq.t3.s1.rdblkl_vic l3fillvicreq.t3.s2.rdblkl_vic l3fillvicreq.t0.s1.rdblkl l3fillvicreq.t7.s2.rdblkl l3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x80,event=0x3 l3victimstate.t3.s0.nol3victimline l3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x01,event=0x9 l3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x02,event=0x9 l3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x02,event=0x9 l3victimstate.t6.s1.none_nol3victimline l3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x02,event=0x9 l3victimstate.t7.s3.none_nol3victimline l3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x04,event=0x9 l3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x08,event=0x9 l3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x10,event=0x9 l3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x20,event=0x9 l3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x20,event=0x9 l3victimstate.t0.s3.m l3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x40,event=0x9 l3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x80,event=0x9 l3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x80,event=0x9 l3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x80,event=0x9 l3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x80,event=0x9 ls_misal_accesses ic_oc_mode_switch.oc_ic_mode_switch umask=0x40,event=0xaf de_dis_dispatch_token_stalls0.alsq1_token_stall umask=0x2,event=0x24 event=0x2c hwpmc FR_RETIRED_TAKEN_BRANCHES DTLB_REFILL L2_STORE_BUFFERABLE PLE_CACHE_LINE_REQ_COMPLETED L1D_CACHE_WB_CLEAN BUS_ACCESS_SHARED BUS_ACCESS_PERIPH L2D_TLB_REFILL TAGCACHE_READ_MISS JTLB_DACCESS DMISS_CYCLES BRANCH_INSNS IP SYNCIOB INSTR_DISPATCHED BRANCH_UNIT_STALL_CYCLES CYCLES_THREE_INSTR_DISPATCHED LS_LM_COMPLETED SS_SM_INSTR_COMPLETED CYCLES_ONE_INSTR_DISPATCHED CACHEABLE_STORE_MERGE_TO_32_BYTES SWITCHES_BETWEEN_PRIV_USER CYCLES_THREE_INSTR_COMPLETED SNOOP_RETRIES RAQ_FULL_CYCLES L1_EXTERNAL_INTERVENTIONS DTQ_FULL_CYCLES BUS_RETRY_DUE_TO_L1_RETRY CYCLES_RUNNING_PURR_INC PMC2_OVERFLOW STALLS_NO_CAQ_OR_COB DECORATED_LOADS count= owner page-miss dimm-turnaround write-to-read-turnaround ls_not_halted_cyc kern.hwpmc.cpuid AuthenticAMD {"type": "map_out" Frontend Summary Total issue-pipeline slots (cstate_pkg@c3\-residency@ / msr@tsc@) * 100 Demand Data Read requests that hit L2 cache RFO requests that hit L2 cache umask=0xe1,period=200003,event=0x24 L2 code requests umask=0xff,period=200003,event=0x24 Not rejected writebacks that hit L2 cache umask=0x1,cmask=1,period=2000003,event=0x48 umask=0x1,period=2000003,event=0x60 offcore_requests_outstanding.all_data_rd Cacheable and noncachaeble code read requests umask=0x12,period=100003,event=0xd0 mem_load_uops_retired.l2_hit This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting excludes unknown and UC data source Supports address when precise (Precise event) mem_load_uops_l3_miss_retired.remote_hitm l2_trans.l2_fill umask=0x20,period=200003,event=0xf0 umask=0x80,period=200003,event=0xf0 umask=0x8,period=100003,event=0xca umask=0x10,period=100003,event=0xca This event counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention umask=0x1e,cmask=1,period=100003,event=0xca This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches umask=0x1,cmask=3,period=2000003,event=0x9c umask=0x2,period=2000003,event=0xab Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:
1. memory disambiguation,
2. external snoop, or
3. cross SMT-HW-thread snoop (stores) hitting load buffer hle_retired.aborted_misc1 rtm_retired.aborted_misc5 mem_trans_retired.load_latency_gt_128 umask=0x8,period=100003,event=0x3 umask=0x0,any=1,period=2000003,event=0x3c Not software-prefetch load dispatches that hit FB allocated for software prefetch Number of SIMD Move Elimination candidate uops that were eliminated This event counts cycles during which the reservation station (RS) is empty for the thread.
Note: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues umask=0x1,period=2000003,event=0x87 umask=0xa0,period=200003,event=0x88 This event counts both taken and not taken speculative and retired branch instructions This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5 umask=0x1,period=2000003,event=0xa8 machine_clears.cycles edge=1,umask=0x1,cmask=1,period=100003,event=0xc3 This event counts the number of mispredicted ret instructions retired.(Precise Event) umask=0x3,event=0x35,filter_opc=0x187 unc_h_requests.writes_remote unc_m_power_channel_ppd umask=0x1,event=0x2 event=0x6 freq_max_os_cycles % Load misses that miss the DTLB and hit the STLB (4K) umask=0x8,period=100003,event=0x49 umask=0x20,period=100003,event=0x49 Store misses that miss the DTLB and hit the STLB (4K) Misses at all ITLB levels that cause page walks Spec update: BDM69 umask=0x14,period=2000003,event=0xbc Number of ITLB page walker hits in the L2 Spec update: BDM69, BDM98 Retiring Instructions per Branch (lower number means higher occurance rate) inst_retired.any / br_inst_retired.near_call 64 * longest_lat_cache.miss / 1000000000 / duration_time offcore_response.demand_data_rd.supplier_none.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0001 offcore_response.demand_code_rd.any_response offcore_response.demand_code_rd.l3_hit.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020008 offcore_response.pf_l2_data_rd.supplier_none.snoop_none offcore_response.pf_l2_data_rd.l3_hit.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020080 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020080 offcore_response.pf_l3_data_rd.supplier_none.snoop_hitm offcore_response.pf_l3_rfo.supplier_none.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0200 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80028000 Counts all prefetch code reads have any response type umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020240 offcore_response.all_rfo.l3_hit.snoop_none Any input SSE* FP Assist - (Precise Event) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000020 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000040 offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_not_needed offcore_response.pf_l3_code_rd.l3_miss.snoop_not_needed offcore_response.other.l3_miss_local_dram.snoop_miss offcore_response.other.l3_miss_local_dram.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020090 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000120 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000091 offcore_response.all_rfo.l3_miss_local_dram.snoop_not_needed offcore_response.all_rfo.l3_miss.snoop_not_needed Unit: uncore_cbox L3 Lookup any request that access cache and found line in M-state Unit: uncore_arb Number of Core coherent Data Read entries allocated in DirectData mode Number of Writes allocated - any write transactions: full/partials writes and evictions This event counts load uops retired to the architected path with a filter on bits 0 and 1 applied.
Note: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement. This event also counts SW prefetches Supports address when precise (Precise event) This event counts retired load uops which data sources were HitM responses from a core on same socket (shared L3) Supports address when precise. Spec update: BDM100 (Precise event) offcore_response.all_reads.llc_hit.hit_other_core_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063BC00091 This event counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight Supports address when precise (Precise event) l2_dbus_busy.self umask=0x42,period=200000,event=0x2c l2_ld_ifetch.self.m_state umask=0x48,period=200000,event=0x2e umask=0x54,period=200000,event=0x2e L2 cache demand requests from this core umask=0x7f,period=200000,event=0x30 simd_uops_exec.ar Retired Streaming SIMD Extensions 2 (SSE2) vector instructions umask=0x8f,period=200000,event=0x5 umask=0x8a,period=200000,event=0x5 Any Software prefetch umask=0xe0,period=200000,event=0x65 Explicit writeback bus transactions bus_trans_ifetch.self bus_trans_pwr.self IO bus transactions umask=0xb,period=200000,event=0x77 store_forwards.good umask=0x7f,period=200000,event=0x3 All indirect calls, including both register and memory indirect Mispredicted return branches uops_retired.any umask=0x2,period=200000,event=0xc4 umask=0x4,period=2000000,event=0xc4 Micro-op reissues on a store-load collision Duration of I-Side page walks umask=0x41,period=200003,event=0xd0 umask=0x10,period=200003,event=0xd1 offcore_response.any_data_rd.l2_miss.snoop_miss_or_no_snoop_needed Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400002000 offcore_response.sw_prefetch.l2_miss.any Counts bus lock and split lock requests that have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts the number of times the prediction (from the predecode cache) for instruction length is incorrect Counts demand reads for ownership (RFO) requests generated by a write to full data cache line have any transaction responses from the uncore subsystem Counts the number of writeback transactions caused by L1 or L2 cache evictions outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cacheline reads generated by hardware L2 cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received Counts reads for ownership (RFO) requests generated by L2 prefetcher true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts bus lock and split lock requests hit the L2 cache offcore_response.full_streaming_stores.any_response offcore_response.sw_prefetch.any_response Counts data cache lines requests by software prefetch instructions have any transaction responses from the uncore subsystem Cycles the code-fetch stalls and an ITLB miss is outstanding Instructions retired (Fixed event) (Must be precise) Page walk completed due to a demand load to a 2M or 4M page Page walks outstanding due to walking the EPT every cycle umask=0x2,period=2000003,event=0x85 All requests to L2 cache Spec update: HSD78 Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue Spec update: HSD78, HSD62, HSD61 Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles Spec update: HSD62, HSD61 offcore_response.all_code_rd.l3_hit.hit_other_core_no_fwd Counts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Instruction Decode Queue (IDQ) empty cycles Spec update: HSD135 Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE Spec update: HSD135 Number of times an HLE execution started umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100400091 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00080 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00010 This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. INST_RETIRED.ANY is counted by a designated fixed counter, leaving the programmable counters available for other events. Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions Spec update: HSD140, HSD143 Cycles which a uop is dispatched on port 4 in this thread Number of uops delivered by the LSD Unit: uncore_cbox An external snoop misses in some processor core A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core umask=0x01,event=0x83 Number of DTLB page walker hits in the L1+FB umask=0x84,period=2000003,event=0xbc page_walker_loads.ept_itlb_memory umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00020 umask=0x8,period=200003,event=0x24 Retired store uops that miss the STLB. (Precise Event) l2_lines_out.pf_dirty Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Counts 256-bit packed single-precision floating-point instructions DSB Fill encountered > 3 DSB lines unc_cbo_xsnp_response.inval_m Filter on processor core initiated cacheable read requests Unit: uncore_arb Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0090 Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0040 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0080 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x67fc00001 offcore_response.demand_data_rd.llc_miss.remote_dram Counts all demand data writes (RFOs) that miss the LLC and the data is found in M state in remote cache and forwarded from there Streaming stores (full cache line). Derived from unc_c_tor_inserts.opcode.streaming_full. Unit: uncore_cbox Read requests to home agent. Unit: uncore_ha unc_q_rxl0p_power_cycles event=0x10 freq_band0_cycles % unc_p_freq_band1_cycles L1D data cache lines in M state evicted due to replacement This event counts all LLC misses for all demand and L2 prefetches. LLC prefetches are excluded umask=0x40,period=2000003,event=0x59 Resource stalls out of order resources full Occupancy counter for memory read queue. Unit: uncore_imc mem_uops_retired.l2_hit_loads Counts all the store micro-ops retired offcore_response.any_read.l2_hit_far_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080022 Counts Demand cacheable data write requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800082000 offcore_response.uc_code_reads.any_response umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000080 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010080 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080020 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080002 Counts demand cacheable data and L1 prefetch data reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002000400 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000022 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008000080 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010008000 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x00100032f7 Counts demand code reads and prefetch code reads that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state Counts Demand cacheable data writes that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode Counts any Read request that accounts for data responses from DRAM Far offcore_response.any_code_rd.mcdram_near offcore_response.pf_software.ddr_far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000200 offcore_response.partial_reads.mcdram_far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400001 Counts the number of mispredicted near indirect CALL branch instructions retired (Precise event) This event counts cycles when the divider is busy. More specifically cycles when the divide unit is unable to accept a new divide uop because it is busy processing a previously dispatched uop. The cycles will be counted irrespective of whether or not another divide uop is waiting to enter the divide unit (from the RS). This event counts integer divides, x87 divides, divss, divsd, sqrtss, sqrtsd event and does not count vector divides recycleq.ld_block_std_notready umask=0x20,period=200003,event=0x3 umask=0x2,period=2000000,event=0x63 l1d.repl umask=0x1,period=2000000,event=0x53 l1d_cache_st.m_state L2 RFO requests l2_transactions.rfo umask=0x40,period=100000,event=0xb0 store_blocks.at_ret umask=0x8,period=200000,event=0x6 mem_inst_retired.latency_above_threshold_32 All offcore data reads umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1844 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3844 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x222 offcore_response.any_rfo.remote_cache Offcore demand code reads that HIT in a remote cache offcore_response.demand_ifetch.remote_cache_hitm Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core offcore_response.demand_rfo.remote_cache offcore_response.demand_rfo.remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F80 offcore_response.other.llc_hit_no_other_core umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1030 offcore_response.pf_data_rd.remote_cache_hitm offcore_response.pf_ifetch.any_cache_dram Offcore prefetch code reads satisfied by the LLC umask=0x1,period=100000,event=0xb7,offcore_rsp=0x840 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x220 offcore_response.prefetch.any_cache_dram All offcore prefetch requests umask=0x1,period=100000,event=0xb7,offcore_rsp=0x170 Offcore prefetch requests satisfied by a remote cache or remote DRAM X87 Floating point assists (Precise Event) fp_assist.output fp_comp_ops_exe.sse_single_precision simd_int_128.packed_shift umask=0x20,period=200000,event=0xfd umask=0x1,period=2000000,event=0xa6 umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF822 Offcore RFO requests that missed the LLC offcore_response.data_ifetch.local_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x6003 umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF804 umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF810 umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF870 baclear.bad_target Branch instructions executed br_inst_exec.cond br_misp_exec.non_calls Mispredicted taken branches executed umask=0x1,period=2000000,event=0x17 umask=0x2,period=200000,event=0xc7 umask=0x10,period=200000,event=0xc7 uops_executed.port2_core umask=0x80,any=1,period=2000000,event=0xb1 inv=1,umask=0x1,any=1,period=2000000,cmask=1,event=0xe Retired load instructions that miss the STLB. (Precise Event) Supports address when precise umask=0x4,period=200003,event=0xf2 Counts the number of lines that have been hardware prefetched but not used and now evicted by L2 cache offcore_response.other.l4_hit_local_l4.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10001C8000 offcore_response.other.l3_hit_e.snoop_none offcore_response.demand_code_rd.l3_hit_e.spl_hit offcore_response.demand_rfo.l4_hit_local_l4.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01001C0002 offcore_response.demand_rfo.l3_hit_s.any_snoop offcore_response.demand_rfo.l3_hit_s.snoop_hitm offcore_response.demand_rfo.l3_hit_s.snoop_none offcore_response.demand_rfo.l3_hit_m.any_snoop offcore_response.demand_rfo.l3_hit_m.snoop_miss offcore_response.demand_data_rd.l3_hit_m.snoop_none Retired Instructions who experienced Instruction L1 Cache true miss. Precise Event (Precise event) frontend_retired.latency_ge_256 umask=0x10,period=2000003,cmask=1,event=0x60 hle_retired.aborted_timer offcore_response.other.l3_miss.snoop_non_dram offcore_response.other.l3_miss.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C400004 offcore_response.demand_code_rd.l3_miss.spl_hit Counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, Counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions umask=0x1,any=1,period=2503,event=0x3c umask=0x1,period=2000003,event=0x59 This is a precise version (that is, uses PEBS) of the event that counts both direct and indirect near call instructions retired Spec update: SKL091 (Precise event) 1000 * mem_load_retired.l2_miss / inst_retired.any Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 2M/4M pages. The page walks can end with or without a page fault umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200008008 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680000010 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680000004 Counts the number of times entered into a ucode flow in the FEC. Includes inserted flows due to front-end detected faults or assists. Speculative count ALL_BRANCHES counts the number of any branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) Counts the number of cycles when no uops are allocated, the IQ is empty, and no other condition is blocking allocation Counts the number of cycles when no uops are allocated for any reason Retired load uops that split across a cacheline boundary. (Precise Event - PEBS) (Precise event) Retired load uops with L2 cache hits as data sources. (Precise Event - PEBS) (Precise event) offcore_response.all_pf_code_rd.llc_hit.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0002 offcore_response.pf_l2_rfo.llc_hit.hitm_other_core umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0020 Counts all prefetch (that bring data to LLC only) data reads that hit in the LLC Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded REQUEST = PF_LLC_IFETCH and RESPONSE = ANY_RESPONSE Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from dram umask=0x8,period=2000000,cmask=1,event=0x60 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5008 REQUEST = DATA_IN and RESPONSE = IO_CSR_MMIO REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITM REQUEST = DEMAND_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT REQUEST = PREFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE REQUEST = PREFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3011 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3033 umask=0x1,period=100000,event=0xb7,offcore_rsp=0xf801 REQUEST = DEMAND_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD REQUEST = OTHER and RESPONSE = REMOTE_DRAM REQUEST = PF_DATA and RESPONSE = ANY_DRAM AND REMOTE_FWD REQUEST = PF_RFO and RESPONSE = ANY_LLC_MISS dtlb_load_misses.walk_cycles dtlb_misses.pde_miss ITLB miss large page walks Offcore uncached memory accesses inv=1,umask=0x1f,period=2000000,cmask=1,edge=1,event=0xb1 Retired load instructions which data sources missed L3 but serviced from local dram Supports address when precise (Precise event) offcore_response.pf_l2_data_rd.l3_hit.no_snoop_needed Counts all prefetch (that bring data to LLC only) data reads TBD TBD offcore_response.pf_l1d_and_sw.l3_hit.hitm_other_core umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0490 offcore_response.pf_l2_data_rd.l3_miss.remote_hit_forward offcore_response.pf_l3_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd offcore_response.pf_l3_rfo.l3_miss.snoop_miss_or_no_fwd offcore_response.pf_l1d_and_sw.l3_miss.remote_hit_forward offcore_response.all_data_rd.l3_miss.remote_hit_forward offcore_response.all_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd umask=0x10,cmask=16,period=2000003,event=0xa3 1000 * l2_lines_out.silent / inst_retired.any event=0x20 umask=0x02,event=0x53 unc_cha_requests.invitoe_local Local requests for exclusive ownership of a cache line without receiving data. Unit: uncore_cha unc_cha_snoop_resp.rspi Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part2 by a unit on the main die (generally a core). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.mem_read.part2 Traffic in which the M2M to iMC Bypass was not taken. Unit: uncore_m2m Counts when messages were sent direct to core (bypassing the CHA) Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory to a new state unc_m2m_imc_reads.all unc_m2m_rxc_ad_inserts unc_upi_direct_attempts.d2c Cycles the Rx of the Intel UPI is in L0p power mode. Unit: uncore_upi ll Counts incoming FLITs (FLow control unITs) which bypassed the slot0 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency umask=0x0F,event=0x3 Valid data FLITs received from any slot. Unit: uncore_upi ll Counts protocol header and credit FLITs (80 bit FLow control unITs) transmitted across any of the 3 UPI (Ultra Path Interconnect) slots on this UPI unit This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD offcore_response.pf_l2_rfo.l3_hit_s.hitm_other_core This event is deprecated. Refer to new event OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE offcore_response.all_rfo.supplier_none.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD Retired store instructions that split across a cacheline boundary Supports address when precise (Precise event) Counts retired store instructions that split across a cacheline boundary Supports address when precise (Precise event) period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100490 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200400 offcore_response.pf_l2_rfo.l3_hit_m.any_snoop This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0120 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200490 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400004 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED offcore_response.pf_l3_rfo.l3_hit_s.hitm_other_core This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0001 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040122 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F801007F7 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100002 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE offcore_response.pf_l3_rfo.l3_hit_e.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040100 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_NONE offcore_response.all_pf_data_rd.l3_hit_e.any_snoop offcore_response.pf_l2_rfo.l3_hit_e.no_snoop_needed This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0080 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040010 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040080 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0002 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400100 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400010 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800088000 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200400 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020491 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000048000 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100001 Average 3DXP Memory Bandwidth Use for reads [GB / sec] Average 3DXP Memory Bandwidth Use for Writes [GB / sec] Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall (Precise event) offcore_response.pf_l3_rfo.l3_miss.no_snoop_needed This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE offcore_response.all_reads.l3_miss_local_dram.hitm_other_core This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS & HIT_OTHER_CORE_FWD offcore_response.other.l3_miss_remote_hop1_dram.hit_other_core_no_fwd offcore_response.all_pf_rfo.l3_miss_local_dram.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000400 Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS & SNOOP_NONE ALL_PF_RFO & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_NO_FWD ALL_PF_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & NO_SNOOP_NEEDED ocr.all_rfo.l3_miss_remote_hop1_dram.any_snoop ocr.all_pf_rfo.l3_miss_remote_hop1_dram.hitm_other_core ALL_PF_RFO & L3_MISS_REMOTE_HOP1_DRAM & HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000080 ocr.all_rfo.l3_miss.remote_hit_forward Counts all demand data writes (RFOs) DEMAND_RFO & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800080 offcore_response.other.l3_miss_remote_dram.snoop_miss_or_no_fwd ocr.demand_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd ocr.demand_rfo.l3_miss_local_dram.hit_other_core_no_fwd ocr.all_pf_rfo.l3_miss_remote_hop1_dram.any_snoop ALL_READS & L3_MISS_REMOTE_HOP1_DRAM & HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000004 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD ALL_PF_RFO & L3_MISS & NO_SNOOP_NEEDED ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.no_snoop_needed This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE ALL_PF_RFO & L3_MISS & HITM_OTHER_CORE Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS & ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD period=20011,umask=0x1,event=0xcd,ldlat=0x10 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.ANY_SNOOP offcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.hitm_other_core offcore_response.all_reads.l3_miss.hitm_other_core This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE ALL_PF_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NONE This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.REMOTE_HIT_FORWARD ALL_DATA_RD & L3_MISS_LOCAL_DRAM & NO_SNOOP_NEEDED offcore_response.pf_l1d_and_sw.l3_miss.hitm_other_core This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD ALL_READS & L3_MISS_REMOTE_HOP1_DRAM & NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED ALL_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & NO_SNOOP_NEEDED ocr.pf_l2_data_rd.l3_miss_local_dram.snoop_miss ALL_PF_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_FWD Counts any other requests OTHER & SUPPLIER_NONE & HITM_OTHER_CORE ALL_PF_RFO & L3_HIT_S & HIT_OTHER_CORE_FWD Counts demand data reads DEMAND_DATA_RD & L3_HIT & SNOOP_MISS ALL_PF_RFO & L3_HIT_E & HIT_OTHER_CORE_NO_FWD ocr.all_pf_rfo.l3_hit_e.hit_other_core_fwd ocr.pf_l3_rfo.l3_hit.snoop_hit_with_fwd ocr.pf_l3_data_rd.l3_hit_s.any_snoop ocr.other.supplier_none.snoop_miss ALL_DATA_RD & L3_HIT_E & NO_SNOOP_NEEDED ocr.all_rfo.l3_hit.no_snoop_needed Counts demand data reads DEMAND_DATA_RD & SUPPLIER_NONE & NO_SNOOP_NEEDED ocr.pf_l2_rfo.l3_hit.any_snoop ocr.all_pf_data_rd.l3_hit_f.snoop_miss Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & PMM_HIT_LOCAL_PMM & SNOOP_NONE ALL_PF_RFO & L3_HIT & NO_SNOOP_NEEDED ALL_PF_RFO & L3_HIT_E & SNOOP_MISS ocr.pf_l3_rfo.supplier_none.hit_other_core_fwd ocr.all_pf_data_rd.l3_hit_m.no_snoop_needed Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT & SNOOP_MISS ocr.demand_data_rd.l3_hit_f.no_snoop_needed ALL_PF_DATA_RD & L3_HIT & NO_SNOOP_NEEDED ocr.all_data_rd.l3_hit.any_snoop ocr.all_reads.l3_hit_f.any_snoop ALL_PF_DATA_RD & L3_HIT_E & SNOOP_NONE Counts all demand data writes (RFOs) DEMAND_RFO & SUPPLIER_NONE & ANY_SNOOP ocr.all_rfo.l3_hit.snoop_none ocr.pf_l3_rfo.supplier_none.hit_other_core_no_fwd ocr.demand_data_rd.supplier_none.hitm_other_core ocr.all_rfo.l3_hit.hit_other_core_fwd ocr.pf_l1d_and_sw.l3_hit_e.hitm_other_core Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & PMM_HIT_LOCAL_PMM & ANY_SNOOP ocr.pf_l1d_and_sw.supplier_none.hit_other_core_fwd Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_S & ANY_SNOOP ocr.pf_l2_rfo.l3_hit_m.hit_other_core_no_fwd Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_E & NO_SNOOP_NEEDED Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & SUPPLIER_NONE & HIT_OTHER_CORE_FWD ocr.demand_data_rd.l3_hit_m.hitm_other_core Counts demand data reads DEMAND_DATA_RD & PMM_HIT_LOCAL_PMM & ANY_SNOOP Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT & HITM_OTHER_CORE ocr.demand_data_rd.l3_hit.snoop_hit_with_fwd ocr.other.l3_hit_e.snoop_miss Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & SUPPLIER_NONE & HIT_OTHER_CORE_FWD Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_M & HITM_OTHER_CORE Counts demand data reads DEMAND_DATA_RD & PMM_HIT_LOCAL_PMM & SNOOP_NONE ocr.demand_code_rd.l3_hit_e.no_snoop_needed Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_S & HIT_OTHER_CORE_NO_FWD ocr.pf_l3_data_rd.l3_hit.snoop_hit_with_fwd ALL_PF_DATA_RD & L3_HIT_S & NO_SNOOP_NEEDED Counts demand data reads DEMAND_DATA_RD & L3_HIT_E & HIT_OTHER_CORE_NO_FWD ocr.all_rfo.l3_hit_f.snoop_none ocr.pf_l2_data_rd.supplier_none.hit_other_core_fwd ocr.all_reads.l3_hit_s.snoop_miss cmask=2,period=2000003,umask=0x1,event=0xb1 period=2000003,umask=0x2,event=0xa1 period=400009,umask=0x20,event=0xc4 unc_m_pmm_rpq_inserts All DRAM Read CAS Commands issued (does not include underfills). Unit: uncore_imc unc_cha_llc_victims.total_m unc_cha_sf_eviction.e_state Peer to peer read request for 4 bytes made by IIO Part0 to an IIO target. Unit: uncore_iio Counts every peer to peer read request for 4 bytes of data made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part3. Unit: uncore_iio Peer to peer write request of up to a 64 byte transaction is made to IIO Part3 by a different IIO unit. Unit: uncore_iio umask=0x20,event=0x38 unc_m2m_rxc_bl_occupancy Clean line underfill read hits to Near Memory(DRAM cache) in Memory Mode. Unit: uncore_m2m unc_m2m_txc_ad_occupancy umask=0x4,period=2000003,event=0x48 Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache Supports address when precise (Precise event) Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle Counts the number of times an HLE execution aborted due to unfriendly events (such as interrupts) Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event uops_dispatched.port_7_8 Counts both direct and indirect near call instructions retired (Precise event) umask=0x11,period=400009,event=0xc5 Counts mispredicted conditional branch instructions retired Supports address when precise (Precise event) Counts number of retired PAUSE instructions (that do not end up with a VMExit to the VMM; TSX aborted Instructions may be counted) ocr.demand_data_rd.l3_miss Counts all demand reads for ownership (RFO) requests and software based prefetches for exclusive ownership (PREFETCHW) that was not supplied by the L3 cache Counts the number of unhalted reference clock cycles at TSC frequency period=2000003,event=0xcd unc_cha_tor_inserts.ia_miss_drd_opt l2_request_g1.rd_blk_l Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request miss in L2 event=0xc7 Div Op Count df_ccm_reqa.node5.anydram df_ccm_reqa.node0.wrsizedfullzero df_ccm_reqa.node6.wrsized umask=0x6B,event=0x8b umask=0xAB,event=0x8b umask=0x4A,event=0x8b df_ccm_reqa.node4.rdsized umask=0x44,event=0x8b umask=0x02,event=0x8b umask=0xAE,event=0x8c umask=0x07,event=0x8c umask=0x83,event=0x8c df_ccm_reqb.node1.rdsized umask=0x65,event=0x108 df_ioms_reqa.node4.largeread df_ioms_reqb.node0.pieiorequest umask=0xEB,event=0x109 df_ioms_reqb.node6.ioanynon-postedwrsized=64b umask=0xC7,event=0x109 umask=0x06,event=0x109 df_ioms_reqb.node2.ioanypostedwrsized=64b umask=0x62,event=0x109 umask=0x10,event=0x3 umask=0x8,event=0x3 Number of SSE Move Ops eliminated This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes. Number of SSE Move Ops eliminated l3_request_g1.t2.s0.wrsizednc l3_request_g1.t7.s1.wrsizednc l3_request_g1.t3.s0.wrsized l3_request_g1.t1.s2.wrsized l3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x04,event=0x1 l3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x04,event=0x1 l3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x20,event=0x1 l3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x20,event=0x1 l3_request_g1.t7.s3.rdsizednc l3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x40,event=0x1 l3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x80,event=0x1 l3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x80,event=0x1 l3_request_g1.t2.s3.caching l3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x01,event=0x3 l3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x01,event=0x3 l3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x01,event=0x3 l3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x02,event=0x3 l3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x04,event=0x3 l3fillvicreq.t7.s1.rdblkc_s_vic l3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x08,event=0x3 l3fillvicreq.t3.s1.rdblkx_vic l3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x20,event=0x3 l3fillvicreq.t3.s1.rdblkx l3fillvicreq.t4.s2.rdblkx l3fillvicreq.t7.s3.rdblkx l3fillvicreq.t5.s1.rdblkl_vic l3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x40,event=0x3 l3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x40,event=0x3 l3fillvicreq.t2.s3.rdblkl_vic l3fillvicreq.t4.s2.rdblkl l3victimstate.t0.s0.nol3victimline l3victimstate.t6.s0.nol3victimline l3victimstate.t7.s3.nol3victimline l3victimstate.t2.s3.none_nol3victimline l3victimstate.t5.s1.f_s l3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x04,event=0x9 l3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x08,event=0x9 l3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x08,event=0x9 l3victimstate.t4.s2.o l3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x08,event=0x9 l3victimstate.t3.s0.e_fe l3victimstate.t4.s1.d l3victimstate.t3.s3.d umask=0x4,event=0x4b bp_l1_tlb_miss_l2_tlb_miss.if2m fp_ret_sse_avx_ops.mult_flops ls_locks.non_spec_lock ls_refills_from_sys.ls_mabresp_rmt_dram All TLB Flushes Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Taken branch buffer resource stall LS_LOCKED_OPERATION FR_RETIRED_FAR_CONTROL_TRANSFERS FR_DISPATCH_STALL_FROM_BRANCH_ABORT_TO_RETIRE FR_DISPATCH_STALL_WHEN_REORDER_BUFFER_IS_FULL L1_DCACHE_REFILL L2_CACHE_WB MEM_REPLAY_EVT L1_ICACHE_HASH_MISS L1_CACHE_ACCESS_NOCP15 L2D_CACHE_REFILL_LD DCACHE_WRITE_MISS L2CACHE_WRITE_HIT MEM_DWORD_WRITE NOP_COMPLETED WBB_FULL_PIPELINE_STALLS L2_CACHE_ACCESSES STORE_INSNS OCP_READ_REQUESTS OCP_READ_CACHEABLE_REQUESTS FSB_LESS_25_FULL WBUFTR IU2_INSTR_COMPLETED L1_DATA_SNOOP_HIT_CASTOUT L1_DATA_TOUCH_HIT DTLB_MISSES L1_DATA_CACHE_OP_HIT VT2_FETCHES IU1_INSTR_COMPLETED L2_INSTR_CACHE_MISSES WAQ_FULL_CYCLES EXTERNAL_SNOOP_RETRY L2_LINEFILL_BUFFER STASH_L1_HITS INSTR_LFB_WENT_HIGH_PRIORITY SNOOP_THROTTLING_TURNED_ON k8-fr-retired-taken-branches k8-fr-taken-hardware-interrupts add-pipe-junk-ops postwrszdword INTEL_NEHALEM_EX INTEL_HASWELL_XEON pmclog_read unknown event event: %s
LLC-REFERENCE frontend_retired.l1i_miss regex '%s' failed to compile, ignoring
l3_slice_mask v13 HygonGenuine-24-00 CORE_CLKS l1d_pend_miss.pending This event counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation) Spec update: BDM76 This event counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS Spec update: BDM76 This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION) Demand and prefetch data reads Retired load uops with locked access. (Precise Event - PEBS) Supports address when precise. Spec update: BDM35 (Precise event) This is a precise version (that is, uses PEBS) of the event that counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K) Supports address when precise (Precise event) mem_load_uops_l3_hit_retired.xsnp_hitm Retired load uop whose Data Source was: forwarded from remote cache (Precise Event) Supports address when precise. Spec update: BDE70 umask=0x1,period=200003,event=0xf0 This event counts L2 writebacks that access L2 cache umask=0x10,period=100003,event=0xf4 Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element fp_arith_inst_retired.double Cycles with any input/output SSE or FP assist idq.all_dsb_cycles_any_uops Number of times RTM commit succeeded Number of times the TSX watchdog signaled an RTM abort Number of times a disallowed operation caused an RTM abort Loads with latency value being above 16 Spec update: BDM100, BDM35 (Must be precise) This event counts loads with latency value being above 32 Spec update: BDM100, BDM35 (Must be precise) edge=1,umask=0x1,cmask=1,period=100007,event=0x5c arith.fpu_div_active br_misp_exec.taken_conditional Cycles per core when uops are dispatched to port 2 Cycles per thread when uops are executed in port 4 uops_executed_port.port_4 cycle_activity.stalls_total Cycles 4 Uops delivered by the LSD, but didn't come from the decoder This is a precise version (that is, uses PEBS) of the event that counts instructions retired Spec update: BDM11, BDM55 (Must be precise) umask=0x1f,period=100003,event=0xe6 (unc_p_freq_max_os_cycles / unc_p_clockticks) * 100. event=0x5 dtlb_store_misses.miss_causes_a_walk This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault Spec update: BDM69 dtlb_store_misses.stlb_hit This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific) Backend_Bound Branches;PGO FLOPS offcore_response.demand_rfo.l3_hit.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010004 offcore_response.demand_code_rd.l3_hit.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020010 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020010 offcore_response.pf_l2_data_rd.supplier_none.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020010 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020100 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020100 offcore_response.pf_l3_rfo.l3_hit.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020090 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0120 offcore_response.all_rfo.l3_hit.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020004 offcore_response.demand_code_rd.l3_miss_local_dram.snoop_non_dram offcore_response.corewb.l3_hit.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000008 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020010 offcore_response.pf_l2_data_rd.l3_hit.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000020 offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_non_dram offcore_response.pf_l3_data_rd.supplier_none.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000080 offcore_response.all_pf_data_rd.l3_miss_local_dram.any_snoop offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000120 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000240 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000091 umask=0x2,period=2000003,cmask=2,event=0xa3 umask=0x21,event=0x34 Unit: uncore_cbox L3 Lookup any request that access cache and found line in I-state Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc This event counts store uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault Supports address when precise (Precise event) Retired load uops which data sources were HitM responses from shared L3 Supports address when precise. Spec update: BDM100 (Precise event) offcore_response.pf_llc_rfo.llc_hit.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063BC007F7 offcore_response.all_data_rd.llc_miss.local_dram offcore_response.demand_rfo.llc_miss.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00002 This event counts both direct and indirect macro near call instructions retired (captured in ring 3) (Precise event) Cycles the L2 cache data bus is busy l2_lines_out.self.any l2_m_lines_out.self.prefetch umask=0x52,period=200000,event=0x29 umask=0x42,period=200000,event=0x2a umask=0x4f,period=200000,event=0x2a umask=0x41,period=200000,event=0x2b umask=0x42,period=200000,event=0x2b l2_rqsts.self.demand.m_state l2_reject_busq.self.demand.i_state l2_reject_busq.self.prefetch.e_state umask=0x81,period=2000000,event=0x10 simd_uop_type_exec.logical.ar SIMD packed logical micro-ops retired umask=0x0,period=2000000,event=0xce umask=0x92,period=200000,event=0x5 Streaming SIMD Extensions (SSE) PrefetchT1 instructions executed prefetch.prefetchnta bus_bnr_drv.this_agent bus_trans_io.self bus_trans_any.all_agents umask=0x11,period=200000,event=0x89 umask=0xf,period=2000000,event=0xc4 reissue.overlap_store umask=0x6,period=200000,event=0x8 Duration of D-side only page walks L1 Cache evictions for dirty data umask=0x2,period=200003,event=0xd1 Load uops retired that missed L1 data cache (Precise event capable) Supports address when precise (Must be precise) Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200003010 offcore_response.any_request.l2_miss.hitm_other_core Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_request.l2_hit umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000018000 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000044800 Counts data cache line reads generated by hardware L1 data cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.full_streaming_stores.l2_miss.snoop_miss_or_no_snoop_needed offcore_response.partial_writes.l2_miss.any offcore_response.pf_l2_rfo.l2_miss.hitm_other_core Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400000008 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600000001 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200000001 Counts demand cacheable data reads of full cache lines that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) umask=0x2,period=200003,event=0x3 Duration of I-side pagewalks in cycles umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010004 Counts the number of writeback transactions caused by L1 or L2 cache evictions true miss for the L2 cache with a snoop miss in the other processor module umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000020 Counts data cache line reads generated by hardware L1 data cache prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_request.outstanding Counts data reads generated by L1 or L2 prefetchers outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Demand data read requests that missed L2, no rejects Spec update: HSD78 Retired load uops with L1 cache hits as data sources Spec update: HSD29, HSM30. Supports address when precise (Precise event) Retired load uops which data sources were HitM responses from shared L3 Spec update: HSD29, HSD25, HSM26, HSM30. Supports address when precise (Precise event) umask=0x1,period=100003,event=0xd3 This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches. This is a precise event Spec update: HSD74, HSD29, HSD25, HSM30. Supports address when precise offcore_response.all_data_rd.l3_hit.hit_other_core_no_fwd Counts prefetch (that bring data to L2) data reads miss in the L3 Any uop executed by the Divider. (This includes all divide uops, sqrt, ...) Stall cycles because IQ is full Cycles per core when uops are executed in port 6 Counts the number of far branch instructions retired (Precise event) L3 Lookup write request that access cache and found line in I-state Unit: uncore_cbox L3 Lookup external snoop request that access cache and found line in E or S-state Number of ITLB page walker hits in the L1+FB umask=0x1,period=100003,event=0xbd Retired store uops that miss the STLB Supports address when precise. Spec update: HSD29, HSM30 (Precise event) offcore_response.demand_data_rd.llc_hit.hit_other_core_no_fwd offcore_response.pf_l2_data_rd.llc_hit.any_response Number of SIMD FP assists due to output values Not rejected writebacks from L1D to L2 cache lines in E state Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles Retired load uops with L1 cache hits as data sources (Precise event) offcore_response.all_data_rd.llc_hit.no_snoop_needed offcore_response.all_reads.any_response Unit: uncore_cbox Filter on cross-core snoops initiated by this Cbox due to external snoop request umask=0x80,event=0x22 unc_cbo_cache_lookup.write_filter Unit: uncore_cbox Filter on external snoop requests Filter on external snoop requests Cycles weighted by number of requests pending in Coherency Tracker umask=0xc,period=100007,event=0xd3 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0091 Counts prefetch (that bring data to LLC only) data reads that miss in the LLC llc_references.itom_write umask=0x2A,event=0x36 unc_c_tor_occupancy.miss_remote Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. (filter_band0=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Unit: uncore_pcu (unc_p_freq_band3_cycles / unc_p_clockticks) * 100. event=0xc,edge=1 This event counts the number of load uops retired (Precise event) umask=0x5,period=100003,cmask=1,event=0xbf Increments the number of flags-merge uops in flight each cycle Mispredicted not taken branch instructions retired (Precise event) Counts the number of load micro-ops retired that hit in the L2 Supports address when precise (Precise event) This event counts the number of store micro-ops retired umask=0x1,period=100007,event=0xb7,offcore_rsp=0x08004032f7 Counts any request that accounts for any response umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800401000 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400400 Counts UC code reads (valid only for Outstanding response type) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400100 offcore_response.pf_l2_code_rd.outstanding offcore_response.demand_rfo.l2_hit_far_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400002 offcore_response.pf_l2_rfo.l2_hit_this_tile_m Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses which hit its own tile's L2 with data in M state offcore_response.demand_rfo.l2_hit_this_tile_e offcore_response.any_rfo.l2_hit_this_tile_e offcore_response.demand_rfo.l2_hit_this_tile_s umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008000022 offcore_response.bus_locks.l2_hit_this_tile_f Counts Demand cacheable data write requests that accounts for responses which hit its own tile's L2 with data in F state umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800180070 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800400080 Counts any Prefetch requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400022 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101002000 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200400 Counts Bus locks and split lock requests that accounts for data responses from DRAM Far offcore_response.pf_l2_rfo.mcdram_far Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Local offcore_response.demand_code_rd.mcdram umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181800040 This event counts the number of scalar SSE, AVX, AVX2, AVX-512 micro-ops retired (floating point, integer and store) except for loads (memory-to-register mov-type micro ops), division, sqrt umask=0x1,period=2000000,event=0x43 umask=0x8,period=100000,event=0xf2 l2_rqsts.ld_hit l2_write.rfo.m_state Load instructions retired IO (Precise Event) Memory instructions retired above 32 clocks (Precise Event) Memory instructions retired above 512 clocks (Precise Event) umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1811 offcore_response.any_request.any_location offcore_response.any_request.llc_hit_no_other_core umask=0x1,period=100000,event=0xb7,offcore_rsp=0x8022 offcore_response.corewb.local_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x808 Offcore code or data read requests satisfied by the LLC and not found in a sibling core umask=0x1,period=100000,event=0xb7,offcore_rsp=0x877 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x833 offcore_response.demand_data.remote_cache_hit Offcore demand data reads satisfied by the LLC and not found in a sibling core offcore_response.demand_data_rd.local_cache Offcore demand data reads satisfied by a remote cache Offcore demand code reads satisfied by the LLC and HITM in a sibling core offcore_response.pf_data_rd.any_cache_dram Offcore prefetch code reads satisfied by the LLC and not found in a sibling core offcore_response.prefetch.llc_hit_other_core_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1070 fp_assist.input simd_int_128.packed_mpy simd_int_64.unpack two_uop_insts_decoded umask=0x1,period=100000,event=0xb7,offcore_rsp=0x6044 offcore_response.any_ifetch.any_llc_miss offcore_response.any_request.any_dram offcore_response.corewb.any_llc_miss offcore_response.prefetch.any_dram Offcore prefetch requests satisfied by any DRAM umask=0x1,period=2000000,event=0xe5 Branch prediction unit missed call or return ROB read port stalls cycles umask=0x1,period=200000,event=0x88 umask=0x10,period=20000,event=0x88 umask=0x30,period=2000,event=0x89 Mispredicted return branches executed umask=0x2,period=2000,event=0xc5 inst_queue_write_cycles Cycles when uops were delivered by the LSD inv=1,umask=0x1,period=2000000,cmask=1,event=0xa8 umask=0x1,period=2000000,event=0xa2 umask=0x2,period=2000000,cmask=1,event=0xd1 umask=0x2,period=2000000,event=0xb1 Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200408000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01001C0004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0100004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0040004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400040004 offcore_response.demand_rfo.l3_hit_m.snoop_none offcore_response.demand_rfo.supplier_none.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040020002 offcore_response.demand_data_rd.l4_hit_local_l4.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400100001 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000080001 umask=0x1,period=100007,event=0xc6,frontend=0x12 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall. Precise Event (Precise event) Retired instructions that are fetched after an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall. Precise Event (Precise event) Unfriendly TSX abort triggered by a vzeroupper instruction cycle_activity.cycles_l3_miss Execution stalls while L3 cache miss demand load is outstanding hle_retired.aborted_events rtm_retired.aborted_unfriendly Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles (Must be precise) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C408000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0044008000 offcore_response.other.l3_hit_s.snoop_non_dram offcore_response.other.l3_hit_e.snoop_non_dram Counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when:a. preceding store conflicts with the load (incomplete overlap),b. store forwarding is impossible due to u-arch limitations,c. preceding lock RMW operations are not forwarded,d. store has the no-forward bit set (uncacheable/page-split/masked stores),e. all-blocking stores are used (mostly, fences and port I/O), and others.The most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events. See the table of not supported store forwards in the Optimization Guide Core crystal clock cycles when at least one thread on the physical core is unhalted Counts cycles during which the reservation station (RS) is empty for the thread.; Note: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk Instruction fetch requests that miss the ITLB and hit the STLB Loads missed UTLB This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K). (Precise Event - PEBS) (Precise event) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0240 offcore_response.pf_llc_code_rd.llc_hit.snoop_miss offcore_response.pf_llc_rfo.llc_hit.hitm_other_core Counts all demand data reads Counts all prefetch (that bring data to LLC only) data reads that miss the LLC and the data returned from dram offcore_response.demand_ifetch.llc_miss_local.dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1f80400040 This event counts the number of retirement slots used each cycle. There are potentially 4 slots that can be used each cycle - meaning, 4 micro-ops or 4 instructions could retire each cycle. This event is used in determining the 'Retiring' category of the Top-Down pipeline slots characterization. (Precise Event - PEBS) (Precise event) umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f44 offcore_response.any_ifetch.local_dram_and_remote_cache_hit offcore_response.any_request.all_local_dram_and_remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0xffff offcore_response.corewb.local_dram_and_remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f01 REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITM umask=0x1,period=100000,event=0xb7,offcore_rsp=0x8050 REQUEST = PF_DATA and RESPONSE = LOCAL_CACHE REQUEST = PF_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f20 REQUEST = PF_IFETCH and RESPONSE = ANY_CACHE_DRAM Misaligned store references REQUEST = ANY_DATA read and RESPONSE = OTHER_LOCAL_DRAM REQUEST = DATA_IFETCH and RESPONSE = OTHER_LOCAL_DRAM REQUEST = OTHER and RESPONSE = OTHER_LOCAL_DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4050 snoopq_requests_outstanding.invalidate Outstanding snoop invalidate requests DTLB load miss large page walks umask=0x10,period=2000000,event=0x4f umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2711 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5802 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5880 offcore_response.demand_data_rd.l3_miss.remote_hit_forward umask=0x1,period=100003,event=0xb7,offcore_rsp=0x083FC00004 offcore_response.pf_l3_data_rd.l3_miss.snoop_miss_or_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBC000100 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063B800120 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x103FC00122 Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule core_power.throttle cha@event\=0x36\\\,umask\=0x21@ / cha@event\=0x36\\\,umask\=0x21\\\,thresh\=1@ read requests from home agent. Unit: uncore_cha 4Bytes fc_mask=0x07,ch_mask=0x08,umask=0x01,event=0x83 Normal priority reads issued to the memory controller from the CHA. Unit: uncore_cha RspIFwd Snoop Responses Received. Unit: uncore_cha umask=0x08,event=0x5c unc_iio_data_req_by_cpu.mem_write.part3 unc_iio_txn_req_of_cpu.mem_read.part0 Multi-socket cacheline Directory lookups (any state found). Unit: uncore_m2m umask=0x20,event=0x2e umask=0x1,event=0x31 unc_upi_txl_flits.all_null offcore_response.all_data_rd.l3_hit_m.any_snoop This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08000807F7 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020080 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE offcore_response.all_rfo.l3_hit_e.snoop_miss This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0001 offcore_response.demand_rfo.l3_hit_s.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l2_rfo.l3_hit_m.hit_other_core_no_fwd offcore_response.pf_l3_data_rd.l3_hit_f.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE offcore_response.all_pf_rfo.l3_hit_s.any_snoop This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD offcore_response.demand_code_rd.pmm_hit_local_pmm.snoop_not_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08000407F7 offcore_response.all_reads.supplier_none.snoop_none This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.ANY_RESPONSE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0010 period=100003,umask=0x41,event=0x2e offcore_response.all_pf_data_rd.l3_hit_f.snoop_none offcore_response.pf_l3_data_rd.l3_hit_f.snoop_miss offcore_response.all_pf_rfo.l3_hit_m.hitm_other_core offcore_response.pf_l2_data_rd.l3_hit_m.hitm_other_core This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_MISS offcore_response.all_rfo.l3_hit_m.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100122 offcore_response.pf_l3_data_rd.l3_hit_f.hitm_other_core This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100002 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED offcore_response.pf_l1d_and_sw.l3_hit_f.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0002 offcore_response.other.l3_hit_e.hitm_other_core This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD Retired load instructions that split across a cacheline boundary Supports address when precise (Precise event) period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C07F7 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020001 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020400 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040100 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020001 offcore_response.all_rfo.l3_hit.hit_other_core_fwd offcore_response.pf_l3_data_rd.l3_hit_m.any_snoop offcore_response.pf_l2_data_rd.pmm_hit_local_pmm.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200004 offcore_response.pf_l3_data_rd.l3_hit_e.hit_other_core_no_fwd offcore_response.other.l3_hit.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0100 offcore_response.pf_l3_rfo.l3_hit_s.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS offcore_response.all_data_rd.l3_hit_f.hit_other_core_fwd offcore_response.pf_l3_data_rd.l3_hit_e.hitm_other_core This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040004 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040491 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080400 offcore_response.all_data_rd.l3_hit_f.snoop_none This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD offcore_response.all_rfo.l3_hit_f.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200120 offcore_response.all_reads.l3_hit_m.any_snoop offcore_response.all_pf_data_rd.supplier_none.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C07F7 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020080 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED cmask=1,period=100003,umask=0x1e,event=0xca Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall (Precise event) ocr.pf_l3_rfo.l3_miss_local_dram.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000100 Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS_REMOTE_HOP1_DRAM & ANY_SNOOP This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000020 This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP period=2000003,umask=0x2,event=0x5d period=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800010 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000010 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C0007F7 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00491 ocr.all_pf_data_rd.l3_miss.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISS ocr.all_reads.l3_miss_remote_dram.snoop_miss_or_no_fwd ocr.pf_l2_data_rd.l3_miss.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC08000 This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED offcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000080 ocr.all_reads.l3_miss.no_snoop_needed Counts demand data reads DEMAND_DATA_RD & L3_MISS & HIT_OTHER_CORE_NO_FWD ocr.demand_data_rd.l3_miss.hitm_other_core ocr.pf_l1d_and_sw.l3_miss.remote_hitm This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP Counts any other requests OTHER & L3_MISS_REMOTE_HOP1_DRAM & ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD offcore_response.all_pf_rfo.l3_miss.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C0007F7 ocr.pf_l3_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS_REMOTE_DRAM & SNOOP_MISS_OR_NO_FWD ocr.pf_l3_data_rd.l3_miss.hit_other_core_fwd offcore_response.other.l3_miss.no_snoop_needed offcore_response.all_reads.l3_miss.hit_other_core_no_fwd ocr.demand_rfo.l3_miss_remote_hop1_dram.no_snoop_needed offcore_response.pf_l1d_and_sw.l3_miss_local_dram.no_snoop_needed ALL_READS & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_FWD ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.hitm_other_core ocr.pf_l2_rfo.supplier_none.hit_other_core_no_fwd ocr.demand_code_rd.supplier_none.snoop_none ocr.all_rfo.l3_hit.snoop_miss ocr.all_rfo.l3_hit_m.snoop_miss ALL_READS & L3_HIT_E & HIT_OTHER_CORE_FWD ocr.pf_l3_rfo.l3_hit.hitm_other_core ocr.demand_rfo.l3_hit_f.hit_other_core_fwd ocr.demand_data_rd.l3_hit_e.hit_other_core_fwd ocr.demand_code_rd.supplier_none.hit_other_core_no_fwd ocr.all_rfo.supplier_none.snoop_none Counts demand data reads DEMAND_DATA_RD & SUPPLIER_NONE & ANY_SNOOP ocr.pf_l3_rfo.l3_hit_s.snoop_none ALL_DATA_RD & L3_HIT_E & ANY_SNOOP ocr.all_reads.l3_hit.hitm_other_core ocr.pf_l2_data_rd.pmm_hit_local_pmm.snoop_not_needed ocr.pf_l2_data_rd.l3_hit.hit_other_core_no_fwd ocr.all_reads.l3_hit_m.any_snoop ocr.pf_l1d_and_sw.l3_hit_s.hit_other_core_fwd ocr.all_pf_rfo.l3_hit_f.hit_other_core_no_fwd ocr.pf_l3_data_rd.pmm_hit_local_pmm.any_snoop ocr.all_pf_data_rd.l3_hit_f.snoop_none ocr.all_rfo.l3_hit_s.snoop_miss ocr.demand_rfo.l3_hit_e.hitm_other_core ALL_PF_RFO & L3_HIT_M & ANY_SNOOP Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_M & HITM_OTHER_CORE ocr.demand_code_rd.l3_hit_s.hit_other_core_fwd Counts prefetch (that bring data to L2) data reads hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_E & HIT_OTHER_CORE_FWD ALL_PF_RFO & L3_HIT_F & ANY_SNOOP ocr.demand_data_rd.l3_hit_m.no_snoop_needed period=2000003,event=0x3c 6000000000ns umask=0x4,event=0x4 umask=0x1,event=0xd3 Lines Victimized; Lines in E state. Unit: uncore_cha Counts when a transaction with the opcode type Rsp*WB Snoop Response was received which indicates which indicates the data was written back to it's home. This is returned when a non-RFO request hits a cacheline in the Modified state. The Cache can either downgrade the cacheline to a S (Shared) or I (Invalid) state depending on how the system has been configured. This reponse will also be sent when a cache requests E (Exclusive) ownership of a cache line without receiving data, because the cache must acquire ownership Peer to peer read request for 4 bytes made by IIO Part2 to an IIO target. Unit: uncore_iio unc_iio_txn_req_by_cpu.peer_read.part2 fc_mask=0x07,ch_mask=0x04,umask=0x08,event=0x84 unc_m2m_txc_ad_inserts BL Egress (to CMS) Allocations; All. Unit: uncore_m2m period=2000003,umask=0x10,event=0x8 period=100003,umask=0x4,event=0x85 Counts the number of times we entered an RTM region. Does not count nested transactions Counts Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes topdown.slots_p Number of uops executed on port 6 Number of uops executed on port 7 and 8 umask=0x80,period=100003,event=0xc4 Mispredicted conditional branch instructions retired Supports address when precise (Precise event) Number of page walks outstanding for a store in the PMH each cycle Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle umask=0x1c,event=0x2 umask=0xC88FFE01,event=0x35 umask=0xC827FE01,event=0x35 unc_cha_tor_inserts.ia_miss_rfo_pref Clockticks of the mesh to PCI (M2P) umask=0x80,event=0x60 umask=0x4,event=0x61 l2_wcb_req.wcb_write umask=0x1,event=0x63 The number of branch instructions retired. This includes all types of architectural control flow changes, including exceptions and interrupts The number of far control transfers retired including far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts. Far control transfers are not subject to branch prediction umask=0xCF,event=0x8b umask=0xEF,event=0x8b df_ccm_reqa.node2.wrsized umask=0xA9,event=0x8b umask=0xA8,event=0x8b df_ccm_reqa.node2.rdsized umask=0xE7,event=0x8b umask=0xEE,event=0x8c Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wbinvblkall df_ccm_reqb.node3.wbinvblkall df_ccm_reqb.node4.wbinvblkall umask=0x86,event=0x8c umask=0x65,event=0x8c df_ccm_reqb.node5.wrsizedfullnc Data Fabric CCM Performance Monitor Event DF CCM Request Type C (PIE Requests)APIC access umask=0x2C,event=0x108 umask=0x8B,event=0x108 umask=0x68,event=0x108 umask=0x27,event=0x108 umask=0x85,event=0x108 umask=0xA4,event=0x108 Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anyrdsized df_ioms_reqb.node2.pieiorequest umask=0xEA,event=0x109 umask=0x88,event=0x109 df_ioms_reqb.node7.ioanypostedwrsized>32band<64b df_ioms_reqb.node1.ioanyrdsized df_ioms_reqb.node7.ioanyrdsized fp_sched_empty fp_ret_sse_avx_ops.sp_mult_add_flops Number of SSE Move Ops l3_request_g1.t4.s2.wrsized l3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x20,event=0x1 l3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x20,event=0x1 l3_request_g1.t0.s0.rdsized l3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x40,event=0x1 l3_request_g1.t5.s2.rdsized l3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x80,event=0x1 l3_request_g1.t7.s2.caching l3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x02,event=0x3 l3fillvicreq.t6.s1.rdblkc_s_vic l3fillvicreq.t7.s2.rdblkc_s l3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x08,event=0x3 l3fillvicreq.t4.s1.rdblkx_vic l3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x10,event=0x3 l3fillvicreq.t4.s0.rdblkl l3victimstate.t5.s0.nol3victimline l3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x01,event=0x9 l3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x01,event=0x9 l3victimstate.t3.s2.nol3victimline l3victimstate.t3.s3.nol3victimline l3victimstate.t5.s3.nol3victimline l3victimstate.t1.s1.none_nol3victimline l3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x02,event=0x9 l3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x02,event=0x9 l3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x04,event=0x9 l3victimstate.t7.s3.f_s l3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x08,event=0x9 l3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x20,event=0x9 l3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x40,event=0x9 l3victimstate.t1.s2.d l3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x80,event=0x9 l3victimstate.t4.s3.od ls_mab_alloc.loads umask=0x20,event=0x45 OC Mode Switch. OC to IC mode switch Retired Fused Instructions. The number of fuse-branch instructions retired per cycle. The number of events logged per cycle can vary from 0-8 umask=0x1,event=0x59 ls_hw_pf_dc_fill.ls_mabresp_lcl_l2 IC_REFILL_FROM_SYSTEM FR_RETIRED_X86_INSTRUCTIONS FR_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES NB_HT_BUS1_BANDWIDTH PC_IMM_BRANCH INSTR_EXECUTED CYCLES_NO_INSTRUCTION INSTR_MICRO_TLB_MISS_STALL L2D_CACHE_ALLOCATE ICACHE_READ_MISS DCACHE_READ_HIT MEM_CAP_WRITE_TAG_SET FP_COMPLETED MIPS16_COMPLETED DCACHE_ACCESSES LOAD_MISS_CONSUMER_REPLAYS CLK ICA CIMISS WBUFFL PMON_EXCEPT DST_STREAM_0_CACHE_LINE_FETCHES VTQ_SUSPENDS_DUE_TO_CTX_CHANGE LSU_INDEXED_ALIAS_STALL LS_LM_INSTR_PIECES FAST_BTIC_HIT CYCLES_NO_INSTR_DISPATCHED SS_SM_INSTR_PIECES BUS_RETRY BUS_RETRY_DUE_TO_PREVIOUS_ADJACENT MARKED_GROUP_COMPLETE_TIMEOUT INSTR_MMU_VSP_RELOADS L2_CACHE_ALLOCATIONS FPU_DIVIDE_CYCLES instructions memory-controller-hi-pri-bypass probe-miss buffer-release INTEL_P6 INTEL_SANDYBRIDGE INTEL_SANDYBRIDGE_XEON ARMV7_CORTEX_A15 event {"type": "pmcdetach" {"type": "proccsw" %s, "pmcid": "0x%08x", "pid": "%d", "start": "0x%016jx", "pathname": "%s"}
%s, "pid": "%d", "start": "0x%016jx", "pathname": "%s"}
v8 GenuineIntel-6-[4589]E GenuineIntel-6-2A GenuineIntel-6-86 Fraction of cycles where both hardware threads were active umask=0x1,period=2000003,event=0x48 This is a precise version (that is, uses PEBS) of the event that counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault Supports address when precise (Precise event) This event counts the number of L2 cache lines filling the L2. Counting does not cover rejects Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy This event counts the number of deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop.
MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.
Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles tx_mem.abort_hle_elision_buffer_unsupported_alignment Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region umask=0x10,period=2000003,event=0xc8 hle_retired.aborted_misc5 Loads with latency value being above 8 Spec update: BDM100, BDM35 (Must be precise) other This event counts the number of cycles during which Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the current thread. This also includes the cycles during which the Allocator is serving another thread cpu_clk_thread_unhalted.ref_xclk Not taken macro-conditional branches This event counts both taken and not taken speculative and retired indirect branches excluding calls and return branches Taken speculative and retired mispredicted indirect calls br_misp_exec.all_conditional br_misp_exec.all_indirect_jump_non_call_ret umask=0x20,any=1,period=2000003,event=0xa1 cycle_activity.stalls_l2_pending Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request machine_clears.maskmov This is a precise version (that is, uses PEBS) of the event that counts conditional branch instructions retired (Precise event) umask=0x0,period=400009,event=0xc5 Count cases of saving new LBR LLC prefetch misses for RFO. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox umask=0x3,event=0x35,filter_opc=0x1c8,filter_tid=0x3e read requests to home agent. Unit: uncore_ha uncore memory write requests to memory controller. Derived from unc_m_cas_count.wr. Unit: uncore_imc power_channel_ppd % unc_p_clockticks unc_p_power_state_occupancy.cores_c6 Counts the number of cycles when current is the upper limit on frequency. Unit: uncore_pcu umask=0x20,period=2000003,event=0x8 Store misses in all DTLB levels that cause page walks Spec update: BDM69 tlb_flush.dtlb_thread bdw metrics 4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )) (( 1 * ( fp_arith_inst_retired.scalar_single + fp_arith_inst_retired.scalar_double ) + 2 * fp_arith_inst_retired.128b_packed_double + 4 * ( fp_arith_inst_retired.128b_packed_single + fp_arith_inst_retired.256b_packed_double ) + 8 * fp_arith_inst_retired.256b_packed_single )) / (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )) ( ((br_misp_retired.all_branches / ( br_misp_retired.all_branches + machine_clears.count )) * (( uops_issued.any - uops_retired.retire_slots + 4 * (( int_misc.recovery_cycles_any / 2 )) ) / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) ))))) + (4 * idq_uops_not_delivered.cycles_0_uops_deliv.core / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )))) * (12 * ( br_misp_retired.all_branches + machine_clears.count + baclears.any ) / cycles) / (4 * idq_uops_not_delivered.cycles_0_uops_deliv.core / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )))) ) * (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) ))) / br_misp_retired.all_branches L3_Cache_Fill_BW Cache_Misses Counts demand data reads have any response type offcore_response.demand_rfo.l3_hit.snoop_not_needed offcore_response.corewb.l3_hit.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010010 offcore_response.pf_l2_data_rd.supplier_none.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020040 offcore_response.pf_l2_code_rd.l3_hit.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0200 umask=0x10,edge=1,period=2000003,cmask=1,event=0x79 This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding “4 – x” when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:
a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;
b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions);
c. Instruction Decode Queue (IDQ) delivers four uops Counts randomly selected loads with latency value being above eight Spec update: BDM100, BDM35 (Must be precise) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000001 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000001 offcore_response.demand_data_rd.l3_miss.snoop_hit_no_fwd offcore_response.demand_rfo.l3_hit.snoop_non_dram offcore_response.pf_l2_data_rd.l3_miss_local_dram.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000020 offcore_response.other.l3_miss.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020120 This is a precise version (that is, uses PEBS) of the event that counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling (Precise event) umask=0x1,edge=1,period=100003,cmask=1,event=0xc3 unc_cbo_cache_lookup.write_m Unit: uncore_cbox L3 Lookup read request that access cache and found line in E or S-state L3 Lookup write request that access cache and found line in E or S-state Retired load uops with L1 cache hits as data sources Supports address when precise (Precise event) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC007F7 Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache Counts all prefetch (that bring data to LLC only) RFOs miss in the L3 This event counts both direct and indirect near call instructions retired (Precise event) l2_st.self.m_state l2_ld_ifetch.self.i_state SIMD packed micro-ops executed SIMD packed logical micro-ops executed Decode stall due to IQ full Load splits bus_trans_brd.self bus_trans_io.all_agents umask=0x40,period=200000,event=0x70 umask=0x81,period=2000000,event=0x12 Multiply operations retired umask=0x0,period=2000000,event=0xa br_inst_type_retired.ind_call br_inst_decoded Bogus branches Load uops retired (Precise event capable) Supports address when precise (Must be precise) Counts load uops retired where the cache line containing the data was in the modified state of another core or modules cache (HITM). More specifically, this means that when the load address was checked by other caching agents (typically another processor) in the system, one of those caching agents indicated that they had a dirty copy of the data. Loads that obtain a HITM response incur greater latency than most is typical for a load. In addition, since HITM indicates that some other processor had this data in its cache, it implies that the data was shared between processors, or potentially was a lock or semaphore value. This event is useful for locating sharing, false sharing, and contended locks Supports address when precise (Must be precise) Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required offcore_response.any_read.l2_miss.hit_other_core_no_fwd Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_data_rd.l2_miss.hitm_other_core offcore_response.any_data_rd.l2_miss.hit_other_core_no_fwd Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts requests to the uncore subsystem that have any transaction responses from the uncore subsystem Counts partial cache line data writes to uncacheable write combining (USWC) memory region that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) umask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600000800 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600000080 Counts reads for ownership (RFO) requests generated by L2 prefetcher that true miss for the L2 cache with a snoop miss in the other processor module Counts reads for ownership (RFO) requests generated by L2 prefetcher that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache Counts data cacheline reads generated by hardware L2 cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_code_rd.outstanding umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000000002 Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that true miss for the L2 cache with a snoop miss in the other processor module Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) umask=0x2,period=200003,event=0x13 umask=0x2,period=200003,event=0xcb umask=0x10,period=200003,event=0x3 Retired branch instructions (Precise event capable) (Must be precise) umask=0xeb,period=200003,event=0xc4 Retired near indirect call instructions (Precise event capable) (Must be precise) Retired mispredicted conditional branch instructions (Precise event capable) (Must be precise) umask=0x4,period=200003,event=0x81 Counts load uops retired that caused a DTLB miss Supports address when precise (Must be precise) offcore_response.corewb.outstanding Counts data cacheline reads generated by hardware L2 cache prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010020 Counts bus lock and split lock requests true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cache lines requests by software prefetch instructions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts any data writes to uncacheable write combining (USWC) memory region have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.streaming_stores.l2_miss.snoop_miss_or_no_snoop_needed Counts any data writes to uncacheable write combining (USWC) memory region true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts reads for ownership (RFO) requests (demand & prefetch) hit the L2 cache offcore_response.any_rfo.outstanding Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module umask=0x8,period=20003,event=0xc3 Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache Spec update: HSD78 Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle Spec update: HSD62, HSD61 This event counts retired load uops that hit in the L3 cache, but required a cross-core snoop which resulted in a HITM (hit modified) in an on-pkg core cache. This does not include hardware prefetches. This is a precise event Spec update: HSD29, HSD25, HSM26, HSM30. Supports address when precise (Precise event) This event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2 cache when there was an L2 miss Number of times an RTM execution aborted due to any reasons (multiple categories may count as one) (Precise event) offcore_response.all_requests.l3_miss.any_response Instructions retired from execution Spec update: HSD140, HSD143 Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads This events counts the cycles where at least two uop were executed. It is counted per thread Spec update: HSD144, HSD30, HSM31 This event counts all mispredicted branch instructions retired. This is a precise event (Must be precise) unc_cbo_xsnp_response.miss_external Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levels Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G) This event counts store operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks Counts the number of Extended Page Table walks from the ITLB that hit in the L2 umask=0x20,period=100003,event=0xbd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0600400001 Counts the number of near return instructions retired (Precise event) l2_store_lock_rqsts.all l2_l1d_wb_rqsts.miss Not rejected writebacks from L1D to L2 cache lines in any state Core-originated cacheable demand requests missed LLC Retired load uops which data sources missed LLC but serviced from local dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x000107F7 Number of transitions from SSE to AVX-256 when penalty applicable Decode Stream Buffer (DSB)-to-MITE switches int_misc.recovery_stalls_count Cycles the RS is empty for the thread Number of instructions at retirement Counts the number of allocated write entries, include full, partial, and LLC evictions Counts the number of LLC evictions allocated Cycle PMH is busy with a walk Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches offcore_response.pf_l2_data_rd.llc_hit.hitm_other_core umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3fffc20004 Counts all demand code reads that miss the LLC and the data returned from local dram Counts all demand code reads that miss the LLC the data is found in M state in remote cache and forwarded from there umask=0x1,period=100003,event=0xb7,offcore_rsp=0x107fc00001 Counts all prefetch (that bring data to L2) code reads that miss the LLC and the data returned from remote & local dram offcore_response.pf_l2_data_rd.llc_miss.remote_dram PCIe read current. Derived from unc_c_tor_inserts.opcode.pcie_read_current. Unit: uncore_cbox unc_p_freq_ge_2000mhz_transitions Number of GSSE-256 Computational FP single precision uops issued this cycle umask=0x2,period=2000003,event=0x4e umask=0x90,period=200003,event=0x89 umask=0xd0,period=200003,event=0x89 umask=0x80,period=2000003,event=0x59 Counts the cycles of stall due to lack of load buffers umask=0x10,period=400009,event=0xc5 umask=0x1,edge=1,period=100003,cmask=1,event=0x14 Each cycle there was a MLC-miss pending demand load this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0 resource_stalls.ooo_rsrc event=0x1 umask=0x1,period=200003,event=0x4 offcore_response.any_code_rd.l2_hit_far_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080044 Counts Demand code reads and prefetch code read requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode Counts L2 data RFO prefetches (includes PREFETCHW instruction) that provides no supplier details umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080004 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002000022 Counts any Read request that accounts for responses which hit its own tile's L2 with data in M state offcore_response.any_request.l2_hit_this_tile_e Counts any Prefetch requests that accounts for responses which hit its own tile's L2 with data in F state umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800180004 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800180044 offcore_response.bus_locks.l2_hit_far_tile umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800400400 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000044 Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from DRAM Far offcore_response.any_request.ddr_near Counts Software Prefetches that accounts for data responses from DRAM Local offcore_response.uc_code_reads.mcdram_far offcore_response.uc_code_reads.mcdram_near Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from MCDRAM Local offcore_response.demand_rfo.mcdram_near umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000001 Counts the number of near RET branch instructions retired (Precise event) Counts the number of scalar SSE, AVX, AVX2, AVX-512 micro-ops retired. More specifically, it counts scalar SSE, AVX, AVX2, AVX-512 micro-ops except for loads (memory-to-register mov-type micro ops), division, sqrt L1 data cache stores in M state l1d_cache_st.s_state L2 data demand loads in E state l2_rqsts.ifetch_miss L2 instruction fetch misses umask=0x8,period=200000,event=0x24 l2_rqsts.rfos l2_write.rfo.hit Longest latency cache reference mem_inst_retired.loads Offcore requests satisfied by the LLC and HITM in a sibling core umask=0x1,period=100000,event=0xb7,offcore_rsp=0x422 Offcore writebacks to the LLC or local DRAM Offcore data reads, RFO's and prefetches satisfied by the IO, CSR, MMIO unit Offcore data reads, RFO's and prefetches statisfied by the LLC and not found in a sibling core offcore_response.demand_data.llc_hit_no_other_core Offcore demand data requests satisfied by the LLC and HIT in a sibling core Offcore demand data requests satisfied by the LLC and HITM in a sibling core umask=0x1,period=100000,event=0xb7,offcore_rsp=0x701 offcore_response.demand_ifetch.llc_hit_other_core_hit offcore_response.pf_data.any_cache_dram Offcore prefetch data reads satisfied by a remote cache or remote DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1840 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x720 Offcore prefetch RFO requests satisfied by the LLC Offcore prefetch RFO requests satisfied by the LLC or local DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0x470 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x870 SSE and SSE2 FP Uops umask=0x1,period=200000,event=0x12 simd_int_128.unpack SIMD integer 64 bit packed multiply operations offcore_response.any_request.any_llc_miss umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF808 offcore_response.pf_ifetch.any_dram large_itlb.hit All loads dispatched All Store buffer stall cycles arith.cycles_div_busy Divide Operations executed umask=0x1,period=200000,event=0xc4 br_misp_exec.direct inst_queue_writes ssex_uops_retired.packed_single uops_executed.port3_core Macro-fused Uops retired (Precise Event) Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches Counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000408000 offcore_response.other.l4_hit_local_l4.snoop_not_needed offcore_response.other.l3_hit_s.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080108000 offcore_response.demand_code_rd.l4_hit_local_l4.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0400004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10001C0004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200080004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02001C0002 offcore_response.demand_rfo.l3_hit_e.snoop_not_needed offcore_response.demand_rfo.l3_hit_e.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200040002 Counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 0–2 cycles umask=0x1,period=100007,event=0xc6,frontend=0x401006 rtm_retired.aborted_mem umask=0x1,period=100003,event=0xb7,offcore_rsp=0x203C408000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000108000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x103C400002 offcore_response.demand_rfo.l3_miss_local_dram.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000400002 offcore_response.demand_data_rd.l3_miss_local_dram.spl_hit umask=0x2,period=2000003,event=0xe exe_activity.exe_bound_0_ports Page walk completed due to a demand data load to a 4K page Cycles when at least one PMH is busy with a page walk for a load. EPT page walk duration are excluded in Skylake rehabq.any_ld Loads missed L1 All Loads Counts DCU hardware prefetcher data read that hit in the other module where modified copies were found in other core's L1 cache Counts DCU hardware prefetcher data read that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Counts demand and DCU prefetch data read that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Machine clears happen when something happens in the machine that causes the hardware to need to take special care to get the right answer. When such a condition is signaled on an instruction, the front end of the machine is notified that it must restart, so no more instructions will be decoded from the current path. All instructions "older" than this one will be allowed to finish. This instruction and all "younger" instructions must be cleared, since they must not be allowed to complete. Essentially, the hardware waits until the problematic instruction is the oldest instruction in the machine. This means all older instructions are retired, and all pending stores (from older instructions) are completed. Then the new path of instructions from the front end are allowed to start into the machine. There are many conditions that might cause a machine clear (including the receipt of an interrupt, or a trap or a fault). All those conditions (including but not limited to MACHINE_CLEARS.MEMORY_ORDERING, MACHINE_CLEARS.SMC, and MACHINE_CLEARS.FP_ASSIST) are captured in the ANY event. In addition, some conditions can be specifically counted (i.e. SMC, MEMORY_ORDERING, FP_ASSIST). However, the sum of SMC, MEMORY_ORDERING, and FP_ASSIST machine clears will not necessarily equal the number of ANY This event counts every cycle when a D-side (walks due to a load) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks This event counts when a data (D) page walk or an instruction (I) page walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks Counts all prefetch data reads that hit in the LLC offcore_response.pf_l2_code_rd.llc_hit.no_snoop_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0100 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10200 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1f80400080 Actually retired uops. (Precise Event - PEBS) (Precise event) REQUEST = ANY IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = ANY_REQUEST and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f33 REQUEST = DEMAND_RFO and RESPONSE = IO_CSR_MMIO offcore_response.other.all_local_dram_and_remote_cache_hit REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HIT REQUEST = ANY_REQUEST and RESPONSE = REMOTE_DRAM offcore_response.data_in.any_dram_and_remote_fwd umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3001 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3004 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3002 umask=0x4,period=100000,event=0xb4 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2722 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2750 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5810 Counts all demand data writes (RFOs) TBD TBD offcore_response.pf_l3_data_rd.l3_hit.hitm_other_core offcore_response.pf_l3_rfo.l3_hit.hit_other_core_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0400 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0490 offcore_response.all_pf_rfo.l3_hit.snoop_hit_with_fwd umask=0x10,cmask=6,period=2000003,event=0x60 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063FC00004 offcore_response.pf_l2_data_rd.l3_miss.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x083FC00100 offcore_response.pf_l3_rfo.l3_miss.remote_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0604000490 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x083FC00120 umask=0x40,period=2000003,event=0xef inv=1,umask=0x2,cmask=10,period=2000003,event=0xc2 skx metrics MMIO writes. Derived from unc_cha_tor_inserts.ia_miss. Unit: uncore_cha 7.11E-06Bytes fc_mask=0x07,ch_mask=0x01,umask=0x01,event=0x83,ch_mask=0x1f Counts transactions that looked into the multi-socket cacheline Directory state, and therefore did not send a snoop because the Directory indicated it was not needed Multi-socket cacheline Directory state lookups; Snoop Needed. Unit: uncore_cha unc_cha_imc_writes_count.full Counts when a transaction with the opcode type Rsp*Fwd*WB Snoop Response was received which indicates the data was written back to it's home socket, and the cacheline was forwarded to the requestor socket. This snoop response is only used in >= 4 socket systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to it's home socket to be written back to memory unc_iio_data_req_by_cpu.mem_read.part1 Read request for 4 bytes made by the CPU to IIO Part1. Unit: uncore_iio Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus fc_mask=0x07,ch_mask=0x08,umask=0x01,event=0xc0 unc_iio_txn_req_by_cpu.mem_read.part0 Counts reads in which direct to Intel Ultra Path Interconnect (UPI) transactions (which would have bypassed the CHA) were overridden umask=0x27,event=0x3 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200002 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020490 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080122 mem_load_l3_miss_retired.remote_pmm offcore_response.pf_l2_data_rd.l3_hit_m.snoop_none This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040020 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l3_rfo.l3_hit.hit_other_core_fwd This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200100 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD offcore_response.all_reads.l3_hit_m.hitm_other_core This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040010 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400010 period=200003,umask=0x2,event=0xf2 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F800807F7 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080491 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.SNOOP_NONE offcore_response.all_data_rd.l3_hit_e.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020010 offcore_response.all_data_rd.l3_hit_e.snoop_none offcore_response.demand_data_rd.l3_hit_f.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000088000 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01001007F7 offcore_response.demand_code_rd.l3_hit_s.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080080 offcore_response.all_pf_rfo.l3_hit_e.hitm_other_core offcore_response.pf_l2_rfo.l3_hit_s.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0100 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100490 Retired load instructions that miss the STLB Supports address when precise (Precise event) period=100003,umask=0x80,event=0xd1 offcore_response.demand_data_rd.l3_hit_e.hitm_other_core This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS period=200003,umask=0xff,event=0x24 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040490 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020004 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200108000 offcore_response.demand_code_rd.l3_hit_e.hit_other_core_no_fwd offcore_response.demand_code_rd.l3_hit_m.no_snoop_needed offcore_response.pf_l3_data_rd.l3_hit_f.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0080 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE period=100003,umask=0x2,event=0xb0 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED offcore_response.pf_l1d_and_sw.supplier_none.hit_other_core_fwd This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200491 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE offcore_response.demand_rfo.l3_hit_f.snoop_miss offcore_response.all_data_rd.l3_hit_e.any_snoop This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0004 offcore_response.other.l3_hit.no_snoop_needed offcore_response.other.l3_hit.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS offcore_response.all_data_rd.l3_hit_f.hitm_other_core cmask=1,inv=1,period=2000003,umask=0x1,event=0x9c Retired Instructions who experienced Instruction L1 Cache true miss (Precise event) This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS offcore_response.pf_l3_rfo.l3_miss_local_dram.no_snoop_needed Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS_LOCAL_DRAM & ANY_SNOOP offcore_response.demand_code_rd.l3_miss_local_dram.no_snoop_needed This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000122 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F900007F7 ocr.demand_rfo.l3_miss.snoop_miss This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000100 offcore_response.demand_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE ocr.pf_l3_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd ocr.all_rfo.l3_miss_local_dram.hitm_other_core ocr.all_pf_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd ALL_READS & L3_MISS_REMOTE_HOP1_DRAM & SNOOP_NONE offcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd offcore_response.demand_code_rd.l3_miss_local_dram.hitm_other_core This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS offcore_response.other.l3_miss_remote_hop1_dram.any_snoop This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD ocr.pf_l2_rfo.l3_miss.snoop_none ALL_RFO & L3_MISS_REMOTE_HOP1_DRAM & NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000004 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800020 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP ocr.pf_l1d_and_sw.l3_miss_local_dram.hitm_other_core offcore_response.pf_l1d_and_sw.l3_miss.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000122 ALL_RFO & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_FWD period=101,umask=0x1,event=0xcd,ldlat=0x200 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED ALL_PF_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & ANY_SNOOP ocr.demand_code_rd.l3_miss.hit_other_core_fwd ALL_RFO & L3_MISS & HITM_OTHER_CORE ALL_DATA_RD & L3_MISS & NO_SNOOP_NEEDED ocr.all_rfo.l3_miss_local_dram.any_snoop ALL_DATA_RD & L3_MISS & HITM_OTHER_CORE ocr.all_data_rd.l3_miss_local_dram.no_snoop_needed ocr.demand_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd offcore_response.demand_data_rd.l3_miss_local_dram.hit_other_core_fwd ocr.demand_code_rd.l3_miss.hit_other_core_no_fwd offcore_response.pf_l1d_and_sw.l3_miss_local_dram.hitm_other_core offcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.no_snoop_needed ocr.pf_l2_rfo.l3_miss_local_dram.snoop_miss ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.any_snoop period=100003,umask=0x1,event=0xcd,ldlat=0x4 period=50021,umask=0x1,event=0xcd,ldlat=0x8 ocr.all_data_rd.l3_hit_f.hitm_other_core Counts all demand code reads DEMAND_CODE_RD & L3_HIT_M & ANY_SNOOP Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_M & HITM_OTHER_CORE ocr.pf_l1d_and_sw.l3_hit.snoop_none Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT & SNOOP_NONE Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & PMM_HIT_LOCAL_PMM & SNOOP_NONE Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_E & NO_SNOOP_NEEDED ocr.all_data_rd.l3_hit_f.any_snoop Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & PMM_HIT_LOCAL_PMM & ANY_SNOOP ALL_READS & L3_HIT_E & SNOOP_MISS ocr.pf_l1d_and_sw.l3_hit_f.no_snoop_needed ocr.all_reads.l3_hit_m.snoop_miss ocr.all_pf_rfo.l3_hit_m.no_snoop_needed ocr.all_data_rd.l3_hit.no_snoop_needed ALL_DATA_RD & PMM_HIT_LOCAL_PMM & SNOOP_NONE ocr.pf_l2_rfo.pmm_hit_local_pmm.any_snoop ocr.all_reads.l3_hit_s.hit_other_core_fwd ocr.all_data_rd.l3_hit_m.hit_other_core_fwd ocr.all_rfo.l3_hit_f.snoop_miss Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_E & HITM_OTHER_CORE ALL_PF_RFO & L3_HIT_M & HITM_OTHER_CORE ocr.demand_rfo.l3_hit.hit_other_core_fwd ocr.all_reads.l3_hit_e.hitm_other_core Counts any other requests OTHER & L3_HIT_F & HIT_OTHER_CORE_FWD ALL_READS & SUPPLIER_NONE & HITM_OTHER_CORE Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_S & NO_SNOOP_NEEDED ocr.all_pf_rfo.l3_hit_m.any_snoop ocr.all_pf_data_rd.l3_hit_f.hit_other_core_fwd Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_S & HIT_OTHER_CORE_FWD ocr.all_rfo.l3_hit_e.any_snoop Counts any other requests OTHER & L3_HIT_F & HIT_OTHER_CORE_NO_FWD Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT & ANY_SNOOP ocr.all_rfo.l3_hit_e.snoop_none Far branch instructions retired Spec update: SKL091 (Precise event) cmask=4,period=2000003,umask=0x1,event=0xa8 period=25003,umask=0x2,event=0x3c period=2000003,umask=0x1,event=0xa2 cmask=3,period=2000003,umask=0x1,event=0xb1 Loads blocked due to overlapping with a preceding store that cannot be forwarded Writes Tag Check; Hit Lines Victimized; Lines in F State. Unit: uncore_cha fc_mask=0x07,ch_mask=0x02,umask=0x08,event=0xc0 unc_iio_data_req_by_cpu.peer_read.part3 fc_mask=0x07,ch_mask=0x08,umask=0x02,event=0x83 unc_iio_txn_req_by_cpu.peer_write.part3 AD Ingress (from CMS) Occupancy. Unit: uncore_m2m BL Ingress (from CMS) Occupancy. Unit: uncore_m2m umask=0x03,event=0x16 FLITs received which bypassed the Slot0 Recieve Buffer. Unit: uncore_upi ll period=100003,umask=0x8,event=0x85 cmask=1,period=100003,umask=0x10,event=0x85 DSB-to-MITE switch true penalty cycles umask=0x1,period=100007,event=0xc6,frontend=0x500406 umask=0x1,period=100007,event=0xc6,frontend=0x500806 Counts Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 5 and 9 Counts cycles where the Store Buffer was full and no loads caused an execution stall br_inst_retired.cond_taken cpu_clk_unhalted.distributed umask=0x30,event=0x4 umask=0x10,event=0x2 umask=0xC867FE01,event=0x35 fc_mask=0x07,ch_mask=0x20,umask=0x01,event=0x83 unc_m2p_clockticks The number of 64 byte instruction cache line was fulfilled from the L2 cache event=0x83 All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2 pipeline, hit or miss. Types of PF and L2 hit/miss broken out in a separate perfmon event umask=0x20,event=0x63 Retired Taken Branch Instructions Mispredicted umask=0x07,event=0x8b umask=0x26,event=0x8b df_ccm_reqa.node3.specdramrd df_ccm_reqa.node5.rdvlkc df_ccm_reqa.node6.rdvlkc umask=0xAA,event=0x8c umask=0x47,event=0x8c umask=0x46,event=0x8c df_ccm_reqb.node4.wrsizednc umask=0xE1,event=0x8c df_ccm_reqc.apicucodeaccess df_ioms_reqa.node0.flush umask=0xA9,event=0x108 df_ioms_reqa.node0.largeread df_ioms_reqb.node2.piesystemmanagement Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered pieinterrupt df_ioms_reqb.node6.ioanynon-postedwrsized>32band<64b umask=0x66,event=0x109 umask=0x86,event=0x109 df_ioms_reqb.node1.ioanypostedwrsized>32band<64b df_ioms_reqb.node5.ioanypostedwrsized>32band<64b df_ioms_reqb.node2.ioanyrdsized df_ioms_reqb.node6.ioanyrdsized Single-precision multiply FLOPS umask=0x2,event=0x5 l3_request_g1.t5.s1.wrsizednc l3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x02,event=0x1 l3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x04,event=0x1 l3_request_g1.t6.s1.wrsized l3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x04,event=0x1 l3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x20,event=0x1 l3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x20,event=0x1 l3_request_g1.t3.s0.rdsized l3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x40,event=0x1 l3_request_g1.t2.s0.caching l3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x80,event=0x1 l3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x01,event=0x3 l3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x02,event=0x3 l3fillvicreq.t5.s0.chgtox l3fillvicreq.t2.s1.chgtox l3fillvicreq.t5.s1.chgtox l3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x02,event=0x3 l3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x02,event=0x3 l3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x04,event=0x3 l3fillvicreq.t0.s2.rdblkc_s_vic l3fillvicreq.t4.s3.rdblkc_s_vic l3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x10,event=0x3 l3fillvicreq.t7.s2.rdblkx_vic l3fillvicreq.t3.s3.rdblkx_vic l3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x10,event=0x3 l3fillvicreq.t3.s0.rdblkx l3fillvicreq.t2.s3.rdblkx l3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x40,event=0x3 l3fillvicreq.t7.s1.rdblkl l3fillvicreq.t1.s2.rdblkl l3fillvicreq.t5.s2.rdblkl l3victimstate.t0.s3.nol3victimline l3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x02,event=0x9 l3victimstate.t5.s2.none_nol3victimline l3victimstate.t1.s0.f_s l3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x04,event=0x9 l3victimstate.t3.s0.f_s l3victimstate.t6.s2.f_s l3victimstate.t1.s3.f_s l3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x04,event=0x9 l3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x08,event=0x9 l3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x08,event=0x9 l3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x08,event=0x9 l3victimstate.t7.s0.e_fe l3victimstate.t6.s2.e_fe l3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x20,event=0x9 l3victimstate.t5.s2.m l3victimstate.t5.s2.od event=0x40 ls_l1_d_tlb_miss.all ls_tablewalker.iside de_dis_dispatch_token_stalls0.alsq3_token_stall L1 Branch Prediction Overrides Existing Prediction (speculative) umask=0xFF,event=0x94 x87 bottom-executing uOps retired. The number of serializing Ops retired event=0x2b Hardware Prefetch Data Cache Fills by Data Source. From DRAM (home node remote) Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Floating point register file resource stall. Applies to all FP ops that have a destination register FP_CYCLES_WITH_NO_FPU_OPS_RETIRED PRED_BRANCH_PRED_TAKEN INSTRUCTIONS_ISSUED_CYCLE EXC_IRQ L1D_TLB_REFILL_ST EXC_SVC L2_MISS WBB_LT_QUARTER IFU_IDU_CLOGED_DOWNSTREAM_CYCLES CLDQ_FULL_DR_STALLS JTLB_DATA_MISSES VA_TRANSALTION_CORNER_CASES CP1_CP2_COND_BRANCH_INSNS MIPS16_INSNS DSPRAM_EVENTS NISSUE BR EC DDIDS TOUCH_ALIAS L1_DATA_SNOOP_HIT_CASTOUT_QUEUE CACHE_INHIBITED_STORES SECOND_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLY L3_LOAD_HITS PREFETCH_ENGINE_COLLISION_VS_INSTR_FETCH PREFETCH_ENGINE_FULL MARKED_INSTR_FINISH_ANY_UNIT REJECT_COMPLETION_STALL_ERAT_MISS LOAD_GUARDED_MISS DATA_MMU_VSP_RELOADS L2_CACHE_UPDATES DECORATED_STORES k8-dc-miss es page-conflict MIPS24K INTEL_PII BR_MISP_RETIRED.ALL_BRANCHES fc_mask %s, "pmcid": "0x%08x", "pid": "%d", "pathname": "%s"}
GenuineIntel-6-3A GenuineIntel-6-3E IFetch_Line_Utilization inst_retired.any / ( cpu_clk_unhalted.thread_any / 2 ) if #smt_on else cycles umask=0x30,period=200003,event=0x24 umask=0xe4,period=200003,event=0x24 Cycles when L1D is locked umask=0x4,period=50021,event=0xd1 umask=0x2,period=200003,event=0xf0 l2_trans.l1d_wb Number of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element umask=0x18,cmask=4,period=2000003,event=0x79 This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ umask=0x3c,period=2000003,event=0x79 Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled memory umask=0x20,period=2000003,event=0x54 Number of times we could not allocate Lock Buffer This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.
Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. This event is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case Taken speculative and retired mispredicted indirect branches with return mnemonic umask=0x4,period=2000003,event=0xa1 Cycles per thread when uops are executed in port 7 resource_stalls.any umask=0x1,cmask=3,period=2000003,event=0xb1 Cycles where at least 3 uops were executed per-thread Cycles at least 2 micro-op is executed from any thread on physical core This is a precise version (that is, uses PEBS) of the event that counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight Supports address when precise (Precise event) This event counts self-modifying code (SMC) detected, which causes a machine clear Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault Conditional branch instructions retired. (Precise Event - PEBS) (Precise event) br_inst_retired.near_call_r3 umask=0x4,period=400009,event=0xc4 Far branch instructions retired Spec update: BDW98 64Bytes PCIe write misses (full cache line). Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox (unc_p_freq_max_power_cycles / unc_p_clockticks) * 100. umask=0xe,period=100003,event=0x49 umask=0x1,period=100007,event=0xae page_walker_loads.dtlb_l1 1 - ( (idq_uops_not_delivered.core / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )))) + (( uops_issued.any - uops_retired.retire_slots + 4 * (( int_misc.recovery_cycles_any / 2 )) ) / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )))) + (uops_retired.retire_slots / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )))) ) uops_retired.retire_slots / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) ))) idq.dsb_uops / (( idq.dsb_uops + lsd.uops + idq.mite_uops + idq.ms_uops ) ) uops_executed.thread / (( cpu@uops_executed.core\,cmask\=1@ / 2 ) if #smt_on else uops_executed.cycles_ge_1_uop_exec) BrMispredicts 1000 * ( l2_rqsts.references - l2_rqsts.miss ) / inst_retired.any 1000 * mem_load_uops_retired.l3_miss / inst_retired.any umask=0xc1,period=200003,event=0x24 offcore_response.demand_data_rd.l3_hit.snoop_none offcore_response.demand_data_rd.l3_hit.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020008 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0008 offcore_response.pf_l2_rfo.supplier_none.snoop_miss offcore_response.pf_l2_code_rd.l3_hit.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020080 offcore_response.pf_l3_rfo.l3_hit.snoop_not_needed Counts all prefetch data reads umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0120 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0091 Randomly selected loads with latency value being above 4 Spec update: BDM100, BDM35 (Must be precise) offcore_response.demand_data_rd.l3_miss_local_dram.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000001 offcore_response.demand_rfo.l3_miss.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000008 offcore_response.corewb.l3_miss.snoop_hit_no_fwd offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000010 offcore_response.pf_l2_code_rd.l3_miss_local_dram.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000100 offcore_response.other.l3_hit.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020240 offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_hit_no_fwd offcore_response.all_pf_code_rd.l3_miss_local_dram.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000091 offcore_response.all_rfo.l3_miss_local_dram.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000122 umask=0x8f,event=0x34 Number of Core coherent Data Read entries allocated in DirectData mode cbox_0@event\=0x0@ Direct and indirect macro near call instructions retired (captured in ring 3) (Precise event) umask=0x50,period=200000,event=0x24 L2 cacheable instruction fetch requests umask=0x48,period=200000,event=0x28 umask=0x48,period=200000,event=0x2d umask=0x4f,period=200000,event=0x2e L1 Cacheable Data Writes SIMD packed shift micro-ops executed umask=0x84,period=200000,event=0x7 umask=0xe0,period=200000,event=0x63 umask=0x22,period=200000,event=0x77 umask=0x28,period=200000,event=0x77 bus_io_wait.self cycles_int_masked.cycles_int_masked Mispredicted indirect calls, including both register and memory indirect umask=0x1,period=2000000,event=0xe0 umask=0x1,period=200000,event=0x3 Memory accesses that missed the DTLB DTLB misses due to load operations data_tlb_misses.l0_dtlb_miss_ld umask=0xa,period=200000,event=0x8 umask=0x2,period=200000,event=0xc Counts locked memory uops retired. This includes regular locks and bus locks. (To specifically count bus locks only, see the Offcore response event.) A locked access is one with a lock prefix, or an exchange to memory. See the SDM for a complete description of which memory load accesses are locks Supports address when precise (Must be precise) umask=0x81,period=200003,event=0xd0 Counts the number of load uops retired Supports address when precise (Must be precise) mem_load_uops_retired.hitm Memory uop retired where cross core or cross module HITM occurred (Precise event capable) Supports address when precise (Must be precise) Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that hit the L2 cache offcore_response.any_data_rd.l2_miss.any offcore_response.any_pf_data_rd.l2_miss.any Counts data cache lines requests by software prefetch instructions that miss the L2 cache umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200000800 offcore_response.demand_code_rd.l2_miss.hit_other_core_no_fwd Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_data_rd.l2_miss.hit_other_core_no_fwd Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts the number of issue slots per core cycle that were not consumed because of a full resource in the backend. Including but not limited to resources such as the Re-order Buffer (ROB), reservation stations (RS), load/store buffers, physical registers, or any other needed machine resource that is currently unavailable. Note that uops must be available for consumption in order for this event to fire. If a uop is not available (Instruction Queue is empty), this event will not count Unfilled issue slots per cycle to recover Counts the number of issue slots per core cycle that were not consumed by the backend because allocation is stalled waiting for a mispredicted jump to retire or other branch-like conditions (e.g. the event is relevant during certain microcode flows). Counts all issue slots blocked while within this window including slots where uops were not available in the Instruction Queue Counts uops retired that are from the complex flows issued by the micro-sequencer (MS). Counts both the uops from a micro-coded instruction, and the uops that might be generated from a micro-coded assist (Must be precise) uops_retired.idiv Counts near CALL branch instructions retired (Must be precise) baclears.all Counts demand cacheable data reads of full cache lines miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand reads for ownership (RFO) requests generated by a write to full data cache line hit the L2 cache Counts data cacheline reads generated by hardware L2 cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes miss the L2 cache with a snoop hit in the other processor module, data forwarding is required umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000002000 Counts requests to the uncore subsystem have any transaction responses from the uncore subsystem umask=0x2,period=20003,event=0xc3 umask=0x0,period=20003,event=0xc3 umask=0x4,period=200003,event=0x8 This event counts each cache miss condition for references to the last level cache umask=0x2,period=2000003,event=0x48 Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore Spec update: HSD78, HSD62, HSD61 Offcore outstanding Demand code Read transactions in SQ to uncore. Set Cmask=1 to count cycles Spec update: HSD62, HSD61 Retired load uops that miss the STLB. (precise Event) Spec update: HSD29, HSM30. Supports address when precise (Precise event) This event counts retired load uops that hit in the L3 cache, but required a cross-core snoop which resulted in a HIT in an on-pkg core cache. This does not include hardware prefetches. This is a precise event Spec update: HSD29, HSD25, HSM26, HSM30. Supports address when precise (Precise event) Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles Number of times an HLE execution successfully committed offcore_response.all_rfo.l3_miss.any_response offcore_response.all_data_rd.l3_miss.local_dram umask=0x2,period=100003,event=0xc4 umask=0x40,period=100003,event=0xc4 unc_cbo_cache_lookup.write_i Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M) Store misses in all DTLB levels that cause completed page walks. (1G) ITLB misses that hit STLB. No page walk Number of DTLB page walker loads that hit in the L2 Counts the number of Extended Page Table walks from the DTLB that hit in the L1 and FB This event counts the number of retirement slots used each cycle. There are potentially 4 slots that can be used each cycle - meaning, 4 uops or 4 instructions could retire each cycle (Precise event) Counts any demand and L1 HW prefetch data load requests to L2 Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles mem_load_uops_retired.llc_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10008 Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores offcore_response.split_lock_uc_lock.any_response Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle Cycles DSB to MITE switches caused delay Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from dram Unit: uncore_cbox A snoop invalidates a modified line in some processor core Number of requests allocated in Coherency Tracker umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0090 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c03f7 offcore_response.all_code_rd.llc_miss.remote_hit_forward Counts all demand & prefetch data reads that hits the LLC Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data forwarded from remote cache umask=0x1,period=100003,event=0xb7,offcore_rsp=0x87f820010 umask=0x1,event=0x35,filter_opc=0x1e6 freq_band1_cycles % event=0xb,edge=1,filter_band0=12 l1d.eviction RFOs that hit cache lines in E state idq_uops_not_delivered.cycles_ge_1_uop_deliv.core offcore_response.all_demand_mlc_pref_reads.llc_miss.any_response uops_dispatched.core Each cycle there was no dispatch for this thread, increment by 1. Note this is connect to Umask 2. No dispatch can be deduced from the UOPS_EXECUTED event resource_stalls2.all_fl_empty Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. (filter_band0=XXX with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Unit: uncore_pcu Counts the number of load micro-ops retired that miss in L1 D cache Counts the number of load micro-ops retired that miss in the L2 Supports address when precise (Precise event) Counts any Prefetch requests that accounts for any response Counts any Read request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800081000 Counts Bus locks and split lock requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0 Counts UC code reads (valid only for Outstanding response type) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode offcore_response.partial_reads.l2_hit_near_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080040 Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state offcore_response.demand_rfo.l2_hit_this_tile_m Counts UC code reads (valid only for Outstanding response type) that accounts for responses which hit its own tile's L2 with data in E state Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in S state offcore_response.demand_data_rd.l2_hit_this_tile_f offcore_response.demand_rfo.l2_hit_this_tile_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800180002 Counts Demand cacheable data writes that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400070 Counts any Prefetch requests that accounts for data responses from MCDRAM Local umask=0x1,period=100007,event=0xb7,offcore_rsp=0x01010032f7 Counts Demand cacheable data write requests that accounts for data responses from MCDRAM Local Counts Software Prefetches that accounts for data responses from MCDRAM Local umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800400 offcore_response.partial_reads.mcdram_near Counts L2 code HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200040 offcore_response.pf_l2_code_rd.ddr_far Counts demand code reads and prefetch code reads that accounts for data responses from MCDRAM Local Counts Demand cacheable data writes that accounts for data responses from DRAM Local offcore_response.demand_data_rd.ddr_far Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from MCDRAM (local and far) no_alloc_cycles.rat_stall Counts the total number of core cycles when no micro-ops are allocated for any reason Counts the number of unhalted reference clock cycles Counts the number of times the front end resteers for conditional branches as a result of another branch handling mechanism in the front end recycleq.any_st mcdram bandwidth write (CPU traffic only) (MB/sec). Unit: uncore_edc_eclk l1d.m_repl L2 data demand loads in M state l2_lines_out.prefetch_clean umask=0xff,period=200000,event=0x24 mem_load_retired.llc_miss Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event) umask=0x10,period=10000,event=0xb,ldlat=0x10 mem_inst_retired.latency_above_threshold_4096 offcore_response.any_data.io_csr_mmio umask=0x1,period=100000,event=0xb7,offcore_rsp=0x8011 Offcore data reads satisfied by the LLC or local DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3811 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7FFF offcore_response.any_rfo.llc_hit_other_core_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x822 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x108 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x8003 Offcore demand data reads satisfied by the LLC and HIT in a sibling core umask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF02 offcore_response.demand_rfo.local_cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x8080 Offcore other requests satisfied by the IO, CSR, MMIO unit offcore_response.pf_data.any_location offcore_response.pf_data.llc_hit_no_other_core offcore_response.pf_data_rd.any_location offcore_response.pf_ifetch.llc_hit_other_core_hitm Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core SSE* FP double precision Uops 128 bit SIMD integer shift operations simd_int_128.shuffle_move umask=0x10,period=200000,event=0xfd umask=0x2,period=200000,event=0xfd offcore_response.any_data.any_llc_miss Offcore code reads satisfied by the local DRAM offcore_response.any_ifetch.remote_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2008 offcore_response.data_ifetch.any_dram offcore_response.demand_data.any_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4004 Offcore demand RFO requests satisfied by a remote DRAM offcore_response.other.any_dram Offcore prefetch RFO requests satisfied by any DRAM Offcore prefetch requests that missed the LLC Offcore prefetch requests satisfied by the local DRAM I/O transactions umask=0x4,period=2000000,event=0x13 rat_stalls.rob_read_port br_inst_exec.indirect_near_call All non call branches executed Mispredicted branches executed Instructions that must be decoded by decoder 0 umask=0x1,period=20000,event=0xc3 uops_executed.port015_stall_cycles umask=0x2,period=2000000,event=0xe inst_retired.total_cycles_ps umask=0x20,period=200000,event=0xc8 umask=0x80,period=200000,event=0xcb Counts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches from L1 and L2. It does not include all misses to the L3 Spec update: SKL057 L1D miss outstandings duration in cycles Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore umask=0x2,period=200003,event=0xf2 Counts demand instruction fetches and L1 instruction cache prefetches that umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080400004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200100004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0080004 offcore_response.demand_data_rd.l4_hit_local_l4.any_snoop offcore_response.demand_data_rd.l3_hit_m.snoop_miss Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall. Precise Event (Precise event) Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall. Precise Event (Precise event) hle_retired.aborted_mem rtm_retired.aborted_events umask=0x1,period=100003,event=0xb7,offcore_rsp=0x007C400004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000040002 offcore_response.demand_rfo.supplier_none.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000100001 Number of PREFETCHNTA instructions executed int_misc.clear_resteer_cycles Counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 2 Counts demand data loads that caused a completed page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels. The page walk can end with or without a fault Counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault rehabq.ld_block_std_notready umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000018008 Counts demand and DCU prefetch data read that miss L2 TAKEN_JCC counts the number of taken conditional branch (JCC) instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) All retired load uops. (Precise Event - PEBS) (Precise event) offcore_response.all_pf_rfo.llc_hit.hitm_other_core Counts demand code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Counts all prefetch (that bring data to L2) data reads that hit in the LLC Counts all prefetch (that bring data to L2) RFOs that hit in the LLC Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded offcore_response.pf_llc_code_rd.llc_hit.hitm_other_core Counts all prefetch (that bring data to LLC only) RFOs that hit in the LLC umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0100 REQUEST = PF_RFO and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM offcore_response.data_in.all_local_dram_and_remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0xff03 umask=0x1,period=100000,event=0xb7,offcore_rsp=0xff80 REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HITM umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f40 REQUEST = PREFETCH and RESPONSE = REMOTE_CACHE_HITM umask=0x1,period=100000,event=0xb7,offcore_rsp=0x30ff offcore_response.any_rfo.other_local_dram REQUEST = PF_RFO and RESPONSE = REMOTE_DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5822 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5877 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5803 offcore_response.demand_code_rd.l3_hit.no_snoop_needed Counts demand instruction fetches and L1 instruction cache prefetches that TBD TBD offcore_response.all_pf_data_rd.l3_hit.no_snoop_needed offcore_response.all_rfo.l3_hit.no_snoop_needed offcore_response.demand_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd offcore_response.pf_l3_data_rd.l3_miss.remote_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063FC00100 offcore_response.all_data_rd.l3_miss.snoop_miss_or_no_fwd umask=0x2,period=2000003,event=0xef unc_iio_data_req_of_cpu.mem_write.part2 unc_cha_core_snp.evict_gtone umask=0x02,event=0x54 umask=0x01,event=0x5b Write request of 4 bytes made to IIO Part1 by the CPU. Unit: uncore_iio Read request for up to a 64 byte transaction is made by the CPU to IIO Part0. Unit: uncore_iio Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) to the MMIO space of a card on IIO Part0. In the general case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus fc_mask=0x07,ch_mask=0x01,umask=0x04,event=0x84 unc_iio_txn_req_of_cpu.mem_write.part3 Multi-socket cacheline Directory lookup (cacheline found in S state) . Unit: uncore_m2m umask=0x10,event=0x2e Prefetches generated by the flow control queue of the M3UPI unit. Unit: uncore_m3upi This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD offcore_response.other.l3_hit_f.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040120 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD offcore_response.all_pf_data_rd.l3_hit_f.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10000207F7 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010020 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0490 offcore_response.all_data_rd.supplier_none.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020491 offcore_response.all_pf_rfo.l3_hit_e.any_snoop This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_MISS offcore_response.demand_rfo.l3_hit_f.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040004 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0491 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED offcore_response.demand_rfo.l3_hit_f.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040004 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080100 offcore_response.pf_l2_rfo.l3_hit_f.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040080 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080490 offcore_response.all_data_rd.pmm_hit_local_pmm.snoop_not_needed This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200400 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100010 offcore_response.pf_l3_data_rd.l3_hit_s.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200004 offcore_response.all_pf_data_rd.l3_hit_s.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020002 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_NONE offcore_response.pf_l2_rfo.l3_hit_m.snoop_none This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080400 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000018000 offcore_response.all_rfo.l3_hit_m.snoop_miss This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C07F7 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100004 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020490 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80048000 period=2000003,umask=0x1,event=0x48 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0120 offcore_response.all_rfo.l3_hit_e.hitm_other_core This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP PMM_Write_BW period=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000002 ocr.pf_l2_rfo.l3_miss.hit_other_core_fwd offcore_response.all_data_rd.l3_miss_remote_hop1_dram.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000004 ocr.pf_l3_rfo.l3_miss_local_dram.any_snoop period=2000003,umask=0x1,event=0x5d ocr.pf_l1d_and_sw.l3_miss.no_snoop_needed ALL_RFO & L3_MISS_LOCAL_DRAM & SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000100 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.REMOTE_HITM period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000002 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000080 offcore_response.all_reads.l3_miss.snoop_miss offcore_response.all_rfo.l3_miss_remote_hop1_dram.no_snoop_needed ocr.all_pf_data_rd.l3_miss.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000490 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090008000 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000122 offcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.any_snoop This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE Counts any other requests OTHER & L3_MISS & REMOTE_HIT_FORWARD ALL_PF_RFO & L3_MISS_REMOTE_HOP1_DRAM & ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00080 Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000080 ocr.pf_l2_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd ocr.other.l3_miss_remote_hop1_dram.hit_other_core_fwd Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS & HITM_OTHER_CORE ocr.all_rfo.l3_miss.remote_hitm period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000020 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000002 Counts demand data reads DEMAND_DATA_RD & L3_MISS & SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000122 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC08000 offcore_response.all_data_rd.l3_miss_local_dram.no_snoop_needed Counts demand data reads DEMAND_DATA_RD & L3_MISS & REMOTE_HIT_FORWARD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00100 Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS_LOCAL_DRAM & HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000002 ocr.demand_code_rd.l3_miss.no_snoop_needed cmask=6,period=2000003,umask=0x10,event=0x60 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD ALL_RFO & L3_MISS & HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000080 Counts all demand data writes (RFOs) DEMAND_RFO & L3_MISS_LOCAL_DRAM & ANY_SNOOP ALL_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & SNOOP_MISS This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE ocr.demand_rfo.l3_miss.any_snoop ALL_PF_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISS This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE offcore_response.demand_code_rd.l3_miss_remote_hop1_dram.no_snoop_needed ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd offcore_response.all_reads.l3_miss_local_dram.snoop_miss This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.SNOOP_MISS ocr.all_pf_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP ocr.all_reads.l3_hit_f.no_snoop_needed ALL_READS & L3_HIT_M & HIT_OTHER_CORE_FWD ocr.demand_code_rd.l3_hit_e.any_snoop ocr.all_rfo.supplier_none.no_snoop_needed Counts any other requests OTHER & L3_HIT_E & HIT_OTHER_CORE_FWD Counts any other requests OTHER & L3_HIT_E & HIT_OTHER_CORE_NO_FWD ocr.demand_rfo.l3_hit_f.snoop_none Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT & SNOOP_MISS Counts demand data reads DEMAND_DATA_RD & L3_HIT_S & HITM_OTHER_CORE Counts demand data reads hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores ocr.demand_code_rd.l3_hit.snoop_miss ALL_PF_RFO & L3_HIT_F & NO_SNOOP_NEEDED ocr.demand_data_rd.supplier_none.snoop_none ocr.all_pf_data_rd.l3_hit_s.hitm_other_core ALL_PF_RFO & L3_HIT_S & NO_SNOOP_NEEDED Counts all demand code reads DEMAND_CODE_RD & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDED ocr.pf_l2_data_rd.l3_hit_e.snoop_miss ocr.all_pf_rfo.pmm_hit_local_pmm.any_snoop Counts any other requests OTHER & L3_HIT & SNOOP_NONE Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_S & HIT_OTHER_CORE_FWD ALL_PF_RFO & L3_HIT_F & HIT_OTHER_CORE_NO_FWD ocr.pf_l1d_and_sw.l3_hit.any_snoop ocr.pf_l3_data_rd.l3_hit.hitm_other_core ocr.demand_code_rd.l3_hit_f.hitm_other_core ocr.all_data_rd.l3_hit.snoop_none Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & PMM_HIT_LOCAL_PMM & SNOOP_NONE ocr.pf_l1d_and_sw.l3_hit_f.hitm_other_core Counts all demand code reads DEMAND_CODE_RD & PMM_HIT_LOCAL_PMM & ANY_SNOOP Counts demand data reads DEMAND_DATA_RD & L3_HIT & ANY_SNOOP ocr.other.l3_hit_s.snoop_none ALL_PF_DATA_RD & L3_HIT_S & SNOOP_MISS ocr.demand_data_rd.l3_hit_m.hit_other_core_no_fwd ocr.pf_l2_rfo.l3_hit_s.hit_other_core_no_fwd Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_F & ANY_SNOOP ocr.demand_rfo.supplier_none.hit_other_core_no_fwd ocr.demand_code_rd.l3_hit_m.snoop_none ALL_DATA_RD & SUPPLIER_NONE & NO_SNOOP_NEEDED ocr.pf_l1d_and_sw.l3_hit.no_snoop_needed Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_M & NO_SNOOP_NEEDED Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT & HIT_OTHER_CORE_FWD ocr.pf_l2_data_rd.l3_hit_s.hit_other_core_fwd ALL_DATA_RD & SUPPLIER_NONE & HITM_OTHER_CORE Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT & HIT_OTHER_CORE_NO_FWD ocr.pf_l3_data_rd.l3_hit_e.hit_other_core_fwd cmask=1,inv=1,period=2000003,umask=0x2,event=0xc2 br_inst_retired.cond_ntaken Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide period=400009,umask=0x4,event=0xc4 umask=0x2,event=0xea Tag Check; Dirty Ingress (from CMS) Request Queue Rejects; PhyAddr Match fc_mask=0x07,ch_mask=0x04,umask=0x08,event=0xc0 Counts every peer to peer write request of 4 bytes of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus Peer to peer write request of up to a 64 byte transaction is made to IIO Part2 by a different IIO unit. Unit: uncore_iio umask=0x80,event=0x38 Dirty line read hits(Regular and RFO) to Near Memory(DRAM cache) in Memory Mode. Unit: uncore_m2m unc_m2m_tag_hit.nm_ufill_hit_clean period=100007,umask=0x1,event=0xbd Cycles MITE is delivering optimal number of Uops umask=0x1,period=100007,event=0xc6,frontend=0x502006 assists.any Number of instructions retired. Fixed Counter - architectural event lsd.cycles_ok Counts taken branch instructions retired (Precise event) misc_retired.pause_inst umask=0x1,period=100003,event=0xb7,offcore_rsp=0x000000003F04000002 TOR Inserts; CRd Pref misses from local IA. Unit: uncore_cha event=0x8e bp_l1_tlb_miss_l2_hit ic_cache_inval.fill_invalidated l2_request_g1.change_to_x l2_request_g2.group1 Miscellaneous events covered in more detail by l2_request_g1 (PMCx060) l2_request_g2.ls_rd_sized umask=0x40,event=0x61 umask=0x20,event=0x61 All L2 Cache Requests (Breakdown 2 - Rare). Bus locks Core to L2 cacheable request access status (not including L2 Prefetch). Data cache request miss in L2 (all types) l2_cache_req_stat.ic_fill_hit_s umask=0x4,event=0xcb ex_ret_mmx_fp_instr.x87_instr ex_div_count umask=0x8E,event=0x8b df_ccm_reqa.node5.wrsizedfullnc umask=0x8A,event=0x8b df_ccm_reqa.node6.rdsizednc df_ccm_reqa.node1.rdvlkx df_ccm_reqa.node4.rdvlkx umask=0x41,event=0x8b umask=0x4E,event=0x8c df_ccm_reqb.node2.anyiorequest. df_ccm_reqb.node3.anyiorequest. umask=0xA5,event=0x8c umask=0x03,event=0x8c df_ccm_reqb.node1.wrsizedfullncposted umask=0xAA,event=0x108 umask=0x08,event=0x108 umask=0xC7,event=0x108 df_ioms_reqa.node6.anywrsized=64b df_ioms_reqa.node6.anywrsized>32band<64b df_ioms_reqb.node5.pieiorequest df_ioms_reqb.node6.pieiorequest Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered piesystemmanagement df_ioms_reqb.node5.piesystemmanagement df_ioms_reqb.node6.pieinterrupt umask=0x6C,event=0x109 umask=0x6A,event=0x109 Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized>32band<64b Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized=32 umask=0xE4,event=0x109 The number of serializing Ops retired. SSE bottom-executing uOps retired l3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x02,event=0x1 l3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x02,event=0x1 l3_request_g1.t7.s3.wrsizednc l3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x20,event=0x1 l3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x80,event=0x1 l3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x80,event=0x1 l3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x80,event=0x1 l3_request_g1.t2.s2.caching l3fillvicreq.t2.s0.vicblk l3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x02,event=0x3 l3fillvicreq.t7.s2.chgtox l3fillvicreq.t3.s1.rdblkc_s_vic l3fillvicreq.t5.s2.rdblkc_s_vic l3fillvicreq.t5.s0.rdblkc_s l3fillvicreq.t6.s3.rdblkc_s l3fillvicreq.t1.s0.rdblkx_vic l3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x10,event=0x3 l3fillvicreq.t5.s3.rdblkx_vic l3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x20,event=0x3 l3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x40,event=0x3 l3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x80,event=0x3 l3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x80,event=0x3 l3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x01,event=0x9 l3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x01,event=0x9 l3victimstate.t6.s2.nol3victimline l3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x02,event=0x9 l3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x04,event=0x9 l3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x04,event=0x9 l3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x08,event=0x9 l3victimstate.t4.s1.o l3victimstate.t7.s1.o l3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x08,event=0x9 l3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x10,event=0x9 l3victimstate.t3.s3.e_fe l3victimstate.t3.s0.m l3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x20,event=0x9 l3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x40,event=0x9 l3victimstate.t6.s2.d l3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x80,event=0x9 ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 3 Tokens unavailable L2 Branch Prediction Overrides Existing Prediction (speculative) umask=0x2,event=0x94 Retired lock instructions. Non-speculative lock succeeded ls_int_taken Demand Data Cache Fills by Data Source. Hit in cache; Remote CCX and the address's Home Node is on a different die umask=0x40,event=0x59 ls_sw_pf_dc_fill.ls_mabresp_lcl_l2 umask=0x1,event=0xae IC_FETCH NB_MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOW ISSUE_DNOT_DISPATCH_ANY_INSTR DATA_MICRO_TLB_MISS_STALL PLE_FIFO_FLUSH L1I_TLB_REFILL MEMORY_ERROR UNALIGNED_LDST_SPEC ST_SPEC EXC_TRAP_PABORT MEM_WORD_READ MEM_DWORD_READ RETURN_NOT_31 BARRIER_COMPLETED UNCACHED_STORE CP2_REG_TO_REG_COMPLETED OOO_AGEN_ISSUE_CYCLES JALR_JALR_HB_INSNS MISPREDICTED_JR_31_INSNS J_JAL_INSNS WBB_LESS_25_FULL UUSTORE CPREF THRESHOLD_INSTR_QUEUE_ENTRIES_CYCLES L1_INSTR_CACHE_ACCESSES WRITE_THROUGH_STORES LSU_TOUCH_LINE_ALIAS_VS_FSQ_WB0_WB1 L1_DATA_TOTAL_MISS L2_LOAD_HITS SNOOP_VALID L2_VALID_REQUEST SRQ_EMPTY DATA_MMU_MISS SNOOP_HITS STASH_BUSY_3 L2_INCOHERENT_LINE_INVALIDATIONS COHERENT_LOOKUP_MISS_DUE_TO_VALID_BUT_INCOHERENT_MATCHES scrubber misses tag-snoop x87-reclass-microfaults INVERT ARMV8_CORTEX_A53 state error unit: %s
{"type": "pmcallocate" GenuineIntel-6-5F GenuineIntel-6-2D GenuineIntel-6-7D IPC Instructions Per Cycle (per physical core) C7_Core_Residency C2 residency percent per package L2 cache misses when fetching instructions l2_rqsts.demand_data_rd_hit Cycles with L1D load Misses outstanding from any thread on physical core mem_uops_retired.lock_loads Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS) Supports address when precise. Spec update: BDM100 (Precise event) This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required Supports address when precise. Spec update: BDM100 (Precise event) This event counts transactions that access the L2 pipe including snoops, pagewalks, and so on fp_arith_inst_retired.128b_packed_double Uops delivered to Instruction Decode Queue (IDQ) from MITE path umask=0x1,period=2000003,event=0x9c This event counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4 umask=0x1,cmask=2,period=2000003,event=0x9c umask=0x2,period=2000003,event=0x5 tx_exec.misc1 Unfriendly TSX abort triggered by a nest count that is too deep Number of times an RTM execution aborted due to incompatible memory type Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt) Unhalted core cycles when thread is in rings 1, 2, or 3 event=0xc0 int_misc.rat_stall_cycles umask=0x8,period=2000003,event=0xd Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not umask=0x1,period=2000003,event=0x3c Number of SIMD Move Elimination candidate uops that were not eliminated ild_stall.lcp Taken speculative and retired macro-conditional branches umask=0xc4,period=200003,event=0x88 This event counts both taken and not taken speculative and retired mispredicted macro conditional branch instructions uops_executed_port.port_5 Cycles per core when uops are exectuted in port 6 inv=1,umask=0x1,cmask=1,period=2000003,event=0xb1 Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes br_inst_retired.near_return llc_misses.pcie_non_snoop_write power_self_refresh % power_state_occupancy.cores_c3 % unc_p_prochot_external_cycles freq_max_limit_thermal_cycles % umask=0x2,period=2000003,event=0x8 Code misses that miss the DTLB and hit the STLB (2M) STLB flush attempts Retiring_SMT Total issue-pipeline slots (per-Physical Core) Memory_BW umask=0x1,period=2000003,cmask=1,event=0x48 umask=0x2,period=2000003,cmask=1,event=0x48 offcore_response.demand_data_rd.l3_hit.snoop_hitm offcore_response.demand_rfo.l3_hit.snoop_none offcore_response.demand_code_rd.supplier_none.snoop_not_needed Counts writebacks (modified to exclusive) Counts all prefetch (that bring data to L2) RFOs offcore_response.other.supplier_none.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C8000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020240 offcore_response.all_pf_code_rd.l3_hit.snoop_miss offcore_response.all_rfo.supplier_none.snoop_none This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1. Uses PEBS umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000001 offcore_response.demand_code_rd.l3_miss_local_dram.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000020 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000020 offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000100 offcore_response.pf_l3_rfo.l3_miss.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004008000 offcore_response.other.l3_miss.snoop_none offcore_response.other.l3_miss.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000090 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000240 offcore_response.all_data_rd.l3_hit.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000091 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000122 umask=0x2,period=2000003,cmask=1,event=0xb1 unc_arb_trk_occupancy.drd_direct ( 64 * ( uncore_imc@cas_count_read@ + uncore_imc@cas_count_write@ ) / 1000000000 ) / duration_time This event counts load uops with locked access retired to the architected path Supports address when precise. Spec update: BDM35 (Precise event) Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI) Supports address when precise. Spec update: BDE70 (Precise event) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C07F7 offcore_response.all_code_rd.llc_miss.any_response QPI clock ticks. Unit: uncore_qpi l2_m_lines_out.self.any l2_ld_ifetch.self.e_state l2_rqsts.self.any.i_state umask=0x4f,period=200000,event=0x30 umask=0x51,period=200000,event=0x30 L1 Data Cacheable reads and writes mem_load_retired.l2_miss x87_comp_ops_exe.any.ar simd_uop_type_exec.mul.s SIMD assists invoked simd_sat_instr_retired Icache hit Decode stall due to PFB empty misalign_mem_ref.split.ar bus_lock_clocks.all_agents umask=0x40,period=200000,event=0x67 umask=0x40,period=200000,event=0x68 umask=0x20,period=200000,event=0x7a bus_hit_drv.this_agent snoop_stall_drv.all_agents store_forwards.any mul.s Mispredicted ind branches that are not calls umask=0x1,period=200000,event=0x82 Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data reads (demand & prefetch) that hit the L2 cache Counts data reads generated by L1 or L2 prefetchers that true miss for the L2 cache with a snoop miss in the other processor module Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200004000 Counts demand data partial reads, including data in uncacheable (UC) or uncacheable write combining (USWC) memory types that miss the L2 cache umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200000020 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000000010 Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts the number of writeback transactions caused by L1 or L2 cache evictions that true miss for the L2 cache with a snoop miss in the other processor module Decode restrictions due to predicting wrong instruction length Counts anytime a load that retires is blocked for any reason (Must be precise) Uops issued to the back end per cycle umask=0x0,period=200003,event=0xc3 Counts the number of times that the processor detects that a program is writing to a code section and has to perform a machine clear because of that modification. Self-modifying code (SMC) causes a severe penalty in all Intel® architecture processors baclears.return Duration of page-walks in cycles Store uops retired that missed the DTLB (Precise event capable) Supports address when precise (Must be precise) Counts demand reads for ownership (RFO) requests generated by a write to full data cache line miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts the number of writeback transactions caused by L1 or L2 cache evictions have any transaction responses from the uncore subsystem Counts data cacheline reads generated by hardware L2 cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module Counts data cache line reads generated by hardware L1 data cache prefetcher hit the L2 cache Counts data cache line reads generated by hardware L1 data cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts requests to the uncore subsystem outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts reads for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Integer divide uops retired (Precise Event Capable) (Must be precise) umask=0x10,period=200003,event=0x85 All L2 requests Spec update: HSD78 offcore_response.pf_l2_data_rd.l3_hit.any_response offcore_response.demand_code_rd.l3_hit.hitm_other_core Counts cycles MITE is delivered four uops. Set Cmask = 4 Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100400004 Cycles which a uop is dispatched on port 0 in this thread This events counts the cycles where at least three uop were executed. It is counted per thread Spec update: HSD144, HSD30, HSM31 Cycles at least 4 micro-op is executed from any thread on physical core Spec update: HSD30, HSM31 unc_cbo_cache_lookup.extsnp_i Number of ITLB page walker hits in Memory Spec update: HSD25 umask=0x41,period=2000003,event=0xbc offcore_response.pf_l2_code_rd.llc_miss.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0600400091 l2_rqsts.pf_hit RFOs that hit cache lines in M state umask=0xf,period=200003,event=0x28 Core-originated cacheable demand requests that refer to LLC Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore Demand data read requests sent to uncore Retired store uops that split across a cacheline boundary. (Precise Event) Counts all demand & prefetch data reads that hit in the LLC Counts all demand code reads that hit in the LLC umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00010002 fp_comp_ops_exe.sse_scalar_double Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines min( 1 , uops_issued.any / ( (uops_retired.retire_slots / inst_retired.any) * 32 * ( icache.hit + icache.misses ) / 4 ) ) offcore_response.all_data_rd.llc_miss.dram Cycles that the divider is active, includes INT and FP. Set 'edge =1, cmask=1' to count the number of divides umask=0x4,edge=1,period=100003,cmask=1,event=0x14 Cycles per thread when uops are dispatched to port 1 Cycles per thread when uops are dispatched to port 4 Unit: uncore_cbox A snoop hits a non-modified line in some processor core umask=0x20,event=0x34 Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded offcore_response.pf_l2_data_rd.llc_hit.hit_other_core_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0080 Counts all data/code/rfo reads (demand & prefetch) that miss the LLC the data is found in M state in remote cache and forwarded from there Counts demand data reads that miss the LLC and the data forwarded from remote cache event=0xe event=0xb,edge=1 unc_p_freq_ge_3000mhz_transitions Miss in last-level (L3) cache. Excludes Unknown data-source umask=0x2,period=2000003,event=0x51 uops_dispatched.thread / (( cpu@uops_dispatched.core\,cmask\=1@ / 2 ) if #smt_on else cpu@uops_dispatched.core\,cmask\=1@) hw_pre_req.dl1_miss Resource stalls2 control structures full for physical registers resource_stalls.mem_rs umask=0xa,event=0x36,filter_opc=0x182 QPI clock ticks. Used to get percentages of QPI cycles events. Unit: uncore_qpi Counts the number of times that the uncore transitioned a frequency greater than or equal to the frequency that is configured in the filter. (filter_band0=XXX with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Derived from unc_p_freq_band0_cycles. Unit: uncore_pcu Counts the number of times that the uncore transistioned to a frequency greater than or equal to the frequency that is configured in the filter. (filter_band1=XXX with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Derived from unc_p_freq_band1_cycles. Unit: uncore_pcu offcore_response.any_read.l2_hit_near_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400044 offcore_response.any_data_rd.l2_hit_far_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000403091 offcore_response.any_request.l2_hit_near_tile_e_f Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state Counts UC code reads (valid only for Outstanding response type) that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0 Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode Counts L2 code HW prefetches that accounts for responses which hit its own tile's L2 with data in E state Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in E state offcore_response.any_read.l2_hit_this_tile_s Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in F state offcore_response.pf_software.l2_hit_near_tile umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800180022 Counts any Read request that accounts for data responses from DRAM Local offcore_response.any_code_rd.ddr_near offcore_response.any_rfo.mcdram_far Counts Bus locks and split lock requests that accounts for data responses from MCDRAM Local Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from MCDRAM Local Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from DRAM Local Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM Far or Other tile L2 hit far offcore_response.pf_software.mcdram Counts the number of micro-ops retired that are from the complex flows issued by the micro-sequencer (MS) no_alloc_cycles.rob_full Counts the total number of core cycles the Alloc pipeline is stalled when any one of the reservation stations is full br_misp_retired.call umask=0x01,event=0x3 L1 data cache load locks in E state umask=0x2,period=200000,event=0x4e l1d_wb_l2.mesi umask=0x1,period=200000,event=0x26 L2 instruction fetch hits umask=0xc,period=200000,event=0x24 umask=0x80,period=200000,event=0xf0 l2_transactions.load L2 demand lock RFOs in E state umask=0x80,period=100000,event=0x27 umask=0x10,period=10000,event=0xcb umask=0x8,period=40000,event=0xcb mem_inst_retired.latency_above_threshold_1024 umask=0x10,period=10,event=0xb,ldlat=0x2000 Offcore data reads satisfied by the LLC and HITM in a sibling core offcore_response.any_data.local_cache_dram offcore_response.any_data.remote_cache_hit offcore_response.any_ifetch.llc_hit_other_core_hitm Offcore code reads satisfied by the LLC All offcore requests Offcore RFO requests that HIT in a remote cache Offcore writebacks to the LLC and not found in a sibling core Offcore request = all data, response = any location Offcore data reads, RFO's and prefetches that HITM in a remote cache Offcore demand data requests satisfied by a remote cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x803 Offcore demand data reads satisfied by the IO, CSR, MMIO unit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F04 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3804 offcore_response.demand_rfo.any_cache_dram Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1880 offcore_response.other.remote_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x8040 offcore_response.pf_ifetch.local_cache_dram offcore_response.pf_ifetch.remote_cache_dram offcore_response.pf_rfo.remote_cache_dram All Floating Point to and from MMX transitions simd_int_128.packed_arith umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2011 offcore_response.any_ifetch.local_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x20FF offcore_response.corewb.local_dram Offcore demand data reads satisfied by any DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF801 Offcore demand code reads satisfied by the local DRAM offcore_response.demand_ifetch.remote_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF820 L1I Instruction fetches umask=0x2,period=2000000,event=0x13 umask=0x4,period=100000,event=0xb8 Mispredicted call branches executed Reference cycles when thread is not halted (fixed counter) inv=1,umask=0x0,period=2000000,cmask=2,event=0x3c Execution pipeline restart due to Memory ordering conflicts Other Resource related stall cycles SIMD Packed-Double Uops retired (Precise Event) umask=0x4,period=2000000,event=0xd1 uops_decoded.ms_cycles_active umask=0x1f,any=1,period=2000000,cmask=1,event=0xb1 uops_executed.core_stall_cycles umask=0x4,any=1,period=2000000,event=0xb1 Uops issued on ports 2, 3 or 4 inv=1,umask=0x1,period=2000000,cmask=1,event=0xe umask=0x1,period=2000000,event=0xc2 dtlb_misses.walk_completed umask=0x1,period=2000000,event=0xae offcore_requests.all_requests Retired load instructions that miss the STLB Supports address when precise Retired load instructions which data sources were HitM responses from shared L3 Supports address when precise (Precise event) Counts the number of L2 cache lines filling the L2. Counting does not cover rejects l2_lines_out.useless_pref offcore_response.other.l4_hit_local_l4.any_snoop offcore_response.other.l4_hit_local_l4.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04001C8000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00801C8000 offcore_response.other.l3_hit_s.snoop_none offcore_response.other.l3_hit_e.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400400004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040400002 offcore_response.demand_rfo.l3_hit_s.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100100002 offcore_response.demand_rfo.l3_hit_e.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200080002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040040001 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040020001 Counts the number of cycles 4 uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. Counting includes uops that may 'bypass' the IDQ. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB) umask=0x1,period=100007,event=0xc6,frontend=0x400206 umask=0x1,period=100007,event=0xc6,frontend=0x400406 frontend_retired.latency_ge_16 frontend_retired.latency_ge_2_bubbles_ge_3 Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ rtm_retired.aborted_timer offcore_response.demand_code_rd.l3_miss.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC4000004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x103C400001 Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to “Mixing Intel AVX and Intel SSE Code” section of the Optimization Guide umask=0x8,period=2000003,event=0xa6 uops_executed.x87 other_assists.any umask=0x40,period=2000003,event=0xcc Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore inst_retired.any / mem_inst_retired.all_stores Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake microarchitecture Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB) Counts code misses in all ITLB levels that caused a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault L2 cache requests from this core Counts any rfo reads (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Counts any data read (demand & prefetch) that miss L2 with a snoop miss response Counts any data read (demand & prefetch) that have any response type Counts any request that hit in the other module where modified copies were found in other core's L1 cache Counts code reads generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Counts the number of times the MSROM starts a flow of UOPS. It does not count every time a UOP is read from the microcode ROM. The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine. Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort. The event will count MSROM startups for UOPS that are speculative, and subsequently cleared by branch mispredict or machine clear. Background: UOPS are produced by two mechanisms. Either they are generated by hardware that decodes instructions into UOPS, or they are delivered by a ROM (called the MSROM) that holds UOPS associated with a specific instruction. MSROM UOPS might also be delivered in response to some condition such as a fault or other exceptional condition. This event is an excellent mechanism for detecting instructions that require the use of MSROM instructions JCC counts the number of conditional branch (JCC) instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) Counts the number of cycles and allocation pipeline is stalled and is waiting for a free MEC reservation station entry. The cycles should be appropriately counted in case of the cracked ops e.g. In case of a cracked load-op, the load portion is sent to M Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. In systems with a constant core frequency, this event can give you a measurement of the elapsed time while the core was not in halt state by dividing the event count by the core frequency. This event is architecturally defined and is a designated fixed counter. CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.CORE_P use the core frequency which may change from time to time. CPU_CLK_UNHALTE.REF_TSC and CPU_CLK_UNHALTED.REF are not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. The fixed events are CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.REF_TSC and the programmable events are CPU_CLK_UNHALTED.CORE_P and CPU_CLK_UNHALTED.REF Retired load uops with locked access. (Precise Event - PEBS) (Precise event) This event counts the number of store uops retired. (Precise Event - PEBS) (Precise event) Counts prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded offcore_response.all_rfo.llc_hit.snoop_miss Counts demand code reads that hit in the LLC and the snoops sent to sibling cores return clean response Counts prefetch (that bring data to L2) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores Counts all demand & prefetch prefetch RFOs offcore_response.pf_l_data_rd.any_response offcore_response.any_request.llc_miss_local.dram Offcore read requests offcore_requests_outstanding.any.read_not_empty offcore_requests_outstanding.demand.read_data offcore_requests_outstanding.demand.read_data_not_empty umask=0x4,period=2000000,event=0xf4 offcore_response.any_data.local_dram_and_remote_cache_hit offcore_response.any_request.local_dram_and_remote_cache_hit REQUEST = CORE_WB and RESPONSE = ANY_CACHE_DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f77 REQUEST = DEMAND_RFO and RESPONSE = ANY_LOCATION REQUEST = PF_DATA_RD and RESPONSE = ANY_CACHE_DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0xff70 misalign_mem_ref.store umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3077 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3003 offcore_response.demand_data_rd.other_local_dram REQUEST = PF_DATA_RD and RESPONSE = REMOTE_DRAM REQUEST = PF_RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD REQUEST = PF_IFETCH and RESPONSE = OTHER_LOCAL_DRAM REQUEST = PREFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD umask=0x2,period=2000000,cmask=1,event=0xb3 Mispredicted retired branch instructions (Precise Event) umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2708 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBC000002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x083FC00020 offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd offcore_response.pf_l1d_and_sw.l3_miss_remote_dram.snoop_miss_or_no_fwd unc_m_act_count.wr MMIO reads. Derived from unc_cha_tor_inserts.ia_miss. Unit: uncore_cha umask=0x21,event=0x35,config1=0x41a33 unc_iio_data_req_of_cpu.mem_write.part1 Local requests for exclusive ownership of a cache line without receiving data. Unit: uncore_cha Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus event=0x29 unc_m2m_directory_update.i2s umask=0x8,event=0x2e unc_upi_rxl0p_power_cycles umask=0x10,cmask=1,period=100003,event=0x85 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400028000 offcore_response.all_data_rd.l3_hit.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD period=20011,umask=0x2,event=0xd2 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400002 offcore_response.pf_l2_data_rd.l3_hit_s.hitm_other_core offcore_response.all_pf_rfo.l3_hit_f.no_snoop_needed period=20011,umask=0x4,event=0xd2 offcore_response.all_pf_rfo.l3_hit_s.hitm_other_core offcore_response.pf_l1d_and_sw.l3_hit_e.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040004 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020100 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD offcore_response.other.l3_hit.hitm_other_core This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020100 period=2000003,umask=0x8,event=0x60 offcore_response.all_reads.l3_hit_e.any_snoop offcore_response.pf_l2_data_rd.l3_hit_f.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020004 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040490 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200002 offcore_response.all_rfo.l3_hit_s.hitm_other_core offcore_response.pf_l3_rfo.l3_hit_e.no_snoop_needed This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE offcore_response.all_reads.l3_hit.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0004 offcore_response.all_reads.l3_hit_m.snoop_miss This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040002 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP offcore_response.demand_rfo.l3_hit_f.any_snoop offcore_response.all_data_rd.l3_hit_m.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010491 period=200003,umask=0x4,event=0xf2 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0122 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100120 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100001 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP This event is deprecated. Refer to new event OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020002 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020080 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00802007F7 offcore_response.all_pf_data_rd.l3_hit_f.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400004 offcore_response.demand_code_rd.pmm_hit_local_pmm.snoop_none This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020400 period=2000003,umask=0x1,event=0xd1 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100208000 offcore_response.pf_l3_data_rd.supplier_none.no_snoop_needed offcore_response.all_rfo.l3_hit_m.snoop_none ( 1000000000 * ( imc@event\=0xe0\\\,umask\=0x1@ / imc@event\=0xe3@ ) / imc_0@event\=0x0@ ) if 1 if 0 == 1 else 0 else 0 period=2000003,umask=0x80,event=0xc7 period=100007,umask=0x1,event=0xc6,frontend=0x100206 cmask=1,period=2000003,umask=0x8,event=0x79 period=200003,umask=0x4,event=0x83 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000010 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000400 offcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000122 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B8007F7 ALL_READS & L3_MISS_REMOTE_HOP1_DRAM & ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000400 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000122 ocr.all_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84008000 offcore_response.demand_rfo.l3_miss_remote_hop1_dram.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000004 offcore_response.demand_code_rd.l3_miss_remote_hop1_dram.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204008000 offcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.hitm_other_core This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP ALL_RFO & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD ocr.other.l3_miss_remote_dram.snoop_miss_or_no_fwd ALL_PF_DATA_RD & L3_MISS & HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC007F7 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000491 ocr.pf_l3_rfo.l3_miss.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000100 offcore_response.pf_l2_rfo.l3_miss.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l3_rfo.l3_miss_local_dram.hit_other_core_fwd Counts any other requests OTHER & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_FWD ocr.pf_l2_rfo.l3_miss.hitm_other_core offcore_response.other.l3_miss_remote_hop1_dram.hitm_other_core ocr.pf_l3_rfo.l3_miss.hit_other_core_fwd offcore_response.all_data_rd.l3_miss_local_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD ocr.pf_l3_rfo.l3_miss.remote_hit_forward period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000001 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000400 This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HITM_OTHER_CORE ocr.all_pf_data_rd.l3_miss_local_dram.snoop_none Counts demand data reads DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM ocr.pf_l3_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd offcore_response.pf_l1d_and_sw.l3_miss.no_snoop_needed ocr.demand_code_rd.l3_miss_local_dram.snoop_none offcore_response.demand_rfo.l3_miss_local_dram.hitm_other_core offcore_response.all_data_rd.l3_miss_remote_hop1_dram.hitm_other_core offcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD offcore_response.demand_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd ALL_PF_RFO & L3_MISS & HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD ocr.other.l3_hit_m.hitm_other_core ocr.other.l3_hit_e.any_snoop ocr.all_reads.l3_hit_f.snoop_miss ocr.pf_l2_rfo.l3_hit_m.snoop_none ALL_RFO & L3_HIT & NO_SNOOP_NEEDED ocr.other.l3_hit_m.snoop_miss Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_E & NO_SNOOP_NEEDED ocr.pf_l2_rfo.l3_hit_f.any_snoop ocr.pf_l2_data_rd.l3_hit.snoop_none ocr.all_data_rd.l3_hit_s.hit_other_core_fwd ALL_RFO & PMM_HIT_LOCAL_PMM & ANY_SNOOP Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_M & HIT_OTHER_CORE_FWD ALL_READS & L3_HIT_F & HIT_OTHER_CORE_FWD ocr.all_data_rd.l3_hit_f.snoop_miss ocr.demand_code_rd.l3_hit_f.any_snoop ocr.demand_code_rd.l3_hit_f.hit_other_core_fwd ocr.pf_l3_rfo.l3_hit_m.hit_other_core_no_fwd ocr.all_data_rd.pmm_hit_local_pmm.snoop_none period=100003,umask=0x2,event=0xfe ocr.other.supplier_none.no_snoop_needed Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & SUPPLIER_NONE & HITM_OTHER_CORE ALL_PF_RFO & L3_HIT & HIT_OTHER_CORE_NO_FWD ocr.demand_rfo.l3_hit.no_snoop_needed ocr.other.l3_hit.snoop_hit_with_fwd Counts any other requests OTHER & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWD ocr.demand_code_rd.pmm_hit_local_pmm.snoop_none ocr.pf_l3_data_rd.supplier_none.any_snoop Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & SUPPLIER_NONE & ANY_SNOOP ocr.pf_l3_data_rd.l3_hit_s.hit_other_core_fwd ocr.demand_rfo.supplier_none.any_snoop Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_F & HIT_OTHER_CORE_FWD ocr.pf_l3_data_rd.l3_hit_e.snoop_miss ALL_PF_RFO & L3_HIT_E & SNOOP_NONE ocr.pf_l2_data_rd.supplier_none.hitm_other_core Counts all demand code reads DEMAND_CODE_RD & L3_HIT_E & NO_SNOOP_NEEDED ALL_PF_RFO & L3_HIT_S & HIT_OTHER_CORE_NO_FWD ocr.all_data_rd.l3_hit_m.hit_other_core_no_fwd ocr.demand_code_rd.l3_hit_m.hitm_other_core ALL_DATA_RD & L3_HIT_F & HIT_OTHER_CORE_FWD ocr.pf_l2_rfo.l3_hit.snoop_hit_with_fwd Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT & HIT_OTHER_CORE_FWD ocr.all_pf_data_rd.l3_hit_e.hit_other_core_fwd ocr.other.l3_hit_f.no_snoop_needed Counts any other requests OTHER & L3_HIT_F & NO_SNOOP_NEEDED ocr.pf_l3_rfo.l3_hit_e.hit_other_core_fwd ALL_DATA_RD & SUPPLIER_NONE & HIT_OTHER_CORE_FWD cmask=1,inv=1,period=2000003,umask=0x1,event=0xb1 Intel Optane DC persistent memory bandwidth write (MB/sec). Derived from unc_m_pmm_wpq_inserts. Unit: uncore_imc Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target. Unit: uncore_iio fc_mask=0x07,ch_mask=0x01,umask=0x02,event=0xc1 unc_iio_txn_req_of_cpu.peer_read.part3 BL Egress (to CMS) Occupancy; All. Unit: uncore_m2m period=100003,umask=0x2,event=0x49 period=2000003,umask=0x20,event=0x8 umask=0x2,period=100003,cmask=1,event=0xc1 umask=0x8,period=2000003,cmask=5,event=0x79 Cycles when uops are being delivered to IDQ while MS is busy Counts the number of times a TSX line had a cache conflict Counts the number of available slots for an unhalted logical processor Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled. Use on Fixed Counter 0 (Must be precise) Counts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch Counts the number of load uops retired that hit the level 1 data cache Supports address when precise (Precise event) Counts the number of unhalted core clock cycles. (Fixed event) umask=0xC001FE01,event=0x35,config1=0x40e33 fc_mask=0x07,ch_mask=0x20,umask=0x04,event=0x83 fc_mask=0x07,ch_mask=0x80,umask=0x01,event=0x83 bp_l1_btb_correct The number of 64 byte instruction cache line fulfilled from system memory or another cache bp_l1_tlb_miss_l2_miss umask=0x8,event=0x64 umask=0x3f,event=0x9a umask=0xCE,event=0x8b umask=0x6C,event=0x8b umask=0x09,event=0x8b df_ccm_reqa.node2.specdramrd df_ccm_reqa.node4.anyrdblk umask=0xC5,event=0x8b umask=0xC3,event=0x8b umask=0xA1,event=0x8b umask=0x8E,event=0x8c umask=0xCE,event=0x8c df_ccm_reqb.node0.wbinvblkall umask=0x0B,event=0x8c df_ccm_reqb.node3.vicblkcln df_ccm_reqb.node7.vicblkcln umask=0x06,event=0x8c df_ccm_reqb.node7.wrsizedfullnc df_ioms_reqa.node0.masterabort umask=0x64,event=0x108 df_ioms_reqa.node5.anywrsized=32b df_ioms_reqa.node7.anywrsized=32b umask=0x83,event=0x108 df_ioms_reqa.node7.anywrsized<32b df_ioms_reqa.node4.anyrdsized umask=0x4F,event=0x109 umask=0x2A,event=0x109 umask=0xC6,event=0x109 df_ioms_reqb.node2.ioanypostedwrsized<32 This is a speculative event. The number of cycles in which the FPU scheduler is empty. Note that some Ops like FP loads bypass the scheduler Divide and square root Ops This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15 umask=0x2,event=0x3 fp_retired_ser_ops.sse_bot_ret l3_request_g1.t2.s3.wrsizednc l3_request_g1.t4.s0.rdsizednc l3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x20,event=0x1 l3_request_g1.t1.s2.rdsized l3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x80,event=0x1 l3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x02,event=0x3 l3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x02,event=0x3 l3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x04,event=0x3 l3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x08,event=0x3 l3fillvicreq.t4.s1.rdblkc_s l3fillvicreq.t3.s2.rdblkc_s l3fillvicreq.t0.s3.rdblkc_s l3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x10,event=0x3 l3fillvicreq.t2.s1.rdblkx_vic l3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x10,event=0x3 l3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x10,event=0x3 l3fillvicreq.t6.s0.rdblkx l3fillvicreq.t2.s1.rdblkx l3fillvicreq.t1.s2.rdblkx l3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x40,event=0x3 l3fillvicreq.t2.s2.rdblkl_vic l3fillvicreq.t5.s3.rdblkl l3victimstate.t4.s0.nol3victimline l3victimstate.t4.s2.none_nol3victimline l3victimstate.t0.s3.none_nol3victimline l3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x04,event=0x9 l3victimstate.t5.s2.f_s l3victimstate.t0.s3.o l3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x08,event=0x9 l3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x10,event=0x9 l3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x10,event=0x9 l3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x10,event=0x9 l3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x10,event=0x9 l3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x10,event=0x9 l3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x10,event=0x9 l3victimstate.t2.s3.e_fe l3victimstate.t6.s1.m l3victimstate.t7.s1.m l3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x20,event=0x9 l3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x40,event=0x9 l3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x40,event=0x9 LS MAB allocates by type - DC prefetcher bp_l1_tlb_fetch_hit umask=0x4,event=0x94 bp_l1_tlb_miss_l2_tlb_miss.if1g Total number of fp uOps umask=0x2,event=0x43 L1 DTLB Miss. DTLB reload hit a coalesced page ls_pref_instr_disp Software Prefetch Data Cache Fills by Data Source. From DRAM (home node remote) Hardware Prefetch Data Cache Fills by Data Source. From another cache (home node remote) Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Load queue resource stall. Applies to all ops with load semantics LS_MICROARCHITECTURAL_RESYNC_BY_SELF_MODIFYING_CODE DC_REFILL_FROM_L2 FR_RETIRED_NEAR_RETURNS MEM_UNALIGNED_ACCESS_REPLAY L1D_CACHE_INVAL EXC_TRAP_FIQ STORE_COMPLETED ICACHE_REQUESTS BRANCH_MISPRED_CYCLES L2_CACHE_SINGLE_BIT_ERRORS OCP_ALL_CACHEABLE_REQUESTS UULOAD CFETCH INSTR_COMPLETED L1_DATA_SNOOPS TRUE_BRANCH_TARGET_HITS GPR_ISSUE_QUEUE_DISPATCHES MTSPR_INSTR_COMPLETED DATA_BKPT_MATCHES STWCX_INSTR_COMPLETED TOUCHES_TRANSLATED_ALLOCATED_TO_DLFB DATA_L1_CACHE_CASTOUTS STASH_REQUESTS_L2 L2_COHERENT_LINE_INVALIDATIONS inv cancelled probe-hit THRESHOLD QUALIFIER UCP INTEL_CORE2EXTREME TC pme->table[idx].name %s
LLC-MISS-RHITM br_misp_retired.all_branches ch_mask %s, "pmcid": "0x%08x", "pid": "%d", "value": "0x%016jx"}
GenuineIntel-6-3F v2 GenuineIntel-6-2E Per-thread actual clocks when the logical processor is active. This is called 'Clockticks' in VTune Core actual clocks when any thread is active on the physical core l2_rqsts.demand_data_rd_miss L1D data line replacements umask=0x1,cmask=1,period=2000003,event=0x60 umask=0x4,cmask=1,period=2000003,event=0x60 umask=0x4,period=100003,event=0xb0 This is a precise version (that is, uses PEBS) of the event that counts load uops with locked access retired to the architected path Supports address when precise. Spec update: BDM35 (Precise event) This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting excludes unknown and UC data source Supports address when precise (Precise event) l2_lines_in.s umask=0x10,period=2000003,event=0xc7 umask=0x2a,period=2000005,event=0xc7 umask=0x2,period=2000003,event=0x79 umask=0x10,cmask=1,period=2000003,event=0x79 idq.all_dsb_cycles_4_uops This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ umask=0x2,period=2000003,event=0x54 Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer Number of times an HLE execution aborted due to uncommon conditions hle_retired.aborted_misc3 cpl_cycles.ring0 umask=0x20,period=2000003,event=0xe Count XClk pulses when this thread is unhalted and the other thread is halted Number of integer Move Elimination candidate uops that were eliminated rs_events.empty_cycles br_inst_exec.taken_direct_jump br_inst_exec.taken_indirect_jump_non_call_ret umask=0x90,period=200003,event=0x88 br_inst_exec.all_branches Cycles stalled due to no eligible RS entry available Cycles while L1 cache miss demand load is outstanding umask=0x1,cmask=1,period=2000003,event=0xb1 umask=0x40,period=100003,event=0xc1 umask=0x2,period=2000003,event=0xc2 umask=0x0,period=400009,event=0xc4 This is a precise version (that is, uses PEBS) of the event that counts mispredicted return instructions retired Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end umask=0x3,event=0x35,filter_opc=0x192 unc_h_requests.reads_local event=0x86 unc_m_power_self_refresh umask=0x8,event=0x2 This is an occupancy event that tracks the number of cores that are in C0. It can be used by itself to get the average number of cores in C0, with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details. Unit: uncore_pcu umask=0x40,period=100003,event=0x49 Misses in all ITLB levels that cause completed page walks Spec update: BDM69 itlb_misses.stlb_hit_4k umask=0x18,period=2000003,event=0xbc page_walker_loads.itlb_l1 This event counts the number of DTLB flush attempts of the thread-specific entries Frontend_Bound FLOPc Branch_Misprediction_Cost_SMT Average data fill bandwidth to the L1 data cache [GB / sec] offcore_response.demand_data_rd.l3_hit.snoop_not_needed offcore_response.demand_rfo.l3_hit.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020004 offcore_response.corewb.l3_hit.snoop_hitm Counts prefetch (that bring data to L2) data reads have any response type umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020010 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020040 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020040 offcore_response.pf_l2_code_rd.l3_hit.snoop_hitm Counts all prefetch (that bring data to LLC only) data reads have any response type umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0122 Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element offcore_response.demand_data_rd.l3_hit.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000010 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000010 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000040 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000100 offcore_response.pf_l3_code_rd.l3_hit.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C8000 offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000240 offcore_response.all_rfo.l3_miss_local_dram.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000122 inv=1,umask=0x1,edge=1,period=200003,cmask=1,event=0x5e umask=0x1,period=2000003,cmask=1,event=0xa3 A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core Unit: uncore_cbox L3 Lookup any request that access cache and found line in MESI-state Unit: uncore_arb Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc All retired load uops Supports address when precise (Precise event) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00200 umask=0x51,period=200000,event=0x29 umask=0x4f,period=200000,event=0x2c umask=0x7f,period=200000,event=0x2e umask=0x42,period=200000,event=0x2e umask=0x82,period=2000000,event=0x10 umask=0x1,period=2000000,event=0xb3 simd_assist macro_insts.all_decoded Nonzero segbase ld-op-st 1 bubble bus_trans_rfo.all_agents bus_trans_p.all_agents Partial bus transactions bus_trans_any.self ext_snoop.this_agent.clean ext_snoop.all_agents.clean Micro-op reissues for any cause Micro-op reissues for any cause (At Retirement) br_missp_type_retired.return br_inst_retired.mispred_not_taken bogus_br umask=0x9,period=200000,event=0x8 Number of page-walks executed itlb.misses umask=0x1,period=200003,event=0x51 umask=0x83,period=200003,event=0xd0 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x00000432b7 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000043010 offcore_response.pf_l1_data_rd.l2_miss.any Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l1_data_rd.l2_hit offcore_response.full_streaming_stores.l2_hit offcore_response.pf_l2_data_rd.l2_miss.hit_other_core_no_fwd umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400000010 Counts data cacheline reads generated by hardware L2 cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module Counts demand cacheable data reads of full cache lines that are outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts when a memory load of a uop spans a page boundary (a split) is retired (Must be precise) issue_slots_not_consumed.resource_full Unfilled issue slots per cycle because of a full resource in the backend issue_slots_not_consumed.recovery Counts loads that block because their address modulo 4K matches a pending store (Must be precise) Loads blocked (Precise event capable) (Must be precise) MS uops retired (Precise event capable) (Must be precise) Counts far branch instructions retired. This includes far jump, far call and return, and Interrupt call and return (Must be precise) Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired, including both when the branch was supposed to be taken and when it was not supposed to be taken (but the processor predicted the opposite condition) (Must be precise) Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired that were supposed to be taken but the processor predicted that it would not be taken (Must be precise) Counts the number of writeback transactions caused by L1 or L2 cache evictions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts reads for ownership (RFO) requests generated by L2 prefetcher hit the L2 cache offcore_response.pf_l2_rfo.outstanding Counts bus lock and split lock requests miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000400 Counts data cache line reads generated by hardware L1 data cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000014800 offcore_response.streaming_stores.l2_miss.hitm_other_core Counts requests to the uncore subsystem true miss for the L2 cache with a snoop miss in the other processor module Counts data reads generated by L1 or L2 prefetchers have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0. You cannot collect a PEBs record for this event (Must be precise) Reference cycles when core is not halted. This event uses a (_P)rogrammable general purpose performance counter dtlb_store_misses.walk_pending tlb_flushes.stlb_any umask=0x20,period=20003,event=0xbd All requests that miss L2 cache Spec update: HSD78 Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e Counts prefetch (that bring data to L2) data reads hit in the L3 (Precise event) Speculative cache-line split load uops dispatched to L1D Stall cycles due to IQ is full Cycles at least 2 micro-op is executed from any thread on physical core Spec update: HSD30, HSM31 Cycles no executable uops retired (Precise event) Unit: uncore_cbox An external snoop hits a non-modified line in some processor core Unit: uncore_cbox A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core L3 Lookup external snoop request that access cache and found line in MESI-state Each cycle count number of valid entries in Coherency Tracker queue from allocation till deallocation. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access memory) Completed page walks due to store misses in one or more TLB levels of 2M/4M page structure offcore_response.pf_l2_rfo.llc_hit.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00080 umask=0x10,period=200003,event=0x24 umask=0x80,period=200003,event=0x24 umask=0x1,period=200003,event=0x28 umask=0x4,period=200003,event=0x28 Counts the number of lines brought into the L1 data cache Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache (Precise event) umask=0x1,period=2000003,event=0x10 umask=0x80,period=2000003,event=0x10 Cycles which a Uop is dispatched on port 3 Unit: uncore_cbox A snoop misses in some processor core umask=0x04,event=0x22 A snoop hits a non-modified line in some processor core Unit: uncore_arb This 48-bit fixed counter counts the UCLK cycles unc_cbo_cache_lookup.es Unit: uncore_cbox LLC lookup request that access cache and found line in E-state or S-state Demand load cycles page miss handler (PMH) is busy with this walk Remote cache HITM Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses umask=0x1,period=100003,event=0xb7,offcore_rsp=0x67fc00010 LLC misses for PCIe read current. Derived from unc_c_tor_inserts.miss_opcode.pcie_read. Unit: uncore_cbox LLC misses for PCIe non-snoop reads. Derived from unc_c_tor_inserts.miss_opcode.pcie_read. Unit: uncore_cbox unc_q_txl0p_power_cycles Number of data flits transmitted . Unit: uncore_qpi Write requests to memory controller. Derived from unc_m_cas_count.wr. Unit: uncore_imc Counts the number of times that the uncore transitioned a frequency greater than or equal to the frequency that is configured in the filter. (filter_band0=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Derived from unc_p_freq_band0_cycles. Unit: uncore_pcu freq_ge_3000mhz_cycles % unc_p_freq_ge_4000mhz_transitions Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache l2_store_lock_rqsts.hit_e dsb_fill.all_cancel Cycles with at least one slow LEA uop being allocated Mispredicted taken branch instructions retired (Precise event) This event counts executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in an Instructions retired. (Precise Event - PEBS) (Must be precise) Counts the number of L2 cache misses mem_uops_retired.utlb_miss_loads umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000082000 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000401000 Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010100 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080080 offcore_response.pf_l2_code_rd.l2_hit_far_tile_e_f offcore_response.pf_l2_code_rd.l2_hit_near_tile_m Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080020 Counts demand code reads and prefetch code reads that accounts for any response offcore_response.partial_reads.l2_hit_this_tile_m Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in E state umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000200 Counts any request that accounts for responses which hit its own tile's L2 with data in E state offcore_response.pf_l1_data_rd.l2_hit_this_tile_s umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000002 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800180040 Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state Counts any Prefetch requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800400100 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100403091 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080203091 Counts Demand cacheable data writes that accounts for data responses from DRAM Far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180600070 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181800001 offcore_response.partial_reads.ddr Counts the number of mispredicted branch instructions retired that were conditional jumps (Precise event) This event counts the number of times that the pipeline stalled due to FP operations needing assists This event counts the number of core cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted branch to retire Counts the number of core cycles when allocation pipeline is stalled and is waiting for a free MEC reservation station entry recycleq.sta_full umask=0xf9,period=200003,event=0xc5 ddr bandwidth write (CPU traffic only) (MB/sec). Unit: uncore_imc cache_lock_cycles.l1d umask=0x4,period=2000000,event=0x51 L1D snoop eviction of cache lines in M state umask=0x1,period=2000000,event=0x40 L1D hardware prefetch requests L1 writebacks to L2 in E state umask=0xf,period=100000,event=0x28 L2 data prefetches in the I state (misses) l2_transactions.fill l2_write.lock.m_state Memory instructions retired above 4 clocks (Precise Event) umask=0x1,period=100000,event=0xb7,offcore_rsp=0x711 Offcore data reads satisfied by a remote cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x144 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2FF offcore_response.any_request.local_cache Offcore RFO requests satisfied by the LLC and HITM in a sibling core offcore_response.any_rfo.remote_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF77 umask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF33 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4733 offcore_response.data_in.remote_cache_hitm umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F03 umask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF04 Offcore demand code reads satisfied by a remote cache Offcore demand RFO requests satisfied by the LLC Offcore prefetch data requests satisfied by a remote cache or remote DRAM offcore_response.pf_data.remote_cache_hitm offcore_response.pf_data_rd.llc_hit_other_core_hitm Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core offcore_response.prefetch.local_cache umask=0x4,period=20000,event=0xf7 umask=0x2,period=2000000,event=0xcc simd_int_64.pack Offcore code reads satisfied by any DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF844 Offcore writebacks to a remote DRAM offcore_response.pf_data.local_dram Offcore prefetch RFO requests satisfied by a remote DRAM bpu_clears.late rat_stalls.flags umask=0x7,period=200000,event=0x4 Indirect return branches executed Retired conditional branch instructions (Precise Event) umask=0x4,period=2000,event=0x89 umask=0x7,period=20000,event=0x89 umask=0x2,period=20000,event=0xc3 uops_executed.port234_core umask=0x2,period=200000,event=0x8 Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS mem_load_l3_hit_retired.xsnp_none offcore_response.other.l4_hit_local_l4.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080080004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200040004 offcore_response.demand_rfo.l4_hit_local_l4.snoop_none offcore_response.demand_rfo.l3_hit.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000100002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0080001 offcore_response.demand_data_rd.l3_hit_m.spl_hit Counts, on the per-thread basis, cycles when less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >= 3 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall. Precise Event (Precise event) offcore_requests_outstanding.l3_miss_demand_data_rd Number of times we entered an HLE region. Does not count nested transactions Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency (Must be precise) offcore_response.demand_code_rd.l3_hit_e.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C400001 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0044000001 offcore_response.demand_data_rd.l4_hit_local_l4.snoop_non_dram umask=0x1,period=2000003,event=0xd Number of instructions retired. General Counter - architectural event Spec update: SKL091, SKL044 Counts demand data stores that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000008008 Counts demand and DCU prefetch RFOs that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Counts the number of cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted jump to retire. After the misprediction is detected, the front end will start immediately but the allocate pipe stalls until the mispredicted umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0240 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0200 This event counts cycles during which the microcode sequencer assisted the front-end in delivering uops. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance. See the Intel® 64 and IA-32 Architectures Optimization Reference Manual for more information Counts all prefetch data reads that miss the LLC and the data returned from dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400040 offcore_response.pf_llc_rfo.llc_miss.dram umask=0x8,period=100000,event=0xb0 offcore_requests.any.rfo Outstanding offcore reads REQUEST = ANY_DATA read and RESPONSE = LOCAL_CACHE REQUEST = ANY RFO and RESPONSE = LOCAL_CACHE REQUEST = ANY RFO and RESPONSE = REMOTE_CACHE_HITM umask=0x1,period=100000,event=0xb7,offcore_rsp=0xff33 REQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HITM REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HIT REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5050 REQUEST = PF_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT offcore_response.pf_ifetch.all_local_dram_and_remote_cache_hit REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT REQUEST = ANY_REQUEST and RESPONSE = ANY_LLC_MISS offcore_response.any_request.other_local_dram REQUEST = ANY_REQUEST and RESPONSE = OTHER_LOCAL_DRAM REQUEST = DATA_IN and RESPONSE = ANY_LLC_MISS REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_DRAM AND REMOTE_FWD REQUEST = OTHER and RESPONSE = ANY_LLC_MISS offcore_response.prefetch.any_dram_and_remote_fwd dtlb_misses.walk_cycles umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5840 offcore_response.pf_l2_data_rd.l3_hit.snoop_hit_with_fwd fp_arith_inst_retired.512b_packed_double offcore_response.pf_l3_rfo.l3_miss.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x103FC00400 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0604000400 Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory) unc_m_cas_count.all event=0x81 uncore_upi ll fc_mask=0x07,ch_mask=0x02,umask=0x01,event=0x83 unc_cha_misc.rfo_hit_s Read request for 4 bytes made by the CPU to IIO Part2. Unit: uncore_iio Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part2 by a unit on the main die (generally a core). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus Write request of up to a 64 byte transaction is made by IIO Part0 to Memory. Unit: uncore_iio unc_m2m_directory_lookup.state_s Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from A (SnoopAll) to I (Invalid) unc_m2m_prefcam_inserts Clocks of the Intel Ultra Path Interconnect (UPI). Unit: uncore_upi ll Protocol header and credit FLITs transmitted across any slot. Unit: uncore_upi ll period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040491 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100004 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0122 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100400 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.SNOOP_NONE This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD offcore_response.other.pmm_hit_local_pmm.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100080 offcore_response.all_reads.l3_hit_s.any_snoop offcore_response.pf_l2_data_rd.l3_hit_f.hit_other_core_no_fwd offcore_response.demand_rfo.l3_hit_s.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200490 offcore_response.pf_l2_rfo.l3_hit_e.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020004 offcore_response.pf_l1d_and_sw.l3_hit.snoop_none cmask=6,period=2000003,umask=0x1,event=0x60 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED offcore_response.pf_l3_rfo.l3_hit_m.snoop_none This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE mem_load_retired.local_pmm period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0002 offcore_response.demand_rfo.l3_hit_e.hit_other_core_fwd offcore_response.other.l3_hit_s.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0020 offcore_response.pf_l3_rfo.l3_hit_s.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200080 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100490 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100010 This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00800407F7 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00800807F7 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0004 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080491 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100490 MEM_PMM_Read_Latency period=2000003,umask=0x8,event=0xc7 period=2000003,umask=0x40,event=0xc7 period=100007,umask=0x1,event=0xc6,frontend=0x14 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS & ANY_SNOOP ocr.pf_l2_rfo.l3_miss_local_dram.no_snoop_needed ocr.all_pf_rfo.l3_miss.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000491 ocr.all_pf_rfo.l3_miss_local_dram.hit_other_core_fwd Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS_REMOTE_DRAM & SNOOP_MISS_OR_NO_FWD Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04040007F7 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110008000 ALL_READS & L3_MISS_LOCAL_DRAM & ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000491 ALL_PF_DATA_RD & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_FWD ocr.pf_l3_rfo.l3_miss_local_dram.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE ocr.all_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000490 ocr.demand_data_rd.l3_miss_remote_hop1_dram.any_snoop offcore_response.all_data_rd.l3_miss_local_dram.hitm_other_core Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_NO_FWD offcore_response.all_reads.l3_miss_remote_hop1_dram.no_snoop_needed offcore_response.pf_l2_data_rd.l3_miss_local_dram.hitm_other_core Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS_LOCAL_DRAM & ANY_SNOOP Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS_LOCAL_DRAM & SNOOP_MISS_OR_NO_FWD offcore_response.all_pf_data_rd.l3_miss_local_dram.no_snoop_needed offcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed ALL_READS & L3_MISS & NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000122 ALL_RFO & L3_MISS & NO_SNOOP_NEEDED ocr.pf_l3_rfo.l3_miss.any_snoop Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE offcore_response.all_reads.l3_miss.snoop_none offcore_response.all_rfo.l3_miss.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000080 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000010 ocr.pf_l1d_and_sw.l3_miss_remote_dram.snoop_miss_or_no_fwd offcore_response.pf_l3_data_rd.l3_miss_local_dram.hit_other_core_fwd ocr.pf_l3_rfo.l3_miss.hit_other_core_no_fwd Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD offcore_response.other.l3_miss_local_dram.hitm_other_core This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS & HIT_OTHER_CORE_FWD ALL_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_NO_FWD Counts any other requests OTHER & L3_HIT_M & HITM_OTHER_CORE ocr.pf_l2_rfo.l3_hit_e.hitm_other_core Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT & SNOOP_NONE Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWD ocr.demand_data_rd.l3_hit.hit_other_core_no_fwd ocr.pf_l2_data_rd.supplier_none.snoop_miss ALL_DATA_RD & L3_HIT_S & ANY_SNOOP Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT & HITM_OTHER_CORE ocr.demand_code_rd.l3_hit_s.hit_other_core_no_fwd ocr.pf_l3_rfo.l3_hit_m.snoop_none ALL_PF_DATA_RD & L3_HIT_M & HIT_OTHER_CORE_FWD ALL_PF_RFO & L3_HIT & HITM_OTHER_CORE ocr.pf_l2_data_rd.any_response ocr.pf_l1d_and_sw.l3_hit_s.hit_other_core_no_fwd ocr.pf_l1d_and_sw.any_response ocr.pf_l1d_and_sw.l3_hit_m.hitm_other_core ocr.pf_l2_data_rd.l3_hit_e.hit_other_core_fwd ocr.pf_l3_rfo.pmm_hit_local_pmm.snoop_none ALL_READS & L3_HIT_E & SNOOP_NONE ALL_DATA_RD & L3_HIT_M & SNOOP_MISS ocr.demand_rfo.pmm_hit_local_pmm.any_snoop Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_F & NO_SNOOP_NEEDED Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT & HIT_OTHER_CORE_NO_FWD ALL_PF_DATA_RD & L3_HIT_F & HIT_OTHER_CORE_FWD ocr.pf_l2_data_rd.l3_hit_e.hitm_other_core Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_E & NO_SNOOP_NEEDED Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT & SNOOP_NONE ALL_DATA_RD & L3_HIT_E & SNOOP_MISS ocr.all_reads.l3_hit_f.hit_other_core_no_fwd ocr.pf_l3_rfo.l3_hit_s.any_snoop ALL_PF_RFO & L3_HIT_S & SNOOP_NONE ocr.pf_l3_data_rd.l3_hit.hit_other_core_fwd Not taken branch instructions retired Spec update: SKL091 period=2000003,umask=0x1,event=0xc0 unc_m_pmm_bandwidth.read unc_m_pmm_cmd1.wr unc_m_pmm_wpq_occupancy.all All Clean line misses to Near Memory(DRAM cache) in Memory Mode. Unit: uncore_imc umask=0x01,event=0x13 Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part1 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus fc_mask=0x07,ch_mask=0x01,umask=0x08,event=0xc1 umask=0x04,event=0x2c umask=0x03,event=0x15 period=100003,umask=0x8,event=0x49 Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache Retired load instructions whose data sources were hits in L3 without snoops required Supports address when precise (Precise event) sq_misc.sq_full Uops not delivered by IDQ when backend of the machine is not stalled Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled Counts the number of times a TSX Abort was triggered due to release/commit but data and address mismatch Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter Precise instruction retired event with a reduced effect of PEBS shadow in IP distribution (Must be precise) umask=0x9,period=2000003,cmask=1,event=0x14 Number of uops executed on port 0 All indirect branch instructions retired (excluding RETs. TSX aborts are considered indirect branch) (Precise event) Page walks completed due to a demand data store to a 4K page Counts code misses in all ITLB (Instruction TLB) levels that caused a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault Precharge due to read on page miss, write on page miss or PGT. Unit: uncore_imc unc_iio_data_req_of_cpu.mem_read.part6 Clockticks of the IO coherency tracker (IRP). Unit: uncore_irp uncore_irp Indirect Branch Prediction for potential multi-target branch (speculative) umask=0x2,event=0x87 ic_fetch_stall.ic_stall_back_pressure bp_tlb_rel Miscellaneous events covered in more detail by l2_request_g2 (PMCx061) l2_request_g2.ic_rd_sized All L3 Miss Request Types. Ignores SliceMask and ThreadMask. Unit: uncore_l3pmc df_ccm_reqa.node1.wrsizedfullnc df_ccm_reqa.node3.wrsized umask=0x4B,event=0x8b df_ccm_reqa.node0.rdsizednc umask=0x48,event=0x8b umask=0x66,event=0x8b df_ccm_reqa.node3.rdvlkc umask=0x63,event=0x8b df_ccm_reqa.node5.rdvlkl Data Fabric CCM Performance Monitor Event DF CCM Request Ordered chgtox umask=0x6D,event=0x8c umask=0xEC,event=0x8c umask=0xEB,event=0x8c df_ccm_reqb.node0.anyiorequest. umask=0xE6,event=0x8c df_ccm_reqb.node4.wrsizedfullncposted umask=0xA1,event=0x8c df_ioms_reqa.node4.masterabort df_ioms_reqa.node0.ios_resp df_ioms_reqa.node2.flush df_ioms_reqa.node2.anyatomic umask=0x45,event=0x108 umask=0xE4,event=0x108 umask=0xE2,event=0x108 umask=0xC1,event=0x108 umask=0x0F,event=0x109 umask=0x6F,event=0x109 umask=0xED,event=0x109 df_ioms_reqb.node0.ioanynon-postedwrsized>32band<64b umask=0x22,event=0x109 umask=0xE2,event=0x109 Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered iolargeread Add/subtract Ops This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Double precision divide/square root FLOPS umask=0x20,event=0x3 This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Double precision multiply FLOPS l3_request_g1.t1.s1.wrsizednc l3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x02,event=0x1 l3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x20,event=0x1 l3_request_g1.t3.s3.rdsizednc l3_request_g1.t6.s1.rdsized l3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x40,event=0x1 l3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x01,event=0x3 l3fillvicreq.t1.s0.chgtox l3fillvicreq.t2.s2.chgtox l3fillvicreq.t3.s3.chgtox l3fillvicreq.t5.s0.rdblkc_s_vic l3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x08,event=0x3 l3fillvicreq.t1.s3.rdblkc_s l3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x10,event=0x3 l3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x10,event=0x3 l3fillvicreq.t5.s2.rdblkx_vic l3fillvicreq.t1.s3.rdblkx_vic l3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x20,event=0x3 l3fillvicreq.t1.s3.rdblkx l3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x20,event=0x3 l3fillvicreq.t5.s3.rdblkx l3fillvicreq.t2.s0.rdblkl_vic l3fillvicreq.t0.s1.rdblkl_vic l3victimstate.t4.s3.nol3victimline l3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x01,event=0x9 l3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x02,event=0x9 l3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x04,event=0x9 l3victimstate.t1.s0.o l3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x08,event=0x9 l3victimstate.t5.s0.e_fe l3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x10,event=0x9 l3victimstate.t7.s1.e_fe l3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x10,event=0x9 l3victimstate.t2.s1.d l3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x80,event=0x9 l3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x80,event=0x9 l3victimstate.t6.s2.od ls_dispatch.ld_st_dispatch Total Page Table Walks on I-side umask=0x2,event=0x4b umask=0x10,event=0xaf umask=0xff,event=0x70 fp_ret_sse_avx_ops.mac_flops umask=0x8,event=0xe ls_locks.spec_lock_hi_spec umask=0x1,event=0x43 umask=0x80,event=0xae umask=0x20,event=0xae , IC_L1_ITLB_MISS_AND_L2_ITLB_MISS FR_DISPATCH_STALL_WHEN_WAITING_FOR_ALL_TO_BE_QUIET L1D_CACHE_WB L1D_CACHE_REFILL_LD ASE_SPEC BR_IMMED_SPEC L3D_CACHE_ALLOCATE CYCLE TAGCACHE_READ_HIT RETURN ISPRAM_STALL_CYCLES FSB_LT_QUARTER DUAL_ISSUE_CYCLES VFPU_INSTR_COMPLETED LSU_LMQ_FULL_STALL FP_ONE_HALF_FPSCR_RENAMES_BUSY COMPLETION_QUEUE_ENTRIES_OVER_THRESHOLD THIRD_SPECULATION_BUFFER_ACTIVE L3_CACHE_CASTOUTS CYCLES_IN_SUPER ONE_PLUS_INSTR_COMPLETED CYCLES_IDLE TOTAL_ALLOCATED_TO_DLFB FPU_RESULT_STALL_CYCLES UNKNOWN LLC_MISSES {"type": "procfork" v9 DSB; Frontend_Bandwidth ( cpu_clk_unhalted.thread_any / 2 ) if #smt_on else cpu_clk_unhalted.thread (cstate_pkg@c7\-residency@ / msr@tsc@) * 100 l2_rqsts.all_demand_data_rd This event counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.
Note: A prefetch promoted to Demand is counted from the promotion point Spec update: BDM76 offcore_requests_outstanding.demand_code_rd Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle Spec update: BDM76 umask=0x2,period=2000003,event=0x63 umask=0x21,period=100007,event=0xd0 This is a precise version (that is, uses PEBS) of the event that counts load uops retired to the architected path with a filter on bits 0 and 1 applied.
Note: This event ?ounts AVX-256bit load/store double-pump memory uops as a single uop at retirement. This event also counts SW prefetches Supports address when precise (Precise event) This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required Supports address when precise. Spec update: BDM100 (Precise event) umask=0x8,period=100003,event=0xd1 Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS) Supports address when precise. Spec update: BDM100 (Precise event) umask=0x1,period=100007,event=0xd3 floating point This event counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable Spec update: BDM30 This event counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ idq.all_mite_cycles_4_uops umask=0x1,cmask=1,period=2000003,event=0x9c dsb2mite_switches.penalty_cycles tx_mem.abort_hle_elision_buffer_mismatch tx_exec.misc4 umask=0x4,period=2000003,event=0xc8 Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts) Loads with latency value being above 128 Spec update: BDM100, BDM35 (Must be precise) ld_blocks.no_sr Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke) Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread move_elimination.simd_eliminated Taken speculative and retired direct near calls Speculative and retired mispredicted macro conditional branches Micro-op dispatches cancelled due to insufficient SIMD physical register file read ports Cycles per core when uops are exectuted in port 1 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7 resource_stalls.sb This event counts stall cycles caused by the store buffer (SB) overflow (excluding draining from synch). This counts cycles that the pipeline backend blocked uop delivery from the front end Counts number of cycles the CPU has at least one pending demand load request (that is cycles with non-completed load waiting for its data from memory subsystem) cycle_activity.cycles_mem_any Cycles where at least 2 uops were executed per-thread uops_executed.core_cycles_ge_3 uops_retired.stall_cycles Number of machine clears (nukes) of any type umask=0x20,period=100003,event=0xc3 This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired Spec update: BDW98 (Must be precise) Taken branch instructions retired. (Precise Event - PEBS) (Precise event) This event counts all mispredicted macro branch instructions retired unc_c_clockticks umask=0x1,event=0x35,filter_opc=0x180,filter_tid=0x3e L2 demand and L2 prefetch code references to LLC. Derived from unc_c_tor_inserts.opcode. Unit: uncore_cbox umask=0x8,event=0x1 Shared line forwarded from remote cache. Unit: uncore_ha freq_trans_cycles % Load miss in all TLB levels causes a page walk that completes. (1G) Spec update: BDM69 dtlb_store_misses.walk_completed Store misses that miss the DTLB and hit the STLB (2M) Number of DTLB page walker hits in Memory Spec update: BDM69, BDM98 umask=0x21,period=2000003,event=0xbc This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired Instructions per Store (lower number means higher occurance rate) umask=0xc4,period=200003,event=0x24 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0010 offcore_response.pf_l2_rfo.supplier_none.any_snoop offcore_response.pf_l2_code_rd.supplier_none.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010080 offcore_response.pf_l3_data_rd.supplier_none.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020100 offcore_response.pf_l3_code_rd.supplier_none.any_snoop offcore_response.all_pf_data_rd.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020090 offcore_response.all_pf_rfo.supplier_none.snoop_none offcore_response.all_pf_rfo.supplier_none.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020120 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0120 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020240 offcore_response.all_pf_code_rd.l3_hit.snoop_none Counts all demand & prefetch RFOs umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020122 input - Invalid Operation, Denormal Operand, SNaN Operand (Precise Event) umask=0x24,period=2000003,cmask=4,event=0x79 This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop.
MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.
Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 0–2 cycles offcore_response.demand_rfo.l3_miss_local_dram.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000008 offcore_response.pf_l2_data_rd.l3_miss.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000020 offcore_response.pf_l3_rfo.l3_miss.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000200 offcore_response.other.l3_miss_local_dram.snoop_hit_no_fwd offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000240 offcore_response.all_rfo.l3_miss.snoop_none A cross-core snoop resulted from L3 Eviction which misses in some processor core Unit: uncore_cbox L3 Lookup write request that access cache and found line in M-state unc_cbo_cache_lookup.any_i Retired load uops which data sources were hits in L3 without snoops required Supports address when precise. Spec update: BDM100 (Precise event) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0244 Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded offcore_response.all_data_rd.llc_hit.hit_other_core_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x087FC007F7 offcore_response.all_reads.llc_miss.local_dram umask=0x4f,period=200000,event=0x2b umask=0x41,period=200000,event=0x2d l2_rqsts.self.prefetch.s_state l2_reject_busq.self.prefetch.s_state umask=0x1,period=10000,event=0x11 umask=0x0,period=2000000,event=0xb1 SIMD Instructions retired thermal_trip umask=0xc0,period=200000,event=0x3b umask=0x40,period=200000,event=0x63 umask=0x40,period=200000,event=0x65 bus_trans_inval.all_agents umask=0x40,period=200000,event=0x6a Deferred bus transactions ext_snoop.this_agent.hitm HIT signal asserted umask=0x20,period=200000,event=0x7b HITM signal asserted cpu_clk_unhalted.bus umask=0x0,period=2000000,event=0xc4 reissue.overlap_store.ar umask=0x5,period=200000,event=0x8 ITLB flushes umask=0x2,period=200003,event=0x86 Store uops retired (Precise event capable) Supports address when precise (Must be precise) mem_load_uops_retired.dram_hit umask=0x1,period=100007,event=0xb7,offcore_rsp=0x10000032b7 offcore_response.any_rfo.l2_miss.hit_other_core_no_fwd umask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600001000 offcore_response.corewb.l2_miss.any offcore_response.demand_code_rd.l2_miss.snoop_miss_or_no_snoop_needed Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that are outstanding, per cycle, from the time of the L2 miss to when any response is received umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000040001 Counts the number of times the Microcode Sequencer (MS) starts a flow of uops from the MSROM. It does not count every time a uop is read from the MSROM. The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine. Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort that initiates a flow of uops. The event will count MS startups for uops that are speculative, and subsequently cleared by branch mispredict or a machine clear umask=0x1,period=200003,event=0xe9 Counts when a memory store of a uop spans a page boundary (a split) is retired (Must be precise) Machine clears due to memory ordering issue umask=0x1,period=200003,event=0x86 Counts the number of issue slots per core cycle that were not consumed by the backend due to either a full resource in the backend (RESOURCE_FULL) or due to the processor recovering from some event (RECOVERY) uops_not_delivered.any Instructions retired (Precise event capable) (Must be precise) uops_retired.ms umask=0x11,period=200003,event=0xd0 dl1.replacement Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache have any transaction responses from the uncore subsystem umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000000004 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000008 offcore_response.bus_locks.l2_hit umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000000400 Counts requests to the uncore subsystem hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) hit the L2 cache Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache Spec update: HSD29, HSD25, HSM26, HSM30. Supports address when precise (Precise event) offcore_response.demand_code_rd.l3_hit.hit_other_core_no_fwd This event counts the number of memory ordering machine clears detected. Memory ordering machine clears can result from memory address aliasing or snoops from another hardware thread or core to data inflight in the pipeline. Machine clears can have a significant performance impact if they are happening frequently umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100400244 offcore_response.pf_l2_rfo.l3_miss.any_response offcore_response.demand_code_rd.l3_miss.any_response uops_issued.core_stall_cycles Cycles with pending memory loads. Set Cmask=2 to count cycle This event counts cycles during which no instructions were executed in the execution stage of the pipeline and there were memory instructions pending (waiting for data) Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution Spec update: HSD140 (Must be precise) Completed page walks due to demand load misses that caused 4K page walks in any TLB levels dtlb_store_misses.pde_cache_miss umask=0x80,period=100003,event=0x49 Counts the number of Extended Page Table walks from the DTLB that hit in memory Number of X87 FP assists due to input values umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0600400122 umask=0xf,period=200003,event=0x27 Retired load uops which data sources following L1 data-cache miss (Precise event) Counts number of X87 uops executed Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations Loads blocked by overlapping with store buffer that cannot be forwarded Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate) Cycles which a Uop is dispatched on port 1 Cycles per core when uops are dispatched to port 1 Uops dispatched to port 2, loads and stores per core (speculative and retired) Retired uops (Precise event) umask=0x02,event=0x34 Unit: uncore_cbox LLC lookup request that access cache and found line in S-state Completed page walks in ITLB due to STLB load misses for large pages offcore_response.demand_data_rd.llc_hit.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x87f8203f7 Counts all prefetch (that bring data to LLC only) code reads that miss in the LLC Partial PCIe reads. Derived from unc_c_tor_inserts.opcode.pcie_partial. Unit: uncore_cbox umask=0x8A,event=0x36 event=0x60 unc_p_freq_ge_1200mhz_cycles event=0xd,edge=1,filter_band2=30 event=0xe,edge=1,filter_band3=40 This event counts cycles during which the microcode sequencer assisted the front-end in delivering uops. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance. See the Intel? 64 and IA-32 Architectures Optimization Reference Manual for more information dsb_fill.other_cancel cycle_activity.cycles_no_dispatch resource_stalls.lb_sb partial_rat_stalls.flags_merge_uop_cycles (unc_c_tor_occupancy.miss_all / unc_c_clockticks) * 100. Load misses at all DTLB levels that cause completed page walks Counts any Prefetch requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0 Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state umask=0x1,period=100007,event=0xb7,offcore_rsp=0x10000832f7 offcore_response.any_code_rd.l2_hit_near_tile_e_f Counts Demand cacheable data write requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode offcore_response.any_data_rd.l2_hit_near_tile_m Counts any request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0 Counts Software Prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0 Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state offcore_response.pf_software.l2_hit_near_tile_m Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state offcore_response.partial_reads.outstanding Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode offcore_response.demand_rfo.l2_hit_near_tile_e_f offcore_response.demand_data_rd.l2_hit_near_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080001 Counts UC code reads (valid only for Outstanding response type) that accounts for responses which hit its own tile's L2 with data in M state Counts Demand cacheable data write requests that accounts for responses which hit its own tile's L2 with data in M state offcore_response.pf_l2_rfo.l2_hit_this_tile_e umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004008000 Counts any Read request that accounts for responses which hit its own tile's L2 with data in S state Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses which hit its own tile's L2 with data in F state Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses which hit its own tile's L2 with data in F state offcore_response.demand_rfo.l2_hit_near_tile Counts L2 code HW prefetches that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state offcore_response.any_pf_l2.l2_hit_near_tile Counts L1 data HW prefetches that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode offcore_response.any_data_rd.mcdram_far Counts any request that accounts for data responses from DRAM Local Counts L2 code HW prefetches that accounts for data responses from MCDRAM Local umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000020 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000004 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180600100 Counts demand cacheable data and L1 prefetch data reads that accounts for responses from DDR (local and far) offcore_response.demand_code_rd.ddr This event counts the number of micro-ops retired that were supplied from MSROM Counts the number of core cycles when no micro-ops are allocated, the IQ is empty, and no other condition is blocking allocation umask=0x02,event=0x3 unc_e_rpq_inserts Cycles L1D locked l1d_all_ref.cacheable L1 data cache load locks in S state L2 data prefetches in the S state umask=0x3,period=200000,event=0x24 l2_rqsts.prefetches umask=0x40,period=200000,event=0xf0 L2 demand store RFOs in S state Load instructions retired remote cache HIT data source (Precise Event) mem_inst_retired.latency_above_threshold_128 umask=0x10,period=500,event=0xb,ldlat=0x100 mem_inst_retired.latency_above_threshold_64 offcore_response.any_data.remote_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF22 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1008 Offcore demand data requests satisfied by the LLC Offcore demand data reads satisfied by the LLC or local DRAM offcore_response.demand_data_rd.remote_cache_hit Offcore demand RFO requests satisfied by a remote cache or remote DRAM Offcore other requests satisfied by the LLC and HITM in a sibling core offcore_response.pf_ifetch.llc_hit_other_core_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x440 Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core umask=0x1,period=100000,event=0xb7,offcore_rsp=0x740 offcore_response.pf_rfo.llc_hit_no_other_core Offcore prefetch RFO requests that HIT in a remote cache Offcore prefetch requests satisfied by the LLC and HITM in a sibling core offcore_response.prefetch.remote_cache_hit umask=0x4,period=2000000,event=0x10 offcore_response.any_ifetch.any_dram offcore_response.any_rfo.any_dram Offcore request = all data, response = any DRAM offcore_response.demand_data.local_dram Offcore demand data requests satisfied by a remote DRAM offcore_response.demand_ifetch.any_dram Offcore prefetch code reads satisfied by any DRAM Offcore prefetch RFO requests that missed the LLC umask=0x1,period=2000000,event=0xd2 Unconditional call branches executed Indirect call branches executed umask=0x40,period=200000,event=0x88 Mispredicted indirect call branches executed br_misp_exec.return_near Cycles instructions are written to the instruction queue resource_stalls.store Store buffer stall cycles Uop unfusions due to FP exceptions uops_executed.port0 uops_executed.port015 DTLB first level misses but second level hit Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache mem_load_retired.l3_miss Retired load instructions which data sources were load missed L1 but hit FB due to preceding miss to the same cache line with data not ready Supports address when precise (Precise event) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0408000 offcore_response.demand_code_rd.l4_hit_local_l4.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02001C0004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01001C0001 offcore_response.demand_data_rd.l3_hit_m.snoop_hit_no_fwd Counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ Counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding “4 – x” when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread. b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions). c. Instruction Decode Queue (IDQ) delivers four uops Retired instructions that are fetched after an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall. Precise Event (Precise event) umask=0x1,period=100007,event=0xc6,frontend=0x404006 offcore_requests_outstanding.l3_miss_demand_data_rd_ge_6 umask=0x10,period=2000003,cmask=6,event=0x60 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C408000 offcore_response.other.l4_hit_local_l4.snoop_non_dram offcore_response.demand_rfo.l3_miss.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFC400002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000002 umask=0x1,period=2000003,event=0x32 Number of PREFETCHW instructions executed Uops inserted at issue-stage in order to preserve upper bits of vector registers partial_rat_stalls.scoreboard Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty Number of cycles using always true condition applied to PEBS instructions retired event Spec update: SKL091, SKL044 (Must be precise) inv=1,umask=0x2,period=2000003,cmask=1,event=0xc2 Counts all (macro) branch instructions retired Spec update: SKL091 1000 * mem_load_retired.l1_miss / inst_retired.any Loads that miss the DTLB and hit the STLB umask=0x10,period=100003,cmask=1,event=0x49 Counts the number of (demand and L1 prefetchers) core requests rejected by the L2Q due to a full or nearly full w condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to insure fairness between cores, or to delay a core?s dirty eviction when the address conflicts incoming external snoops. (Note that L2 prefetcher requests that are dropped are not counted by this event.) This event counts the number of retired stores that are delayed because there is not a store address buffer available Loads missed L2 (Precise event) Counts any data read (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache Counts demand and DCU prefetch RFOs that miss L2 Instruction fetches from Icache Counts the number of cycles when no uops are allocated and the ROB is full (less than 2 entries available) This event counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time Counts demand & prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops sent to sibling cores return clean response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0040 Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_M and SNOOP = HITM offcore_response.pf_l_ifetch.any_response offcore_requests.any.read umask=0x1,period=100000,event=0xb7,offcore_rsp=0xff44 REQUEST = CORE_WB and RESPONSE = REMOTE_CACHE_HITM REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_CORE REQUEST = PREFETCH and RESPONSE = LOCAL_CACHE offcore_response.pf_data.other_local_dram mem_uncore_retired.remote_hitm offcore_response.demand_data_rd.l3_hit.no_snoop_needed offcore_response.demand_rfo.l3_hit.no_snoop_needed Counts L1 data cache hardware prefetch requests and software prefetch requests umask=0x1,period=100003,event=0xb7,offcore_rsp=0x083FC00002 offcore_response.pf_l2_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd offcore_response.pf_l1d_and_sw.l3_miss.remote_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0604000491 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063B800122 core_snoop_response.rsp_ifwdm unc_m_rpq_inserts unc_cha_requests.writes_remote write requests from remote home agent. Unit: uncore_cha umask=0x01,event=0x59 umask=0x40,event=0x5c RspI Snoop Responses Received. Unit: uncore_cha umask=0x20,event=0x5c umask=0x10,event=0x5c Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus fc_mask=0x07,ch_mask=0x04,umask=0x01,event=0x84 Counts traffic in which the M2M (Mesh to Memory) to iMC (Memory Controller) bypass was not taken unc_m2m_directory_lookup.state_a umask=0x8,event=0x2d Multi-socket cacheline Directory update from I to S. Unit: uncore_m2m Counts when the a new entry is Received(RxC) and then added to the AD (Address Ring) Ingress Queue from the CMS (Common Mesh Stop). This is generally used for reads, and Data Response packets that go direct to Intel UPI. Unit: uncore_upi ll Counts Data Response (DRS) packets that attempted to go direct to Intel Ultra Path Interconnect (UPI) bypassing the CHA Null FLITs transmitted from any slot. Unit: uncore_upi ll offcore_response.demand_rfo.pmm_hit_local_pmm.snoop_not_needed Counts retired load instructions with at least one uop that hit in the L3 cache Supports address when precise (Precise event) This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE offcore_response.all_pf_data_rd.l3_hit_f.no_snoop_needed This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD period=100007,umask=0x8,event=0xd3 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x8,event=0xd1 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020122 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400122 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020491 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040001 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020491 This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080120 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100100 offcore_response.all_reads.pmm_hit_local_pmm.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00804007F7 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080002 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.ANY_RESPONSE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400010 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040490 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0004 offcore_response.all_pf_rfo.l3_hit_s.hit_other_core_fwd This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE offcore_response.demand_code_rd.l3_hit_f.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200120 offcore_response.all_pf_data_rd.l3_hit_m.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080100 offcore_response.pf_l3_data_rd.l3_hit_f.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01002007F7 offcore_response.pf_l1d_and_sw.l3_hit_e.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040004 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020120 This event is deprecated. Refer to new event OCR.OTHER.ANY_RESPONSE offcore_response.pf_l2_rfo.l3_hit_s.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0122 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100100 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080080 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020122 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200004 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020120 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100400 offcore_response.other.l3_hit.snoop_hit_with_fwd offcore_response.all_reads.l3_hit_f.hit_other_core_no_fwd period=2000003,umask=0x10,event=0xc7 period=100007,umask=0x1,event=0xc6,frontend=0x400406 period=200003,umask=0x2,event=0x83 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall (Precise event) cmask=4,period=2000003,umask=0x24,event=0x79 offcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.snoop_miss This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00490 offcore_response.all_reads.l3_miss_local_dram.snoop_miss_or_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000010 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_CORE Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS_LOCAL_DRAM & NO_SNOOP_NEEDED offcore_response.pf_l2_rfo.l3_miss_local_dram.hit_other_core_no_fwd offcore_response.all_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd period=2000003,umask=0x8,event=0x5d period=2000003,umask=0x4,event=0x5d offcore_response.all_reads.l3_miss_remote_dram.snoop_miss_or_no_fwd offcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000490 Counts any other requests OTHER & L3_MISS_REMOTE_HOP1_DRAM & NO_SNOOP_NEEDED ALL_RFO & L3_MISS_LOCAL_DRAM & HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00002 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED ALL_PF_DATA_RD & L3_MISS & ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000122 ALL_PF_DATA_RD & L3_MISS & NO_SNOOP_NEEDED ALL_RFO & L3_MISS_REMOTE_HOP1_DRAM & ANY_SNOOP Counts demand data reads DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & HITM_OTHER_CORE Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS & NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000491 ocr.all_pf_data_rd.l3_miss.hit_other_core_fwd offcore_response.other.l3_miss_local_dram.snoop_miss_or_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000001 ocr.pf_l1d_and_sw.l3_miss_local_dram.snoop_none This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP offcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.hitm_other_core This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP offcore_response.demand_rfo.l3_miss_remote_hop1_dram.snoop_miss This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000002 Counts all demand code reads DEMAND_CODE_RD & L3_MISS & SNOOP_NONE ocr.all_pf_rfo.l3_miss.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02100007F7 ALL_PF_DATA_RD & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_NO_FWD ocr.demand_data_rd.l3_miss.remote_hit_forward This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00001 ocr.demand_code_rd.l3_miss_local_dram.no_snoop_needed Counts all demand data writes (RFOs) DEMAND_RFO & L3_MISS & SNOOP_NONE period=2000003,umask=0x40,event=0xc8 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE ocr.all_rfo.l3_miss.any_snoop ALL_RFO & L3_MISS & ANY_SNOOP ALL_PF_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISS_OR_NO_FWD ocr.other.l3_miss_local_dram.any_snoop ocr.other.l3_miss.remote_hitm This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000001 ocr.demand_rfo.l3_miss.remote_hit_forward Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_FWD ocr.all_reads.l3_miss_local_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD offcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hitm_other_core offcore_response.other.l3_miss_remote_hop1_dram.hit_other_core_fwd ocr.all_pf_rfo.l3_hit.any_snoop ocr.all_pf_data_rd.l3_hit.hitm_other_core ocr.all_reads.pmm_hit_local_pmm.any_snoop ocr.all_pf_rfo.l3_hit_e.hit_other_core_no_fwd ocr.pf_l1d_and_sw.l3_hit_e.snoop_miss ocr.pf_l2_data_rd.l3_hit_f.snoop_miss ocr.pf_l3_rfo.supplier_none.any_snoop ocr.pf_l1d_and_sw.pmm_hit_local_pmm.any_snoop Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDED ocr.all_pf_data_rd.l3_hit_m.any_snoop Counts all demand code reads DEMAND_CODE_RD & L3_HIT_E & HITM_OTHER_CORE Counts all demand code reads DEMAND_CODE_RD & L3_HIT & SNOOP_MISS ocr.pf_l3_data_rd.l3_hit_s.hitm_other_core ocr.all_data_rd.any_response ocr.all_pf_data_rd.l3_hit.snoop_hit_with_fwd ALL_DATA_RD & L3_HIT_F & SNOOP_NONE Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_S & NO_SNOOP_NEEDED ocr.all_reads.l3_hit.hit_other_core_no_fwd ALL_RFO & SUPPLIER_NONE & HITM_OTHER_CORE Counts any other requests OTHER & L3_HIT_M & ANY_SNOOP ocr.all_reads.l3_hit.snoop_hit_with_fwd Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT & SNOOP_MISS ALL_READS & SUPPLIER_NONE & SNOOP_MISS ocr.demand_rfo.l3_hit_e.hit_other_core_fwd ALL_PF_DATA_RD & L3_HIT_F & HIT_OTHER_CORE_NO_FWD Counts all prefetch (that bring data to LLC only) RFOs hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores ALL_PF_RFO & L3_HIT_F & HIT_OTHER_CORE_FWD ocr.pf_l1d_and_sw.l3_hit_s.snoop_miss ALL_PF_DATA_RD & L3_HIT & HIT_OTHER_CORE_NO_FWD ocr.pf_l3_rfo.l3_hit_f.snoop_miss ocr.all_pf_rfo.l3_hit_f.hitm_other_core ocr.pf_l1d_and_sw.l3_hit_e.any_snoop Counts all prefetch (that bring data to LLC only) data reads hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores ocr.demand_data_rd.pmm_hit_local_pmm.snoop_none ocr.pf_l3_data_rd.l3_hit_f.snoop_miss ocr.demand_rfo.any_response ocr.other.l3_hit_m.hit_other_core_no_fwd ocr.pf_l3_rfo.l3_hit_s.snoop_miss period=2000003,umask=0x1,event=0x32 ocr.demand_code_rd.l3_hit_f.no_snoop_needed ocr.pf_l1d_and_sw.l3_hit.hit_other_core_fwd cmask=10,inv=1,period=2000003,umask=0x2,event=0xc2 period=400009,umask=0x20,event=0xc5 period=2000003,umask=0x80,event=0xd period=2000003,umask=0x4,event=0xa1 period=2000003,umask=0x10,event=0xa1 cmask=4,period=2000003,umask=0x1,event=0xb1 period=100003,umask=0x2,event=0x3 cmask=1,edge=1,period=100007,event=0x3c umask=0x04,event=0x3d Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part2 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus fc_mask=0x07,ch_mask=0x08,umask=0x08,event=0xc0 unc_iio_data_req_by_cpu.peer_write.part1 fc_mask=0x07,ch_mask=0x02,umask=0x02,event=0xc0 fc_mask=0x07,ch_mask=0x01,umask=0x02,event=0x83 unc_iio_data_req_of_cpu.peer_write.part2 Peer to peer write request of up to a 64 byte transaction is made by IIO Part3 to an IIO target. Unit: uncore_iio M2M Writes Issued to iMC; All, regardless of priority period=100003,umask=0xe,event=0x49 umask=0x4,period=100003,event=0xf4 Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity Counts the number of times a TSX Abort was triggered due to a non-release/commit store to lock Counts the number of times we entered an HLE region. Does not count nested transactions Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events) Number of uops executed on port 4 and 9 uops_dispatched.port_6 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 7 and 8 Counts cycles when at least 2 micro-ops are executed from any thread on physical core Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request Counts the number of load uops retired that miss in the level 3 cache (Precise event) unc_m_pre_count.all umask=0xC80FFE01,event=0x35 TOR Inserts; DRd Opt Pref misses from local IA. Unit: uncore_cha Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 unc_iio_data_req_of_cpu.mem_write.part6 The number of 32B fetch windows transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheable fill responses) l2_request_g1.prefetch_l2_cmd Core to L2 cacheable request access status (not including L2 Prefetch). Data cache store or state change hit in L2 umask=0x1,event=0x64 L3 cache misses. Unit: uncore_l3pmc Retired Branch Instructions Mispredicted df_ccm_reqa.node4.anydram umask=0xED,event=0x8b Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdsized umask=0x47,event=0x8b umask=0xC7,event=0x8b umask=0x83,event=0x8b df_ccm_reqa.node2.rdvlkl df_ccm_reqb.node0.vicblkcln Data Fabric CCM Performance Monitor Event DF CCM Request Ordered vicblkcln umask=0x27,event=0x8c umask=0xC7,event=0x8c df_ccm_reqb.node4.anywrsized df_ccm_reqb.node4.wrsizedncposted umask=0x4B,event=0x108 umask=0x47,event=0x108 df_ioms_reqa.node1.anywrsized=64b umask=0xE6,event=0x108 umask=0x04,event=0x108 df_ioms_reqa.node2.anyrdsized df_ioms_reqa.node7.anyrdsized umask=0x6B,event=0x109 df_ioms_reqb.node7.ioanyatomic df_ioms_reqb.node2.ioanynon-postedwrsized=64b df_ioms_reqb.node5.ioanynon-postedwrsized=64b df_ioms_reqb.node2.ioanynon-postedwrsized>32band<64b df_ioms_reqb.node2.ioanypostedwrsized=32 df_ioms_reqb.node4.ioanypostedwrsized=32 Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized<32 df_ioms_reqb.node5.ioanypostedwrsized<32 umask=0x01,event=0x109 df_ioms_reqb.node4.iolargeread umask=0x80,event=0 umask=0x1,event=0 All FLOPS l3_request_g1.t4.s0.wrsizednc l3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x02,event=0x1 l3_request_g1.t3.s2.wrsizednc l3_request_g1.t6.s2.wrsizednc l3_request_g1.t6.s3.wrsizednc l3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x04,event=0x1 l3_request_g1.t2.s0.wrsized l3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x04,event=0x1 l3_request_g1.t2.s1.wrsized l3_request_g1.t0.s0.rdsizednc l3_request_g1.t3.s2.rdsized l3_request_g1.t0.s3.rdsized l3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x80,event=0x1 l3fillvicreq.t6.s0.vicblk l3fillvicreq.t5.s2.chgtox l3fillvicreq.t7.s0.rdblkc_s_vic l3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x04,event=0x3 l3fillvicreq.t2.s1.rdblkc_s_vic l3fillvicreq.t5.s3.rdblkc_s_vic l3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x08,event=0x3 l3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x08,event=0x3 l3fillvicreq.t6.s0.rdblkc_s l3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x08,event=0x3 l3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x10,event=0x3 l3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x20,event=0x3 l3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x20,event=0x3 l3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x20,event=0x3 l3fillvicreq.t1.s0.rdblkl l3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x80,event=0x3 l3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x80,event=0x3 l3victimstate.t1.s0.nol3victimline l3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x01,event=0x9 l3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x02,event=0x9 l3victimstate.t0.s1.f_s l3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x04,event=0x9 l3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x04,event=0x9 l3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x04,event=0x9 l3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x08,event=0x9 l3victimstate.t5.s0.m l3victimstate.t2.s1.m l3victimstate.t7.s3.m l3victimstate.t6.s0.d l3victimstate.t0.s3.d l3victimstate.t5.s1.od L1 DTLB Miss of a page of 2M size ls_l1_d_tlb_miss.tlb_reload_32k_l2_miss L1 DTLB Reload of a page of 2M size ls_tablewalker.dc_type0 Cycles where a dispatch group is valid but does not get dispatched due to a token stall. RETIRE Tokens unavailable umask=0x1,event=0x94 Divide/square root FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15 Floating Point Dispatch Faults. YMM fill fault Floating Point Dispatch Faults. x87 fill fault ls_locks.spec_lock_lo_spec Retired lock instructions. Low speculative cacheable lock speculation succeeded Number of retired CPUID instructions Number of reads of the TSC (RDTSC instructions). The count is speculative Software Prefetch Data Cache Fills by Data Source. DRAM or IO from this thread's die. From DRAM (home node local) Hardware Prefetch Data Cache Fills by Data Source. From DRAM (home node local) umask=0x4,event=0xae LS_SEGMENT_REGISTER_LOAD FR_DISPATCH_STALL_WHEN_FAR_XFER_OR_RESYNC_BRANCH_PENDING BUS_ACCESS OPS_ISSUED L2D_CACHE_INVAL RC_LD_SPEC MEM_CAP_READ BRANCH_MISPRED ITLB_ACCESS BASE_MISPRED_STALLS CP1_CP2_LOAD_INSNS MISPREDICTED_BRANCH_INSNS LOAD_INSNS RET USTORE CYCLES_NO_COMPLETED_INSTRS DTLB_HW_SEARCH_CYCLES_OVER_THRESHOLD INSTR_BKPT_MATCHES LSU_LMQ_INDEX_ALIAS LSU_MISALIGN_STALL CYCLES_WAITING_FROM_L1_INSTR_CACHE_MISS L1_DATA_LOAD_ACCESS_MISS L1_DATA_LOAD_MISS_CYCLES THIRD_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLY L3_CACHE_MISSES BUS_READS_NOT_RETRIED SNOOP_REQUESTS GCT_EMPTY L3_LOAD_MISS LOAD_NO_REAL_ADDR CYCLES_WITH_INSTRS_DISPATCHED INSTR_FETCHED UOPS_DECODED CYCLES_ISSUE_STALLED CACHE_INHIBITED_ACCESS_TRANSLATED STASH_BUSY_1 STASH_BUSY_2 L2_CACHE_DIRTY_DATA_ALLOCATIONS DVT0_DETECTED multiply-pipe-junk-ops fs cycles-to-complete tlb-reload K7 K8 SC PMUDEBUG period {"type": "thr_create" %s, "oldpid": "%d", "newpid": "%d"}
TopDownL1 4*( cpu_clk_unhalted.thread_any / 2 ) if #smt_on else cycles Instruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed) umask=0x42,period=200003,event=0x24 umask=0x50,period=200003,event=0x24 This event counts the total number of L2 code requests This event counts the total number of requests from the L2 hardware prefetchers Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle Spec update: BDM76 Retired load uops with L2 cache hits as data sources. (Precise Event - PEBS) Supports address when precise. Spec update: BDM35 (Precise event) Hit in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS) Supports address when precise. Spec update: BDM100 (Precise event) Retired load uops with L2 cache misses as data sources. Uses PEBS Supports address when precise (Precise event) This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were HitM responses from a core on same socket (shared L3) Supports address when precise. Spec update: BDM100 (Precise event) Retired load uops which data sources were hits in L3 without snoops required. (Precise Event - PEBS) Supports address when precise. Spec update: BDM100 (Precise event) other_assists.avx_to_sse fp_arith_inst_retired.256b_packed_single idq.ms_dsb_uops This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ Cycles Decode Stream Buffer (DSB) is delivering any Uop This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB) umask=0x30,period=2000003,event=0x79 edge=1,umask=0x30,cmask=1,period=2000003,event=0x79 Speculative cache line split load uops dispatched to L1 cache umask=0x8,period=2000003,event=0x5d Counts the number of machine clears due to memory order conflicts umask=0x20,period=2000003,event=0xc8 umask=0x10,period=2000003,event=0xc9 Number of times a RTM caused a fault mem_trans_retired.load_latency_gt_64 umask=0x2,period=2000003,event=0x5c Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke) Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS) cpu_clk_thread_unhalted.ref_xclk_any cpu_clk_unhalted.ref_xclk umask=0x1,period=2000003,event=0x5e This event counts taken speculative and retired indirect branches that have a return mnemonic This event counts the number of micro-operations cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports across all dispatch ports exceeds the read bandwidth of the physical register file. The SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*. See the Broadwell Optimization Guide for more information uops_executed_port.port_5_core This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6 uops_dispatched_port.port_7 umask=0x1,period=2000003,event=0xc2 umask=0x3,event=0x35,filter_opc=0x19e LLC misses for PCIe read current. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox PCIe writes (partial cache line). Derived from unc_c_tor_inserts.opcode. Unit: uncore_cbox umask=0x1,event=0x1 umask=0xC,event=0x4 power_state_occupancy.cores_c0 % This is an occupancy event that tracks the number of cores that are in C6. It can be used by itself to get the average number of cores in C0, with threshholding to generate histograms, or with other PCU events . Unit: uncore_pcu event=0x74 umask=0x1,period=100003,event=0x8 Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size Spec update: BDM69 Store misses in all DTLB levels that cause completed page walks (2M/4M) Spec update: BDM69 umask=0xe,period=100003,event=0x85 Bad_Speculation CoreIPC_SMT Retired load uops with L2 cache hits as data sources. (Precise Event - PEBS) Spec update: BDM35. Supports address when precise (Precise event) offcore_response.demand_code_rd.l3_hit.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020010 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0010 Counts all prefetch (that bring data to L2) RFOs have any response type offcore_response.pf_l2_rfo.l3_hit.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020040 offcore_response.pf_l3_data_rd.l3_hit.snoop_none offcore_response.pf_l3_code_rd.l3_hit.snoop_miss Counts any other requests umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C8000 offcore_response.all_pf_data_rd.supplier_none.snoop_miss offcore_response.all_pf_data_rd.l3_hit.snoop_miss offcore_response.all_rfo.l3_hit.snoop_miss offcore_response.demand_data_rd.l3_miss.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000004 offcore_response.corewb.supplier_none.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000010 offcore_response.pf_l2_rfo.l3_hit.snoop_non_dram offcore_response.pf_l2_rfo.l3_miss.snoop_none offcore_response.pf_l2_code_rd.l3_miss.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000080 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000200 offcore_response.all_pf_data_rd.supplier_none.snoop_non_dram offcore_response.all_pf_data_rd.l3_miss.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000120 offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000240 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000122 inv=1,umask=0x1,period=2000003,cmask=10,event=0xc2 Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches Socket_CLKS This event counts retired load uops which data sources were hits in the nearest-level (L1) cache.
Note: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. This event also counts SW prefetches independent of the actual data source Supports address when precise (Precise event) Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00244 Return instructions retired (Precise event) This event counts taken branch instructions retired (Precise event) number of near branch instructions retired that were mispredicted and taken (Precise event) l2_m_lines_in.self l2_lock.self.e_state l2_ld_ifetch.self.s_state umask=0x2,period=2000000,event=0x10 SIMD unpacked micro-ops executed Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions umask=0x2,period=2000000,event=0x87 umask=0xa,period=200000,event=0x5 Memory cluster signals to block micro-op dispatch for any reason eist_trans umask=0xe0,period=200000,event=0x60 Bus cycles while processor receives data Burst read bus transactions umask=0x40,period=200000,event=0x66 bus_trans_inval.self bus_trans_p.self Cycles during which interrupts are disabled mul.ar Bus cycles when core is not halted umask=0x20,period=2000000,event=0x88 umask=0x3,period=2000000,event=0xc L2 cache request misses Counts memory load uops retired where the data is retrieved from the WCB (or fill buffer), indicating that the load found its data while that data was in the process of being brought into the L1 cache. Typically a load will receive this indication when some other load or prefetch missed the L1 cache and was in the process of retrieving the cache line containing the data, but that process had not yet finished (and written the data back to the cache). For example, consider load X and Y, both referencing the same cache line that is not in the L1 cache. If load X misses cache first, it obtains and WCB (or fill buffer) and begins the process of requesting the data. When load Y requests the data, it will either hit the WCB, or the L1 cache, depending on exactly what time the request to Y occurs Supports address when precise (Must be precise) Counts memory load uops retired where the data is retrieved from DRAM. Event is counted at retirement, so the speculative loads are ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit DRAM, hit in the WCB or receive a HITM response Supports address when precise (Must be precise) umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400008000 offcore_response.partial_streaming_stores.l2_miss.hitm_other_core Counts data cache lines requests by software prefetch instructions that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cacheline reads generated by hardware L2 cache prefetcher that hit the L2 cache umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000004 umask=0x4,period=200003,event=0x13 Core cycles when core is not halted (Fixed event) Loads blocked because address in not in the UTLB (Precise event capable) (Must be precise) br_misp_retired.jcc umask=0x2,period=200003,event=0x5 Counts data cacheline reads generated by hardware L2 cache prefetcher hit the L2 cache Counts data cacheline reads generated by hardware L2 cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts bus lock and split lock requests outstanding, per cycle, from the time of the L2 miss to when any response is received Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000004800 Counts any data writes to uncacheable write combining (USWC) memory region outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_pf_data_rd.outstanding Counts reads for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Page walks outstanding due to an instruction fetch every cycle Counts once per cycle for each page walk occurring due to an instruction fetch. Includes cycles spent traversing the Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of walks Counts all L2 store RFO requests Retired load uops with L2 cache hits as data sources Spec update: HSD76, HSD29, HSM30. Supports address when precise (Precise event) Approximate counts of AVX & AVX2 256-bit instructions, including non-arithmetic instructions, loads, and stores. May count non-AVX instructions that employ 256-bit operations, including (but not necessarily limited to) rep string instructions that use 256-bit loads and stores for optimized performance, XSAVE* and XRSTOR*, and operations that transition the x87 FPU data registers between x87 and MMX Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero Randomly selected loads with latency value being above 256 Spec update: HSD76, HSD25, HSM26 (Must be precise) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00244 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00001 Number of multiply packed/scalar single precision uops allocated inv=1,umask=0x1,any=1,period=2000003,cmask=1,event=0xc2 This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear. Machine clears can have a significant performance impact if they are happening frequently unc_cbo_xsnp_response.hit_external unc_cbo_xsnp_response.hit_eviction Number of ITLB page walker loads that hit in the L2 page_walker_loads.ept_dtlb_memory page_walker_loads.ept_itlb_l2 Count number of STLB flush attempts This is a non-precise version (that is, does not use PEBS) of the event that counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling umask=0x4,period=200003,event=0x24 umask=0xc,period=200003,event=0x24 RFOs that access cache lines in any state Retired load uops with locked access. (Precise Event) Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0122 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0004 Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Counts number of SSE* or AVX-128 double precision FP scalar uops executed Counts cycles the IDQ is empty Speculative cache-line split Store-address uops dispatched to L1D Loads with latency value being above 8 (Must be precise) umask=0x08,event=0x22 A snoop invalidates a modified line in some processor core umask=0x20,event=0x22 Unit: uncore_cbox LLC lookup request that access cache and found line in M-state mem_load_uops_llc_miss_retired.remote_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0010 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0080 Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from local dram Memory controller clock ticks. Use to generate percentages for memory controller CYCLES events. Unit: uncore_imc event=0xd,edge=1 Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...) umask=0x10,period=100003,event=0x8 Counts the number of load micro-ops retired that caused micro TLB miss offcore_response.any_pf_l2.any_response Counts Demand cacheable data and L1 prefetch data read requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800083091 Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state offcore_response.pf_software.any_response Counts Partial reads (UC or WC and is valid only for Outstanding response type). that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0 Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400080 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080040 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400020 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080004 Counts demand cacheable data and L1 prefetch data reads that accounts for any response offcore_response.demand_code_rd.l2_hit_this_tile_m offcore_response.pf_l2_code_rd.l2_hit_this_tile_e umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000100 Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in E state Counts any request that accounts for responses which hit its own tile's L2 with data in S state offcore_response.pf_l2_code_rd.l2_hit_this_tile_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000070 Counts UC code reads (valid only for Outstanding response type) that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800408000 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800400022 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000022 Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Local umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200080 Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from any NON_DRAM system address. This includes MMIO transactions Counts Demand cacheable data writes that accounts for data responses from MCDRAM Local Counts UC code reads (valid only for Outstanding response type) that accounts for responses from MCDRAM (local and far) Counts any request that accounts for responses from MCDRAM (local and far) umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181800020 Counts all the retired locked loads. It does not include stores because we would double count if we count stores Counts the number of mispredicted near CALL branch instructions retired (Precise event) l1d_cache_ld.i_state umask=0x4,period=2000000,event=0x41 l2_data_rqsts.demand.e_state umask=0x10,period=200000,event=0x24 umask=0x1,period=200000,event=0x24 l2_rqsts.prefetch_hit umask=0x4,period=200000,event=0x24 L2 writeback to LLC transactions umask=0x8,period=20000,event=0xf umask=0x10,period=20,event=0xb,ldlat=0x1000 mem_inst_retired.latency_above_threshold_8 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x211 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x244 offcore_response.corewb.llc_hit_other_core_hitm umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3808 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F77 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x733 offcore_response.data_in.remote_cache_dram offcore_response.demand_data.remote_cache_dram offcore_response.demand_rfo.llc_hit_other_core_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1802 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x240 SIMD integer 64 bit shuffle/move operations offcore_response.any_rfo.any_llc_miss umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4008 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x6033 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4033 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x6030 umask=0x3,period=2000000,event=0x80 rat_stalls.scoreboard umask=0x2,period=2000000,event=0x14 br_inst_exec.direct_near_call umask=0x7f,period=20000,event=0x89 br_misp_exec.indirect_non_call umask=0x1,period=2000000,cmask=1,event=0xa8 lsd_overflow ssex_uops_retired.scalar_single uops_issued.cycles_all_threads umask=0x4,period=2000000,event=0xc2 Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace Counts retired load instructions with at least one uop that missed in the L1 cache Supports address when precise (Precise event) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400108000 offcore_response.other.l3_hit_m.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000100004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100040002 offcore_response.demand_rfo.supplier_none.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020002 offcore_response.demand_data_rd.l3_hit_s.snoop_not_needed offcore_response.demand_data_rd.l3_hit_e.spl_hit frontend_retired.latency_ge_32 frontend_retired.latency_ge_2_bubbles_ge_1 hle_retired.aborted_memtype offcore_response.demand_data_rd.l3_hit_e.snoop_non_dram Cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations Counts when the Current Privilege Level (CPL) transitions from ring 1, 2 or 3 to ring 0 (Kernel) Cycles where no uops were executed, the Reservation Station was not empty, the Store Buffer was full and there was no outstanding load Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector) Counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two) Spec update: SKL091, SKL044 Counts cycles for each PMH (Page Miss Handler) that is busy with an EPT (Extended Page Table) walk for any request type Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake umask=0x10,period=100003,cmask=1,event=0x85 This event counts the total number of L2 cache references and the number of L2 cache misses respectively This event counts the number of retired loads that were prohibited from receiving forwarded data from the store because of address mismatch (Precise event) This event counts the number of load uops reissued from Rehabq Counts RFO requests generated by L2 prefetchers that miss L2 with a snoop miss response umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080000008 This event counts all instruction fetches, not including most uncacheable
fetches mem_load_uops_misc_retired.llc_miss Counts prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10433 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400240 Counts all prefetch (that bring data to LLC only) RFOs that miss the LLC and the data returned from dram offcore_response.pf_l_data_rd.llc_miss_local.dram umask=0x2,period=100000,event=0xb0 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x80ff REQUEST = DATA_IFETCH and RESPONSE = IO_CSR_MMIO REQUEST = DATA_IN and RESPONSE = ANY_LOCATION REQUEST = DATA_IN and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = DEMAND_DATA_RD and RESPONSE = IO_CSR_MMIO REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE REQUEST = DEMAND_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = OTHER and RESPONSE = LOCAL_CACHE umask=0x1,period=100000,event=0xb7,offcore_rsp=0x250 REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITM REQUEST = PF_RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5020 REQUEST = PREFETCH and RESPONSE = ANY_CACHE_DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3008 offcore_response.demand_ifetch.other_local_dram umask=0x1,period=100000,event=0xb4 dtlb_misses.large_walk_completed umask=0x20,period=200000,event=0x49 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2720 mem_load_l3_miss_retired.local_dram Retired load instructions whose data sources was remote HITM Supports address when precise (Precise event) offcore_response.demand_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd core_power.lvl1_turbo_license core_snoop_response.rsp_ifwdfe Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly edge=1,inv=1,umask=0x1,cmask=1,period=2000003,event=0x5e 1000 * l2_lines_out.non_silent / inst_retired.any All DRAM CAS Commands issued. Unit: uncore_imc Counts CAS (Column Access Select) underfill read commands issued to DRAM due to a partial write, on a per channel basis. CAS commands are issued to specify the address to read or write on DRAM, and this command counts underfill reads. Partial writes must be completed by first reading in the underfill from DRAM and then merging in the partial write data before writing the full line back to DRAM. This event will generally count about the same as the number of partial writes, but may be slightly less because of partials hitting in the WPQ (due to a previous write request) upi_data_bandwidth_tx fc_mask=0x07,ch_mask=0x01,umask=0x04,event=0x83,ch_mask=0x1f unc_iio_data_req_of_cpu.mem_read.part0 PCI Express bandwidth reading at IIO, part 2. Unit: uncore_iio PCI Express bandwidth reading at IIO, part 3. Unit: uncore_iio Multi-socket cacheline Directory state updates; Directory Updated memory write from the HA pipe. Unit: uncore_cha umask=0x10,event=0x50 Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA Clockticks of the IIO Traffic Controller. Unit: uncore_iio Write request of up to a 64 byte transaction is made to IIO Part0 by the CPU. Unit: uncore_iio unc_iio_txn_req_of_cpu.mem_read.part2 Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state, and found the cacheline marked in Any State (A, I, S or unused) Multi-socket cacheline Directory update from A to S. Unit: uncore_m2m umask=0x4,event=0x2e umask=0x2,event=0x12 unc_upi_rxl_flits.all_data event=0x41 offcore_response.all_data_rd.l3_hit_f.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020004 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED offcore_response.all_rfo.l3_hit_s.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020080 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100491 offcore_response.pf_l2_data_rd.l3_hit_e.hit_other_core_fwd offcore_response.other.l3_hit_m.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400080 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l3_rfo.pmm_hit_local_pmm.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040120 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010080 offcore_response.pf_l3_rfo.l3_hit_e.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0020 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100100 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP All retired load instructions Supports address when precise (Precise event) period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040100 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD offcore_response.pf_l2_data_rd.l3_hit_m.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080491 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080490 offcore_response.all_data_rd.l3_hit_e.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP offcore_response.pf_l3_rfo.l3_hit_m.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP offcore_response.all_pf_rfo.l3_hit_m.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400122 Retired load instructions which data sources missed L3 but serviced from local DRAM Supports address when precise (Precise event) period=100003,umask=0x1,event=0xb0 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020020 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0020 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020122 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200491 cmask=1,period=2000003,umask=0x4,event=0x79 period=2000003,umask=0x2,event=0xab offcore_response.other.l3_miss_local_dram.hit_other_core_fwd offcore_response.pf_l2_data_rd.l3_miss_local_dram.hit_other_core_fwd ocr.pf_l1d_and_sw.l3_miss_local_dram.no_snoop_needed ocr.pf_l2_data_rd.l3_miss_local_dram.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000400 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000004 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000002 This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10100007F7 Counts all demand data writes (RFOs) DEMAND_RFO & L3_MISS & SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000010 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000122 This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC008000 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000020 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C0007F7 ALL_PF_DATA_RD & L3_MISS & SNOOP_MISS ocr.all_rfo.l3_miss_local_dram.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000010 ALL_READS & L3_MISS_REMOTE_DRAM & SNOOP_MISS_OR_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000100 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000491 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000002 This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP ocr.demand_code_rd.l3_miss.any_snoop ocr.all_reads.l3_miss_remote_hop1_dram.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000100 This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS & SNOOP_NONE Counts all demand data writes (RFOs) DEMAND_RFO & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_FWD ALL_READS & L3_MISS & SNOOP_NONE offcore_response.demand_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS_LOCAL_DRAM & HITM_OTHER_CORE offcore_response.pf_l2_rfo.l3_miss_local_dram.no_snoop_needed This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE ocr.all_pf_data_rd.l3_miss_remote_hop1_dram.snoop_miss Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS & HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000122 offcore_response.demand_data_rd.l3_miss.hit_other_core_fwd Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS & HIT_OTHER_CORE_NO_FWD ocr.pf_l3_rfo.l3_miss_local_dram.hitm_other_core period=2000003,umask=0x4,event=0xc8 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000010 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD Counts demand data reads DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & NO_SNOOP_NEEDED Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS_REMOTE_HOP1_DRAM & HITM_OTHER_CORE ocr.demand_data_rd.l3_hit.snoop_miss Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT & HIT_OTHER_CORE_FWD ALL_RFO & SUPPLIER_NONE & NO_SNOOP_NEEDED ocr.pf_l1d_and_sw.l3_hit.snoop_hit_with_fwd Counts any other requests OTHER & L3_HIT & SNOOP_MISS ocr.all_rfo.l3_hit.hitm_other_core ALL_RFO & L3_HIT & HITM_OTHER_CORE ALL_DATA_RD & L3_HIT_S & SNOOP_MISS Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_F & HIT_OTHER_CORE_FWD ocr.pf_l3_rfo.supplier_none.hitm_other_core ocr.all_pf_data_rd.l3_hit_e.snoop_miss ocr.all_rfo.l3_hit_e.hit_other_core_fwd ocr.pf_l3_rfo.l3_hit_m.snoop_miss Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_E & HIT_OTHER_CORE_NO_FWD Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_F & ANY_SNOOP Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & PMM_HIT_LOCAL_PMM & SNOOP_NONE ALL_DATA_RD & L3_HIT_M & SNOOP_NONE ALL_RFO & L3_HIT_M & HIT_OTHER_CORE_FWD ocr.demand_code_rd.l3_hit.hit_other_core_fwd Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_M & ANY_SNOOP ocr.all_pf_rfo.l3_hit_m.snoop_none ocr.all_rfo.supplier_none.hit_other_core_fwd ALL_RFO & SUPPLIER_NONE & HIT_OTHER_CORE_FWD Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_F & HITM_OTHER_CORE Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & SUPPLIER_NONE & NO_SNOOP_NEEDED Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & SUPPLIER_NONE & NO_SNOOP_NEEDED Counts all demand code reads DEMAND_CODE_RD & L3_HIT & SNOOP_NONE ALL_DATA_RD & L3_HIT & HITM_OTHER_CORE Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & SUPPLIER_NONE & ANY_SNOOP Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_F & HIT_OTHER_CORE_FWD ocr.demand_code_rd.l3_hit_m.no_snoop_needed Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_E & ANY_SNOOP ocr.pf_l2_rfo.l3_hit_m.any_snoop ALL_PF_DATA_RD & L3_HIT_S & HITM_OTHER_CORE ocr.other.l3_hit_m.any_snoop ALL_READS & L3_HIT_E & NO_SNOOP_NEEDED Counts any other requests OTHER & SUPPLIER_NONE & ANY_SNOOP ocr.demand_rfo.l3_hit_s.hitm_other_core ALL_DATA_RD & L3_HIT_S & SNOOP_NONE ALL_RFO & L3_HIT_S & SNOOP_MISS Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_F & HITM_OTHER_CORE ocr.demand_data_rd.pmm_hit_local_pmm.snoop_not_needed Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & PMM_HIT_LOCAL_PMM & ANY_SNOOP Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_F & ANY_SNOOP Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_S & HIT_OTHER_CORE_FWD ocr.pf_l3_data_rd.l3_hit_s.no_snoop_needed ocr.demand_data_rd.l3_hit_f.hitm_other_core ocr.all_pf_rfo.l3_hit_s.snoop_none period=100007,umask=0x40,event=0xc4 cmask=4,period=2000003,umask=0x4,event=0xa3 period=400009,umask=0x10,event=0xc4 event=0xe7 unc_m_pmm_cmd1.all Counts snoop filter capacity evictions for entries tracking exclusive lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part3. Unit: uncore_iio Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part3 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus Counts every peer to peer write request of 4 bytes of data made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.peer_read.part3 Tag Hit; Read Hit from NearMem, Dirty Line umask=0x28,period=200003,event=0x24 Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailablability Counts retired load instructions that true miss the STLB Supports address when precise (Precise event) Counts retired load instructions with L2 cache hits as data sources Supports address when precise (Precise event) Retired load instructions whose data sources were HitM responses from shared L3 Supports address when precise (Precise event) idq.ms_cycles_any Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled Counts the number of times a TSX Abort was triggered due to commit but Lock Buffer not empty Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts) uops_dispatched.port_1 Number of retired PAUSE instructions Page walks completed due to a demand data load to a 2M/4M page Number of page walks outstanding for a demand load in the PMH each cycle Counts the number of store uops retired. This event is Precise Event capable Supports address when precise (Precise event) ocr.demand_rfo.l3_miss Counts the number of instructions that retire. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0 (Precise event) DRAM Precharge commands. : Precharge due to page table : Counts the number of DRAM Precharge commands sent on this channel unc_cha_tor_inserts.ia_miss_drd_opt_pref fc_mask=0x07,ch_mask=0x10,umask=0x04,event=0x83 unc_iio_data_req_of_cpu.mem_write.part5 Clockticks of the mesh to memory (M2M) event=0x8b Dynamic Indirect Predictions bp_de_redirect The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB umask=0x4,event=0x87 IC line invalidated due to overwriting fill response. The number of instruction cache lines invalidated. A non-SMC event is CMC (cross modifying code), either from the other thread of the core or another core All L2 Cache Requests (Breakdown 1 - Common). Data cache stores All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheable l2_request_g2.ic_rd_sized_nc umask=0x80,event=0x64 l3_lookup_state.all_l3_req_typs The number of retired taken branch instructions that were mispredicted The number of resync branches. These reflect pipeline restarts due to certain microcode assists and events such as writes to the active instruction stream, among other things. Each occurrence reflects a restart penalty similar to a branch mispredict. This is relatively rare umask=0x0F,event=0x8b df_ccm_reqa.node3.wrsizedfullnc umask=0xEA,event=0x8b umask=0xA6,event=0x8b df_ccm_reqa.node2.rdvlkc umask=0xE4,event=0x8b df_ccm_reqa.node3.rdvlkx umask=0x82,event=0x8b df_ccm_reqa.node7.rdvlks df_ccm_reqb.node6.vicblkfull. df_ccm_reqb.node2.wbinvblkall umask=0x8B,event=0x8c umask=0x66,event=0x8c df_ccm_reqb.node2.rdsized df_ccm_reqb.node4.rdsized umask=0x0C,event=0x108 df_ioms_reqa.node5.masterabort umask=0xAC,event=0x108 df_ioms_reqa.node6.masterabort umask=0x09,event=0x108 Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) fence df_ioms_reqa.node3.anyatomic umask=0x67,event=0x108 umask=0x03,event=0x108 umask=0x2F,event=0x109 df_ioms_reqb.node3.pieiorequest umask=0x4A,event=0x109 df_ioms_reqb.node7.ioanynon-postedwrsized>32band<64b umask=0xA8,event=0x109 df_ioms_reqb.node0.ioanynon-postedwrsized<32b umask=0x87,event=0x109 df_ioms_reqb.node5.ioanypostedwrsized=64b umask=0x05,event=0x109 umask=0x24,event=0x109 umask=0x64,event=0x109 umask=0xA4,event=0x109 df_ioms_reqb.node7.ioanypostedwrsized=32 fp_retx87_fp_ops.div_sqr_r_ops fp_retx87_fp_ops.mul_ops Multiply Ops l3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x02,event=0x1 l3_request_g1.t4.s3.wrsizednc l3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x04,event=0x1 l3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x04,event=0x1 l3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x04,event=0x1 l3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x20,event=0x1 l3_request_g1.t4.s3.rdsizednc l3_request_g1.t3.s3.rdsized l3_request_g1.t1.s2.caching l3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x80,event=0x1 l3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x80,event=0x1 l3fillvicreq.t1.s0.vicblk l3fillvicreq.t4.s1.vicblk l3fillvicreq.t0.s2.vicblk l3fillvicreq.t4.s2.chgtox l3fillvicreq.t3.s1.rdblkc_s l3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x08,event=0x3 l3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x10,event=0x3 l3fillvicreq.t0.s1.rdblkx l3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x20,event=0x3 l3fillvicreq.t7.s1.rdblkx l3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x40,event=0x3 l3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x40,event=0x3 l3fillvicreq.t3.s0.rdblkl l3fillvicreq.t5.s1.rdblkl l3fillvicreq.t3.s2.rdblkl l3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x80,event=0x3 L3 Cache Performance Monitor Counters RequestMiss: L3 miss l3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x01,event=0x9 l3victimstate.t7.s1.nol3victimline l3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x01,event=0x9 l3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x02,event=0x9 l3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x04,event=0x9 l3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x08,event=0x9 l3victimstate.t7.s3.o l3victimstate.t5.s2.e_fe l3victimstate.t5.s3.e_fe l3victimstate.t1.s1.m l3victimstate.t6.s2.m l3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x80,event=0x9 l3victimstate.t0.s2.od L1 DTLB Miss of a page of 1G size Total Page Table Walks on D-side ls_pref_instr_disp.prefetch_nta The number of instruction fetches that hit in the L1 ITLB. Instruction fetches to a 2MB page umask=0xff,event=0x85 Dispatch of a single op that performs a load from and store to the same memory address. Number of single ops that do load/store to an address ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss ls_sw_pf_dc_fill.ls_mabresp_rmt_dram de_dis_dispatch_token_stalls1.fp_reg_file_rsrc_stall umask=0x2,event=0xae FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED_BY_ADDR_MISCOMPARE FR_DISPATCH_STALL_WHEN_RESERVATION_STATIONS_ARE_FULL FR_NUMBER_OF_BREAKPOINTS_FOR_DR0 L1_DCACHE_WB L2_STORE_MERGED AXI_READ DATA_MAIN_TLB_MISS_STALL EXC_RETURN BR_PRED L2D_CACHE TTBR_WRITE_RETIRED L2D_TLB_REFILL_RD L2D_TLB_WR INST_KERNEL MISPREDICTED_BRANCH_LIKELY_INSNS NOP_INSNS ISPRAM_EVENTS REPLAY CSRC L1_DATA_TOTAL_HITS BUS_RETRY_DUE_TO_COLLISION CYCLES_SU1_SCHED_STALLED STORES_COMPLETED DATA_MMU_BUSY CRIT_INPUT_INTR_LATENCY_CYCLES DAC2S_DTECTED k8-ic-miss ss piggyback rdszdword PPC_POWER8 DISABLED ALLOCATED metric_group: %s
hw_interrupts.received GenuineIntel Memory_Bound;Memory_BW Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses Power offcore_requests.demand_rfo This event counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.
Note: Writeback pending FIFO has six entries This is a precise version (that is, uses PEBS) of the event that counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K) Supports address when precise (Precise event) mem_load_uops_l3_hit_retired.xsnp_miss umask=0x1,period=20011,event=0xd2 umask=0x4,period=20011,event=0xd2 umask=0x20,period=100007,event=0xd3 RFO requests that access L2 cache This event counts L1D writebacks that access L2 cache L2 cache lines in I state filling L2 umask=0x10,period=100003,event=0xc1 umask=0x8,cmask=1,period=2000003,event=0x79 This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB) umask=0x1,period=2000003,event=0x80 Number of times an HLE execution aborted due to incompatible memory type umask=0x1,period=2000003,event=0xc9 Number of times an RTM execution aborted due to HLE-unfriendly instructions umask=0x80,period=2000003,event=0xc9 Loads with latency value being above 256 Spec update: BDM100, BDM35 (Must be precise) umask=0x1,period=2000003,event=0x63 inv=1,umask=0x1,cmask=1,period=2000003,event=0xe umask=0x1,period=2000003,event=0x14 umask=0x4,period=1000003,event=0x58 umask=0x82,period=200003,event=0x88 Speculative and retired indirect branches excluding calls and returns umask=0x1,period=2000003,event=0xa1 Cycles per thread when uops are executed in port 1 uops_dispatched_port.port_2 Cycles per thread when uops are executed in port 2 resource_stalls.rs cycle_activity.cycles_l2_pending cycle_activity.stalls_ldm_pending cycle_activity.cycles_l1d_miss umask=0x2,period=2000003,event=0xb1 uops_executed.core_cycles_ge_1 inst_retired.prec_dist Actually retired uops. (Precise Event - PEBS) Supports address when precise (Precise event) Retirement slots used. (Precise Event - PEBS) (Precise event) This event counts both thread-specific (TS) and all-thread (AT) nukes umask=0x3,event=0x35,filter_opc=0x187,filter_nc=1 Memory controller clock ticks. Unit: uncore_imc event=0x80,occ_sel=1 power_state_occupancy.cores_c6 % (unc_p_freq_max_limit_thermal_cycles / unc_p_clockticks) * 100. dtlb_load_misses.stlb_hit_2m This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault Spec update: BDM69 dtlb_store_misses.stlb_hit_2m page_walker_loads.itlb_l3 1 - ( (idq_uops_not_delivered.core / (4 * cycles)) + (( uops_issued.any - uops_retired.retire_slots + 4 * int_misc.recovery_cycles ) / (4 * cycles)) + (uops_retired.retire_slots / (4 * cycles)) ) IpTB Branch instructions per taken branch 4 * cycles TLB_SMT offcore_response.demand_code_rd.supplier_none.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0008 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0008 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020020 offcore_response.pf_l3_data_rd.l3_hit.snoop_miss offcore_response.pf_l3_data_rd.l3_hit.any_snoop offcore_response.pf_l3_rfo.supplier_none.snoop_not_needed offcore_response.pf_l3_rfo.l3_hit.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0100 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020200 offcore_response.other.supplier_none.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020240 Counts all demand & prefetch data reads offcore_response.demand_code_rd.l3_miss.snoop_none offcore_response.corewb.l3_miss.snoop_none offcore_response.corewb.l3_miss.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000020 offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_miss offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000100 offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_miss offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_miss offcore_response.all_pf_data_rd.l3_miss.snoop_not_needed offcore_response.all_pf_code_rd.supplier_none.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0240 offcore_response.all_rfo.l3_miss_local_dram.snoop_hitm umask=0x1,period=2000003,cmask=2,event=0xb1 umask=0x1,period=2000003,cmask=3,event=0xb1 L3 Lookup any request that access cache and found line in E or S-state umask=0x02,event=0x80 Each cycle count number of 'valid' coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case umask=0x01,event=0x84 umask=0x01,event=0 Retired load uop whose Data Source was: Remote cache HITM Supports address when precise. Spec update: BDE70 (Precise event) Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Counts all requests miss in the L3 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00091 Number of non data (control) flits transmitted . Derived from unc_q_txl_flits_g0.non_data. Unit: uncore_qpi (unc_m_power_self_refresh / unc_m_clockticks) * 100. l2_lines_out.self.demand l2_ld.self.any.s_state umask=0x72,period=200000,event=0x29 l2_st.self.i_state l2_st.self.mesi All data requests from the L1 data cache l2_rqsts.self.any.mesi umask=0x44,period=200000,event=0x30 x87_comp_ops_exe.fxch.s simd_uop_type_exec.arithmetic.ar simd_inst_retired.scalar_double Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions umask=0x1,period=2000000,event=0xca icache.accesses umask=0x3,period=2000000,event=0xaa Memory references that cross an 8-byte boundary misalign_mem_ref.ld_bubble ext_snoop.this_agent.any umask=0x41,period=2000000,event=0x88 Retired branch instructions that were mispredicted not-taken Retired branch instructions that were mispredicted taken ITLB hits umask=0x0,period=200003,event=0x30 Counts load uops retired where the data requested spans a 64 byte cache line boundary Supports address when precise (Must be precise) Counts store uops retired where the data requested spans a 64 byte cache line boundary Supports address when precise (Must be precise) umask=0x43,period=200003,event=0xd0 Load uops retired that hit L1 data cache (Precise event capable) Supports address when precise (Must be precise) Load uops retired that missed L2 (Precise event capable) Supports address when precise (Must be precise) offcore_response.any_data_rd.l2_hit Counts requests to the uncore subsystem that have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000004000 Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) umask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600000100 offcore_response.pf_l2_data_rd.l2_miss.any umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200000010 offcore_response.demand_rfo.l2_hit Counts demand cacheable data reads of full cache lines that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400000001 Counts demand cacheable data reads of full cache lines that hit the L2 cache Loads blocked due to store forward restriction (Precise event capable) (Must be precise) umask=0x0,period=200003,event=0xe machine_clears.disambiguation Counts mispredicted branch instructions retired including all branch types (Must be precise) umask=0xeb,period=200003,event=0xc5 Counts core cycles the floating point divide unit is busy Counts store uops retired that caused a DTLB miss Supports address when precise (Must be precise) Memory uops retired that missed the DTLB (Precise event capable) Supports address when precise (Must be precise) Counts reads for ownership (RFO) requests generated by L2 prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000011000 Counts data cache lines requests by software prefetch instructions hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cache lines requests by software prefetch instructions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required offcore_response.pf_l1_data_rd.any_response Counts data cache line reads generated by hardware L1 data cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts any data writes to uncacheable write combining (USWC) memory region have any transaction responses from the uncore subsystem Counts data reads generated by L1 or L2 prefetchers true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault Offcore outstanding demand data read transactions in SQ to uncore. Set Cmask=1 to count cycles Spec update: HSD78, HSD62, HSD61 umask=0x6,period=100003,event=0xf2 offcore_response.pf_l3_rfo.l3_hit.any_response offcore_response.pf_l3_data_rd.l3_hit.any_response Note that a whole rep string only counts AVX_INST.ALL once Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer offcore_response.pf_l2_data_rd.l3_miss.any_response offcore_response.demand_code_rd.l3_miss.local_dram Increments at the frequency of XCLK (100 MHz) when not halted Cycles per core when uops are executed in port 0 uops_retired.core_stall_cycles An external snoop misses in some processor core unc_cbo_cache_lookup.extsnp_m Unit: uncore_cbox L3 Lookup external snoop request that access cache and found line in MESI-state Cycles when PMH is busy with page walks offcore_response.demand_code_rd.llc_hit.hit_other_core_no_fwd offcore_response.demand_rfo.llc_miss.local_dram offcore_response.demand_code_rd.llc_miss.local_dram umask=0x1,period=200003,event=0x27 mem_load_uops_retired.llc_hit Retired load uops with L2 cache misses as data sources (Precise event) Retired load uops which data sources were HitM responses from shared LLC (Precise event) Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00010001 Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle umask=0x8,period=2000003,event=0xac Number of flags-merge uops allocated. Such uops adds delay Execution stalls while L2 cache miss load* is outstanding umask=0x80,period=100003,event=0xc1 umask=0x02,event=0x22 unc_cbo_xsnp_response.hitm umask=0x40,event=0x22 Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC offcore_response.all_pf_data_rd.llc_hit.no_snoop_needed Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded offcore_response.all_code_rd.llc_miss.remote_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x600400001 offcore_response.demand_data_rd.llc_miss.remote_hit_forward Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote & local dram event=0xc Counts the number of cycles that the uncore transitioned to a frequency greater than or equal to the frequency that is configured in the filter. (filter_band2=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Derived from unc_p_freq_band2_cycles. Unit: uncore_pcu freq_ge_1200mhz_cycles % freq_ge_4000mhz_cycles % Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacement This event counts the number of micro-ops retired (Precise event) This event counts the number of the divide operations executed uops_dispatched.thread umask=0x10,period=100003,event=0x3 Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K. This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline. The enhanced address check typically has a performance penalty of 5 cycles umask=0x4f,period=2000003,event=0x5b Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. (filter_band2=XXX with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Unit: uncore_pcu umask=0x2,period=200003,event=0x4 mem_uops_retired.hitm Counts any Read request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode Counts Demand cacheable data write requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state Counts Bus locks and split lock requests that accounts for any response Counts UC code reads (valid only for Outstanding response type) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010200 Counts UC code reads (valid only for Outstanding response type) that accounts for any response umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400080 Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for any response Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state offcore_response.partial_writes.l2_hit_this_tile_m offcore_response.demand_code_rd.l2_hit_this_tile_e offcore_response.partial_writes.l2_hit_this_tile_e offcore_response.partial_writes.l2_hit_this_tile_s offcore_response.any_rfo.l2_hit_this_tile_s offcore_response.pf_l2_rfo.l2_hit_this_tile_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800400002 offcore_response.pf_l1_data_rd.l2_hit_far_tile offcore_response.any_request.l2_hit_far_tile Counts any Read request that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode Counts all instruction fetches that hit the instruction cache offcore_response.any_read.ddr_far offcore_response.any_rfo.mcdram_near offcore_response.pf_l1_data_rd.ddr_near umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080802000 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800004 Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from MCDRAM (local and far) offcore_response.partial_reads.mcdram Counts Software Prefetches that accounts for responses from DDR (local and far) uops_retired.scalar_simd umask=0x40,period=200003,event=0xc2 This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter This event counts every cycle when a data (D) page walk or instruction (I) page walk is in progress umask=0x8,period=2000000,event=0x51 umask=0x2,period=2000000,event=0x43 L1D hardware prefetch misses All L1 writebacks to L2 L1 writebacks to L2 in S state umask=0x4,period=100000,event=0xf1 l2_lines_out.any l2_lines_out.prefetch_dirty L2 requests l2_write.lock.i_state umask=0x1,period=2000000,event=0xcb umask=0x10,period=50000,event=0xb,ldlat=0x4 Memory instructions retired above 8192 clocks (Precise Event) umask=0x1,period=100000,event=0xb7,offcore_rsp=0x844 Offcore requests satisfied by the LLC or local DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1033 Offcore data reads, RFO's and prefetches that HIT in a remote cache Offcore demand data requests satisfied by the LLC and not found in a sibling core Offcore demand data reads satisfied by any cache or DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1001 Offcore demand code reads satisfied by any cache or DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0x180 Offcore other requests satisfied by the LLC and not found in a sibling core Offcore prefetch data requests satisfied by any cache or DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF40 All offcore prefetch code reads umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1040 offcore_response.pf_rfo.io_csr_mmio umask=0x1,period=100000,event=0xb7,offcore_rsp=0x120 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x420 offcore_response.pf_rfo.local_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4720 Offcore prefetch requests satisfied by the LLC and HIT in a sibling core umask=0x4,period=200000,event=0x12 128 bit SIMD integer shuffle/move operations SIMD integer 64 bit arithmetic operations umask=0x1,period=100000,event=0xb7,offcore_rsp=0x6022 umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF803 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4010 Offcore prefetch code reads that missed the LLC offcore_response.prefetch.local_dram Early Branch Prediciton Unit clears br_inst_exec.indirect_non_call br_inst_exec.near_calls Cycles when thread is not halted (programmable counter) Instructions retired (fixed counter) resource_stalls.rs_full uops_executed.core_active_cycles_no_port5 Total cycles using precise uop retired event (Precise Event) Retired store instructions that miss the STLB Supports address when precise All retired store instructions. (Precise Event) Supports address when precise Retired load instructions missed L2 cache as data sources Supports address when precise (Precise event) mem_load_l3_hit_retired.xsnp_hitm l2_lines_out.silent l2_lines_out.non_silent Counts the number of cache line split locks sent to the uncore umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC01C8000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00401C8000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100108000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00801C0004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100080004 offcore_response.demand_rfo.l3_hit_m.snoop_not_needed offcore_response.demand_data_rd.l3_hit_s.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200100001 offcore_response.demand_data_rd.l3_hit_e.snoop_none Cycles where a code fetch is stalled due to L1 instruction cache miss Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall (Precise event) umask=0x1,period=100007,event=0xc6,frontend=0x402006 Number of times an RTM execution aborted due to uncommon conditions Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency (Must be precise) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000040001 Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS) exe_activity.2_ports_util inv=1,umask=0x2,period=2000003,cmask=10,event=0xc2 Counts completed page walks (4K page size) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB. The page walk can end with or without a fault This event counts the number of retire stores that experienced cache line boundary splits rehabq.sta_full All Stores Counts any rfo reads (demand & prefetch) that miss L2 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400008008 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680000080 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680000008 CALL counts the number of near CALL branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) The NO_ALLOC_CYCLES.ALL event counts the number of cycles when the front-end does not provide any instructions to be allocated for any reason. This event indicates the cycles where an allocation stalls occurs, and no UOPS are allocated in that cycle umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0120 Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0020 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0020 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1f80400010 REQUEST = ANY_DATA read and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = ANY IFETCH and RESPONSE = ANY_LOCATION REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HITM REQUEST = ANY_REQUEST and RESPONSE = LOCAL_CACHE offcore_response.demand_data.all_local_dram_and_remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f04 REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT umask=0x1,period=100000,event=0xb7,offcore_rsp=0xff02 REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT REQUEST = PF_RFO and RESPONSE = ANY_CACHE_DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0xf822 REQUEST = DATA_IN and RESPONSE = ANY_DRAM AND REMOTE_FWD offcore_response.pf_ifetch.any_dram_and_remote_fwd REQUEST = PF_RFO and RESPONSE = OTHER_LOCAL_DRAM offcore_response.pf_l2_data_rd.l3_hit.hitm_other_core umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0400 TBD have any response type umask=0x10,cmask=1,period=2000003,event=0x60 offcore_response.pf_l2_rfo.l3_miss.any_snoop offcore_response.pf_l2_rfo.l3_miss.remote_hit_forward TBD TBD Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly umask=0xF,event=0x4 Counts the number of entries in the Read Pending Queue (RPQ) at each cycle. This can then be used to calculate both the average occupancy of the queue (in conjunction with the number of cycles not empty) and the average latency in the queue (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate from the RPQ after the CAS command has been issued to memory Uncore cache clock ticks. Unit: uncore_cha Counts when a RFO (the Read for Ownership issued before a write) request hit a cacheline in the S (Shared) state fc_mask=0x07,ch_mask=0x02,umask=0x04,event=0xc0 unc_iio_data_req_by_cpu.mem_write.part1 Write request of 4 bytes made to IIO Part2 by the CPU . Unit: uncore_iio unc_iio_txn_req_by_cpu.mem_write.part2 Counts every write request of up to a 64 byte transaction of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_m2m_direct2core_not_taken_dirstate unc_m2m_direct2core_txn_override unc_upi_rxl_bypassed.slot1 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040080 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100001 offcore_response.demand_code_rd.l3_hit_f.no_snoop_needed This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP Retired load instructions whose data sources was forwarded from a remote cache Supports address when precise offcore_response.other.l3_hit_s.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020122 This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100002 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400208000 offcore_response.pf_l3_data_rd.supplier_none.hitm_other_core This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD This event is deprecated. Refer to new event OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100002 offcore_response.all_pf_rfo.l3_hit_s.snoop_miss This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.ANY_RESPONSE This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED offcore_response.pf_l2_rfo.l3_hit_e.any_snoop offcore_response.all_pf_data_rd.pmm_hit_local_pmm.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400490 offcore_response.pf_l1d_and_sw.pmm_hit_local_pmm.any_snoop period=200003,umask=0x38,event=0x24 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE offcore_response.all_reads.supplier_none.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080028000 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS offcore_response.pf_l3_rfo.l3_hit_f.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020100 offcore_response.all_pf_data_rd.l3_hit_m.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED offcore_response.pf_l3_rfo.l3_hit_e.hit_other_core_no_fwd offcore_response.all_pf_data_rd.l3_hit_m.no_snoop_needed offcore_response.other.l3_hit_s.hitm_other_core This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.SNOOP_MISS This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l2_data_rd.l3_hit_f.hitm_other_core offcore_response.demand_data_rd.pmm_hit_local_pmm.snoop_none offcore_response.all_data_rd.l3_hit_m.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040491 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100028000 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080004 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0120 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100100 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0491 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_MISS offcore_response.all_pf_rfo.l3_hit_s.no_snoop_needed period=100007,umask=0x1,event=0xd3 offcore_response.demand_code_rd.l3_hit_m.hit_other_core_no_fwd offcore_response.all_pf_rfo.pmm_hit_local_pmm.snoop_none offcore_response.pf_l2_rfo.l3_hit_e.hit_other_core_fwd offcore_response.pf_l2_data_rd.l3_hit_s.snoop_miss offcore_response.demand_rfo.supplier_none.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD offcore_response.demand_data_rd.supplier_none.hitm_other_core This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD offcore_response.all_pf_data_rd.l3_hit_e.snoop_miss This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE offcore_response.pf_l3_data_rd.supplier_none.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80208000 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100080 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400491 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800048000 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.SNOOP_HIT_WITH_FWD period=100007,umask=0x1,event=0xc6,frontend=0x13 Retired Instructions who experienced decode stream buffer (DSB - the decoded instruction-cache) miss (Precise event) period=100007,umask=0x1,event=0xc6,frontend=0x15 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10040007F7 Counts all demand data writes (RFOs) DEMAND_RFO & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD ocr.pf_l2_rfo.l3_miss.hit_other_core_no_fwd offcore_response.all_data_rd.l3_miss.no_snoop_needed This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD offcore_response.all_rfo.l3_miss_local_dram.hit_other_core_no_fwd ocr.all_pf_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000001 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD ALL_PF_RFO & L3_MISS_LOCAL_DRAM & ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000490 ocr.all_pf_data_rd.l3_miss_local_dram.hit_other_core_fwd ALL_PF_RFO & L3_MISS & HIT_OTHER_CORE_NO_FWD Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS_LOCAL_DRAM & ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000002 ocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.snoop_none This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.REMOTE_HITM period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000100 offcore_response.demand_rfo.l3_miss_remote_hop1_dram.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010008000 cmask=1,period=2000003,umask=0x10,event=0x60 Counts demand data reads DEMAND_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000001 offcore_response.other.l3_miss_remote_hop1_dram.no_snoop_needed ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.snoop_none ocr.all_data_rd.l3_miss_remote_hop1_dram.snoop_none ocr.all_pf_data_rd.l3_miss_local_dram.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C008000 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000491 ALL_PF_RFO & L3_MISS_REMOTE_HOP1_DRAM & SNOOP_NONE offcore_response.pf_l1d_and_sw.l3_miss.snoop_none ocr.demand_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed ocr.all_data_rd.l3_miss_remote_hop1_dram.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800400 Counts demand data reads DEMAND_DATA_RD & L3_MISS & REMOTE_HITM This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000122 This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD ocr.all_data_rd.l3_miss.no_snoop_needed This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD ocr.all_pf_rfo.l3_miss_local_dram.snoop_none offcore_response.demand_data_rd.l3_miss.hit_other_core_no_fwd offcore_response.demand_rfo.l3_miss_local_dram.no_snoop_needed This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED ocr.all_data_rd.l3_miss.remote_hit_forward Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_FWD Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS & HIT_OTHER_CORE_NO_FWD ocr.pf_l2_rfo.l3_hit_f.hit_other_core_no_fwd ocr.pf_l3_data_rd.l3_hit_f.hit_other_core_no_fwd ocr.all_data_rd.pmm_hit_local_pmm.any_snoop ALL_RFO & L3_HIT_M & SNOOP_MISS Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_E & NO_SNOOP_NEEDED Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_F & HIT_OTHER_CORE_NO_FWD Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_F & ANY_SNOOP ocr.pf_l3_data_rd.l3_hit_s.hit_other_core_no_fwd ocr.demand_code_rd.supplier_none.hitm_other_core Counts all demand data writes (RFOs) DEMAND_RFO & SUPPLIER_NONE & HITM_OTHER_CORE ocr.other.supplier_none.snoop_none ocr.pf_l3_data_rd.l3_hit_m.no_snoop_needed Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT & SNOOP_MISS ALL_DATA_RD & ANY_RESPONSE have any response type ocr.all_pf_data_rd.l3_hit_e.hitm_other_core Counts all demand code reads DEMAND_CODE_RD & L3_HIT_S & NO_SNOOP_NEEDED ocr.pf_l1d_and_sw.l3_hit_s.no_snoop_needed ALL_READS & L3_HIT_S & HIT_OTHER_CORE_FWD ocr.demand_code_rd.l3_hit_s.any_snoop ocr.all_pf_rfo.l3_hit_s.no_snoop_needed ocr.all_rfo.supplier_none.hit_other_core_no_fwd ALL_READS & L3_HIT & ANY_SNOOP ALL_PF_DATA_RD & L3_HIT & ANY_SNOOP ocr.pf_l3_data_rd.l3_hit.snoop_miss ocr.all_reads.l3_hit_e.snoop_none period=200003,umask=0x20,event=0x28 Counts all prefetch (that bring data to L2) RFOs hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores ALL_PF_DATA_RD & L3_HIT_F & SNOOP_NONE Counts all demand code reads DEMAND_CODE_RD & L3_HIT_F & HITM_OTHER_CORE ocr.pf_l3_data_rd.l3_hit_f.hit_other_core_fwd Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_M & HIT_OTHER_CORE_FWD ocr.other.l3_hit_m.snoop_none ocr.demand_rfo.l3_hit_m.hit_other_core_no_fwd ALL_RFO & L3_HIT_M & NO_SNOOP_NEEDED ocr.pf_l3_data_rd.supplier_none.snoop_miss ocr.pf_l2_rfo.l3_hit_m.snoop_miss ocr.all_rfo.l3_hit_m.snoop_none ocr.all_pf_data_rd.l3_hit_m.hitm_other_core ALL_PF_RFO & L3_HIT & SNOOP_NONE ocr.other.l3_hit_f.snoop_miss ocr.demand_data_rd.l3_hit_e.hit_other_core_no_fwd ocr.all_rfo.l3_hit_e.hitm_other_core Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_S & ANY_SNOOP ocr.pf_l2_rfo.l3_hit_s.no_snoop_needed ocr.all_data_rd.supplier_none.hitm_other_core ocr.pf_l3_data_rd.l3_hit.hit_other_core_no_fwd ocr.all_rfo.pmm_hit_local_pmm.snoop_not_needed ocr.pf_l3_data_rd.l3_hit_m.any_snoop ocr.all_data_rd.supplier_none.hit_other_core_fwd This event counts not taken branch instructions retired Spec update: SKL091 period=100003,umask=0x1,event=0x4c unc_m_pmm_bandwidth.write Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus fc_mask=0x07,ch_mask=0x08,umask=0x02,event=0xc0 fc_mask=0x07,ch_mask=0x02,umask=0x08,event=0x83 Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part0. Unit: uncore_iio Multi-socket cacheline Directory lookups (cacheline found in A state). Unit: uncore_m2m Counts incoming FLITs (FLow control unITs) whcih bypassed the slot2 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency Speculatively counts the number TSX Aborts due to a data capacity limitation for transactional writes Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path Cycles when divide unit is busy executing divide or square root operations umask=0x80,period=2000003,event=0xa6 uops_executed.cycles_ge_1 All branch instructions retired (Precise event) umask=0x80,period=100003,event=0xc5 Page walks completed due to a demand data load to a 4K page Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle Cycles when at least one PMH is busy with a page walk for a demand load Counts memory requests originating from the core that reference a cache line in the last level cache. If the platform has an L3 cache, last level cache is the L3, otherwise it is the L2 Counts the number of load uops retired that hit in the level 2 cache Supports address when precise (Precise event) Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time. This event is not affected by core frequency changes and at a fixed frequency. This event uses fixed counter 2 Counts the number of branch instructions retired for all branch types (Precise event) Counts cycles the floating point divider or integer divider or both are busy. Does not imply a stall waiting for either divider DRAM Precharge commands. : Precharge due to page table. Unit: uncore_imc unc_cha_tor_inserts.ia_miss_crd TOR Inserts; Data read opt from local IA that misses in the snoop filter umask=0xC807FE01,event=0x35 unc_i_clockticks l3_comb_clstr_state.request_miss event=0xc1 The number of branch instructions retired, of any type, that were not correctly predicted. This includes those for which prediction is not attempted (far control transfers, exceptions and interrupts) ex_ret_brn_ind_misp ex_ret_cond df_ccm_reqa.node0.wrsizedfullnc df_ccm_reqa.node5.wrsized Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullzero df_ccm_reqa.node2.rdsizednc umask=0x87,event=0x8b df_ccm_reqa.node7.specdramrd umask=0x24,event=0x8b umask=0xCD,event=0x8c umask=0x2B,event=0x8c umask=0xEA,event=0x8c df_ccm_reqb.node1.wrsizednc df_ccm_reqb.node2.wrsizednc umask=0xC4,event=0x8c Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) masterabort df_ioms_reqa.node2.masterabort umask=0x6B,event=0x108 umask=0x2A,event=0x108 Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anydramtransaction umask=0xA8,event=0x108 df_ioms_reqa.node6.anyatomic umask=0x8E,event=0x109 df_ioms_reqb.node1.anyiotransaction df_ioms_reqb.node6.anyiotransaction Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanyatomic umask=0xCB,event=0x109 df_ioms_reqb.node3.ioanynon-postedwrsized<32b umask=0xE7,event=0x109 umask=0x26,event=0x109 umask=0x23,event=0x109 df_ioms_reqb.node3.ioanypostedwrsized<32 df_ioms_reqb.node6.ioanypostedwrsized<32 df_ioms_reqb.node3.ioanyrdsized df_ioms_reqb.node5.iolargeread umask=0xf,event=0 Total number of fp uOps on pipe 1 This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Double precision add/subtract FLOPS fp_retired_ser_ops.x87_ctrl_ret The number of serializing Ops retired. x87 bottom-executing uOps retired L3 Cache Performance Monitor Counters L3 Cache Accesses l3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x02,event=0x1 l3_request_g1.t4.s2.wrsizednc l3_request_g1.t1.s3.wrsizednc l3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x04,event=0x1 l3_request_g1.t4.s1.rdsizednc l3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x20,event=0x1 l3_request_g1.t1.s2.rdsizednc l3_request_g1.t3.s2.rdsizednc l3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x40,event=0x1 l3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x40,event=0x1 l3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x40,event=0x1 l3_request_g1.t0.s1.caching l3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x01,event=0x3 l3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x02,event=0x3 l3fillvicreq.t0.s1.chgtox l3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x02,event=0x3 l3fillvicreq.t5.s3.chgtox l3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x04,event=0x3 l3fillvicreq.t1.s0.rdblkc_s l3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x08,event=0x3 l3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x08,event=0x3 l3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x08,event=0x3 l3fillvicreq.t4.s2.rdblkx_vic l3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x10,event=0x3 l3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x40,event=0x3 l3fillvicreq.t4.s1.rdblkl l3victimstate.t2.s3.nol3victimline l3victimstate.t2.s2.none_nol3victimline l3victimstate.t7.s2.none_nol3victimline l3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x02,event=0x9 l3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x04,event=0x9 l3victimstate.t3.s3.f_s l3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x08,event=0x9 l3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x08,event=0x9 l3victimstate.t7.s2.o l3victimstate.t0.s2.e_fe l3victimstate.t2.s2.e_fe l3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x20,event=0x9 l3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x20,event=0x9 l3victimstate.t7.s0.d l3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x40,event=0x9 l3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x40,event=0x9 l3victimstate.t5.s0.od ls_locks.bus_lock Counts the number of loads dispatched to the LS unit. Unit Masks ADDed umask=0x80,event=0x45 Total Page Table Walks IC Type 1 umask=0x1,event=0x46 Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 1 Tokens unavailable The number of instruction fetches that miss in both the L1 and L2 TLBs. Instruction fetches to a 1GB page The number of instruction fetches that miss in both the L1 and L2 TLBs. Instruction fetches to a 2MB page bp_l1_tlb_miss_l2_tlb_miss.if4k umask=0x4,event=0x25 Software Prefetch Data Cache Fills by Data Source. Local L2 hit Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Integer Scheduler miscellaneous resource stall IC_MISS FR_RETIRED_UOPS FR_RETIRED_BRANCHES FR_RETIRED_BRANCHES_MISPREDICTED FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED FR_RETIRED_RESYNCS FR_INTERRUPTS_MASKED_CYCLES FR_NUMBER_OF_BREAKPOINTS_FOR_DR2 L2_CACHE_REFILL PLE_FIFO_OVERFLOW L2D_CACHE_WB_VICTIM LDREX_SPEC VFP_SPEC L1D_CACHE_REFILL_OUTER RETURN_NOTPRED DTLB_ACCESS IFU_IDU_MISS_PRED_UPSTREAM_CYCLES LOAD_STORE_REPLAYS EJTAG_INSN_TRIGGERS WBUF BFILL IOBDMA LOAD_MISS_ALIAS L1_DATA_LOAD_HIT BTIC_MISS DTLB_HW_SEARCH_CYCLES FP_STORE_DOUBLE_COMPLETES_IN_LSU BUS_RETRY_DUE_TO_INTERVENTION_ORDERING GROUP_DISPATCH FXU_LONG_INSTR_COMPLETION_STALL ERAT_INSTR_MISS BRANCH_TAKEN TLB_DATA_MISS TLB_INSTR_MISS CYCLES_MU_SCHED_STALLED LOAD_MISS_LDQ_FULL STORE_TRANSLATE_WHEN_QUEUE_FULL LV2_VS STASH_REQUESTS_L1 DVT5_DETECTED branches SYSTEM PPC7450 INTEL_COREI7 desc: %s
l3_thread_mask {"type": "sysexit" {"type": "map_in" Rough Estimation of fraction of fetched lines bytes that were likely consumed by program instructions Actual Average Latency for L1 data-cache miss demand loads TLB l2_rqsts.rfo_miss l2_rqsts.all_demand_miss All requests that miss L2 cache Demand Data Read requests Core-originated cacheable demand requests that refer to L3 Offcore outstanding Demand Data Read transactions in uncore queue Spec update: BDM76 offcore_requests_outstanding.cycles_with_demand_data_rd Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore Spec update: BDM76 This event counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS Spec update: BDM76 umask=0x82,period=2000003,event=0xd0 l2_trans.rfo l2_trans.code_rd umask=0x10,period=200003,event=0xf0 umask=0x40,period=200003,event=0xf0 This event counts the number of L2 cache lines in the Shared state filling the L2. Counting does not cover rejects fp_assist.x87_input umask=0x18,cmask=1,period=2000003,event=0x79 hle_retired.aborted_misc4 rtm_retired.aborted_misc2 umask=0x1,period=20011,event=0xcd,ldlat=0x10 umask=0x1,period=2003,event=0xcd,ldlat=0x40 event=0x3c,any=1 cpu_clk_unhalted.ref_tsc ld_blocks.store_forward False dependencies in MOB due to partial compare umask=0x3,any=1,cmask=1,period=2000003,event=0xd Cycles when divider is busy executing divide operations rs_events.empty_end Not taken speculative and retired mispredicted macro conditional branches This event counts not taken speculative and retired mispredicted macro conditional branch instructions This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0 umask=0x8,period=2000003,event=0xa1 umask=0x40,period=2000003,event=0xa1 umask=0x80,any=1,period=2000003,event=0xa1 Cycles stalled due to no store buffers available. (not including draining form sync) uops_executed.core_cycles_ge_2 Cycles without actually retired uops This event counts cycles without actually retired uops This event counts far branch instructions retired Spec update: BDW98 event=0 llc_misses.mmio_write llc_misses.pcie_write unc_h_requests.reads umask=0x40,event=0x21 unc_m_power_critical_throttle_cycles (unc_p_power_state_occupancy.cores_c3 / unc_p_clockticks) * 100. (unc_p_prochot_external_cycles / unc_p_clockticks) * 100. unc_p_freq_max_limit_thermal_cycles Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K) Spec update: BDM69 dtlb_store_misses.walk_completed_4k umask=0x12,period=2000003,event=0xbc idq_uops_not_delivered.core / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) ))) BrMispredicts_SMT Average external Memory Bandwidth Use for reads and writes [GB / sec] 64 * ( arb@event\=0x81\,umask\=0x1@ + arb@event\=0x84\,umask\=0x1@ ) / 1000000 / duration_time / 1000 Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0001 offcore_response.demand_rfo.l3_hit.any_snoop offcore_response.corewb.supplier_none.snoop_miss offcore_response.corewb.l3_hit.any_snoop offcore_response.pf_l3_data_rd.supplier_none.any_snoop Counts all prefetch (that bring data to LLC only) RFOs have any response type offcore_response.pf_l3_code_rd.supplier_none.snoop_not_needed offcore_response.all_pf_rfo.l3_hit.snoop_none offcore_response.all_rfo.supplier_none.snoop_hit_no_fwd This is a precise version (that is, uses PEBS) of the event that counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable Spec update: BDM30 Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. (RSQRT for single precision?) Randomly selected loads with latency value being above 64 Spec update: BDM100, BDM35 (Must be precise) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020001 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000002 offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000122 umask=0x5,period=2000003,cmask=5,event=0xa3 unc_cbo_xsnp_response.miss_eviction umask=0x81,event=0x22 umask=0x81,event=0x34 L3 Lookup read request that access cache and found line in I-state umask=0x88,event=0x34 umask=0x86,event=0x34 Unit: uncore_cbox L3 Lookup write request that access cache and found line in E or S-state uncore_ncu This event counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required Supports address when precise. Spec update: BDM100 (Precise event) This event counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache Supports address when precise. Spec update: BDM100 (Precise event) Taken branch instructions retired (Precise event) umask=0x50,period=200000,event=0x26 umask=0x71,period=200000,event=0x29 l2_ld.self.demand.mesi umask=0x4f,period=200000,event=0x29 l2_lock.self.i_state l1d_cache.repl Modified cache lines allocated in the L1 data cache fp_assist.s simd_uop_type_exec.unpack.s umask=0x20,period=200000,event=0x9 Outstanding cacheable data read bus requests duration umask=0x40,period=200000,event=0x6b umask=0x0,period=200000,event=0x7a umask=0x1,period=2000000,event=0x88 umask=0x4,period=2000000,event=0x88 Retired mispredicted branch instructions (precise event) (Precise event) umask=0x1,period=200000,event=0xc Counts cycles that fetch is stalled due to an outstanding ICache miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ICache miss. Note: this event is not the same as the total number of cycles spent retrieving instruction cache lines from the memory hierarchy Counts the number of memory uops retired that is either a loads or a store or both Supports address when precise (Must be precise) mem_load_uops_retired.wcb_hit Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l1_data_rd.l2_miss.hitm_other_core umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200002000 Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000041000 offcore_response.corewb.l2_hit offcore_response.demand_rfo.l2_miss.any umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400000002 umask=0x1,period=200003,event=0xe7 Store uops that split a page (Precise event capable) (Must be precise) Counts machine clears due to memory ordering issues. This occurs when a snoop request happens and the machine is uncertain if memory ordering will be preserved as another core is in the process of modifying the data umask=0x0,period=200003,event=0x86 Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The event continues counting during hardware interrupts, traps, and inside interrupt handlers. This is an architectural performance event. This event uses a (_P)rogrammable general purpose performance counter. *This event is Precise Event capable: The EventingRIP field in the PEBS record is precise to the address of the instruction which caused the event. Note: Because PEBS records can be collected only on IA32_PMC0, only one event can use the PEBS facility at a time (Must be precise) Counts retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired, including both when the branch was taken and when it was not taken (Must be precise) umask=0xfe,period=200003,event=0xc5 umask=0x0,period=2000003,event=0xcd Cycles a divider is busy Cycles the integer divide unit is busy Counts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) for a linear address of an instruction fetch. It counts when new translation are filled into the ITLB. The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLB Counts the number of writeback transactions caused by L1 or L2 cache evictions outstanding, per cycle, from the time of the L2 miss to when any response is received Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes hit the L2 cache offcore_response.any_data_rd.any_response Counts data reads (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Page walk completed due to a demand data store to a 4K page Page walk completed due to a demand data store to a 1GB page offcore_response.all_data_rd.l3_hit.hitm_other_core Number of transitions from legacy SSE to AVX-256 when penalty applicable Spec update: HSD56, HSM57 (Precise event) output - Numeric Overflow, Numeric Underflow, Inexact Result (Precise event) umask=0x1,period=100003,event=0xcd,ldlat=0x20 miss the L3 and the data is returned from local dram Counts all prefetch (that bring data to LLC only) code reads miss in the L3 False dependencies in MOB due to partial compare on address Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K. This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline which can have a performance impact FP operations retired. X87 FP operations that have no exceptions: Counts also flows that have several X87 or flows that use X87 uops in the exception handling (Precise event) Unit: uncore_cbox L3 Lookup write request that access cache and found line in I-state L3 Lookup external snoop request that access cache and found line in E or S-state Store misses in all DTLB levels that cause page walks ITLB misses that hit STLB (2M) Number of DTLB page walker loads from memory Spec update: HSD25 page_walker_loads.ept_dtlb_l2 umask=0x82,period=2000003,event=0xbc Retired load uops with L2 cache hits as data sources Supports address when precise. Spec update: HSD76, HSD29, HSM30 (Precise event) umask=0x20,period=100003,event=0xd3 Number of transitions from SSE to AVX-256 when penalty applicable Spec update: HSD56, HSM57 Retired load uops that split across a cacheline boundary. (Precise Event) l2_lines_out.dirty_all umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0244 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0091 Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores umask=0x20,period=2000003,event=0x10 Cycles per thread when uops are dispatched to port 0 A snoop invalidates a non-modified line in some processor core Unit: uncore_arb Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC umask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0090 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c03f7 offcore_response.other.portio_mmio_uc offcore_response.pf_llc_data_rd.llc_hit.snoop_miss umask=0x1,event=0x35,filter_opc=0x1e4 unc_q_txl_flits_g0.non_data Not rejected writebacks from L1D to L2 cache lines in S state umask=0x1,period=100003,event=0xb7,offcore_rsp=0x187FC20077 umask=0x1,period=2000003,event=0x17 umask=0x40,period=2000003,event=0xd umask=0x2,period=100007,event=0xc5 This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceeding smaller uncompleted store. See the table of not supported store forwards in the Intel? 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued inv=1,umask=0x1,edge=1,period=2000003,cmask=1,event=0x5e Counts any request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state Counts Software Prefetches that accounts for any response Counts UC code reads (valid only for Outstanding response type) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state Counts L2 code HW prefetches that accounts for any response offcore_response.demand_code_rd.l2_hit_near_tile_m Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in M state umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002002000 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002003091 Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses which hit its own tile's L2 with data in E state offcore_response.pf_l2_rfo.l2_hit_this_tile_s umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008003091 offcore_response.demand_code_rd.l2_hit_near_tile Counts any Prefetch requests that accounts for data responses from DRAM Local Counts Demand code reads and prefetch code read requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far Counts Demand cacheable data write requests that accounts for data responses from DRAM Far Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101003091 offcore_response.any_request.ddr_far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100401000 offcore_response.demand_rfo.mcdram_far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400002 Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from MCDRAM (local and far) Counts Demand cacheable data write requests that accounts for responses from MCDRAM (local and far) umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180600044 offcore_response.any_data_rd.ddr Counts the number of times the front end resteers for RET branches as a result of another branch handling mechanism in the front end Counts the number of occurences a retired store that is a cache line split. Each split should be counted only once umask=0x40,period=200003,event=0x3 Counts the number of mispredicted near relative CALL branch instructions retired (Precise event) Counts the total number of core cycles for all the page walks. The cycles for page walks started in speculative path will also be included L1 data cache load lock hits L2 data prefetches in E state umask=0xaa,period=200000,event=0x24 l2_transactions.l1d_wb All demand L2 lock RFOs that hit the cache umask=0xf0,period=100000,event=0x27 umask=0xe,period=100000,event=0x27 Offcore data reads satisfied by a remote cache or remote DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F44 offcore_response.any_ifetch.any_location offcore_response.any_ifetch.io_csr_mmio Offcore code reads that HIT in a remote cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4FF umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7FF Offcore RFO requests satisfied by the LLC or local DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F08 offcore_response.corewb.remote_cache_hitm umask=0x1,period=100000,event=0xb7,offcore_rsp=0x8077 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x477 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F33 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x433 offcore_response.demand_data_rd.io_csr_mmio umask=0x1,period=100000,event=0xb7,offcore_rsp=0x8001 Offcore demand data reads satisfied by the LLC Offcore demand data reads that HITM in a remote cache offcore_response.demand_ifetch.llc_hit_other_core_hitm umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1004 All offcore demand RFO requests umask=0x1,period=100000,event=0xb7,offcore_rsp=0x802 offcore_response.other.any_location offcore_response.other.remote_cache Offcore prefetch code reads satisfied by a remote cache or remote DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0x8020 Offcore prefetch requests that HIT in a remote cache SSE2 integer Uops fp_mmx_trans.any 128 bit SIMD integer multiply operations simd_int_64.packed_arith Macro-fused instructions decoded Offcore data reads satisfied by the local DRAM offcore_response.any_request.local_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2022 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2003 umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF830 umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF840 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4070 Offcore prefetch requests satisfied by a remote DRAM Segment rename stall cycles br_inst_exec.return_near umask=0x4,period=200000,event=0xc4 inv=1,umask=0x1,period=2000000,cmask=16,event=0xc0 Resource related stall cycles uop_unfusion uops_executed.port4_core Fused Uops issued umask=0x1,period=200000,event=0x49 Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore Any memory transaction that reached the SQ l2_lines_out.useless_hwpf offcore_response.other.l3_hit_s.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400088000 offcore_response.other.l3_hit_m.spl_hit offcore_response.demand_code_rd.l4_hit_local_l4.snoop_hit_no_fwd offcore_response.demand_code_rd.l3_hit_e.snoop_none offcore_response.demand_code_rd.l3_hit_m.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00801C0002 offcore_response.demand_rfo.l3_hit_s.snoop_miss offcore_response.demand_rfo.l3_hit_e.snoop_hit_no_fwd offcore_response.demand_rfo.supplier_none.snoop_hit_no_fwd offcore_response.demand_data_rd.l4_hit_local_l4.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100100001 offcore_response.demand_data_rd.l3_hit_e.snoop_hitm Cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity icache_64b.iftag_hit Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity Counts the number of machine clears due to memory order conflicts Spec update: SKL089 rtm_retired.aborted_memtype offcore_response.demand_code_rd.l4_hit_local_l4.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC400002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000002 offcore_response.demand_data_rd.l3_hit_s.snoop_non_dram umask=0x2,period=400009,event=0xc5 IpFarBranch Store address buffer full rehabq.any_st Countsof demand RFO requests to write to partial cache lines that miss L2 Counts writeback (modified to exclusive) that miss L2 with no details on snoop-related information The BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end. The BACLEARS.RETURN event counts the number of RETURN baclears I-side page-walks Retired store uops that split across a cacheline boundary. (Precise Event - PEBS) (Precise event) All retired store uops. (Precise Event - PEBS) (Precise event) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0244 offcore_response.all_pf_rfo.llc_hit.any_response offcore_response.pf_l2_rfo.llc_hit.hit_other_core_no_fwd offcore_response.pf_l2_rfo.llc_miss.dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400020 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1f80400200 Offcore demand data read requests umask=0x2,period=2000000,cmask=1,event=0x60 umask=0x1,period=100000,event=0xb7,offcore_rsp=0xff11 offcore_response.data_ifetch.all_local_dram_and_remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5077 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5033 offcore_response.demand_data_rd.local_dram_and_remote_cache_hit REQUEST = DEMAND_IFETCH and RESPONSE = REMOTE_CACHE_HITM umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f02 REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HIT umask=0x1,period=100000,event=0xb7,offcore_rsp=0xff50 REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HIT REQUEST = PF_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT offcore_response.prefetch.local_dram_and_remote_cache_hit offcore_response.any_data.other_local_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0xf844 offcore_response.any_request.any_dram_and_remote_fwd REQUEST = DEMAND_DATA and RESPONSE = OTHER_LOCAL_DRAM REQUEST = DEMAND_IFETCH and RESPONSE = OTHER_LOCAL_DRAM REQUEST = PF_DATA and RESPONSE = ANY_LLC_MISS Extended Page Table walk cycles umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2710 offcore_response.pf_l2_rfo.l3_hit.no_snoop_needed Counts all prefetch (that bring data to LLC only) RFOs TBD TBD offcore_response.all_pf_rfo.l3_hit.no_snoop_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0491 offcore_response.demand_code_rd.l3_hit.snoop_hit_with_fwd offcore_response.all_rfo.l3_hit.snoop_hit_with_fwd offcore_response.demand_rfo.l3_miss.snoop_miss_or_no_fwd offcore_response.pf_l3_data_rd.l3_miss.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBC000120 umask=0x7,period=200003,event=0x28 Core cycles the out-of-order engine was throttled due to a pending power level request umask=0x1,period=2000003,event=0xef inv=1,umask=0x2,cmask=1,period=2000003,event=0xc2 Counts the number of writes requests allocated into the Write Pending Queue (WPQ). The WPQ is used to schedule writes out to the memory controller and to track the requests. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC (Memory Controller). The write requests deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC unc_cha_requests.reads Counts transactions that looked into the multi-socket cacheline Directory state, and sent one or more snoops, because the Directory indicated it was needed umask=0x08,event=0x39 umask=0x01,event=0x5c unc_iio_data_req_by_cpu.mem_read.part3 fc_mask=0x07,ch_mask=0x02,umask=0x04,event=0xc1 unc_iio_txn_req_by_cpu.mem_write.part1 fc_mask=0x07,ch_mask=0x01,umask=0x01,event=0x84 event=0x23 umask=0x2,event=0x2d unc_upi_rxl_bypassed.slot0 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200020 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040020 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80028000 offcore_response.pf_l1d_and_sw.supplier_none.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100020 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080400 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02001007F7 offcore_response.all_reads.l3_hit.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080001 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0400 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040020 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080080 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020100 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020010 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010400 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080490 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP offcore_response.other.supplier_none.no_snoop_needed offcore_response.pf_l3_data_rd.l3_hit_f.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100004 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100100 offcore_response.pf_l3_data_rd.pmm_hit_local_pmm.any_snoop offcore_response.other.supplier_none.hit_other_core_fwd offcore_response.pf_l1d_and_sw.supplier_none.snoop_none This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS offcore_response.demand_rfo.supplier_none.hit_other_core_fwd offcore_response.all_data_rd.l3_hit_s.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020001 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISS This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP offcore_response.all_pf_rfo.l3_hit.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.SNOOP_NONE This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.ANY_SNOOP period=100003,umask=0x2,event=0xd1 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0020 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE offcore_response.all_rfo.l3_hit_s.any_snoop period=2000003,umask=0x1,event=0x9c cmask=1,period=2000003,umask=0x24,event=0x79 ocr.all_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000120 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000020 ocr.all_rfo.l3_miss.hit_other_core_fwd ocr.pf_l2_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd ALL_PF_DATA_RD & L3_MISS & REMOTE_HIT_FORWARD This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000002 ALL_READS & L3_MISS & SNOOP_MISS ALL_READS & L3_MISS_LOCAL_DRAM & HITM_OTHER_CORE ocr.demand_rfo.l3_miss_remote_hop1_dram.any_snoop Counts any other requests OTHER & L3_MISS_LOCAL_DRAM & HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD ocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000120 ocr.pf_l3_rfo.l3_miss.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC007F7 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000100 Counts any other requests OTHER & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD period=2000003,umask=0x10,event=0x54 Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS & REMOTE_HITM Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS & HIT_OTHER_CORE_FWD ocr.all_reads.l3_miss.remote_hitm offcore_response.demand_code_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd ocr.all_pf_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE period=2000003,umask=0x8,event=0xc8 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD ocr.demand_data_rd.l3_miss_remote_hop1_dram.hitm_other_core offcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.hitm_other_core ocr.all_data_rd.l3_miss_remote_hop1_dram.snoop_miss offcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000001 offcore_response.all_reads.l3_miss_remote_hop1_dram.any_snoop offcore_response.pf_l1d_and_sw.l3_miss_local_dram.snoop_none This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED ALL_PF_RFO & L3_HIT_E & HITM_OTHER_CORE ALL_READS & PMM_HIT_LOCAL_PMM & ANY_SNOOP ALL_RFO & L3_HIT_S & HIT_OTHER_CORE_NO_FWD ocr.all_data_rd.supplier_none.snoop_miss ALL_DATA_RD & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWD ALL_PF_DATA_RD & SUPPLIER_NONE & HIT_OTHER_CORE_FWD Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT & ANY_SNOOP Counts demand data reads DEMAND_DATA_RD & L3_HIT_F & HIT_OTHER_CORE_NO_FWD Counts any other requests OTHER & L3_HIT_E & NO_SNOOP_NEEDED ocr.pf_l3_data_rd.l3_hit_f.any_snoop ocr.all_data_rd.l3_hit_m.snoop_none ocr.all_rfo.l3_hit_e.hit_other_core_no_fwd ALL_RFO & SUPPLIER_NONE & SNOOP_NONE ocr.all_rfo.l3_hit.hit_other_core_no_fwd ALL_READS & L3_HIT_M & SNOOP_MISS Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_E & ANY_SNOOP ALL_PF_DATA_RD & L3_HIT_E & HITM_OTHER_CORE Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_M & HIT_OTHER_CORE_NO_FWD ocr.pf_l1d_and_sw.l3_hit_m.hit_other_core_fwd Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_S & NO_SNOOP_NEEDED Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT & HIT_OTHER_CORE_NO_FWD Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & SUPPLIER_NONE & HITM_OTHER_CORE ocr.pf_l3_data_rd.l3_hit_s.snoop_none ALL_READS & L3_HIT & SNOOP_HIT_WITH_FWD ocr.all_reads.l3_hit.snoop_none ALL_DATA_RD & L3_HIT_M & NO_SNOOP_NEEDED ocr.other.l3_hit_f.hitm_other_core ocr.pf_l1d_and_sw.l3_hit_e.snoop_none ocr.all_reads.l3_hit_m.hit_other_core_no_fwd ALL_READS & L3_HIT_F & SNOOP_NONE ALL_PF_RFO & L3_HIT_S & SNOOP_MISS ALL_PF_RFO & SUPPLIER_NONE & HITM_OTHER_CORE ocr.demand_data_rd.supplier_none.hit_other_core_no_fwd ocr.pf_l3_rfo.l3_hit_m.hit_other_core_fwd period=2000003,umask=0x80,event=0xa1 UNC_M_PMM_BANDWIDTH.TOTAL Counts the total number or DRAM Write CAS commands issued on this channel while in Write-Major-Mode Write Pending Queue Occupancy of all write requests for Intel Optane DC persistent memory umask=0x02,event=0xa5 unc_cha_sf_eviction.m_state Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part2. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus fc_mask=0x07,ch_mask=0x04,umask=0x02,event=0xc0 unc_iio_txn_req_by_cpu.peer_read.part0 fc_mask=0x07,ch_mask=0x04,umask=0x02,event=0x84 Multi-socket cacheline Directory update from/to Any state. Unit: uncore_m2m Read requests to Intel Optane DC persistent memory issued to the iMC from M2M. Unit: uncore_m2m Counts when the M2M (Mesh to Memory) recieves a prefetch request and inserts it into its outstanding prefetch queue. Explanatory Side Note: the prefect queue is made from CAM: Content Addressable Memory AD Ingress (from CMS) Occupancy cmask=1,period=100003,umask=0x10,event=0x49 Counts demand requests that miss L2 cache SW prefetch requests that hit L2 cache Counts Software prefetch requests that hit the L2 cache. This event accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture). This includes high current AVX 512-bit instructions Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists Counts cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall Cycles when RAT does not issue Uops to RS for the thread uops_executed.cycles_ge_4 Page walks completed due to a demand data store to a 2M/4M page Counts the number of unhalted reference clock cycles at TSC frequency. (Fixed event) umask=0x08,event=0x2 unc_cha_tor_inserts.ia_miss_wcilf Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 l2_request_g1.group2 l2_cache_req_stat.ic_fill_miss Retired Instructions Retired Uops The number of taken branches that were retired. This includes all types of architectural control flow changes, including exceptions and interrupts event=0xd3 ex_ret_fus_brnch_inst umask=0x2F,event=0x8b umask=0x4F,event=0x8b umask=0xAD,event=0x8b umask=0x0B,event=0x8b umask=0xCA,event=0x8b df_ccm_reqa.node5.rdvlks df_ccm_reqb.node4.chgtox Data Fabric CCM Performance Monitor Event DF CCM Request Ordered vicblkfull df_ccm_reqb.node7.vicblkfull. df_ccm_reqb.node2.vicblkcln df_ccm_reqb.node2.wrsizedfullncposted umask=0x61,event=0x8c umask=0x4C,event=0x108 df_ioms_reqa.node1.ios_resp umask=0x8A,event=0x108 df_ioms_reqa.node5.flush df_ioms_reqa.node3.anywrsized=64b df_ioms_reqa.node1.anywrsized=32b df_ioms_reqa.node3.anywrsized=32b umask=0xCF,event=0x109 df_ioms_reqb.node7.piesystemmanagement df_ioms_reqb.node1.ioanypostedwrsized=64b umask=0x46,event=0x109 df_ioms_reqb.node1.ioanypostedwrsized=32 umask=0x82,event=0x109 Total number multi-pipe uOps assigned to all pipes This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Double precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes. Number of SSE Move Ops l3_request_g1.t0.s0.wrsizednc l3_request_g1.t1.s2.wrsizednc l3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x02,event=0x1 l3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x04,event=0x1 l3_request_g1.t3.s3.wrsized l3_request_g1.t0.s1.rdsizednc l3_request_g1.t5.s1.rdsizednc l3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x20,event=0x1 l3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x40,event=0x1 l3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x40,event=0x1 l3_request_g1.t6.s3.rdsized l3_request_g1.t4.s1.caching l3fillvicreq.t1.s1.vicblk l3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x01,event=0x3 l3fillvicreq.t7.s3.vicblk l3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x02,event=0x3 l3fillvicreq.t1.s2.chgtox l3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x02,event=0x3 l3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x02,event=0x3 l3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x04,event=0x3 l3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x04,event=0x3 l3fillvicreq.t0.s0.rdblkc_s l3fillvicreq.t4.s0.rdblkc_s l3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x08,event=0x3 l3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x08,event=0x3 l3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x08,event=0x3 l3fillvicreq.t2.s3.rdblkx_vic l3fillvicreq.t0.s3.rdblkx l3fillvicreq.t7.s3.rdblkl_vic l3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x01,event=0x9 l3victimstate.t1.s0.none_nol3victimline l3victimstate.t0.s1.none_nol3victimline l3victimstate.t6.s2.none_nol3victimline l3victimstate.t2.s3.f_s l3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x08,event=0x9 l3victimstate.t3.s2.o l3victimstate.t4.s2.e_fe l3victimstate.t5.s3.m l3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x20,event=0x9 l3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x80,event=0x9 ls_mab_alloc.stores LS MAB allocates by type - loads ls_l1_d_tlb_miss.tlb_reload_32k_l2_hit Number of Ops that are candidates for optimization (have Z-bit either set or pass). This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes umask=0x1,event=0x41 L1 DTLB Miss. DTLB reload to a 1G page that hit in the L2 TLB de_dis_uops_from_decoder.opcache_dispatched Count of dispatched Ops from OpCache DC_ACCESS DC_MISS IC_L1_ITLB_MISS_AND_L2_ITLB_HIT NB_MEMORY_CONTROLLER_DRAM_COMMAND_SLOTS_MISSED NB_MEMORY_CONTROLLER_TURNAROUND CLOCK_CYCLES L2_ACCESS L2_CACHE_NEON_MEM_ACCESS PRED_BRANCH_EXEC_TAKEN INTEGER_CORE_CLOCK_ENABLED DSB_SPEC LL_CACHE_MISS_RD INTEGER_COMPLETED LDQ_LT_QUARTER ICACHE_MISS_STALLS ALU_BUBBLE_CYCLES DCACHE_WRITEBACKS L2_CACHE_WRITEBACKS WBB_FULL_STALLS DSP_INSNS DMLDS VIU2_INSTR_COMPLETED TLBIE_INSTR_COMPLETED VR_ISSUE_QUEUE_DISPATCHES THRESHOLD_TIMEOUT STOP_COMPLETION ERAT_DATA_MISS INSTR_L1_CACHE_FETCHES EXT_INPUT_INTR_PENDING_LATENCY_CYCLES STASH_HITS DVT6_DETECTED P6 LLC_MISS_RHITM RESOURCE_STALLS.ANY BRANCH-INSTRUCTION-RETIRED BRANCH-MISSES-RETIRED HygonGenuine {"type": "pmcallocatedyn" GenuineIntel-6-57 bdwde metrics Pipeline;Ports_Utilization CPU_Utilization ( 1*( fp_arith_inst_retired.scalar_single + fp_arith_inst_retired.scalar_double ) + 2* fp_arith_inst_retired.128b_packed_double + 4*( fp_arith_inst_retired.128b_packed_single + fp_arith_inst_retired.256b_packed_double ) + 8* fp_arith_inst_retired.256b_packed_single ) / 1000000000 / duration_time l2_rqsts.all_code_rd umask=0x50,period=200003,event=0x27 mem_load_uops_l3_hit_retired.xsnp_hit umask=0x10,period=100007,event=0xd3 Retired load uop whose Data Source was: Remote cache HITM (Precise Event) Supports address when precise. Spec update: BDE70 l2_trans.demand_data_rd Transactions accessing L2 pipe umask=0x1,period=100003,event=0xf1 This event counts the number of L2 cache lines in the Exclusive state filling the L2. Counting does not cover rejects Number of X87 assists due to output value Cycles Decode Stream Buffer (DSB) is delivering 4 Uops idq.ms_switches icache.ifdata_stall misalign_mem_ref.stores tx_mem.abort_conflict umask=0x4,period=2000003,event=0x54 Number of times a TSX Abort was triggered due to a non-release/commit store to lock Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region hle_retired.commit Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts) Number of times we entered an RTM region; does not count nested transactions Number of times we entered an RTM region
does not count nested transactions This event counts loads with latency value being above 128 Spec update: BDM100, BDM35 (Must be precise) Core cycles when at least one thread on the physical core is not in halt state Reference cycles when the thread is unhalted (counts at 100 MHz rate) umask=0x1,any=1,period=2000003,event=0x3c Taken speculative and retired macro-conditional branch instructions excluding calls and indirects br_misp_exec.taken_indirect_near_call uops_executed_port.port_0_core uops_executed_port.port_1_core uops_executed_port.port_6_core This event counts resource-related stall cycles. Reasons for stalls can be as follows:
- *any* u-arch structure got full (LB, SB, RS, ROB, BOB, LM, Physical Register Reclaim Table (PRRT), or Physical History Table (PHT) slots)
- *any* u-arch structure got empty (like INT/SIMD FreeLists)
- FPU control word (FPCW), MXCSR
and others. This counts cycles that the pipeline backend blocked uop delivery from the front end This event counts stall cycles caused by absence of eligible entries in the reservation station (RS). This may result from RS overflow, or from RS deallocation because of the RS array Write Port allocation scheme (each RS entry has two write ports instead of four. As a result, empty entries could not be used, although RS is not really full). This counts cycles that the pipeline backend blocked uop delivery from the front end umask=0x2,cmask=2,period=2000003,event=0xa3 uops_retired.total_cycles br_inst_retired.not_taken uncore_cbox LLC prefetch misses for data reads. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox unc_h_snoop_resp.rsp_fwd_wb uncore_imc (unc_m_power_channel_ppd / unc_m_dclockticks) * 100. event=0x43 event=0x80,occ_sel=2 (unc_p_power_state_occupancy.cores_c6 / unc_p_clockticks) * 100. umask=0x4,period=100003,event=0x85 Number of ITLB page walker hits in the L1+FB Spec update: BDM69, BDM98 TopdownL1 Bad_Speculation_SMT Instruction per taken branch ( cpu@itlb_misses.walk_duration\,cmask\=1@ + cpu@dtlb_load_misses.walk_duration\,cmask\=1@ + cpu@dtlb_store_misses.walk_duration\,cmask\=1@ + 7 * ( dtlb_store_misses.walk_completed + dtlb_load_misses.walk_completed + itlb_misses.walk_completed ) ) / cycles This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache Spec update: BDM100. Supports address when precise (Precise event) Counts all demand code reads have any response type umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020004 offcore_response.corewb.supplier_none.snoop_hit_no_fwd offcore_response.corewb.l3_hit.snoop_none offcore_response.pf_l2_code_rd.supplier_none.snoop_none offcore_response.pf_l2_code_rd.supplier_none.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020080 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0200 offcore_response.all_pf_data_rd.l3_hit.snoop_not_needed offcore_response.all_pf_rfo.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010240 offcore_response.all_pf_code_rd.supplier_none.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020240 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0091 offcore_response.all_rfo.supplier_none.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0122 Randomly selected loads with latency value being above 256 Spec update: BDM100, BDM35 (Must be precise) offcore_response.demand_data_rd.l3_miss_local_dram.any_snoop offcore_response.demand_code_rd.l3_miss_local_dram.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000020 offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_hitm offcore_response.pf_l3_rfo.l3_miss_local_dram.any_snoop offcore_response.all_pf_data_rd.l3_miss.snoop_none offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000122 inv=1,umask=0x1,period=2000003,cmask=1,event=0xe umask=0x8,period=2000003,cmask=8,event=0xa3 FP operations retired. X87 FP operations that have no exceptions: (Precise event) Number of cycles using always true condition (uops_ret < 16) applied to PEBS uops retired event (Precise event) This is a precise version (that is, uses PEBS) of the event that counts not taken branch instructions retired umask=0x01,event=0x81 This event counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required Supports address when precise. Spec update: BDM100 (Precise event) Number of times RTM abort was triggered (Precise event) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0604000122 l2_ld.self.any.e_state umask=0x48,period=200000,event=0x29 umask=0x44,period=200000,event=0x2e umask=0x52,period=200000,event=0x2e l1d_cache.st Retired loads that hit the L2 cache (precise event) simd_uop_type_exec.shift.s simd_uop_type_exec.pack.ar simd_inst_retired.vector cycles_icache_mem_stalled.icache_mem_stalled bus_trans_mem.all_agents All bus transactions umask=0x40,period=200000,event=0x7e Divide operations executed umask=0x81,period=2000000,event=0x13 resource_stalls.div_busy Number of I-Side page walks Requests rejected by the XQ dl1.dirty_eviction offcore_response.any_read.l2_miss.any Counts data reads (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module Counts requests to the uncore subsystem that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts requests to the uncore subsystem that hit the L2 cache offcore_response.partial_streaming_stores.l2_miss.snoop_miss_or_no_snoop_needed umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000002000 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010400 Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.corewb.l2_miss.snoop_miss_or_no_snoop_needed umask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600000004 offcore_response.demand_data_rd.l2_miss.snoop_miss_or_no_snoop_needed umask=0x2,period=2000003,event=0 umask=0xfd,period=200003,event=0xc4 br_inst_retired.taken_jcc Retired mispredicted branch instructions (Precise event capable) (Must be precise) umask=0x8,period=200003,event=0xe6 Counts every core cycle when a Data-side (walks due to a data operation) page walk is in progress Counts reads for ownership (RFO) requests generated by L2 prefetcher have any transaction responses from the uncore subsystem Counts reads for ownership (RFO) requests generated by L2 prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000040400 offcore_response.bus_locks.l2_miss.hitm_other_core Counts bus lock and split lock requests outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000008000 Counts requests to the uncore subsystem outstanding, per cycle, from the time of the L2 miss to when any response is received Counts reads for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem Retired mispredicted instructions of near indirect Jmp or near indirect call (Precise event capable) (Must be precise) Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 4K pages. The page walks can end with or without a page fault umask=0x8,period=2000003,event=0x49 Demand Data Read miss L2, no rejects Spec update: HSD78 Demand Data Read requests that hit L2 cache Spec update: HSD78 Offcore outstanding Demand Data Read transactions in uncore queue Spec update: HSD78, HSD62, HSD61 Retired load uops with L2 cache misses as data sources Spec update: HSD29, HSM30. Supports address when precise (Precise event) Retired load uops which data sources were hits in L3 without snoops required Spec update: HSD74, HSD29, HSD25, HSM26, HSM30. Supports address when precise (Precise event) offcore_response.all_reads.l3_hit.hitm_other_core offcore_response.all_rfo.l3_hit.hit_other_core_no_fwd SSE* FP micro-code assist when output value is invalid (Precise event) Counts cycles DSB is delivered at least one uops. Set Cmask = 1 Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled Spec update: HSD135 Counts all prefetch (that bring data to LLC only) data reads miss in the L3 Counts all prefetch (that bring data to L2) RFOs miss in the L3 Counts all demand data writes (RFOs) miss the L3 and the data is returned from local dram offcore_response.demand_data_rd.l3_miss.local_dram offcore_response.demand_data_rd.l3_miss.any_response Counts demand data reads miss in the L3 Cycles per core when uops are executed in port 1 Cycles allocation is stalled due to resource related reason Spec update: HSD135 Number of instructions at retirement Spec update: HSD11, HSD140 umask=0x28,event=0x22 DTLB store misses with low part of linear-to-physical address translation missed Counts the number of Extended Page Table walks from the ITLB that hit in the L1 and FB Retired load uops with L3 cache hits as data sources Supports address when precise. Spec update: HSD74, HSD29, HSD25, HSM26, HSM30 (Precise event) offcore_response.demand_code_rd.llc_miss.any_response umask=0x8,period=200003,event=0x28 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0122 dsb2mite_switches.count (( 1 * ( fp_comp_ops_exe.sse_scalar_single + fp_comp_ops_exe.sse_scalar_double ) + 2 * fp_comp_ops_exe.sse_packed_double + 4 * ( fp_comp_ops_exe.sse_packed_single + simd_fp_256.packed_double ) + 8 * simd_fp_256.packed_single )) / (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )) Number of any page walk that had a miss in LLC Loads with latency value being above 4 (Must be precise) Cycles per thread when load or STA uops are dispatched to port 2 Cycles which a Uop is dispatched on port 5 Unit: uncore_arb Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC Page walk for a large page completed for Demand load umask=0x3,period=100007,event=0xd3 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0200 offcore_response.demand_data_rd.llc_miss.any_dram PCIe allocating writes that miss LLC - DDIO misses. Derived from unc_c_tor_inserts.miss_opcode.ddio_miss. Unit: uncore_cbox LLC misses for PCIe non-snoop writes (full line). Derived from unc_c_tor_inserts.miss_opcode.pcie_write. Unit: uncore_cbox umask=0x1,event=0x35,filter_opc=0x1e5 unc_p_freq_band1_transitions Cycles spent changing Frequency. Unit: uncore_pcu Retired store uops that split across a cacheline boundary (Precise event) This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a modified state, so the line had to be invalidated in that L2 cache and transferred to the requesting L2 Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled Taken speculative and retired mispredicted direct near calls resource_stalls.lb Actually retired uops (Precise event) Performance sensitive flags-merging uops added by Sandy Bridge u-arch Memory controller clock ticks. Used to get percentages of memory controller cycles events. Unit: uncore_imc Counts all the load micro-ops retired offcore_response.any_pf_l2.l2_hit_far_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080070 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000083091 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080400 Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode offcore_response.pf_l2_code_rd.l2_hit_far_tile_m offcore_response.pf_l2_rfo.l2_hit_near_tile_e_f Counts Demand cacheable data writes that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0 Counts any request that accounts for responses which hit its own tile's L2 with data in M state umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008000001 offcore_response.demand_code_rd.l2_hit_this_tile_s umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008000004 offcore_response.any_code_rd.l2_hit_this_tile_f Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode Counts Software Prefetches that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode offcore_response.any_read.l2_hit_far_tile offcore_response.any_code_rd.mcdram_far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400080 offcore_response.demand_code_rd.ddr_far Counts Demand cacheable data writes that accounts for responses from MCDRAM (local and far) offcore_response.pf_l2_code_rd.ddr Counts any Read request that accounts for responses from DDR (local and far) umask=0x1,period=200003,event=0xcb Fixed Counter: Counts the number of unhalted core clock cycles Counts the number of mispredicted far branch instructions retired (Precise event) umask=0x01,event=0x2 Counts the total I-side page walks that are completed l1d_wb_l2.i_state l2_data_rqsts.any l2_data_rqsts.prefetch.i_state l2_lines_in.s_state L2 RFO transactions Instructions retired which contains a store (Precise Event) Retired loads that miss L1D and hit an previously allocated LFB (Precise Event) Retired loads that hit the L2 cache (Precise Event) umask=0x4,period=40000,event=0xcb umask=0x80,period=4000,event=0xf umask=0x10,period=1000,event=0xb,ldlat=0x80 umask=0x10,period=5000,event=0xb,ldlat=0x20 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4711 Offcore code reads satisfied by any cache or DRAM Offcore code reads satisfied by the LLC and HITM in a sibling core umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1FF umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3822 offcore_response.any_rfo.remote_cache_hit Offcore code or data read requests satisfied by the LLC and HITM in a sibling core umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1877 offcore_response.demand_data_rd.any_location All offcore demand code reads umask=0x1,period=100000,event=0xb7,offcore_rsp=0x8004 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x204 Offcore demand code reads satisfied by a remote cache or remote DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F02 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x402 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F30 umask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF30 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x210 Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit fp_comp_ops_exe.sse_fp_packed umask=0x40,period=200000,event=0xfd umask=0x1,period=2000000,event=0x19 Two Uop instructions decoded umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4022 Offcore writebacks to the local DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2010 offcore_response.pf_rfo.local_dram l1i.misses load_dispatch.rs_delayed Thread responded HITE to snoop Thread responded HITM to snoop umask=0x2,period=2000000,event=0xe6 umask=0x7f,period=200000,event=0x88 umask=0x20,period=20000,event=0x88 br_inst_exec.non_calls Retired floating-point operations (Precise Event) Cycles machine clear asserted itlb_flush All retired store instructions Supports address when precise This event is deprecated. Refer to new event L2_LINES_OUT.USELESS_HWPF offcore_response.other.l3_hit_e.snoop_not_needed offcore_response.other.supplier_none.spl_hit offcore_response.demand_code_rd.l3_hit_m.any_snoop offcore_response.demand_rfo.l4_hit_local_l4.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080400001 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040400001 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000100001 frontend_retired.latency_ge_512 umask=0x10,period=2000003,event=0x60 Number of times an HLE execution aborted due to unfriendly events (such as interrupts) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020002 umask=0x2,period=2503,event=0x3c Cycles where the pipeline is stalled due to serializing operations Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty Counts the retirement slots used Counts self-modifying code (SMC) detected, which causes a machine clear Counts page walks of any page size (4K/2M/4M/1G) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB, but the walk need not have completed Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake Loads blocked due to store forward restriction (Precise event) umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680003091 offcore_response.pf_l2_code_rd.l2_miss.hit_other_core_no_fwd Counts demand and DCU prefetch data read that hit in the other module where modified copies were found in other core's L1 cache This event counts the number of load ops retired that had DTLB miss (Precise event) This event counts retired demand loads that missed the last-level (L3) cache. This means that the load is usually satisfied from memory in a client system or possibly from the remote socket in a server. Demand loads are non speculative load uops. (Precise Event - PEBS) (Precise event) offcore_response.all_pf_code_rd.llc_hit.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0240 offcore_response.demand_rfo.llc_hit.snoop_miss Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0040 Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded offcore_response.pf_llc_code_rd.llc_miss.dram offcore_response.pf_ifetch.llc_miss_local.dram offcore_requests_outstanding.demand.rfo_not_empty umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5003 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x850 offcore_response.pf_data_rd.all_local_dram_and_remote_cache_hit REQUEST = PF_DATA_RD and RESPONSE = IO_CSR_MMIO REQUEST = PF_DATA_RD and RESPONSE = LOCAL_CACHE umask=0x1,period=100000,event=0xb7,offcore_rsp=0xff20 REQUEST = PF_IFETCH and RESPONSE = REMOTE_CACHE_HITM REQUEST = ANY RFO and RESPONSE = ANY_LLC_MISS offcore_response.demand_data_rd.any_dram_and_remote_fwd offcore_response.demand_rfo.any_dram_and_remote_fwd umask=0x1,period=100000,event=0xb7,offcore_rsp=0xf840 DTLB miss page walk cycles umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2740 Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared state. A non-threaded event umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0490 offcore_response.pf_l2_rfo.l3_hit.snoop_hit_with_fwd umask=0x40,period=2000003,event=0xc7 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x103FC00004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063FC00490 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063FC00491 core_snoop_response.rsp_shitfse umask=0x8,period=2000003,event=0xef Write Pending Queue Occupancy. Unit: uncore_imc umask=0x21,event=0x35,config1=0x40e33 umask=0x08,event=0x50 Read request for up to a 64 byte transaction is made by the CPU to IIO Part1. Unit: uncore_iio Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus Counts every read request for up to a 64 byte transaction of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_upi_clockticks unc_upi_rxl_flits.non_data umask=0x27,event=0x2 Counts when the Intel Ultra Path Interconnect(UPI) transmits an idle FLIT(80 bit FLow control unITs). Every UPI cycle must be sending either data FLITs, protocol/credit FLITs or idle FLITs offcore_response.pf_l2_data_rd.l3_hit_m.snoop_miss This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_MISS offcore_response.all_reads.l3_hit_e.hit_other_core_fwd period=200003,umask=0x1,event=0xf2 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP cmask=1,period=2000003,umask=0x4,event=0x60 offcore_response.all_pf_rfo.l3_hit_m.snoop_none This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP offcore_response.demand_data_rd.l3_hit_m.hit_other_core_no_fwd offcore_response.all_pf_data_rd.l3_hit_f.hitm_other_core offcore_response.all_pf_rfo.supplier_none.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200001 offcore_response.all_pf_data_rd.l3_hit.hit_other_core_fwd offcore_response.pf_l3_data_rd.supplier_none.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD period=100007,umask=0x20,event=0xd1 This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.SNOOP_NONE This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0491 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100100 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800208000 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400001 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040080 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040122 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020122 offcore_response.all_pf_data_rd.l3_hit_e.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040100 offcore_response.all_pf_data_rd.l3_hit_s.hitm_other_core This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP offcore_response.demand_rfo.l3_hit.hit_other_core_fwd This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100490 This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS offcore_response.all_reads.l3_hit_s.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.SNOOP_NONE period=100007,umask=0x4,event=0xd3 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_MISS offcore_response.all_pf_data_rd.l3_hit_s.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80088000 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080001 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020400 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080120 offcore_response.pf_l1d_and_sw.l3_hit_m.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080400 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0120 offcore_response.demand_code_rd.supplier_none.hitm_other_core This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.SNOOP_MISS offcore_response.all_data_rd.l3_hit_s.no_snoop_needed offcore_response.pf_l2_rfo.supplier_none.hit_other_core_no_fwd offcore_response.all_data_rd.l3_hit_f.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F802007F7 Retired Instructions who experienced Instruction L2 Cache true miss (Precise event) Retired Instructions who experienced iTLB true miss (Precise event) offcore_response.all_pf_data_rd.l3_miss_local_dram.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000010 This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410008000 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00490 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000491 ocr.all_rfo.l3_miss_local_dram.snoop_miss Counts all demand code reads DEMAND_CODE_RD & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000490 ocr.all_pf_rfo.l3_miss.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC008000 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000120 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000100 Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS & HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE offcore_response.demand_data_rd.l3_miss.hitm_other_core ocr.all_pf_rfo.l3_miss.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000020 ocr.all_reads.l3_miss.any_snoop Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS & SNOOP_NONE ocr.demand_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd ocr.all_pf_rfo.l3_miss.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000400 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000001 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000001 offcore_response.other.l3_miss.remote_hitm offcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000490 ocr.other.l3_miss_remote_hop1_dram.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000020 ocr.pf_l2_rfo.l3_miss_local_dram.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000020 ocr.all_pf_rfo.l3_miss.hitm_other_core offcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.no_snoop_needed ocr.pf_l3_data_rd.l3_miss.snoop_miss ocr.demand_data_rd.l3_miss_remote_hop1_dram.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000002 Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS_REMOTE_DRAM & SNOOP_MISS_OR_NO_FWD ALL_PF_DATA_RD & L3_MISS & SNOOP_NONE offcore_response.all_rfo.l3_miss_remote_hop1_dram.snoop_none ocr.all_pf_rfo.l3_miss.remote_hit_forward ALL_DATA_RD & L3_MISS & SNOOP_NONE ALL_DATA_RD & L3_MISS_LOCAL_DRAM & HITM_OTHER_CORE period=2000003,umask=0x80,event=0xc8 This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE Counts all demand code reads DEMAND_CODE_RD & L3_MISS & REMOTE_HITM ocr.pf_l3_rfo.l3_miss_local_dram.snoop_miss This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD ocr.all_pf_rfo.l3_hit_s.hitm_other_core ALL_RFO & L3_HIT_S & NO_SNOOP_NEEDED ocr.pf_l3_data_rd.l3_hit_e.hit_other_core_no_fwd ocr.all_pf_data_rd.l3_hit_s.hit_other_core_fwd ocr.pf_l2_rfo.l3_hit_e.no_snoop_needed Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_M & HIT_OTHER_CORE_NO_FWD ALL_PF_DATA_RD & L3_HIT_F & HITM_OTHER_CORE ocr.demand_data_rd.l3_hit_e.no_snoop_needed ocr.all_reads.l3_hit.snoop_miss ocr.all_pf_data_rd.supplier_none.snoop_miss ocr.other.l3_hit_e.no_snoop_needed ALL_READS & SUPPLIER_NONE & ANY_SNOOP Counts all demand code reads DEMAND_CODE_RD & L3_HIT_M & HIT_OTHER_CORE_NO_FWD Counts all demand code reads DEMAND_CODE_RD & L3_HIT & HIT_OTHER_CORE_FWD ocr.pf_l2_rfo.l3_hit.snoop_miss ocr.other.l3_hit_f.snoop_none Counts all demand data writes (RFOs) DEMAND_RFO & PMM_HIT_LOCAL_PMM & SNOOP_NONE Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_S & NO_SNOOP_NEEDED Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWD Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT & HIT_OTHER_CORE_NO_FWD ocr.pf_l3_rfo.l3_hit.hit_other_core_fwd ocr.pf_l1d_and_sw.l3_hit_f.any_snoop Counts all demand code reads DEMAND_CODE_RD & L3_HIT_M & NO_SNOOP_NEEDED Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT & HIT_OTHER_CORE_NO_FWD ocr.demand_data_rd.l3_hit_s.snoop_miss ocr.all_pf_data_rd.l3_hit.no_snoop_needed Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_E & HIT_OTHER_CORE_FWD Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_S & HIT_OTHER_CORE_FWD ocr.all_data_rd.l3_hit_e.snoop_none ALL_DATA_RD & L3_HIT_E & SNOOP_NONE ocr.demand_rfo.l3_hit.hit_other_core_no_fwd Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT & HIT_OTHER_CORE_NO_FWD Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT & HITM_OTHER_CORE ALL_READS & L3_HIT_E & HITM_OTHER_CORE ocr.other.l3_hit_f.hit_other_core_fwd Counts any other requests OTHER & L3_HIT_S & HIT_OTHER_CORE_NO_FWD ocr.all_data_rd.supplier_none.any_snoop ALL_RFO & L3_HIT_M & SNOOP_NONE ALL_RFO & L3_HIT_E & SNOOP_MISS ocr.all_pf_rfo.supplier_none.hit_other_core_no_fwd ocr.all_pf_rfo.supplier_none.any_snoop Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_M & HIT_OTHER_CORE_FWD cmask=5,period=2000003,umask=0x5,event=0xa3 period=100003,umask=0x3f,event=0xc1 period=100003,umask=0x1,event=0xe6 unc_m_pmm_rpq_occupancy.all / unc_m_pmm_rpq_inserts / unc_m_clockticks Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus event=0x9 umask=0xc8,period=200003,event=0x24 Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB) umask=0x1,period=25003,event=0x3c Counts Core crystal clock cycles when current thread is unhalted and the other thread is halted load_hit_prefetch.swpf Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder uops_executed.cycles_ge_2 Counts the number of cycles using always true condition (uops_ret &lt; 16) applied to non PEBS uops retired event Counts the retirement slots used each cycle br_inst_retired.cond br_misp_retired.cond Counts the number of instructions retired. (Fixed event) (Precise event) period=20003,event=0xc3 umask=0xC001FE01,event=0x35,config1=0x40040e33 TOR Inserts; CRd misses from local IA. Unit: uncore_cha unc_u_clockticks umask=0x2,event=0x8c umask=0x8,event=0x60 l2_wcb_req.wcb_close l2_cache_req_stat.ic_fill_hit_x The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. x87 instructions df_ccm_reqa.node7.wrsizedfullzero umask=0x2D,event=0x8a umask=0x27,event=0x8b df_ccm_reqa.node3.rdsized df_ccm_reqa.node5.rdsized df_ccm_reqa.node6.specdramrd umask=0x25,event=0x8b umask=0xA4,event=0x8b df_ccm_reqa.node4.rdvlks umask=0x21,event=0x8b df_ccm_reqa.node4.rdvlkl df_ccm_reqa.node7.rdvlkl df_ccm_reqb.node3.chgtox df_ccm_reqb.node4.vicblkfullzero df_ccm_reqb.node7.vicblkfullzero umask=0x6A,event=0x8c df_ccm_reqb.node6.anyiorequest. umask=0xC6,event=0x8c umask=0x05,event=0x8c umask=0xE5,event=0x8c umask=0xC3,event=0x8c umask=0x62,event=0x8c df_ccm_reqb.node5.wrsizedncposted df_ccm_reqb.node0.rdsized Data Fabric CCM Performance Monitor Event DF CCM Request Type C (PIE Requests)APIC access Any Bus Lock request df_ioms_reqa.node2.ios_resp df_ioms_reqa.node4.ios_resp umask=0x48,event=0x108 umask=0x07,event=0x108 umask=0x66,event=0x108 umask=0xC5,event=0x108 umask=0x43,event=0x108 umask=0xA2,event=0x108 umask=0xC2,event=0x108 df_ioms_reqa.node5.largeread df_ioms_reqb.node4.piesystemmanagement umask=0xEE,event=0x109 df_ioms_reqb.node1.pieinterrupt umask=0xAD,event=0x109 umask=0x8C,event=0x109 umask=0x0A,event=0x109 df_ioms_reqb.node3.ioanynon-postedwrsized=32b df_ioms_reqb.node2.ioanynon-postedwrsized<32b df_ioms_reqb.node0.ioanypostedwrsized>32band<64b df_ioms_reqb.node2.ioanypostedwrsized>32band<64b Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanyrdsized fpu_pipe_assignment.total2 Double precision add/subtract FLOPS fp_ret_sse_avx_ops.sp_div_flops fp_ret_sse_avx_ops.sp_mult_flops fp_num_mov_elim_scal_op.sse_mov_ops l3_request_g1.t4.s1.wrsizednc l3_request_g1.t1.s3.wrsized l3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x04,event=0x1 l3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x20,event=0x1 l3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x20,event=0x1 l3_request_g1.t1.s3.rdsized l3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x80,event=0x1 l3_request_g1.t6.s1.caching l3_request_g1.t3.s3.caching l3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x80,event=0x1 L3 Cache Performance Monitor Counters L3 cache access types l3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x01,event=0x3 l3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x02,event=0x3 l3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x04,event=0x3 l3fillvicreq.t3.s0.rdblkc_s l3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x10,event=0x3 l3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x20,event=0x3 l3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x20,event=0x3 l3fillvicreq.t4.s0.rdblkl_vic l3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x40,event=0x3 l3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x80,event=0x3 l3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x80,event=0x3 l3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x80,event=0x3 l3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x01,event=0x9 l3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x01,event=0x9 l3victimstate.t3.s1.none_nol3victimline l3victimstate.t1.s1.f_s l3victimstate.t4.s1.f_s l3victimstate.t3.s2.f_s l3victimstate.t5.s2.o l3victimstate.t4.s1.m l3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x40,event=0x9 l3victimstate.t0.s0.od l3victimstate.t3.s2.od l3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x80,event=0x9 ls_dispatch.store_dispatch umask=0x2,event=0x46 de_dis_dispatch_token_stalls0.alu_token_stall Total number uOps assigned to pipe 3 fp_disp_faults.x87_fill_fault Store-to-load conflicts: A load was unable to complete due to a non-forwardable conflict with an older store. Most commonly, a load's address range partially but not completely overlaps with an uncompleted older store. Software can avoid this problem by using same-size and same-alignment loads and stores when accessing the same data. Vector/SIMD code is particularly susceptible to this problem; software should construct wide vector stores by manipulating vector elements in registers using shuffle/blend/swap instructions prior to storing to memory, instead of using narrow element-by-element stores Number of accesses to the dcache for load/store references umask=0x8,event=0x43 ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit Software Prefetch Instructions Dispatched (Speculative) ls_pref_instr_disp.prefetch_w ls_hw_pf_dc_fill.ls_mabresp_lcl_cache LS_MICROARCHITECTURAL_RESYNC_BY_SNOOP LS_RETIRED_CFLUSH_INSTRUCTIONS IC_INSTRUCTION_FETCH_STALL EXTERNAL_INTERRUPT PLE_REQUEST_PROGRAMMED STREX_FAIL_SPEC EXC_HVC STALL_BACKEND INST_USER L2_DMISS_STALL_CYCLES FSB_QUARTER_TO_HALF AGCB_FULL_DR_STALLS L2_CACHE_MISS_CYCLES SYSTEM_EVENT_1 SYSTEM_EVENT_5 SYNCW VIU2_INSTR_WAIT_CYCLES VTQ_LINE_FETCH_HIT CYCLES_TWO_INSTR_COMPLETED L1_DATA_CACHE_CASTOUTS_TO_L2 CYCLES_RUNNING L1_LOAD_MISS PMC1_OVERFLOW PMC3_OVERFLOW DLFB_RETRIES_TO_MBAR L2_CACHE_DIRTY_UPDATES store-pipe-junk-ops exclusive sse-and-x87-microtraps EDGE POWER8 INTEL_P5 ARMV8_CORTEX_A57 TS STOPPED true GenuineIntel-6-36 v19 Pipeline;Summary cache RFO requests that miss L2 cache l2_rqsts.all_demand_references This event counts duration of L1D miss outstanding in cycles umask=0x2,cmask=1,period=2000003,event=0x48 umask=0x4,period=2000003,event=0x60 This event counts both cacheable and noncachaeble code read requests mem_load_uops_l3_miss_retired.local_dram Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI) (Precise Event) Supports address when precise. Spec update: BDE70 umask=0x1,period=2000003,event=0xc7 fp_arith_inst_retired.scalar fp_arith_inst_retired.128b_packed_single umask=0x2,period=100003,event=0xca umask=0x20,period=2000003,event=0x79 umask=0x4,period=2000003,event=0x80 Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled Cycles with less than 2 uops delivered by the front end Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region umask=0x8,period=2000003,event=0xc8 umask=0x40,period=2000003,event=0xc9 umask=0x2,period=100003,event=0x3 umask=0x2,period=2000003,event=0x3c br_inst_exec.taken_conditional This event counts taken speculative and retired mispredicted indirect branches excluding calls and returns umask=0x88,period=200003,event=0x89 umask=0xff,period=200003,event=0x89 Cycles per thread when uops are executed in port 0 Cycles per core when uops are exectuted in port 0 umask=0x2,any=1,period=2000003,event=0xa1 uops_executed_port.port_2_core uops_dispatched_port.port_5 cycle_activity.stalls_l2_miss Cycles where at least 4 uops were executed per-thread Number of times any microcode assist is invoked by HW upon uop writeback inv=1,umask=0x1,cmask=10,period=2000003,event=0xc2 This event counts all (macro) branch instructions retired This is a precise version (that is, uses PEBS) of the event that counts both direct and indirect near call instructions retired (Precise event) Number of near branch instructions retired that were mispredicted and taken. (Precise Event - PEBS) (Precise event) Streaming stores (full cache line). Derived from unc_c_tor_inserts.opcode. Unit: uncore_cbox unc_h_requests.writes_local unc_m_pre_count.rd Pre-charge for reads. Unit: uncore_imc umask=0x4,period=2000003,event=0x8 Load misses that miss the DTLB and hit the STLB (2M) This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G) Spec update: BDM69 Number of DTLB page walker hits in the L2 Spec update: BDM69, BDM98 IpCall Number of Instructions per non-speculative Branch Misprediction (JEClear) Core actual clocks when any Logical Processor is active on the Physical Core umask=0xc2,period=200003,event=0x24 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020001 offcore_response.demand_data_rd.supplier_none.snoop_hitm offcore_response.demand_code_rd.supplier_none.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0008 offcore_response.pf_l2_data_rd.l3_hit.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0020 offcore_response.pf_l3_rfo.supplier_none.snoop_hit_no_fwd offcore_response.pf_l3_code_rd.supplier_none.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0200 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0200 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000028000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C8000 offcore_response.other.l3_hit.snoop_hitm offcore_response.all_pf_data_rd.supplier_none.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020090 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0240 offcore_response.all_data_rd.any_response offcore_response.all_data_rd.supplier_none.any_snoop offcore_response.all_data_rd.l3_hit.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020122 Randomly selected loads with latency value being above 32 Spec update: BDM100, BDM35 (Must be precise) Randomly selected loads with latency value being above 512 Spec update: BDM100, BDM35 (Must be precise) offcore_response.demand_code_rd.l3_miss_local_dram.snoop_hitm offcore_response.demand_code_rd.l3_miss.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020008 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000008 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000040 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000040 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000100 offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000200 offcore_response.pf_l3_code_rd.l3_miss.snoop_miss offcore_response.other.l3_miss_local_dram.snoop_hitm offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_hit_no_fwd A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core Unit: uncore_arb Each cycle count number of 'valid' coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case 1000000000 * ( cbox@event\=0x36\,umask\=0x3\,filter_opc\=0x182@ / cbox@event\=0x35\,umask\=0x3\,filter_opc\=0x182@ ) / ( cbox_0@event\=0x0@ / duration_time ) Retired load uops with L2 cache hits as data sources Supports address when precise. Spec update: BDM35 (Precise event) Retired load uops misses in L1 cache as data sources Supports address when precise (Precise event) This event counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache Supports address when precise. Spec update: BDM100 (Precise event) offcore_response.pf_llc_code_rd.llc_hit.any_response offcore_response.all_data_rd.llc_miss.remote_dram Counts prefetch (that bring data to LLC only) code reads miss in the L3 Number of near branch instructions retired that were mispredicted and taken (Precise event) l2_ifetch.self.s_state umask=0x44,period=200000,event=0x29 umask=0x54,period=200000,event=0x29 l2_data_rqsts.self.e_state umask=0x48,period=200000,event=0x2c l2_ld_ifetch.self.mesi umask=0x74,period=200000,event=0x30 simd_sat_uop_exec.s simd_sat_uop_exec.ar SIMD packed multiply micro-ops executed simd_inst_retired.scalar_single umask=0xe0,period=200000,event=0x66 umask=0xe0,period=200000,event=0x68 bus_trans_def.self umask=0xe0,period=200000,event=0x70 umask=0x83,period=200000,event=0x2 data_tlb_misses.dtlb_miss Duration of page-walks in core cycles Counts when a modified (dirty) cache line is evicted from the data L1 cache and needs to be written back to memory. No count will occur if the evicted line is clean, and hence does not require a writeback fetch_stall.icache_fill_pending_cycles Counts data reads (demand & prefetch) that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000001000 offcore_response.bus_locks.any_response offcore_response.pf_l2_data_rd.l2_miss.hitm_other_core Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that hit the L2 cache umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200000002 Load uops that split a page (Precise event capable) (Must be precise) Floating point divide uops retired. (Precise Event Capable) (Must be precise) Counts the number of taken branch instructions retired (Must be precise) baclears.cond Counts demand cacheable data reads of full cache lines true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand reads for ownership (RFO) requests generated by a write to full data cache line have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200000400 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010800 Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts reads for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Floating point divide uops retired (Precise Event Capable) (Must be precise) Page walks outstanding due to a demand load every cycle Counts once per cycle for each page walk occurring due to a load (demand data loads or SW prefetches). Includes cycles spent traversing the Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of walks Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault Demand Data Read requests Spec update: HSD78 Miss in last-level (L3) cache. Excludes Unknown data-source Spec update: HSD74, HSD29, HSD25, HSM26, HSM30. Supports address when precise (Precise event) Any MLC or L3 HW prefetch accessing L2, including rejects offcore_response.demand_rfo.l3_hit.hit_other_core_no_fwd Counts cycles MITE is delivered at least one uop. Set Cmask = 1 Randomly selected loads with latency value being above 4 Spec update: HSD76, HSD25, HSM26 (Must be precise) Randomly selected loads with latency value being above 32 Spec update: HSD76, HSD25, HSM26 (Must be precise) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100400002 umask=0x1,edge=1,period=100003,cmask=1,event=0x5c Counts all near executed branches (not necessarily retired) Cycles where at least 3 uops were executed per-thread Spec update: HSD144, HSD30, HSM31 umask=0x84,event=0x22 umask=0x88,event=0x22 Store miss in all TLB levels causes a page walk that completes. (4K) Number of ITLB page walker hits in the L2 Miss in mid-level (L2) cache. Excludes Unknown data-source Supports address when precise. Spec update: HSD29, HSM30 (Precise event) This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches Supports address when precise. Spec update: HSD74, HSD29, HSD25, HSM30 (Precise event) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0600400004 Counts the number of not taken branch instructions retired All retired load uops. (Precise Event) mem_load_uops_llc_hit_retired.xsnp_miss Clean L2 cache lines evicted by the MLC prefetcher offcore_response.all_rfo.llc_hit.no_snoop_needed offcore_response.demand_code_rd.llc_hit.any_response simd_fp_256.packed_single umask=0xc,period=2000003,event=0xa1 umask=0xc,any=1,period=2000003,event=0xa1 Cycles per thread when load or STA uops are dispatched to port 3 unc_cbo_cache_lookup.m Retired load uops whose data source was local DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x87f820004 offcore_response.demand_data_rd.llc_miss.remote_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x67f800010 Write requests to home agent. Unit: uncore_ha Cycles where transmitting QPI link is in half-width mode. Unit: uncore_qpi event=0xb freq_ge_2000mhz_cycles % (unc_p_freq_ge_4000mhz_cycles / unc_p_clockticks) * 100. Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache This event counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decoded instructions, to the legacy decode pipeline. It excludes cycles when the back-end cannot accept new micro-ops. The penalty for these switches is potentially several cycles of instruction starvation, where no micro-ops are delivered to the back-end Counts all local dram accesses for all demand and L2 prefetches. LLC prefetches are excluded other_assists.itlb_miss_retired umask=0x1,period=100003,event=0x3 unc_m_act_count Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state Counts any Read request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state offcore_response.any_code_rd.outstanding offcore_response.any_code_rd.l2_hit_far_tile_e_f offcore_response.any_data_rd.l2_hit_far_tile_e_f Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode Counts Demand cacheable data and L1 prefetch data read requests that accounts for any response umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000408000 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800408000 Counts Partial streaming stores (WC and should be programmed on PMC1) that accounts for any response offcore_response.pf_l1_data_rd.l2_hit_far_tile_e_f Counts L1 data HW prefetches that accounts for any response offcore_response.pf_software.l2_hit_far_tile_e_f offcore_response.uc_code_reads.l2_hit_far_tile_m offcore_response.partial_writes.l2_hit_far_tile_m Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state offcore_response.pf_l2_code_rd.l2_hit_near_tile_e_f Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state offcore_response.demand_data_rd.l2_hit_this_tile_m Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in M state offcore_response.pf_software.l2_hit_this_tile_m Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in E state Counts Demand cacheable data write requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode offcore_response.any_pf_l2.mcdram_far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000070 offcore_response.any_read.mcdram_near offcore_response.pf_l1_data_rd.mcdram_near Counts Bus locks and split lock requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Far or Other tile L2 hit far offcore_response.partial_writes.ddr_far Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Local offcore_response.partial_reads.ddr_far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400040 offcore_response.demand_code_rd.mcdram_near umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180600004 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180600080 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x01818032f7 L1D cache lines allocated in the M state l1d.m_snoop_evict l1d_cache_ld.m_state l1d_cache_lock.s_state umask=0x4,period=200000,event=0x4e L2 data demand loads in I state (misses) l2_data_rqsts.prefetch.mesi umask=0x20,period=200000,event=0x24 umask=0x20,period=10000,event=0xf Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event) Offcore code reads satisfied by the LLC and HIT in a sibling core offcore_response.any_ifetch.remote_cache_dram Offcore code reads that HITM in a remote cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0xFFFF umask=0x1,period=100000,event=0xb7,offcore_rsp=0x47FF Offcore writebacks that HIT in a remote cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x177 offcore_response.data_in.remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3803 Offcore demand data reads that HIT in a remote cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x104 Offcore demand code reads satisfied by the LLC and not found in a sibling core Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core offcore_response.pf_data.remote_cache Offcore prefetch data reads satisfied by any cache or DRAM Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit Offcore prefetch data reads satisfied by the LLC and not found in a sibling core umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F20 Offcore prefetch requests satisfied by a remote cache offcore_response.prefetch.remote_cache_dram umask=0x1,period=2000000,event=0xcc SIMD integer 64 bit unpack operations Offcore code reads that missed the LLC Offcore code or data read requests that missed the LLC offcore_response.data_in.any_llc_miss umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4003 Offcore prefetch data requests satisfied by the local DRAM offcore_response.pf_ifetch.any_llc_miss Late Branch Prediction Unit clears umask=0x2,period=100000,event=0xb8 cpu_clk_unhalted.total_cycles umask=0x1,period=2000000,event=0x20 ssex_uops_retired.packed_double Cycles no Uops issued on any port (core count) umask=0x20,period=2000000,event=0xb1 Counts the total number of L2 code requests Counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation) Counts both cacheable and non-cacheable code read requests mem_inst_retired.all_stores umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040408000 offcore_response.other.l3_hit_m.snoop_not_needed offcore_response.demand_code_rd.l4_hit_local_l4.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040400004 offcore_response.demand_code_rd.l3_hit.spl_hit offcore_response.demand_code_rd.l3_hit_s.snoop_none offcore_response.demand_rfo.l3_hit_e.snoop_miss offcore_response.demand_rfo.l3_hit_m.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080100001 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200040001 icache_16b.ifdata_stall Cycles where a code fetch is stalled due to L1 instruction cache tag miss frontend_retired.l2_miss umask=0x1,period=100007,event=0xc6,frontend=0x15 Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops (Precise event) offcore_requests_outstanding.cycles_with_l3_miss_demand_data_rd Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles (Must be precise) offcore_response.demand_code_rd.l3_miss.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20001C0004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x007C400001 sw_prefetch_access.nta umask=0x4,period=2000003,event=0x32 Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate front-end Latency Bound issues umask=0x3f,period=100003,event=0xc1 Counts any rfo reads (demand & prefetch) that miss L2 with a snoop miss response umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680000040 umask=0x3f,period=200003,event=0xca Total page walks that are completed (I-side and D-side) Counts all prefetch code reads that hit in the LLC Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0200 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0200 offcore_response.all_pf_data_rd.llc_miss.dram offcore_response.data_in_socket.llc_miss_local.any_llc_hit Mispredicted not taken branch instructions retired.(Precise Event - PEBS) (Precise event) Outstanding offcore demand code reads offcore_requests_outstanding.demand.rfo umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5044 REQUEST = ANY_REQUEST and RESPONSE = ANY_CACHE_DRAM REQUEST = ANY RFO and RESPONSE = ANY_CACHE_DRAM REQUEST = ANY RFO and RESPONSE = ANY_LOCATION umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f03 REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_LOCATION offcore_response.other.local_dram_and_remote_cache_hit REQUEST = PF_DATA_RD and RESPONSE = ANY_LOCATION REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITM offcore_response.pf_data_rd.local_dram_and_remote_cache_hit REQUEST = PF_DATA_RD and RESPONSE = REMOTE_CACHE_HITM umask=0x1,period=100000,event=0xb7,offcore_rsp=0xf811 REQUEST = DATA_IN and RESPONSE = REMOTE_DRAM offcore_response.other.other_local_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3040 REQUEST = PF_IFETCH and RESPONSE = ANY_LLC_MISS umask=0x80,period=200000,event=0x85 offcore_response.pf_l2_rfo.l3_hit.hit_other_core_no_fwd offcore_response.all_pf_rfo.l3_hit.hit_other_core_no_fwd offcore_response.pf_l3_data_rd.l3_hit.snoop_hit_with_fwd offcore_response.all_data_rd.l3_hit.snoop_hit_with_fwd fp_arith_inst_retired.512b_packed_single offcore_response.demand_data_rd.l3_miss.snoop_miss_or_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063FC00020 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063FC00400 core_snoop_response.rsp_sfwdfe idi_misc.wb_upgrade LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.ia_miss. Unit: uncore_cha PCI Express bandwidth writing at IIO, part 0. Unit: uncore_iio umask=0x01,event=0x53 umask=0x01,event=0x54 Number of times that an RFO hit in S state. Unit: uncore_cha unc_iio_txn_req_by_cpu.mem_read.part3 fc_mask=0x07,ch_mask=0x02,umask=0x04,event=0x84 unc_iio_txn_req_of_cpu.mem_write.part1 Messages sent direct to core (bypassing the CHA). Unit: uncore_m2m Counts cycles when the ability to send messages direct to the Intel Ultra Path Interconnect (bypassing the CHA) was disabled unc_m2m_directory_lookup.any Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from S (Shared) to I (Invalid) Counts when the M2M (Mesh to Memory) receives a prefetch request and inserts it into its outstanding prefetch queue. Explanatory Side Note: the prefect queue is made from CAM: Content Addressable Memory unc_upi_txl_flits.idle period=200003,umask=0x27,event=0x24 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400001 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0010 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800108000 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040120 Counts retired load instructions with remote Intel® Optane™ DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode). Precise event Supports address when precise (Precise event) offcore_response.all_rfo.l3_hit_e.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100001 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200080 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.SNOOP_MISS offcore_response.demand_rfo.pmm_hit_local_pmm.any_snoop This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100122 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020490 offcore_response.pf_l3_data_rd.l3_hit_s.hit_other_core_fwd offcore_response.demand_code_rd.supplier_none.no_snoop_needed This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080020 offcore_response.all_rfo.l3_hit_e.any_snoop offcore_response.all_rfo.l3_hit_e.no_snoop_needed offcore_response.other.l3_hit_e.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020020 period=200003,umask=0xf8,event=0x24 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP offcore_response.all_reads.l3_hit_m.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE offcore_response.all_reads.l3_hit_s.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020120 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0400 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080002 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080020 offcore_response.pf_l3_rfo.l3_hit_f.hit_other_core_no_fwd offcore_response.demand_code_rd.l3_hit_m.hitm_other_core offcore_response.all_pf_rfo.pmm_hit_local_pmm.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0120 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD offcore_response.demand_code_rd.pmm_hit_local_pmm.any_snoop offcore_response.all_data_rd.pmm_hit_local_pmm.any_snoop offcore_response.pf_l1d_and_sw.l3_hit_s.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080122 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0400 offcore_response.pf_l3_rfo.l3_hit_m.no_snoop_needed idq.dsb_uops / (idq.dsb_uops + lsd.uops + idq.mite_uops + idq.ms_uops) Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches period=2000003,umask=0x4,event=0x79 cmask=1,period=2000003,umask=0x10,event=0x79 period=100007,umask=0x1,event=0xc6,frontend=0x402006 Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS_LOCAL_DRAM & NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000400 offcore_response.demand_rfo.l3_miss_remote_hop1_dram.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00080 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS & SNOOP_MISS ALL_PF_RFO & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_FWD ALL_PF_DATA_RD & L3_MISS_LOCAL_DRAM & ANY_SNOOP offcore_response.pf_l3_rfo.l3_miss_local_dram.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000004 This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000020 offcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000004 ALL_PF_DATA_RD & L3_MISS_REMOTE_DRAM & SNOOP_MISS_OR_NO_FWD offcore_response.all_reads.l3_miss_remote_hop1_dram.hit_other_core_fwd ocr.all_reads.l3_miss.remote_hit_forward This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP ocr.pf_l3_data_rd.l3_miss.remote_hit_forward ocr.pf_l3_rfo.l3_miss.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000120 ocr.demand_data_rd.l3_miss_local_dram.hit_other_core_no_fwd offcore_response.all_rfo.l3_miss_local_dram.hitm_other_core This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000400 ocr.demand_code_rd.l3_miss_local_dram.snoop_miss ocr.all_reads.l3_miss_remote_hop1_dram.snoop_miss Counts all demand code reads DEMAND_CODE_RD & L3_MISS & NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD ALL_RFO & L3_MISS_LOCAL_DRAM & SNOOP_MISS_OR_NO_FWD ocr.all_pf_rfo.l3_miss_local_dram.hitm_other_core This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP ocr.all_data_rd.l3_miss.remote_hitm offcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.any_snoop ocr.all_pf_rfo.l3_miss_local_dram.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD ocr.pf_l1d_and_sw.l3_miss_local_dram.hit_other_core_fwd period=2000003,umask=0x1,event=0xc8 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS ALL_READS & L3_MISS & HIT_OTHER_CORE_FWD Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_F & HIT_OTHER_CORE_NO_FWD ALL_PF_RFO & L3_HIT & ANY_SNOOP ALL_PF_RFO & L3_HIT_S & ANY_SNOOP ocr.other.l3_hit_s.no_snoop_needed ocr.pf_l1d_and_sw.l3_hit_m.snoop_miss ocr.demand_rfo.supplier_none.hit_other_core_fwd ocr.all_rfo.l3_hit_f.hit_other_core_no_fwd ocr.pf_l2_rfo.l3_hit_s.snoop_none ocr.demand_data_rd.l3_hit.snoop_none ocr.pf_l3_rfo.supplier_none.snoop_miss ocr.pf_l1d_and_sw.l3_hit_m.hit_other_core_no_fwd ocr.demand_data_rd.l3_hit_f.hit_other_core_no_fwd ocr.pf_l2_data_rd.l3_hit_f.snoop_none Counts demand data reads DEMAND_DATA_RD & L3_HIT_E & ANY_SNOOP ALL_RFO & L3_HIT_F & HIT_OTHER_CORE_FWD ocr.demand_rfo.l3_hit_m.hit_other_core_fwd ocr.all_reads.l3_hit_f.hit_other_core_fwd ALL_DATA_RD & L3_HIT_F & SNOOP_MISS ocr.all_pf_rfo.supplier_none.snoop_none ocr.demand_data_rd.l3_hit_s.hitm_other_core ocr.demand_code_rd.supplier_none.hit_other_core_fwd ocr.demand_data_rd.supplier_none.any_snoop ocr.all_pf_rfo.l3_hit_f.snoop_none ocr.pf_l3_rfo.l3_hit.snoop_miss ocr.demand_rfo.l3_hit_s.hit_other_core_no_fwd Counts any other requests OTHER & L3_HIT_M & NO_SNOOP_NEEDED ALL_READS & L3_HIT & HITM_OTHER_CORE ocr.all_rfo.l3_hit_s.any_snoop Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_M & HIT_OTHER_CORE_FWD ocr.demand_code_rd.pmm_hit_local_pmm.snoop_not_needed Counts any other requests OTHER & SUPPLIER_NONE & HIT_OTHER_CORE_FWD ALL_READS & L3_HIT_S & HITM_OTHER_CORE ALL_READS & L3_HIT_M & HIT_OTHER_CORE_NO_FWD Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWD Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_F & NO_SNOOP_NEEDED ocr.pf_l2_data_rd.l3_hit_f.any_snoop ocr.pf_l2_data_rd.l3_hit.hit_other_core_fwd ocr.all_pf_data_rd.l3_hit_s.snoop_none ocr.all_pf_rfo.l3_hit_s.hit_other_core_no_fwd ALL_DATA_RD & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDED Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_M & HITM_OTHER_CORE Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_F & HITM_OTHER_CORE period=400009,event=0xc5 any=1,period=2000003,event=0x3c Underfill reads Tag Check; Clean Ingress (from CMS) Request Queue Rejects; PhyAddr Match. Unit: uncore_cha unc_iio_data_req_by_cpu.peer_read.part1 Counts every peer to peer read request for 4 bytes of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus Peer to peer read request for 4 bytes made by IIO Part1 to an IIO target. Unit: uncore_iio fc_mask=0x07,ch_mask=0x04,umask=0x02,event=0x83 Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus AD Egress (to CMS) Occupancy. Unit: uncore_m2m period=100003,umask=0x1,event=0x8 period=100007,umask=0x1,event=0xae Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses Counts retired store instructions that true miss the STLB Supports address when precise (Precise event) Counts retired load instructions whose data sources were HitM responses from shared L3 Supports address when precise (Precise event) Cycles the thread is active and superQ cannot take any more entries Counts the cycles for which the thread is active and the superQ cannot take any more entries umask=0x1,period=100007,event=0xc6,frontend=0x508006 Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region Counts the number of times HLE abort was triggered topdown.slots umask=0x1,period=10000003,event=0xa4 Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector) Cycle counts are evenly distributed between active threads in the Core Counts completed page walks (2M and 4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault Counts cacheable memory requests that miss in the the Last Level Cache. Requests include Demand Loads, Reads for Ownership(RFO), Instruction fetches and L1 HW prefetches. If the platform has an L3 cache, last level cache is the L3, otherwise it is the L2 Counts requests to the Instruction Cache (ICache) for one or more bytes cache Line Counts reference cycles (at TSC frequency) when core is not halted. This event uses a programmable general purpose perfmon counter fc_mask=0x07,ch_mask=0x10,umask=0x01,event=0x83 The number of pipeline restarts caused by invalidating probes that hit on the instruction stream currently being executed. This would happen if the active instruction stream was being modified by another processor in an MP system - typically a highly unlikely event umask=0x1,event=0x87 l2_request_g1.rd_blk_x umask=0x40,event=0x60 All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized event=0xc4 ex_ret_brn_far The number of near return instructions (RET or RET Iw) retired umask=0x6F,event=0x8b umask=0x0E,event=0x8b umask=0x0A,event=0x8b umask=0x69,event=0x8b umask=0x89,event=0x8b df_ccm_reqa.node3.rdvlks df_ccm_reqb.node1.chgtox umask=0xE7,event=0x8c df_ccm_reqb.node1.anywrsized umask=0xA6,event=0x8c df_ccm_reqb.node7.wrsizednc umask=0xA2,event=0x8c umask=0x2B,event=0x108 df_ioms_reqa.node7.flush umask=0x28,event=0x108 Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anyatomic umask=0x81,event=0x108 umask=0x0B,event=0x109 df_ioms_reqb.node5.ioanynon-postedwrsized=32b umask=0x27,event=0x109 df_ioms_reqb.node7.ioanypostedwrsized=64b umask=0x44,event=0x109 umask=0x63,event=0x109 The number of x87 floating-point Ops that have retired. The number of events logged per cycle can vary from 0 to 8. Divide and square root Ops umask=0x40,event=0x3 umask=0x1,event=0x5 l3_request_g1.t6.s0.wrsizednc l3_request_g1.t0.s2.wrsizednc l3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x04,event=0x1 l3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x04,event=0x1 l3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x20,event=0x1 l3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x20,event=0x1 l3_request_g1.t7.s2.rdsized l3_request_g1.t5.s0.caching l3_request_g1.t6.s3.caching l3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x01,event=0x3 l3fillvicreq.t1.s2.vicblk l3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x01,event=0x3 l3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x02,event=0x3 l3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x04,event=0x3 l3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x04,event=0x3 l3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x04,event=0x3 l3fillvicreq.t6.s3.rdblkc_s_vic l3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x08,event=0x3 l3fillvicreq.t2.s2.rdblkc_s l3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x08,event=0x3 l3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x08,event=0x3 l3fillvicreq.t3.s3.rdblkc_s l3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x10,event=0x3 l3fillvicreq.t2.s0.rdblkx l3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x20,event=0x3 l3fillvicreq.t5.s1.rdblkx l3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x20,event=0x3 l3fillvicreq.t0.s0.rdblkl_vic l3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x40,event=0x3 l3victimstate.t0.s1.nol3victimline l3victimstate.t0.s2.nol3victimline l3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x01,event=0x9 l3victimstate.t6.s3.none_nol3victimline l3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x04,event=0x9 l3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x04,event=0x9 l3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x04,event=0x9 l3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x08,event=0x9 l3victimstate.t4.s0.o l3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x08,event=0x9 l3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x10,event=0x9 l3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x10,event=0x9 l3victimstate.t6.s3.e_fe l3victimstate.t2.s0.m l3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x20,event=0x9 l3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x20,event=0x9 l3victimstate.t6.s3.m l3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x40,event=0x9 l3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x40,event=0x9 l3victimstate.t3.s2.d l3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x40,event=0x9 l3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x80,event=0x9 l3victimstate.t7.s1.od l3victimstate.t7.s2.od l3victimstate.t6.s3.od umask=0x3,event=0x46 umask=0x2,event=0x52 Cycles where a dispatch group is valid but does not get dispatched due to a token stall. AGSQ Tokens unavailable umask=0x4,event=0xe LS_MICROARCHITECTURAL_LATE_CANCEL NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT PC_BRANCH_MIS_PRED PMUEXTIN0_EVT INST_RETIRED UNALIGNED_LD_SPEC IMPRECISE_SETBOUNDS L2CACHE_EVICT L2CACHEMASTER_READ_RSP RF_STALL DSPRAM_STALL_CYCLES EJTAG_DTRIGGER IFU_REPLAYS IFU_IDU_NO_FETCH_CYCLES UNCACHED_LOAD_INSNS SYSTEM_EVENT_7 CC FP_STORE_CAUSES_STALL_IN_LSU FP_THREE_QUARTERS_FPSCR_RENAMES_BUSY FP_DENORMALIZED_RESULT DISPATCHES_TO_FPR_ISSUE_QUEUE REFETCH_SERIALIZATION VPU_MARKED_INSTR_COMPLETED FXU0_IDLE_FXU1_IDLE MARKED_STORE_SENT_TO_STS ADDRESS_COLLISION INSTR_MMU_TLB4K_RELOADS BIU_MASTER_RETRIES EXT_INPUT_INTR_TAKEN L2_CACHE_LOCKS DVT2_DETECTED shared IAF MIPS_BERI THREAD pmc_pmu_event_get_by_idx name: %s
l3cache %s, "pmcid": "0x%08x", "pid": "%d", "tid": "%d", "cpuflags": "0x%08x", "cpuflags2": "0x%08x", "pc": [ v24 Cycles Per Instruction (threaded) Instructions Average Branch Address Clear Cost (fraction of cycles) 1 - cpu_clk_thread_unhalted.one_thread_active / ( cpu_clk_thread_unhalted.ref_xclk_any / 2 ) if #smt_on else 0 Demand Data Read miss L2, no rejects l2_rqsts.code_rd_hit mem_uops_retired.stlb_miss_stores umask=0x41,period=100003,event=0xd0 mem_uops_retired.split_stores This is a precise version (that is, uses PEBS) of the event that counts store uops retired to the architected path with a filter on bits 0 and 1 applied.
Note: This event ?ounts AVX-256bit load/store double-pump memory uops as a single uop at retirement Supports address when precise (Precise event) umask=0x1,period=2000003,event=0xd1 umask=0x40,period=100003,event=0xd1 This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache Supports address when precise. Spec update: BDM100 (Precise event) mem_load_uops_l3_miss_retired.remote_fwd Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element Instruction Decode Queue (IDQ) empty cycles umask=0x4,period=2000003,event=0x79 This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy Cycles where a code fetch is stalled due to L1 instruction-cache miss This event counts, on the per-thread basis, cycles when less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >=3 idq_uops_not_delivered.cycles_le_2_uop_deliv.core Speculative cache line split STA uops dispatched to L1 cache tx_exec.misc2 Number of times HLE commit succeeded Number of times RTM abort was triggered (PEBS) (Precise event) mem_trans_retired.load_latency_gt_8 This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode This event counts when there is a transition from ring 1,2 or 3 to ring0 umask=0x40,period=2000003,event=0xe Number of Multiply packed/scalar single precision uops allocated Number of integer Move Elimination candidate uops that were not eliminated umask=0x8,period=1000003,event=0x58 This event counts taken speculative and retired indirect calls including both register and memory indirect br_inst_exec.all_indirect_jump_non_call_ret umask=0x2,period=2000003,event=0xa1 Counts number of cycles nothing is executed on any execution port Number of uops to be executed per-thread each cycle Cycles where at least 1 uop was executed per-thread br_inst_retired.near_call umask=0x2,period=100007,event=0xc4 rob_misc_events.lbr_inserts umask=0x11,event=0x34,filter_state=0x1 umask=0x3,event=0x35,filter_opc=0x182 uncore_ha read requests to local home agent. Unit: uncore_ha unc_h_requests.reads_remote umask=0x20,event=0x21 PCU clock ticks. Use to get percentages of PCU cycles events. Unit: uncore_pcu umask=0xe,period=100003,event=0x8 Cycles when PMH is busy with page walks Spec update: BDM69 This event counts the number of cycles while PMH is busy with the page walk Spec update: BDM69 itlb_misses.walk_completed_4k Per-Logical Processor actual clocks when the Logical Processor is active Instruction per (near) call (lower number means higher occurance rate) Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS) Spec update: BDM100. Supports address when precise (Precise event) offcore_response.demand_rfo.l3_hit.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0004 offcore_response.corewb.any_response Counts prefetch (that bring data to L2) data reads offcore_response.pf_l2_rfo.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020020 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0020 offcore_response.pf_l3_rfo.l3_hit.any_snoop offcore_response.all_pf_data_rd.supplier_none.any_snoop offcore_response.all_pf_rfo.supplier_none.any_snoop offcore_response.all_pf_code_rd.supplier_none.snoop_none Randomly selected loads with latency value being above 128 Spec update: BDM100, BDM35 (Must be precise) offcore_response.demand_data_rd.supplier_none.snoop_non_dram offcore_response.demand_rfo.l3_miss.snoop_none offcore_response.demand_code_rd.l3_miss.snoop_not_needed offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000040 offcore_response.pf_l3_data_rd.l3_miss_local_dram.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000200 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000090 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000120 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000120 offcore_response.all_pf_rfo.l3_miss.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020091 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000091 umask=0x1,edge=1,period=100007,cmask=1,event=0x5c umask=0x1,period=2000003,cmask=1,event=0xb1 L3 Lookup any request that access cache and found line in I-state unc_cbo_cache_lookup.read_mesi Retired load uops that miss the STLB Supports address when precise (Precise event) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x103FC00091 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0604000091 (unc_m_power_channel_ppd / unc_m_clockticks) * 100. Cycles L2 address bus is in use umask=0x70,period=200000,event=0x24 umask=0x78,period=200000,event=0x2e Retired loads that miss the L2 cache simd_uop_type_exec.pack.s simd_instr_retired decode_stall.pfb_empty decode_stall.iq_full macro_insts.cisc_decoded prefetch.software_prefetch.ar bus_trans_def.all_agents umask=0xe0,period=200000,event=0x6e snoop_stall_drv.self umask=0x0,period=2000000,event=0x3c Core cycles when core is not halted cpu_clk_unhalted.core All macro conditional branch instructions br_inst_type_retired.uncond All non-indirect calls uops_retired.stalled_cycles Cycles issue is stalled due to div busy Retired loads that miss the DTLB (precise event) (Precise event) l2_reject_xq.all Counts the number of store uops retired Supports address when precise (Must be precise) Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required Counts data reads generated by L1 or L2 prefetchers that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000048000 Counts requests to the uncore subsystem that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache offcore_response.partial_streaming_stores.l2_hit Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400000800 Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) ms_decoded.ms_entry fetch_stall.itlb_fill_pending_cycles Reference cycles when core is not halted (Fixed event) uops_retired.fpdiv umask=0x7e,period=200003,event=0xc4 Retired conditional branch instructions (Precise event capable) (Must be precise) br_inst_retired.call umask=0x0,period=200003,event=0xc5 cycles_div_busy.all umask=0x3,period=200003,event=0x5 Counts requests to the uncore subsystem have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_data_rd.outstanding Counts reads for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received umask=0x1,period=20003,event=0xc3 Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 2M or 4M pages. The page walks can end with or without a page fault STLB flushes Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle Spec update: HSD62, HSD61 Counts all prefetch (that bring data to LLC only) data reads hit in the L3 Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00040 This event counts cycles where the decoder is stalled on an instruction with a length changing prefix (LCP) This event counts cycles during which no instructions were executed in the execution stage of the pipeline Number of uops executed on the core Spec update: HSD30, HSM31 umask=0x28,event=0x34 Number of DTLB page walker loads that hit in the L1+FB Data from local DRAM either Snoop not needed or Snoop Miss (RspI) Supports address when precise. Spec update: HSD74, HSD29, HSD25, HSM30 (Precise event) Retired load uop whose Data Source was: forwarded from remote cache Supports address when precise. Spec update: HSM30 (Precise event) offcore_response.pf_llc_data_rd.llc_miss.any_response edge=1,umask=0x1,cmask=1,period=100003,event=0x5c Number of microcode assists invoked by HW upon uop writeback Not rejected writebacks from L1D to L2 cache lines in M state umask=0x4,period=100003,event=0xf2 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0244 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00010122 Counts all data/code/rfo references (demand & prefetch) fp_comp_ops_exe.sse_packed_double ( (( 1 * ( fp_comp_ops_exe.sse_scalar_single + fp_comp_ops_exe.sse_scalar_double ) + 2 * fp_comp_ops_exe.sse_packed_double + 4 * ( fp_comp_ops_exe.sse_packed_single + simd_fp_256.packed_double ) + 8 * simd_fp_256.packed_single )) / 1000000000 ) / duration_time umask=0x1,period=100003,event=0xbe Counts demand code reads that miss the LLC and the data returned from dram Increments each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core Unit: uncore_cbox A snoop invalidates a non-modified line in some processor core A snoop hits a modified line in some processor core umask=0x10,event=0x34 Filter on processor core initiated cacheable write requests unc_cbo_cache_lookup.extsnp_filter Unit: uncore_arb Counts the number of LLC evictions allocated Cycles PMH is busy with this walk offcore_response.all_data_rd.llc_hit.snoop_miss offcore_response.pf_l2_data_rd.llc_hit.no_snoop_needed Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC umask=0x1,period=100003,event=0xb7,offcore_rsp=0x67f800244 Counts demand data reads that miss the LLC and the data returned from local dram Counts demand data reads that miss the LLC the data is found in M state in remote cache and forwarded from there umask=0x1,period=100003,event=0xb7,offcore_rsp=0x107fc20002 umask=0x1,event=0x35,filter_opc=0x19c event=0xd Memory page conflicts. Unit: uncore_imc event=0xe,filter_band3=40 unc_p_freq_ge_1200mhz_transitions umask=0x20,period=2000003,event=0x59 This event counts the number of core cycles the fetch stalls because of an icache miss. This is a cumulative count of cycles the NIP stalled for all icache misses offcore_response.any_pf_l2.l2_hit_near_tile_m offcore_response.any_rfo.l2_hit_near_tile_e_f Counts any request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state offcore_response.partial_reads.l2_hit_far_tile_e_f offcore_response.partial_reads.any_response umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400040 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400001 offcore_response.bus_locks.l2_hit_this_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008002000 Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in S state umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000200 offcore_response.any_request.l2_hit_this_tile_f offcore_response.pf_software.l2_hit_far_tile umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800400070 Counts Demand code reads and prefetch code read requests that accounts for data responses from MCDRAM Local umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200022 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800200 Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from MCDRAM (local and far) offcore_response.bus_locks.mcdram Counts any Prefetch requests that accounts for responses from MCDRAM (local and far) offcore_response.pf_software.ddr Counts the number of mispredicted near RET branch instructions retired (Precise event) no_alloc_cycles.mispredicts Counts the total number of instructions retired Counts the total page walks that are completed (I-side and D-side) Cycles L1D and L2 locked l1d_cache_lock.m_state l1d_cache_lock_fb_hit umask=0x8,period=2000000,event=0x41 umask=0x2,period=200000,event=0x26 L2 modified lines evicted by a demand request umask=0x4,period=100000,event=0xf2 l2_rqsts.prefetch_miss umask=0x80,period=200000,event=0x24 mem_load_retired.l1d_hit Memory instructions retired above 1024 clocks (Precise Event) offcore_response.any_data.llc_hit_other_core_hit offcore_response.any_ifetch.local_cache_dram offcore_response.any_rfo.local_cache offcore_response.corewb.remote_cache_dram offcore_response.data_ifetch.local_cache_dram offcore_response.data_ifetch.remote_cache_dram offcore_response.data_in.io_csr_mmio Offcore request = all data, response = local cache or dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4703 offcore_response.demand_ifetch.io_csr_mmio Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core Offcore other requests satisfied by any cache or DRAM Offcore other requests satisfied by a remote cache All offcore prefetch data requests umask=0x1,period=100000,event=0xb7,offcore_rsp=0x730 All offcore prefetch data reads Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core offcore_response.pf_rfo.llc_hit_other_core_hit offcore_response.pf_rfo.llc_hit_other_core_hitm Offcore prefetch RFO requests that HITM in a remote cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x270 offcore_response.prefetch.remote_cache_hitm SIMD integer 64 bit shift operations umask=0x1,period=2000000,event=0xd0 umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF8FF Offcore writebacks that missed the LLC Offcore code or data read requests satisfied by the local DRAM Offcore prefetch code reads satisfied by the local DRAM offcore_response.pf_ifetch.remote_dram offcore_response.pf_rfo.remote_dram load_dispatch.rs Flag stall cycles umask=0x2,period=2000000,event=0xd2 Retired branch instructions (Precise Event) Total CPU cycles umask=0xf,period=2000000,event=0x87 Stall cycles due to BPU MRU bypass Instructions retired (Programmable counter and Precise Event) (Precise event) umask=0x40,period=2000000,event=0xa2 umask=0x4,period=2000000,event=0xa2 Uops executed on port 5 umask=0x1,period=2000000,cmask=1,event=0xc2 itlb_misses.any Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle Counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS mem_inst_retired.split_loads umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01001C8000 offcore_response.other.l3_hit_e.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0020004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040100002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0400001 offcore_response.demand_data_rd.l4_hit_local_l4.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00401C0001 offcore_response.demand_data_rd.l3_hit_e.snoop_not_needed Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE frontend_retired.latency_ge_4 frontend_retired.latency_ge_128 umask=0x1,period=100007,event=0xc6,frontend=0x420006 Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles (Must be precise) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000048000 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 4 Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread Counts the number of x87 uops executed This event counts requests originating from the core that references a cache line in the L2 cache umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400000044 Counts data cacheline reads generated by L2 prefetchers that miss L2 with a snoop miss response Counts demand and DCU prefetch instruction cacheline that miss L2 with a snoop miss response Counts demand and DCU prefetch data read that are are outstanding, per cycle, from the time of the L2 miss to when any response is received Stalls due to Memory ordering umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0240 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0120 offcore_response.all_pf_rfo.llc_hit.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0002 Counts demand data writes (RFOs) that hit in the LLC and the snoops sent to sibling cores return clean response offcore_response.pf_l2_rfo.llc_hit.no_snoop_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400200 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f11 REQUEST = ANY IFETCH and RESPONSE = ANY_CACHE_DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0xff08 REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HITM offcore_response.data_ifetch.local_dram_and_remote_cache_hit REQUEST = DEMAND_IFETCH and RESPONSE = IO_CSR_MMIO REQUEST = DEMAND_RFO and RESPONSE = LOCAL_CACHE umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f10 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x40ff umask=0x1,period=100000,event=0xb7,offcore_rsp=0xf803 offcore_response.demand_rfo.other_local_dram offcore_response.pf_rfo.other_local_dram umask=0x80,period=200000,event=0x8 itlb_misses.walk_cycles umask=0x8,period=100007,event=0xd3 Counts demand data reads TBD TBD offcore_response.pf_l3_rfo.l3_hit.no_snoop_needed Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD offcore_response.pf_l1d_and_sw.l3_hit.hit_other_core_no_fwd offcore_response.demand_rfo.l3_hit.snoop_hit_with_fwd offcore_response.demand_code_rd.l3_miss_local_dram.snoop_miss_or_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063FC00010 offcore_response.pf_l3_data_rd.l3_miss.remote_hit_forward offcore_response.pf_l1d_and_sw.l3_miss.snoop_miss_or_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBC000490 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBC000491 offcore_response.all_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd Counts DRAM Page Activate commands sent on this channel due to a write request to the iMC (Memory Controller). Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS (Column Access Select) command unc_cha_requests.reads_remote unc_iio_data_req_of_cpu.mem_write.part3 unc_cha_dir_lookup.no_snp Counts read requests from a remote socket which hit in the HitME cache (used to cache the multi-socket Directory state) to a line in the E(Exclusive) state. This includes the following read opcodes (RdCode, RdData, RdDataMigratory, RdCur, RdInv*, Inv*) Counts every read request for up to a 64 byte transaction of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_m2m_directory_update.any umask=0x4,event=0x37 umask=0x10,event=0x38 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD offcore_response.pf_l3_rfo.l3_hit_f.any_snoop period=200003,umask=0x3f,event=0x24 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400490 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040001 offcore_response.all_rfo.l3_hit_f.hit_other_core_fwd offcore_response.pf_l2_data_rd.l3_hit_f.no_snoop_needed period=100003,umask=0x8,event=0xd2 offcore_response.pf_l2_rfo.l3_hit_f.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080120 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080020 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400122 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020080 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.SNOOP_MISS Counts retired load instructions with at least one uop that missed in the L3 cache Supports address when precise (Precise event) offcore_response.pf_l1d_and_sw.l3_hit_s.any_snoop This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED offcore_response.pf_l3_rfo.l3_hit_s.any_snoop offcore_response.all_rfo.l3_hit_e.hit_other_core_fwd period=2000003,umask=0x81,event=0xd0 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020080 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200020 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02000407F7 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100004 offcore_response.demand_code_rd.l3_hit_f.snoop_none period=100007,umask=0x2,event=0xd3 offcore_response.all_reads.l3_hit_m.no_snoop_needed offcore_response.all_reads.supplier_none.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020001 offcore_response.pf_l3_rfo.pmm_hit_local_pmm.snoop_not_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020002 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02002007F7 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD offcore_response.all_rfo.l3_hit_m.hitm_other_core This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l3_data_rd.l3_hit_s.hitm_other_core This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE offcore_response.pf_l1d_and_sw.l3_hit_e.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200004 offcore_response.all_pf_rfo.l3_hit_f.snoop_miss offcore_response.demand_data_rd.l3_hit_s.hitm_other_core This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80408000 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0002 offcore_response.pf_l2_data_rd.l3_hit_e.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F800407F7 offcore_response.all_rfo.l3_hit_f.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080002 offcore_response.all_reads.l3_hit_f.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C8000 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10002007F7 offcore_response.pf_l1d_and_sw.supplier_none.hit_other_core_no_fwd offcore_response.other.l3_hit_f.no_snoop_needed ( ( 64 * imc@event\=0xe3@ / 1000000000 ) / duration_time ) if 1 if 0 == 1 else 0 else 0 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804008000 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000010 offcore_response.demand_rfo.l3_miss_local_dram.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.SNOOP_MISS ocr.pf_l2_data_rd.l3_miss_local_dram.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000004 period=2000003,umask=0x10,event=0xc9 ocr.pf_l2_data_rd.l3_miss.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000400 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000004 ocr.all_reads.l3_miss.snoop_miss ocr.pf_l2_rfo.l3_miss.remote_hit_forward period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000122 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE ocr.all_pf_rfo.l3_miss_local_dram.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000490 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000122 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00122 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.SNOOP_NONE ocr.pf_l3_data_rd.l3_miss_local_dram.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000080 ALL_READS & L3_MISS & ANY_SNOOP ocr.pf_l2_rfo.l3_miss_local_dram.hit_other_core_no_fwd ocr.pf_l3_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000080 offcore_response.pf_l2_data_rd.l3_miss.hit_other_core_fwd period=100003,umask=0x2,event=0xc3 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD Counts any other requests OTHER & L3_MISS_LOCAL_DRAM & SNOOP_MISS_OR_NO_FWD period=100007,umask=0x1,event=0xcd,ldlat=0x20 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED ocr.all_pf_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000491 offcore_response.demand_data_rd.l3_miss_local_dram.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000400 Counts demand data reads DEMAND_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000002 offcore_response.pf_l2_data_rd.l3_miss_local_dram.hit_other_core_no_fwd ocr.demand_rfo.l3_miss.hitm_other_core offcore_response.all_rfo.l3_miss.no_snoop_needed offcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.snoop_miss ALL_DATA_RD & L3_MISS & REMOTE_HITM This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP ocr.demand_code_rd.l3_miss.hitm_other_core offcore_response.pf_l2_data_rd.l3_miss.no_snoop_needed ALL_DATA_RD & L3_MISS_LOCAL_DRAM & ANY_SNOOP offcore_response.all_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE ALL_READS & L3_MISS & HITM_OTHER_CORE ocr.pf_l2_data_rd.l3_hit_s.hit_other_core_no_fwd ocr.all_reads.l3_hit_m.no_snoop_needed Counts any other requests OTHER & L3_HIT_S & ANY_SNOOP Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_E & HITM_OTHER_CORE Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT & ANY_SNOOP Counts demand data reads DEMAND_DATA_RD & L3_HIT & HIT_OTHER_CORE_FWD ALL_PF_RFO & L3_HIT & HIT_OTHER_CORE_FWD Counts all demand code reads DEMAND_CODE_RD & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWD period=200003,umask=0x7,event=0x28 ALL_PF_DATA_RD & PMM_HIT_LOCAL_PMM & SNOOP_NONE period=200003,umask=0x40,event=0x28 ocr.demand_code_rd.l3_hit_e.hit_other_core_fwd Counts all demand data writes (RFOs) DEMAND_RFO & SUPPLIER_NONE & NO_SNOOP_NEEDED ALL_RFO & L3_HIT_S & SNOOP_NONE ocr.all_reads.l3_hit_f.hitm_other_core ocr.all_data_rd.l3_hit_f.snoop_none ocr.demand_code_rd.l3_hit_s.no_snoop_needed ocr.pf_l2_data_rd.l3_hit.snoop_miss ocr.all_rfo.l3_hit_f.any_snoop ALL_RFO & L3_HIT_F & ANY_SNOOP ocr.all_reads.l3_hit_s.hit_other_core_no_fwd ocr.demand_rfo.l3_hit_f.snoop_miss ALL_RFO & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWD ocr.pf_l3_data_rd.l3_hit_e.hitm_other_core Counts any other requests OTHER & L3_HIT_F & HITM_OTHER_CORE Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWD ocr.demand_data_rd.l3_hit_f.hit_other_core_fwd ocr.all_data_rd.l3_hit_s.hit_other_core_no_fwd Counts all demand code reads DEMAND_CODE_RD & L3_HIT & HIT_OTHER_CORE_NO_FWD ocr.all_pf_data_rd.l3_hit_e.any_snoop ocr.pf_l3_rfo.l3_hit.no_snoop_needed ALL_RFO & L3_HIT_F & NO_SNOOP_NEEDED ocr.pf_l2_data_rd.l3_hit.hitm_other_core Counts all demand code reads DEMAND_CODE_RD & L3_HIT_F & HIT_OTHER_CORE_NO_FWD ocr.pf_l2_rfo.l3_hit.hitm_other_core ocr.pf_l2_rfo.l3_hit_e.snoop_miss ocr.pf_l2_data_rd.l3_hit_f.hit_other_core_no_fwd cmask=1,period=2000003,umask=0x1,event=0xb1 period=2000003,umask=0x20,event=0xa1 cmask=1,inv=1,period=2000003,umask=0x1,event=0xe This event counts return instructions retired Spec update: SKL091 (Precise event) period=100003,umask=0x1,event=0x7 Regular reads(RPQ) commands for Intel Optane DC persistent memory. Unit: uncore_imc umask=0x2,event=0xd3 unc_cha_rxc_irq1_reject.pa_match umask=0x01,event=0x3d unc_iio_data_req_by_cpu.peer_read.part0 Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part1. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part2. Unit: uncore_iio Peer to peer read request for 4 bytes made by IIO Part3 to an IIO target. Unit: uncore_iio unc_iio_txn_req_by_cpu.peer_read.part1 unc_iio_txn_req_by_cpu.peer_write.part1 Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part3 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus period=2000003,umask=0x10,event=0x4f period=100003,umask=0x20,event=0x85 Counts retired load instructions with locked access Supports address when precise (Precise event) Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT14 RCP14 RANGE DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall (Precise event) Cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall Counts cycles when at least 3 micro-ops are executed from any thread on physical core Counts all indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch) (Precise event) TOR Inserts; WCiL misses from local IA. Unit: uncore_cha itlb.fills bp_dyn_ind_pred Retired Taken Branch Instructions ex_ret_brn_tkn_misp The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX) Retired Conditional Branch Instructions Div Cycles Busy count The number of fused retired branch instructions retired per cycle. The number of events logged per cycle can vary from 0 to 3 umask=0xAF,event=0x8b umask=0x6A,event=0x8b df_ccm_reqa.node0.anyrdblk umask=0x05,event=0x8b df_ccm_reqa.node1.rdvlks umask=0x22,event=0x8b df_ccm_reqb.node7.chgtox df_ccm_reqb.node7.wbinvblkall umask=0xCA,event=0x8c umask=0x89,event=0x8c df_ccm_reqb.node6.vicblkcln umask=0x85,event=0x8c umask=0x43,event=0x8c df_ccm_reqb.node6.wrsizedfullncposted umask=0x04,event=0x8d df_ioms_reqa.node0.anyatomic umask=0x05,event=0x108 df_ioms_reqa.node2.anywrsized>32band<64b df_ioms_reqa.node2.anywrsized<32b umask=0xEF,event=0x109 umask=0x2E,event=0x109 umask=0x07,event=0x109 Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized<32b umask=0x04,event=0x109 umask=0x03,event=0x109 df_ioms_reqb.node1.iolargeread The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to pipe 1 fp_ret_sse_avx_ops.dp_div_flops l3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x04,event=0x1 l3_request_g1.t3.s0.rdsizednc l3_request_g1.t6.s0.rdsizednc l3_request_g1.t7.s0.rdsizednc l3_request_g1.t7.s1.rdsizednc l3_request_g1.t0.s2.rdsized l3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x40,event=0x1 l3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x80,event=0x1 l3_request_g1.t1.s1.caching l3_request_g1.t5.s2.caching l3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x80,event=0x1 l3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x02,event=0x3 l3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x02,event=0x3 l3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x08,event=0x3 l3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x08,event=0x3 l3fillvicreq.t7.s0.rdblkx_vic l3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x10,event=0x3 l3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x20,event=0x3 l3fillvicreq.t5.s2.rdblkx l3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x20,event=0x3 l3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x20,event=0x3 l3fillvicreq.t2.s1.rdblkl_vic l3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x40,event=0x3 l3fillvicreq.t5.s3.rdblkl_vic l3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x80,event=0x3 l3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x80,event=0x3 l3fillvicreq.t0.s3.rdblkl l3fillvicreq.t1.s3.rdblkl l3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x01,event=0x9 l3victimstate.t2.s2.nol3victimline l3victimstate.t7.s2.nol3victimline l3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x02,event=0x9 l3victimstate.t4.s1.none_nol3victimline l3victimstate.t0.s2.none_nol3victimline l3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x02,event=0x9 l3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x02,event=0x9 l3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x04,event=0x9 l3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x08,event=0x9 l3victimstate.t3.s2.e_fe l3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x20,event=0x9 l3victimstate.t1.s0.d l3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x40,event=0x9 l3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x40,event=0x9 l3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x40,event=0x9 l3victimstate.t2.s2.od l3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x80,event=0x9 umask=0xff,event=0x45 umask=0x4,event=0x45 L1 DTLB Reload of a page of 32K size ls_tablewalker.dside ls_pref_instr_disp.store_prefetch_w l2_pf_hit_l2 Total number uOps assigned to pipe 2 x87 control word mispredict traps due to mispredictions in RC or PC, or changes in mask bits. The number of serializing Ops retired Retired lock instructions. High speculative cacheable lock speculation succeeded Software Prefetch Data Cache Fills by Data Source. From another cache (home node local) umask=0x40,event=0x5a ls_hw_pf_dc_fill.ls_mabresp_rmt_cache umask=0x10,event=0xae FP_DISPATCHED_FPU_FAST_FLAG_OPS DC_MISALIGNED_DATA_REFERENCE FR_DISPATCH_STALL_WHEN_FPU_IS_FULL ITLB_REFILL EXC_EXECUTED BUS_CYCLES PMUEXTIN_EVT JAVA_BYTECODE CID_WRITE_RETIRED LDST_SPEC EXC_TRAP_DABORT LL_CACHE_RD L2CACHE_READ_MISS L2CACHEMASTER_READ_REQ UNCACHED_BLOCK_CYCLES FETCH_BUFFER_ALLOCATED FSB_FULL_PIPELINE_STALLS DCACHE_LOAD_ACCESSES LOAD_STORE_NO_FILL_REQUESTS BADD TLB_BIT_TRANSITIONS UNRESOLVED_BRANCHES SC_INSTR_COMPLETED LSU_LOAD_VS_STORE_QUEUE_ALIAS_STALL DST_STREAM_1_CACHE_LINE_FETCHES GPR_ISSUE_QUEUE_ENTRIES_OVER_THRESHOLD FOLDED_BRANCHES FXU_COMPLETION_STALL BUS_LOW FINISHED_UNCOND_BRANCHES_MISS_BTB LOADS_TRANSLATED L2_CACHE_DATA_ALLOCATIONS STWCX_SUCCESSES interrupts invalid memory-controller-lo-pri-bypass READ PRECISE P5 metric_expr: %s
UNHALTED_CORE_CYCLES = inst_retired.any v20 SMT Kernel_Utilization l2_rqsts.l2_pf_miss l2_rqsts.miss L2 cache hits when fetching instructions, code reads Retired store uops that miss the STLB. (Precise Event - PEBS) Supports address when precise (Precise event) mem_load_uops_retired.l3_miss Number of SSE/AVX computational scalar single precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element fp_assist.x87_output This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1 idq_uops_not_delivered.cycles_le_1_uop_deliv.core tx_exec.misc3 machine_clears.memory_ordering umask=0x8,period=2000003,event=0xc9 Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details) This event counts loads with latency value being above 16 Spec update: BDM100, BDM35 (Must be precise) Reference cycles when the core is not in halt state umask=0x3,cmask=1,period=2000003,event=0xd uops_issued.stall_cycles uops_issued.slow_lea Thread cycles when thread is not in halt state cpu_clk_unhalted.thread_p_any cpu_clk_unhalted.one_thread_active load_hit_pre.hw_pf br_inst_exec.nontaken_conditional This event counts both taken and not taken speculative and retired mispredicted branch instructions This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3 umask=0x1,period=2000003,event=0xa2 Counts number of cycles the CPU has at least one pending demand* load request missing the L2 cache umask=0x4,cmask=4,period=2000003,event=0xa3 Total execution stalls Execution stalls while memory subsystem has an outstanding load Counts number of cycles the CPU has at least one pending demand load request missing the L1 data cache lsd.cycles_active uops_executed.thread umask=0x2,cmask=1,period=2000003,event=0xb1 uops_executed.core_cycles_ge_4 umask=0x2,period=2000003,event=0xc0 other_assists.any_wb_assist machine_clears.smc umask=0x8,period=100007,event=0xc4 umask=0x20,period=400009,event=0xc4 number of near branch instructions retired that were mispredicted and taken. (Precise Event - PEBS) (Precise event) unc_c_llc_lookup.any MMIO reads. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox umask=0x3,event=0x36,filter_opc=0x182 llc_misses.mem_write event=0x85 Cycles Memory is in self refresh power mode. Unit: uncore_imc umask=0x4,event=0x2 unc_p_power_state_occupancy.cores_c0 dtlb_store_misses.stlb_hit_4k itlb_misses.walk_completed_1g umask=0x11,period=2000003,event=0xbc page_walker_loads.dtlb_l2 umask=0x20,period=100007,event=0xbd Branch Misprediction Cost: Fraction of TopDown slots wasted per non-speculative branch misprediction (jeclear) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020004 offcore_response.demand_code_rd.supplier_none.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0008 offcore_response.pf_l2_code_rd.supplier_none.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020080 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0100 offcore_response.pf_l3_code_rd.l3_hit.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C8000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020090 offcore_response.all_pf_data_rd.l3_hit.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010120 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0240 Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired. Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element umask=0x1,period=2000003,cmask=1,event=0x9c offcore_response.demand_data_rd.l3_miss.snoop_none offcore_response.corewb.l3_miss_local_dram.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0020 offcore_response.pf_l2_code_rd.l3_miss.snoop_hit_no_fwd offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000100 offcore_response.other.l3_miss_local_dram.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000090 offcore_response.all_pf_rfo.supplier_none.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000120 offcore_response.all_pf_code_rd.l3_miss.snoop_none offcore_response.all_pf_code_rd.l3_miss.snoop_miss offcore_response.all_data_rd.l3_miss.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000122 umask=0x1,period=2000003,cmask=4,event=0xb1 A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core unc_cbo_cache_lookup.write_es Retired load uops that split across a cacheline boundary Supports address when precise (Precise event) This event counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting excludes unknown and UC data source Supports address when precise (Precise event) Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache Supports address when precise. Spec update: BDM100 (Precise event) offcore_response.all_data_rd.llc_miss.remote_hitm umask=0x40,period=200000,event=0x21 umask=0x44,period=200000,event=0x28 l2_ld.self.demand.i_state umask=0x71,period=200000,event=0x2e l2_rqsts.self.prefetch.m_state l2_rqsts.self.demand.i_state l2_rqsts.self.demand.mesi l2_reject_busq.self.any.s_state umask=0x10,period=200000,event=0x40 umask=0x20,period=2000000,event=0xb3 umask=0x0,period=200000,event=0x61 ext_snoop.this_agent.hit umask=0xff,period=200000,event=0x3 Mispredicted cond branch instructions retired br_missp_type_retired.cond_taken Retired branch instructions that were predicted taken umask=0x0,period=200003,event=0x31 Requests rejected by the L2Q Cycles code-fetch stalled due to an outstanding ICache miss Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts memory uops retired where the data requested spans a 64 byte cache line boundary Supports address when precise (Must be precise) mem_uops_retired.all umask=0x1,period=200003,event=0xd1 Loads retired that hit WCB (Precise event capable) Supports address when precise (Must be precise) offcore_response.any_read.l2_miss.hitm_other_core Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_rfo.l2_miss.hitm_other_core umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200003091 Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts data cache line reads generated by hardware L1 data cache prefetcher that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cache lines requests by software prefetch instructions that true miss for the L2 cache with a snoop miss in the other processor module Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000040800 Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000040020 offcore_response.demand_code_rd.l2_miss.any Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000002 umask=0x0,period=200003,event=0xca umask=0x1,period=200003,event=0xca Counts core cycles during which there are pending interrupts, but interrupts are masked (EFLAGS.IF = 0) Reference cycles when core is not halted. This event uses a programmable general purpose performance counter Counts machine clears due to memory disambiguation. Memory disambiguation happens when a load which has been issued conflicts with a previous unretired store in the pipeline whose address was not known at issue time, but is later resolved to be the same as the load address br_inst_retired.non_return_ind umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010001 Counts demand cacheable data reads of full cache lines true miss for the L2 cache with a snoop miss in the other processor module Counts data cache line reads generated by hardware L1 data cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.streaming_stores.outstanding umask=0x4,period=20003,event=0xc3 Page walk completed due to a demand data store to a 2M or 4M page Counts the number of store RFO requests that miss the L2 cache Retired load uops misses in L1 cache as data sources Spec update: HSM30. Supports address when precise (Precise event) offcore_response.all_requests.l3_hit.any_response Spec update: HSD56, HSM57 (Precise event) Counts demand data reads miss the L3 and the data is returned from local dram Number of integer move elimination candidate uops that were eliminated Execution stalls due to L1 data cache miss loads. Set Cmask=0CH Unit: uncore_cbox L3 Lookup external snoop request that access cache and found line in I-state page_walker_loads.itlb_memory Counts the number of Extended Page Table walks from the ITLB that hit in memory All retired load uops Supports address when precise. Spec update: HSD29, HSM30 (Precise event) All retired store uops Supports address when precise. Spec update: HSD29, HSM30 (Precise event) Far branch instructions retired l2_l1d_wb_rqsts.hit_m Retired load uops with L2 cache hits as data sources (Precise event) mem_load_uops_llc_miss_retired.local_dram L2 or LLC HW prefetches that access L2 cache umask=0xa,period=100003,event=0xf2 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0091 Counts all demand data writes (RFOs) that hit in the LLC umask=0x1,period=100003,event=0xb7,offcore_rsp=0x18000 Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle Loads with latency value being above 64 (Must be precise) offcore_response.demand_data_rd.llc_miss.dram Filter on cross-core snoops initiated by this Cbox due to external snoop request Unit: uncore_arb Counts the number of allocated write entries, include full, partial, and LLC evictions LLC lookup request that access cache and found line in E-state or S-state umask=0x81,period=100003,event=0x8 umask=0x88,period=100003,event=0x8 offcore_response.pf_llc_data_rd.llc_hit.hit_other_core_no_fwd Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded LLC prefetch misses for RFO. Derived from unc_c_tor_inserts.miss_opcode.rfo_prefetch. Unit: uncore_cbox LLC misses for ItoM writes (as part of fast string memcpy stores). Derived from unc_c_tor_inserts.miss_opcode.itom_write. Unit: uncore_cbox umask=0x1,event=0x35,filter_opc=0x1c8 llc_references.pcie_ns_write Cycles where receiving QPI link is in half-width mode. Unit: uncore_qpi unc_p_freq_ge_3000mhz_cycles Data from local DRAM either Snoop not needed or Snoop Miss (RspI) umask=0x8,period=2000003,event=0x51 Cases of cancelling valid DSB fill not because of exceeding way limit agu_bypass_cancel.count umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000070 offcore_response.partial_streaming_stores.any_response umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000402000 offcore_response.partial_writes.l2_hit_near_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080002 Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008000002 Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in S state offcore_response.any_request.l2_hit_this_tile_s umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000020 Counts any request that accounts for responses which hit its own tile's L2 with data in F state offcore_response.any_pf_l2.l2_hit_this_tile_f offcore_response.uc_code_reads.l2_hit_near_tile offcore_response.partial_reads.l2_hit_far_tile Counts any Read request that accounts for data responses from MCDRAM Local umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800040 Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Far offcore_response.uc_code_reads.mcdram offcore_response.any_data_rd.mcdram Counts Demand cacheable data writes that accounts for responses from DDR (local and far) umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181802000 Counts Demand code reads and prefetch code read requests that accounts for responses from DDR (local and far) umask=0x4,period=200003,event=0xca Counts the number of occurences a retired load that is a cache line split. Each split should be counted only once Supports address when precise (Precise event) Counts the store micro-ops retired that were pushed in the rehad queue because the store address buffer is full unc_m_cas_count.wr umask=0x2,period=100003,edge=1,event=0x5 l1d_prefetch.triggers L1 writebacks to L2 in I state (misses) L2 lines alloacated L2 lines evicted by a demand request umask=0x2,period=100000,event=0xf2 l2_rqsts.ifetch_hit l2_write.rfo.i_state offcore_requests.l1d_writeback Memory instructions retired above 32768 clocks (Precise Event) offcore_response.any_data.llc_hit_other_core_hitm umask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF44 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x8044 Offcore requests satisfied by the LLC and HIT in a sibling core offcore_response.any_rfo.llc_hit_other_core_hitm Offcore RFO requests satisfied by the LLC umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1808 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x133 Offcore demand code reads satisfied by the IO, CSR, MMIO unit offcore_response.demand_ifetch.local_cache Offcore demand RFO requests satisfied by any cache or DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3802 Offcore prefetch code reads satisfied by any cache or DRAM offcore_response.pf_ifetch.remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x8070 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x770 Offcore requests satisfied by any DRAM Offcore requests satisfied by the local DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0x6077 Offcore request = all data, response = any LLC miss offcore_response.data_in.remote_dram Offcore data reads, RFO's and prefetches statisfied by the remote DRAM offcore_response.pf_data_rd.any_dram umask=0x1,period=2000000,event=0xd5 umask=0x4,period=20000,event=0x88 Call branches executed Instruction Queue full stall cycles Retired MMX instructions (Precise Event) MXCSR rename stall cycles Stack pointer sync operations uops_executed.port5 Retired stores that miss the DTLB (Precise Event) umask=0xd8,period=200003,event=0x24 offcore_response.demand_code_rd.l4_hit_local_l4.snoop_none offcore_response.demand_rfo.l4_hit_local_l4.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400100002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100080001 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400040001 offcore_response.demand_data_rd.supplier_none.spl_hit Cycles with less than 3 uops delivered by the front-end Retired Instructions who experienced STLB (2nd level TLB) true miss. Precise Event (Precise event) frontend_retired.latency_ge_8 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall. Precise Event (Precise event) Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall. Precise Event (Precise event) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x007C408000 offcore_response.demand_rfo.l3_miss_local_dram.snoop_miss umask=0x80,period=2000003,event=0xd umask=0x4,period=2000003,event=0xa6 Return instructions retired Spec update: SKL091 (Precise event) inst_retired.any / mem_inst_retired.all_loads Unit: uncore_arb Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic Counts demand data stores that caused a completed page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels. The page walk can end with or without a fault Store uops that split cache line boundary Any reissued store uops umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680000022 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680002000 Counts DCU hardware prefetcher data read that miss L2 with a snoop miss response Counts demand reads of partial cache lines (including UC and WC) that miss L2 offcore_response.pf_l2_rfo.l2_miss.snoop_miss Counts writeback (modified to exclusive) that miss L2 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680000001 NON_RETURN_IND counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa. When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event) This event counts when an instruction (I) page walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks Retired load uops with L1 cache hits as data sources. (Precise Event - PEBS) (Precise event) umask=0x2,period=100007,event=0xd4 offcore_response.pf_l2_code_rd.llc_hit.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400080 umask=0x80,period=100000,event=0xb0 offcore_requests.demand.read_code umask=0x1,period=100000,event=0xb0 umask=0x8,period=2000000,event=0x60 offcore_requests_outstanding.demand.read_code_not_empty umask=0x1,period=2000000,cmask=1,event=0x60 umask=0x4,period=2000000,event=0x60 REQUEST = ANY_DATA read and RESPONSE = IO_CSR_MMIO REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HIT offcore_response.any_ifetch.all_local_dram_and_remote_cache_hit REQUEST = DEMAND_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = PF_DATA and RESPONSE = ANY_LOCATION REQUEST = PF_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5040 REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM offcore_response.any_ifetch.any_dram_and_remote_fwd REQUEST = ANY IFETCH and RESPONSE = OTHER_LOCAL_DRAM REQUEST = DATA_IFETCH and RESPONSE = ANY_LLC_MISS umask=0x1,period=100000,event=0xb7,offcore_rsp=0xf833 offcore_response.demand_data.any_dram_and_remote_fwd umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3080 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5801 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1850 offcore_response.pf_l3_rfo.l3_hit.hitm_other_core umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0491 offcore_response.pf_l1d_and_sw.l3_hit.snoop_hit_with_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0604000001 offcore_response.pf_l2_data_rd.l3_miss.remote_hitm offcore_response.all_pf_data_rd.l3_miss.remote_hit_forward umask=0x1,period=100003,event=0xb7,offcore_rsp=0x083FC00491 Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions Rate of non silent evictions from the L2 cache per Kilo instruction cha_0@event\=0x0@ Read Pending Queue Allocations. Unit: uncore_imc Counts the number of read requests allocated into the Read Pending Queue (RPQ). This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. The requests deallocate after the read CAS command has been issued to DRAM. This event counts both Isochronous and non-Isochronous requests which were issued to the RPQ PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0. Unit: uncore_iio Counts only multi-socket cacheline Directory state updates due to memory writes issued from the TOR pipe which are the result of remote transaction hitting the SF/LLC and returning data Core2Core. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) to the MMIO space of a card on IIO Part0. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state, and found the cacheline marked in the A (SnoopAll) state, indicating the cacheline is stored in another socket in any state, and we must snoop the other sockets to make sure we get the latest data. The data may be stored in any state in the local socket Reads to iMC issued at Normal Priority (Non-Isochronous). Unit: uncore_m2m Idle FLITs transmitted. Unit: uncore_upi ll This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040010 offcore_response.pf_l3_data_rd.l3_hit_e.no_snoop_needed offcore_response.pf_l3_data_rd.l3_hit_s.any_snoop offcore_response.all_pf_data_rd.pmm_hit_local_pmm.snoop_none offcore_response.all_data_rd.supplier_none.hit_other_core_no_fwd offcore_response.all_data_rd.l3_hit_s.snoop_none offcore_response.all_rfo.pmm_hit_local_pmm.snoop_not_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020010 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED offcore_response.all_data_rd.l3_hit_m.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040491 This event is deprecated. Refer to new event OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080100 This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200010 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080491 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0400 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200122 offcore_response.pf_l1d_and_sw.l3_hit_f.no_snoop_needed offcore_response.demand_rfo.l3_hit_m.no_snoop_needed period=200003,umask=0xe7,event=0x24 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD period=2000003,umask=0x1,event=0x60 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0122 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020490 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080020 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0122 offcore_response.pf_l1d_and_sw.l3_hit.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080108000 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080002 offcore_response.all_reads.supplier_none.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040400 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080122 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE offcore_response.all_reads.l3_hit_f.hit_other_core_fwd offcore_response.all_reads.l3_hit.snoop_miss This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.SNOOP_NONE This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP offcore_response.pf_l1d_and_sw.l3_hit_e.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED offcore_response.pf_l3_data_rd.l3_hit_s.hit_other_core_no_fwd offcore_response.pf_l3_data_rd.l3_hit_e.hit_other_core_fwd This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C8000 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200002 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080004 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall (Precise event) period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000004 ALL_PF_RFO & L3_MISS & ANY_SNOOP ocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.snoop_miss ocr.other.l3_miss_local_dram.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800122 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD ocr.all_reads.l3_miss_local_dram.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000002 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000491 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000120 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000001 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000002 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP Counts demand data reads DEMAND_DATA_RD & L3_MISS & HIT_OTHER_CORE_FWD ocr.pf_l3_data_rd.l3_miss.remote_hitm Counts any other requests OTHER & L3_MISS & SNOOP_MISS This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000080 ALL_RFO & L3_MISS_REMOTE_HOP1_DRAM & SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000004 Counts any other requests OTHER & L3_MISS & HIT_OTHER_CORE_NO_FWD ocr.all_data_rd.l3_miss.snoop_miss Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS & SNOOP_MISS ocr.all_pf_rfo.l3_miss_remote_hop1_dram.no_snoop_needed This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000080 Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS & REMOTE_HITM offcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.snoop_miss ocr.demand_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd ocr.pf_l3_data_rd.l3_miss.no_snoop_needed ALL_PF_RFO & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS ocr.pf_l2_data_rd.l3_miss.hit_other_core_no_fwd Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_FWD ocr.pf_l1d_and_sw.l3_miss.hit_other_core_fwd ALL_RFO & SUPPLIER_NONE & SNOOP_MISS ocr.all_pf_rfo.l3_hit_s.hit_other_core_fwd Counts all demand code reads DEMAND_CODE_RD & L3_HIT_E & ANY_SNOOP Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_F & HIT_OTHER_CORE_NO_FWD Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_E & HIT_OTHER_CORE_NO_FWD ocr.pf_l3_data_rd.pmm_hit_local_pmm.snoop_not_needed ALL_RFO & L3_HIT_M & HITM_OTHER_CORE ocr.pf_l2_rfo.l3_hit_e.hit_other_core_no_fwd ocr.all_reads.supplier_none.any_snoop ocr.pf_l2_rfo.l3_hit_s.hitm_other_core ALL_PF_RFO & L3_HIT_M & SNOOP_NONE ocr.pf_l3_rfo.l3_hit_e.hitm_other_core ocr.pf_l3_data_rd.supplier_none.hit_other_core_no_fwd ocr.demand_data_rd.l3_hit_m.any_snoop ocr.pf_l2_data_rd.l3_hit_s.snoop_miss Counts any other requests OTHER & PMM_HIT_LOCAL_PMM & SNOOP_NONE Counts any other requests OTHER & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDED ALL_DATA_RD & L3_HIT_E & HITM_OTHER_CORE ocr.all_pf_data_rd.supplier_none.no_snoop_needed ALL_DATA_RD & L3_HIT & ANY_SNOOP ALL_RFO & L3_HIT & SNOOP_NONE ALL_RFO & L3_HIT & HIT_OTHER_CORE_FWD Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_E & HIT_OTHER_CORE_FWD ALL_PF_DATA_RD & L3_HIT_M & SNOOP_MISS Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_M & HIT_OTHER_CORE_NO_FWD ocr.all_pf_rfo.l3_hit_s.snoop_miss ocr.demand_code_rd.pmm_hit_local_pmm.any_snoop ALL_PF_RFO & L3_HIT_M & SNOOP_MISS ocr.pf_l3_data_rd.l3_hit_m.hitm_other_core ocr.pf_l2_rfo.l3_hit_m.hit_other_core_fwd ALL_PF_DATA_RD & L3_HIT_S & SNOOP_NONE Counts any other requests OTHER & L3_HIT & HITM_OTHER_CORE ocr.all_reads.l3_hit_s.any_snoop This event counts far branch instructions retired Spec update: SKL091 (Precise event) cmask=16,period=2000003,umask=0x10,event=0xa3 period=100003,umask=0x8,event=0x3 unc_m_pmm_rpq_inserts + unc_m_pmm_wpq_inserts umask=0x8,event=0xea Write commands for Intel Optane DC persistent memory. Unit: uncore_imc Lines Victimized; Lines in S State. Unit: uncore_cha Peer to peer write request of 4 bytes made to IIO Part3 by a different IIO unit. Unit: uncore_iio Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus Write request of up to a 64 byte transaction is made to IIO Part2 by the CPU. Unit: uncore_iio Write request of up to a 64 byte transaction is made to IIO Part3 by the CPU. Unit: uncore_iio unc_iio_txn_req_of_cpu.peer_read.part0 unc_iio_txn_req_of_cpu.peer_read.part1 Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.peer_write.part1 Multi-socket cacheline Directory lookup (cacheline found in S state). Unit: uncore_m2m Counts when the a new entry is Received(RxC) and then added to the AD (Address Ring) Ingress Queue from the CMS (Common Mesh Stop). This is generally used for reads, and Counts retired Instructions who experienced Instruction L1 Cache true miss (Precise event) umask=0x4,period=10000003,event=0 Counts the number of times a load got blocked due to false dependencies in MOB due to partial compare on address Number of uops executed on port 1 Counts cycles when at least 4 micro-ops are executed from any thread on physical core Counts the number of machine clears (nukes) of any type Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path Supports address when precise (Precise event) Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 Data requested of the CPU : Card writing to DRAM. Unit: uncore_iio Clockticks of the mesh to PCI (M2P). Unit: uncore_m2pcie The number of instruction fetches that miss in both the L1 and L2 TLBs ic_fetch_stall.ic_stall_any The number of ITLB reload requests umask=0x1,event=0x60 umask=0x40,event=0x64 Retired Far Control Transfers df_ccm_reqa.node6.anydram Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullnc umask=0x68,event=0x8b umask=0x88,event=0x8b df_ccm_reqa.node1.rdvlkc umask=0x61,event=0x8b df_ccm_reqb.node2.chgtox df_ccm_reqb.node1.wbinvblkall umask=0x25,event=0x8c df_ccm_reqb.node2.wrsizedfullnc umask=0x42,event=0x8c df_ccm_reqb.node7.rdsized Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) ios_resp df_ioms_reqa.node7.fence umask=0xE9,event=0x108 df_ioms_reqa.node3.anydramtransaction df_ioms_reqa.node7.anydramtransaction umask=0xE8,event=0x108 umask=0x46,event=0x108 df_ioms_reqa.node4.anywrsized=64b umask=0x86,event=0x108 umask=0x25,event=0x108 umask=0x44,event=0x108 df_ioms_reqa.node6.anywrsized=32b df_ioms_reqa.node3.anyrdsized df_ioms_reqb.node3.piesystemmanagement umask=0x0D,event=0x109 Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized=64b umask=0x8A,event=0x109 df_ioms_reqb.node1.ioanynon-postedwrsized<32b umask=0x45,event=0x109 df_ioms_reqb.node3.iolargeread The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to pipe 3 Total number multi-pipe uOps assigned to pipe 2 Total number of fp uOps on pipe 0 The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 0 fp_retired_ser_ops.sse_ctrl_ret l3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x02,event=0x1 l3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x02,event=0x1 l3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x02,event=0x1 l3_request_g1.t7.s1.rdsized l3fillvicreq.t6.s1.vicblk l3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x01,event=0x3 l3fillvicreq.t0.s3.vicblk l3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x01,event=0x3 l3fillvicreq.t4.s3.vicblk l3fillvicreq.t6.s2.chgtox l3fillvicreq.t4.s1.rdblkc_s_vic l3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x08,event=0x3 l3fillvicreq.t6.s1.rdblkc_s l3fillvicreq.t2.s3.rdblkc_s l3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x10,event=0x3 l3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x10,event=0x3 l3fillvicreq.t2.s2.rdblkx_vic l3fillvicreq.t6.s3.rdblkx_vic l3fillvicreq.t7.s3.rdblkx_vic l3fillvicreq.t3.s3.rdblkx l3fillvicreq.t6.s2.rdblkl_vic l3fillvicreq.t5.s0.rdblkl l3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x80,event=0x3 l3victimstate.t6.s0.none_nol3victimline l3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x04,event=0x9 l3victimstate.t6.s0.o l3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x08,event=0x9 l3victimstate.t0.s0.e_fe l3victimstate.t2.s0.e_fe l3victimstate.t3.s1.e_fe l3victimstate.t4.s3.e_fe l3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x20,event=0x9 l3victimstate.t0.s1.m l3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x40,event=0x9 l3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x80,event=0x9 l3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x80,event=0x9 l3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x80,event=0x9 ls_dispatch.ld_dispatch ls_mab_alloc.dc_prefetcher ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss Total Page Table Walks IC Type 0 ls_tablewalker.dc_type1 umask=0x1,event=0x4b umask=0x2,event=0x28a bp_l1_tlb_fetch_hit.if1g ls_sw_pf_dc_fill.ls_mabresp_lcl_dram Hardware Prefetch Data Cache Fills by Data Source. Local L2 hit ERROR: pmc_pmu_allocate failed, check for ctrname %s
BU_INTERNAL_L2_REQUEST FR_RETIRED_FPU_INSTRUCTIONS FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS FR_FPU_EXCEPTIONS FR_NUMBER_OF_BREAKPOINTS_FOR_DR1 NB_HT_BUS0_BANDWIDTH INSTR_RENAMED DMB_STALL DATA_ENGINE_CLOCK_ENABLED L1I_CACHE INST_SPEC MEM_ACCESS_ST STREX_PASS_SPEC DTLB_WALK MEM_BYTE_READ TAGCACHE_WRITE_MISS BRANCH_COMPLETED ICACHE_ACCESSES OOO_ALU_ISSUE_CYCLES PREFETCH_INSNS TRAP VPU_INSTR_COMPLETED L1_DATA_SNOOP_HIT_ON_MODIFIED LSU_TOUCH_ALIAS_VS_CSQ FP_ONE_QUARTER_FPSCR_RENAMES_BUSY FP_ALL_FPSCR_RENAMES_BUSY L1_DATA_TOUCH_MISS_CYCLES TLBSYNC_INSTR_COMPLETED L2_CACHE_HITS L3_EXTERNAL_INTERVENTIONS TIMEBASE_EVENT DCACHE_MISS_COMPLETION_STALL store-pipe-excluding-junk-ops hs locked-instructions low-op-pos-0 probe-hit-dirty-no-memory-cancel + INTEL_ATOM_GOLDMONT /usr/src/lib/libpmc/pmclog.c BRANCH_MISSES_RETIRED {"type": "proc_create" C6_Pkg_Residency L2 prefetch requests that miss L2 cache L2 prefetch requests that hit L2 cache This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch.
Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type umask=0x8,cmask=1,period=2000003,event=0x60 umask=0x8,period=100003,event=0xb0 offcore_requests_buffer.sq_full mem_load_uops_retired.l1_miss This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were load uops missed L1 but hit a fill buffer due to a preceding miss to the same cache line with the data not ready.
Note: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load Supports address when precise (Precise event) Demand Data Read requests that access L2 cache other_assists.sse_to_avx Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy RTM region detected inside HLE hle_retired.aborted hle_retired.aborted_misc2 cpl_cycles.ring123 Instructions retired from execution This event counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when:
- preceding store conflicts with the load (incomplete overlap);
- store forwarding is impossible due to u-arch limitations;
- preceding lock RMW operations are not forwarded;
- store has the no-forward bit set (uncacheable/page-split/masked stores);
- all-blocking stores are used (mostly, fences and port I/O);
and others.
The most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events.
See the table of not supported store forwards in the Optimization Guide umask=0xff,period=200003,event=0x88 br_misp_exec.taken_return_near umask=0x4,period=2000003,event=0xa2 br_inst_retired.all_branches_pebs This is a precise version of BR_MISP_RETIRED.ALL_BRANCHES that counts all mispredicted macro branch instructions retired (Must be precise) Uncore cache clock ticks. Unit: uncore_cbox All LLC Misses (code+ data rd + data wr - including demand and prefetch). Unit: uncore_cbox M line evictions from LLC (writebacks to memory). Unit: uncore_cbox llc_misses.uncacheable unc_h_snoop_resp.rspcnflct Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M) Spec update: BDM69 umask=0x60,period=100003,event=0x49 This event counts cycles for an extended page table walk. The Extended Page directory cache differs from standard TLB caches by the operating system that use it. Virtual machine operating systems use the extended page directory cache, while guest operating systems use the standard TLB caches itlb_misses.walk_duration itlb.itlb_flush idq_uops_not_delivered.core / (4 * cycles) L1MPKI Fraction of cycles where both hardware Logical Processors were active umask=0x1,period=2000003,cmask=6,event=0x60 Retired load uops which data sources were HitM responses from shared L3. (Precise Event - PEBS) Spec update: BDM100. Supports address when precise (Precise event) Counts all demand data writes (RFOs) have any response type offcore_response.pf_l2_code_rd.l3_hit.snoop_hit_no_fwd offcore_response.pf_l3_data_rd.supplier_none.snoop_none offcore_response.pf_l3_data_rd.supplier_none.snoop_hit_no_fwd offcore_response.pf_l3_data_rd.l3_hit.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020200 offcore_response.other.supplier_none.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0120 offcore_response.all_data_rd.l3_hit.snoop_not_needed offcore_response.all_data_rd.l3_hit.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0091 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010122 Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element Counts randomly selected loads with latency value being above 128 Spec update: BDM100, BDM35 (Must be precise) offcore_response.corewb.l3_miss.snoop_miss offcore_response.pf_l2_data_rd.supplier_none.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020020 offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_none offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_hitm offcore_response.pf_l2_rfo.l3_miss.snoop_not_needed offcore_response.pf_l2_rfo.l3_miss.snoop_miss offcore_response.pf_l3_data_rd.l3_miss.snoop_not_needed offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000100 offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000240 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000240 offcore_response.all_pf_code_rd.l3_miss.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0091 Unit: uncore_cbox A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core Unit: uncore_cbox A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core unc_cbo_cache_lookup.read_i umask=0x1f,event=0x34 unc_cbo_cache_lookup.any_es umask=0x26,event=0x34 offcore_response.all_requests.llc_miss.any_response uncore_qpi umask=0x40,period=200000,event=0x26 l2_m_lines_out.self.demand l2_ld.self.prefetch.e_state l2_ld.self.prefetch.m_state umask=0x5f,period=200000,event=0x29 umask=0x44,period=200000,event=0x2d l2_rqsts.self.any.s_state umask=0x71,period=200000,event=0x30 l2_reject_busq.self.prefetch.m_state umask=0x52,period=200000,event=0x30 l1d_cache.ld Floating point computational micro-ops executed umask=0x8,period=2000000,event=0xb3 simd_uop_type_exec.logical.s umask=0x8,period=2000000,event=0xca Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions Icache miss umask=0x2,period=2000000,event=0xaa umask=0x91,period=200000,event=0x5 prefetch.sw_l2 dispatch_blocked.any Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions bus_lock_clocks.self Invalidate bus transactions umask=0xe0,period=200000,event=0x6a umask=0x40,period=200000,event=0x7d Hardware interrupts received Good store forwards umask=0x1,period=2000000,event=0x13 All macro unconditional branch instructions, excluding calls and indirects br_missp_type_retired.cond umask=0x1,period=200000,event=0xc3 br_inst_retired.any umask=0x21,period=200003,event=0xd0 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x02000032b7 Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts reads for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data reads (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_pf_data_rd.l2_miss.hitm_other_core offcore_response.any_request.any_response Counts data cache line reads generated by hardware L1 data cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000000800 offcore_response.pf_l2_data_rd.l2_hit Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_data_rd.outstanding Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is in the ICache (hit). The event strives to count on a cache line basis, so that multiple accesses which hit in a single cache line count as one ICACHE.HIT. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture umask=0x3,period=200003,event=0x80 misalign_mem_ref.store_page_split Counts loads blocked because they are unable to find their physical address in the micro TLB (UTLB) (Must be precise) ld_blocks.all_block Integer divide uops retired. (Precise Event Capable) (Must be precise) Counts BACLEARS on return instructions Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache true miss for the L2 cache with a snoop miss in the other processor module Counts bus lock and split lock requests have any transaction responses from the uncore subsystem Counts data cache lines requests by software prefetch instructions true miss for the L2 cache with a snoop miss in the other processor module umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000001000 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010022 umask=0x0,period=2000003,event=0xc0 umask=0x20,period=20003,event=0xc3 Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 1GB pages. The page walks can end with or without a page fault umask=0x2,period=2000003,event=0x49 umask=0x4,period=2000003,event=0x49 Page walks outstanding due to a demand data store every cycle Data read requests sent to uncore (demand and prefetch) Retired store uops that miss the STLB. (precise Event) Spec update: HSD29, HSM30. Supports address when precise (Precise event) This event counts uops delivered by the Front-end with the assistance of the microcode sequencer. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance This event counts Instruction Cache (ICACHE) misses hsw metrics Number of times a transactional abort was signaled due to a data capacity limitation for transactional writes umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01004007F7 offcore_response.pf_l3_code_rd.l3_miss.any_response Cycles which a uop is dispatched on port 6 in this thread Resource-related stall cycles Spec update: HSD135 Mispredicted macro branch instructions retired (Must be precise) umask=0x41,event=0x34 DTLB demand load misses with low part of linear-to-physical address translation missed Counts the number of Extended Page Table walks from the DTLB that hit in the L2 Retired load uop whose Data Source was: Remote cache HITM Supports address when precise. Spec update: HSM30 (Precise event) offcore_response.pf_llc_data_rd.llc_hit.any_response Number of X87 FP assists due to output values umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0600400244 Retired load uops which data sources were data hits in LLC without snoops required (Precise event) mem_load_uops_llc_hit_retired.xsnp_none offcore_response.all_data_rd.llc_hit.any_response Counts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0002 Loads with latency value being above 32 (Must be precise) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400091 offcore_response.all_reads.llc_miss.dram Counts the number of executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0 unc_cbo_xsnp_response.external_filter unc_cbo_cache_lookup.e Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c03f7 offcore_response.other.lru_hints umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0010 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0010 Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response Counts demand data reads that miss in the LLC offcore_response.pf_l2_data_rd.llc_miss.local_dram PCIe allocating writes that hit in LLC (DDIO hits). Derived from unc_c_tor_inserts.opcode.ddio_hit. Unit: uncore_cbox PCIe non-snoop writes (full line). Derived from unc_c_tor_inserts.opcode.pcie_full_write. Unit: uncore_cbox Occupancy for all LLC misses that are addressed to remote memory. Unit: uncore_cbox (unc_q_rxl0p_power_cycles / unc_q_clockticks) * 100. Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. (filter_band1=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Unit: uncore_pcu This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a non-modified state Retired load uops which data sources were HitM responses from shared LLC This event counts L1D data line replacements. Replacements occur when a new line is brought into the cache, causing eviction of a line loaded earlier This event counts the number of cycles with at least one slow LEA uop being allocated. A uop is generally considered as slow LEA if it has three sources (for example, two sources and immediate) regardless of whether it is a result of LEA instruction or not. Examples of the slow LEA uop are or uops with base, index, and offset source operands using base and index reqisters, where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel? 64 and IA-32 Architectures Optimization Reference Manual for more details about slow LEA instructions Retired instructions experiencing ITLB misses Each cycle there was a miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING umask=0xc,period=2000003,event=0x5b resource_stalls2.ooo_rsrc Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. (filter_band1=XXX with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Unit: uncore_pcu l2_requests.miss This event counts the number of load micro-ops retired that miss in L1 Data cache. Note that prefetch misses will not be counted Counts Demand code reads and prefetch code read requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400022 Counts Demand cacheable data write requests that accounts for any response umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400004 offcore_response.demand_data_rd.l2_hit_far_tile_m Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses which hit its own tile's L2 with data in M state offcore_response.partial_reads.l2_hit_this_tile_e Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in S state umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008000400 offcore_response.any_code_rd.l2_hit_this_tile_s Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in F state Counts L1 data HW prefetches that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800188000 Counts Demand code reads and prefetch code read requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state offcore_response.any_rfo.l2_hit_far_tile offcore_response.any_code_rd.l2_hit_far_tile umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800070 Counts any Read request that accounts for data responses from MCDRAM Far or Other tile L2 hit far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x00808032f7 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080202000 Counts Software Prefetches that accounts for data responses from DRAM Far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400400 offcore_response.partial_writes.mcdram_near offcore_response.pf_l2_code_rd.mcdram_far offcore_response.pf_l2_rfo.ddr_far offcore_response.demand_rfo.ddr umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181801000 offcore_response.any_rfo.ddr Counts the number of branch instructions retired that were conditional jumps (Precise event) umask=0x90,period=200003,event=0xca rs_full_stall.mec rs_full_stall.all Cycles the number of core cycles when divider is busy. Does not imply a stall waiting for the divider l1d_cache_lock.e_state umask=0x2,period=100000,event=0x28 l2_transactions.ifetch L2 Load transactions L2 prefetch transactions L2 demand lock RFOs in S state Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event) umask=0x1,period=100000,event=0xb2 Offcore requests blocked due to Super Queue full mem_inst_retired.latency_above_threshold_0 mem_inst_retired.latency_above_threshold_16 Memory instructions retired above 16 clocks (Precise Event) mem_inst_retired.latency_above_threshold_8192 offcore_response.any_ifetch.llc_hit_other_core_hit offcore_response.any_ifetch.remote_cache_hitm offcore_response.any_rfo.any_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1822 All offcore writebacks umask=0x1,period=100000,event=0xb7,offcore_rsp=0x8008 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x408 Offcore code or data read requests satisfied by the IO, CSR, MMIO unit offcore_response.data_ifetch.local_cache Offcore request = all data, response = remote cache or dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x401 Offcore demand code reads that HITM in a remote cache offcore_response.demand_rfo.llc_hit_no_other_core umask=0x1,period=100000,event=0xb7,offcore_rsp=0x202 offcore_response.other.remote_cache_hit offcore_response.pf_data_rd.io_csr_mmio umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1810 Offcore prefetch data reads that HITM in a remote cache umask=0x80,period=2000000,event=0x10 SSE FP packed Uops Offcore data reads satisfied by any DRAM offcore_response.data_ifetch.remote_dram offcore_response.demand_data_rd.any_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x6001 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2001 Offcore demand RFO requests satisfied by the local DRAM Loads dispatched from the MOB partial_address_alias snoop_response.hite umask=0x7,period=200000,event=0x88 br_inst_exec.taken br_misp_exec.indirect_near_call Cycles no uops were delivered by the LSD resource_stalls.fpcw Retired load instructions which data sources were L3 hit and cross-core snoop missed in on-pkg core cache Supports address when precise (Precise event) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100408000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040108000 offcore_response.other.l3_hit_e.snoop_hit_no_fwd offcore_response.other.l3_hit_m.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0028000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400100004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040100004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080100002 offcore_response.demand_data_rd.l3_hit_e.any_snoop Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ Retired Instructions who experienced Instruction L2 Cache true miss. Precise Event (Precise event) Counts retired Instructions that experienced iTLB (Instruction TLB) true miss (Precise event) umask=0x1,period=100007,event=0xc6,frontend=0x300206 Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency (Must be precise) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x103C400004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFC400001 uops_issued.vector_width_mismatch exe_activity.4_ports_util inv=1,umask=0x1,period=2000003,cmask=10,event=0xc0 Taken branch instructions retired Spec update: SKL091 (Precise event) This is a precise version (that is, uses PEBS) of the event that counts taken branch instructions retired Spec update: SKL091 (Precise event) umask=0x10,period=100003,cmask=1,event=0x8 Counts cycles that fetch is stalled due to an outstanding ICache miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ICache miss. Note: this event is not the same as the total number of cycles spent retrieving instruction cache lines from the memory hierarchy.
Counts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes. This will include cycles due to an ITLB miss, ICache miss and other events rehabq.lock Counts any code reads (demand & prefetch) that miss L2 with a snoop miss response Counts demand and DCU prefetch RFOs that are are outstanding, per cycle, from the time of the L2 miss to when any response is received RETURN counts the number of near RET branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) This event counts the number of load uops retired (Precise Event) (Precise event) Retired load uops which data sources were data hits in LLC without snoops required. (Precise Event - PEBS) (Precise event) Counts prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean response Counts demand & prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean response Counts demand code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded Counts demand data writes (RFOs) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2380408000 offcore_response.pf_l2_code_rd.llc_hit.hit_other_core_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0020 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0200 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0100 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10080 offcore_response.all_pf_code_rd.llc_miss.dram This event counts all data requests (demand/prefetch data reads and demand data writes (RFOs) that miss the LLC where the data is returned from local DRAM umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1f80408fff REQUEST = DATA_IN and RESPONSE = LLC_HIT_NO_OTHER_CORE REQUEST = DATA_IN and RESPONSE = LOCAL_CACHE offcore_response.demand_ifetch.all_local_dram_and_remote_cache_hit offcore_response.pf_ifetch.local_dram_and_remote_cache_hit offcore_response.any_data.any_dram_and_remote_fwd offcore_response.any_ifetch.other_local_dram REQUEST = ANY RFO and RESPONSE = REMOTE_DRAM offcore_response.pf_ifetch.other_local_dram load_block.overlap_store snoopq_requests_outstanding.data snoopq_requests_outstanding.data_not_empty umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5820 Retired load instructions which data sources missed L3 but serviced from remote dram Supports address when precise (Precise event) Counts L1 data cache hardware prefetch requests and software prefetch requests have any response type umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0400 Counts demand data reads TBD umask=0x1,period=100003,event=0xb7,offcore_rsp=0x103FC00100 offcore_response.all_pf_rfo.l3_miss.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0604000120 edge=1,umask=0x0,cmask=1,period=100007,event=0x3c ( (( 1 * ( fp_arith_inst_retired.scalar_single + fp_arith_inst_retired.scalar_double ) + 2 * fp_arith_inst_retired.128b_packed_double + 4 * ( fp_arith_inst_retired.128b_packed_single + fp_arith_inst_retired.256b_packed_double ) + 8 * ( fp_arith_inst_retired.256b_packed_single + fp_arith_inst_retired.512b_packed_double ) + 16 * fp_arith_inst_retired.512b_packed_single )) / 1000000000 ) / duration_time unc_m_cas_count.rd_reg Read Pending Queue Occupancy. Unit: uncore_imc write requests from local home agent. Unit: uncore_cha Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) Multi-socket cacheline Directory state lookups; Snoop Not Needed. Unit: uncore_cha Multi-socket cacheline Directory state updates; Directory Updated memory write from TOR pipe. Unit: uncore_cha Read request from a remote socket which hit in the HitMe Cache to a line In the E state. Unit: uncore_cha Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA uncore_m2m Cycles when direct to core mode (which bypasses the CHA) was disabled. Unit: uncore_m2m Counts when a read message that was sent direct to the Intel Ultra Path Interconnect (bypassing the CHA) was overridden Multi-socket cacheline Directory lookup (cacheline found in I state) . Unit: uncore_m2m Reads to iMC issued. Unit: uncore_m2m Counts Data Response (DRS) packets that attempted to go direct to core bypassing the CHA umask=0x97,event=0x3 offcore_response.other.supplier_none.hit_other_core_no_fwd period=200003,umask=0x40,event=0xf0 offcore_response.pf_l2_rfo.l3_hit_s.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080004 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040491 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200028000 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08001007F7 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C07F7 This event is deprecated. Refer to new event OCR.DEMAND_RFO.ANY_RESPONSE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0100 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400020 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10000407F7 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08000207F7 period=2000003,umask=0x4,event=0x60 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040010 offcore_response.all_rfo.l3_hit_s.no_snoop_needed offcore_response.pf_l1d_and_sw.supplier_none.hitm_other_core period=2000003,umask=0x1,event=0x51 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200010 offcore_response.pf_l2_data_rd.l3_hit_e.hitm_other_core This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080122 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0491 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080491 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01000207F7 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040002 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS offcore_response.all_pf_rfo.l3_hit_s.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100491 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE offcore_response.all_pf_data_rd.l3_hit_m.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200002 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0010 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD offcore_response.pf_l3_data_rd.l3_hit_e.snoop_none This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0490 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0004 offcore_response.all_data_rd.l3_hit_e.snoop_miss Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element Counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles period=2000003,umask=0x4,event=0x80 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000100 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000490 ocr.pf_l1d_and_sw.l3_miss.any_snoop ALL_READS & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000120 period=2000003,umask=0x1,event=0x54 ALL_PF_RFO & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000122 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED ocr.demand_code_rd.l3_miss.snoop_miss Counts all demand code reads DEMAND_CODE_RD & L3_MISS & SNOOP_MISS This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.REMOTE_HITM ocr.all_reads.l3_miss.hit_other_core_no_fwd offcore_response.demand_code_rd.l3_miss_remote_hop1_dram.any_snoop offcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000120 Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS & REMOTE_HIT_FORWARD This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CORE ocr.all_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD ocr.pf_l3_rfo.l3_miss.hitm_other_core Counts demand data reads DEMAND_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & ANY_SNOOP Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000002 This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD offcore_response.demand_rfo.l3_miss_local_dram.hit_other_core_fwd ocr.all_pf_data_rd.l3_miss_local_dram.hitm_other_core Counts all demand data writes (RFOs) DEMAND_RFO & L3_MISS_REMOTE_DRAM & SNOOP_MISS_OR_NO_FWD This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & ANY_SNOOP period=2000003,umask=0x20,event=0xc9 Counts demand data reads DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISS_OR_NO_FWD ocr.all_rfo.l3_miss_remote_hop1_dram.hitm_other_core Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS & SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000020 ocr.demand_code_rd.l3_miss_remote_hop1_dram.snoop_miss offcore_response.all_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000001 offcore_response.all_pf_rfo.l3_miss.hitm_other_core offcore_response.pf_l3_data_rd.l3_miss.hit_other_core_no_fwd ocr.demand_rfo.l3_miss_local_dram.hitm_other_core Counts all demand data writes (RFOs) DEMAND_RFO & L3_MISS_LOCAL_DRAM & HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000490 ocr.pf_l2_data_rd.l3_miss_local_dram.hit_other_core_no_fwd Counts demand data reads DEMAND_DATA_RD & L3_MISS & NO_SNOOP_NEEDED offcore_response.other.l3_miss.hitm_other_core This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED ocr.all_data_rd.l3_miss.snoop_none offcore_response.other.l3_miss.hit_other_core_fwd ALL_DATA_RD & L3_MISS & REMOTE_HIT_FORWARD ocr.all_data_rd.l3_miss.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD ocr.all_pf_rfo.l3_miss.hit_other_core_fwd ocr.all_reads.l3_miss.hitm_other_core ocr.other.l3_hit_e.snoop_none ocr.pf_l2_rfo.l3_hit.hit_other_core_fwd ocr.all_pf_rfo.l3_hit_e.hitm_other_core ALL_DATA_RD & L3_HIT_F & HITM_OTHER_CORE Counts any other requests OTHER & PMM_HIT_LOCAL_PMM & ANY_SNOOP ocr.pf_l2_data_rd.l3_hit_e.hit_other_core_no_fwd Counts demand data reads DEMAND_DATA_RD & L3_HIT_M & HIT_OTHER_CORE_FWD Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_M & NO_SNOOP_NEEDED ocr.demand_code_rd.any_response ALL_READS & L3_HIT & SNOOP_MISS ocr.pf_l3_rfo.l3_hit_e.snoop_miss ALL_DATA_RD & L3_HIT_S & NO_SNOOP_NEEDED ocr.pf_l3_rfo.pmm_hit_local_pmm.snoop_not_needed ocr.all_rfo.pmm_hit_local_pmm.any_snoop ocr.pf_l2_data_rd.l3_hit_m.hit_other_core_no_fwd Counts demand data reads DEMAND_DATA_RD & L3_HIT & HIT_OTHER_CORE_NO_FWD ocr.demand_rfo.l3_hit_f.no_snoop_needed ALL_PF_RFO & SUPPLIER_NONE & SNOOP_NONE Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_M & HITM_OTHER_CORE Counts all demand code reads DEMAND_CODE_RD & L3_HIT_S & HIT_OTHER_CORE_NO_FWD ocr.demand_data_rd.any_response Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_E & HITM_OTHER_CORE ocr.pf_l3_rfo.l3_hit_f.no_snoop_needed Counts any other requests OTHER & L3_HIT & HIT_OTHER_CORE_FWD Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & SUPPLIER_NONE & HIT_OTHER_CORE_FWD ALL_PF_DATA_RD & L3_HIT & HIT_OTHER_CORE_FWD ocr.demand_code_rd.l3_hit.snoop_hit_with_fwd ALL_PF_DATA_RD & L3_HIT_M & NO_SNOOP_NEEDED ALL_READS & L3_HIT & HIT_OTHER_CORE_NO_FWD ALL_PF_DATA_RD & L3_HIT_F & NO_SNOOP_NEEDED ocr.pf_l2_rfo.l3_hit_f.snoop_none ALL_PF_DATA_RD & SUPPLIER_NONE & ANY_SNOOP Counts all demand code reads DEMAND_CODE_RD & L3_HIT_S & ANY_SNOOP ocr.pf_l1d_and_sw.supplier_none.hit_other_core_no_fwd Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_S & ANY_SNOOP ocr.demand_code_rd.l3_hit.hit_other_core_no_fwd Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT & ANY_SNOOP ocr.pf_l3_rfo.l3_hit_s.hit_other_core_no_fwd ocr.pf_l2_rfo.supplier_none.hit_other_core_fwd ocr.pf_l2_data_rd.l3_hit_s.snoop_none Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_E & ANY_SNOOP ocr.all_pf_data_rd.supplier_none.hit_other_core_no_fwd ALL_PF_RFO & SUPPLIER_NONE & ANY_SNOOP Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_M & NO_SNOOP_NEEDED ocr.pf_l1d_and_sw.l3_hit_f.snoop_miss ALL_RFO & L3_HIT_E & SNOOP_NONE Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & SUPPLIER_NONE & HIT_OTHER_CORE_FWD period=100007,umask=0x2,event=0xc4 period=2000003,umask=0x8,event=0xa6 period=2000003,umask=0x1,event=0xa6 period=2000003,umask=0x10,event=0xb1 period=100003,umask=0x4,event=0xc3 period=2000003,umask=0x1,event=0x5e unc_m_pmm_bandwidth.total All commands for Intel Optane DC persistent memory. Unit: uncore_imc unc_m_tagchk.hit Counts snoop filter capacity evictions for entries tracking modified lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline unc_iio_data_req_of_cpu.peer_write.part0 M2M Writes Issued to iMC; All, regardless of priority. Unit: uncore_m2m Valid Flits Sent; Data. Unit: uncore_upi ll period=100003,umask=0xe,event=0x85 Uops delivered to IDQ while MS is busy Number of times an RTM execution aborted Supports address when precise br_inst_retired.indirect umask=0x0f,event=0x4 umask=0xC001FE01,event=0x35,config1=0x41833 unc_iio_data_req_of_cpu.mem_read.part4 unc_m2m_clockticks Clockticks of the power control unit (PCU). Unit: uncore_pcu l2_request_g2.ls_rd_sized_nc l2_cache_req_stat.ls_rd_blk_l_hit_x uncore_l3pmc The number of near returns retired that were not correctly predicted by the return address predictor. Each such mispredict incurs the same penalty as a mispredicted conditional branch instruction umask=0x1,event=0xcb Data Fabric CCM Performance Monitor Event DF CCM Request Any DRAM transaction df_ccm_reqa.node5.rdsizednc df_ccm_reqa.node7.rdsizednc umask=0xC6,event=0x8b umask=0xA5,event=0x8b df_ccm_reqa.node6.anyrdblk umask=0x04,event=0x8b df_ccm_reqa.node4.rdvlkc umask=0xE2,event=0x8b umask=0x0E,event=0x8c df_ccm_reqb.node5.chgtox umask=0x8D,event=0x8c df_ccm_reqb.node0.vicblkfullzero df_ccm_reqb.node3.vicblkfullzero df_ccm_reqb.node1.vicblkcln Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizednc umask=0x24,event=0x8c umask=0xE3,event=0x8c Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedncposted umask=0x89,event=0x108 umask=0x88,event=0x108 df_ioms_reqa.node5.anydramtransaction df_ioms_reqa.node7.anyatomic df_ioms_reqa.node5.anywrsized<32b df_ioms_reqa.node1.anyrdsized df_ioms_reqa.node7.largeread df_ioms_reqb.node4.pieiorequest df_ioms_reqb.node2.pieinterrupt df_ioms_reqb.node2.anyiotransaction df_ioms_reqb.node4.anyiotransaction df_ioms_reqb.node4.ioanynon-postedwrsized>32band<64b df_ioms_reqb.node4.ioanynon-postedwrsized<32b umask=0x83,event=0x109 fpu_pipe_assignment.dual1 The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one-cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 3 fpu_pipe_assignment.total1 fp_ret_sse_avx_ops.sp_add_sub_flops l3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x02,event=0x1 l3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x02,event=0x1 l3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x04,event=0x1 l3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x20,event=0x1 l3_request_g1.t7.s2.rdsizednc l3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x40,event=0x1 l3_request_g1.t4.s2.caching l3fillvicreq.t5.s1.vicblk l3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x01,event=0x3 l3fillvicreq.t5.s2.vicblk l3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x01,event=0x3 l3fillvicreq.t0.s0.chgtox l3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x02,event=0x3 l3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x04,event=0x3 l3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x10,event=0x3 l3fillvicreq.t5.s0.rdblkx_vic l3fillvicreq.t7.s0.rdblkx l3fillvicreq.t0.s2.rdblkx l3fillvicreq.t7.s2.rdblkx l3fillvicreq.t5.s0.rdblkl_vic l3fillvicreq.t7.s1.rdblkl_vic l3fillvicreq.t6.s0.rdblkl l3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x80,event=0x3 l3fillvicreq.t0.s2.rdblkl l3fillvicreq.t7.s3.rdblkl l3victimstate.t6.s3.nol3victimline l3victimstate.t2.s1.none_nol3victimline l3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x02,event=0x9 l3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x02,event=0x9 l3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x04,event=0x9 l3victimstate.t6.s1.o l3victimstate.t1.s2.o l3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x08,event=0x9 l3victimstate.t2.s1.e_fe l3victimstate.t3.s3.m l3victimstate.t0.s1.d l3victimstate.t1.s3.d l3victimstate.t7.s3.d l3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x80,event=0x9 l3victimstate.t5.s3.od umask=0x2,event=0x29 event=0x76 ic_oc_mode_switch.ic_oc_mode_switch umask=0x20,event=0xaf event=0xd2 Non-forwardable conflict; used to reduce STLI's via software. All reasons. Store To Load Interlock (STLI) are loads that were unable to complete because of a possible match with an older store, and the older store could not do STLF for some reason Cycles where a dispatch group is valid but does not get dispatched due to a token stall. FP Miscellaneous resource unavailable. Applies to the recovery of mispredicts with FP ops de_dis_dispatch_token_stalls1.store_queue_token_stall Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Integer Physical Register File resource stall. Applies to all ops that have an integer destination register SECOND_EXECUTION_UNIT_PIPE WRITE_STALL BUS_ACCESS_LD ST_RETIRED PC_WRITE_RETIRED UNALIGNED_LDST_RETIRED L1D_TLB_REFILL_LD L2D_CACHE_ST REMOTE_ACCESS ICACHE_WRITE_HIT DCACHE_SET_TAG_WRITE MEM_HWORD_READ MEM_HWORD_WRITE TAGCACHEMASTER_WRITE_REQ_FLIT TAGCACHEMASTER_READ_RSP_FLIT FPU_STALL_CYCLES LOAD_TO_USE_STALLS ALU_OPERANDS_NOT_READY_CYCLES JTLB_DATA_ACCESSES FSB_OVER_50_FULL LOAD_MISS_INSNS SYSTEM_EVENT_3 OCP_WRITE_REQUESTS ULOAD STS IOSTS VIU1_INSTR_WAIT_CYCLES SUCCESSFUL_DST_TABLE_SEARCHES L2_EXTERNAL_INTERVENTIONS L2_LOAD_MISS GUARDED_LOADS_TRANSLATED DATA_L1_CACHE_RELOADS DVT3_DETECTED accesses nonpostwrszdword rdszbyte INTEL_PM INTEL_SKYLAKE UNHALTED-CORE-CYCLES CPU_CLK_UNHALTED.THREAD_P_ANY BR_INST_RETIRED.ALL_BRANCHES ldlat longest_lat_cache.miss v18 GenuineIntel-6-55-[56789ABCDEF] l1d_pend_miss.pending / ( mem_load_uops_retired.l1_miss + mem_load_uops_retired.hit_lfb ) Memory_Bound;Memory_Lat SMT;Summary umask=0x41,period=100003,event=0x2e umask=0x1,cmask=6,period=2000003,event=0x60 Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue Spec update: BDM76 offcore_requests_outstanding.demand_rfo Retired load uops that split across a cacheline boundary.(Precise Event - PEBS) Supports address when precise (Precise event) This event counts L2 or L3 HW prefetches that access L2 cache including rejects idq.dsb_uops Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path hle_retired.start Number of times HLE caused a fault Number of intervals between processor halts while thread is in ring 0 Core cycles when the thread is not in halt state load_hit_pre.sw_pf Taken speculative and retired indirect branches excluding calls and returns br_inst_exec.taken_indirect_near_return This event counts both taken and not taken speculative and retired direct near calls br_misp_exec.nontaken_conditional umask=0xa0,period=200003,event=0x89 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4 uops_dispatched_port.port_6 resource_stalls.rob cycle_activity.cycles_ldm_pending Number of uops executed from any thread inst_retired.x87 This event counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling Mispredicted macro branch instructions retired. (Precise Event - PEBS) (Must be precise) llc_misses.pcie_read umask=0x2,event=0x1 power_critical_throttle_cycles % Counts the number of cycles that we are in external PROCHOT mode. This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip. Unit: uncore_pcu itlb_misses.stlb_hit page_walker_loads.dtlb_l3 Number of DTLB page walker hits in the L3 + XSNP Spec update: BDM69, BDM98 TopdownL1_SMT This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum 4 uops retired per cycle has been achieved. Maximizing Retiring typically increases the Instruction-Per-Cycle metric. Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Microcode assists are categorized under Retiring. They hurt performance and can often be avoided. SMT version; use when SMT is enabled and measuring per logical CPU min( 1 , idq.mite_uops / ( (uops_retired.retire_slots / inst_retired.any) * 16 * ( icache.hit + icache.misses ) / 4.0 ) ) L1D_Cache_Fill_BW This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were hits in the mid-level (L2) cache Spec update: BDM35. Supports address when precise (Precise event) Hit in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS) Spec update: BDM100. Supports address when precise (Precise event) Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS) Spec update: BDM100. Supports address when precise (Precise event) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010001 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020001 Counts all demand data writes (RFOs) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020004 offcore_response.demand_code_rd.l3_hit.snoop_hitm offcore_response.pf_l2_rfo.supplier_none.snoop_hit_no_fwd offcore_response.pf_l2_code_rd.supplier_none.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020040 offcore_response.pf_l3_code_rd.l3_hit.snoop_none offcore_response.pf_l3_code_rd.l3_hit.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000018000 offcore_response.all_pf_rfo.supplier_none.snoop_miss offcore_response.all_rfo.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020122 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0122 This is a precise version (that is, uses PEBS) of the event that counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable Spec update: BDM30 umask=0x8,period=2000003,cmask=1,event=0x79 offcore_response.demand_data_rd.l3_miss_local_dram.snoop_none offcore_response.demand_rfo.l3_miss.snoop_not_needed offcore_response.demand_code_rd.l3_hit.snoop_non_dram offcore_response.demand_code_rd.l3_miss_local_dram.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0008 offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000080 offcore_response.pf_l3_rfo.supplier_none.snoop_non_dram offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_non_dram offcore_response.other.l3_miss_local_dram.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000090 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000240 offcore_response.all_rfo.l3_miss_local_dram.snoop_none L3 Lookup read request that access cache and found line in any MESI-state unc_arb_trk_requests.writes This 48-bit fixed counter counts the UCLK cycles This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K) Supports address when precise (Precise event) offcore_response.all_rfo.llc_hit.hit_other_core_no_fwd Number of times HLE abort was triggered (Precise event) offcore_response.all_rfo.llc_miss.local_dram This event counts return instructions retired (Precise event) l2_ld.self.prefetch.i_state l2_lock.self.m_state l2_rqsts.self.any.m_state l2_reject_busq.self.any.e_state x87_comp_ops_exe.fxch.ar umask=0x81,period=10000,event=0x11 umask=0x82,period=2000000,event=0xb3 SIMD packed arithmetic micro-ops retired umask=0x2,period=2000000,event=0xca umask=0x1,period=2000000,event=0x86 Cycles during which instruction fetches are stalled umask=0x1,period=2000000,event=0x87 Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed umask=0xf,period=200000,event=0x7 Bus cycles when data is sent on the bus bus_trans_wb.all_agents umask=0x40,period=200000,event=0x6d hw_int_rcv umask=0x1,period=200000,event=0x89 uops_retired.stalls umask=0x8,period=200000,event=0xc4 umask=0x2,period=200000,event=0x82 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000043091 Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache umask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600000020 Counts reads for ownership (RFO) requests generated by L2 prefetcher that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required offcore_response.demand_rfo.l2_miss.snoop_miss_or_no_snoop_needed Cycles code-fetch stalled due to an outstanding ITLB miss umask=0x2,period=200003,event=0xcd umask=0x1,period=200003,event=0x5 ITLB misses umask=0x12,period=200003,event=0xd0 mem_uops_retired.dtlb_miss Counts demand cacheable data reads of full cache lines outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand reads for ownership (RFO) requests generated by a write to full data cache line true miss for the L2 cache with a snoop miss in the other processor module Counts demand reads for ownership (RFO) requests generated by a write to full data cache line true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cacheline reads generated by hardware L2 cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts reads for ownership (RFO) requests generated by L2 prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cache line reads generated by hardware L1 data cache prefetcher have any transaction responses from the uncore subsystem offcore_response.pf_l1_data_rd.outstanding Counts data reads generated by L1 or L2 prefetchers miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts reads for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 2M or 4M pages. The page walks can end with or without a page fault Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 1GB pages. The page walks can end with or without a page fault Counts all L2 HW prefetcher requests that hit L2 l1d_pend_miss.request_fb_full This event counts retired load uops in which data sources missed in the L1 cache. This does not include hardware prefetches. This is a precise event Spec update: HSM30. Supports address when precise (Precise event) Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address offcore_response.all_code_rd.l3_miss.local_dram offcore_response.all_data_rd.l3_miss.any_response The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use Reference cycles when the thread is unhalted. (counts at 100 MHz rate) umask=0x8,period=100003,event=0xc4 Counts all not taken macro branch instructions retired (Precise event) Count cases of saving new LBR records by hardware unc_cbo_cache_lookup.extsnp_es ITLB misses that hit STLB (4K) umask=0x1,period=100003,event=0xae Number of ITLB page walker hits in the L3 + XSNP Spec update: HSD25 Cycles with any input/output SSE* or FP assists Number of far branches retired l2_rqsts.pf_miss offcore_response.all_code_rd.llc_hit.any_response Counts all writebacks from the core to the LLC umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0001 offcore_response.demand_data_rd.llc_hit.no_snoop_needed Count issue pipeline slots where no uop was delivered from the front end to the back end when there is no back-end stall Counts all demand & prefetch code reads that miss the LLC and the data returned from dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x6004001b3 Cycles per core when load or STA uops are dispatched to port 3 Counts total number of uops to be executed per-core each cycle A snoop misses in some processor core unc_cbo_cache_lookup.read_filter Unit: uncore_arb Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC unc_arb_trk_requests.evictions umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0001 PCIe non-snoop writes (partial). Derived from unc_c_tor_inserts.opcode.pcie_partial_write. Unit: uncore_cbox Counts the number of times that the uncore transitioned to a frequency greater than or equal to the frequency that is configured in the filter. (filter_band1=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Derived from unc_p_freq_band1_cycles. Unit: uncore_pcu Counts the number of times that the uncore transitioned to a frequency greater than or equal to 2Ghz. Derived from unc_p_freq_band1_cycles. Unit: uncore_pcu Retired load uops which data sources were hits in LLC without snoops required Each cycle there was a miss-pending demand load this thread and no uops dispatched, increment by 1. Note this is in DCU and connected to Umask 1 and 2. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING tor_occupancy.miss_all % offcore_response.any_code_rd.l2_hit_near_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400400 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080200 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080100 Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state offcore_response.demand_rfo.l2_hit_far_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000002 Counts any Prefetch requests that accounts for responses which hit its own tile's L2 with data in E state offcore_response.demand_data_rd.l2_hit_this_tile_s offcore_response.uc_code_reads.l2_hit_this_tile_s umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000001 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000040 Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in F state offcore_response.any_rfo.l2_hit_this_tile_f Counts Software Prefetches that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state offcore_response.pf_l1_data_rd.l2_hit_near_tile offcore_response.any_request.l2_hit_near_tile Counts any request that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state offcore_response.any_read.mcdram_far offcore_response.pf_software.mcdram_near Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from MCDRAM Far or Other tile L2 hit far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200100 Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Local umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180601000 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x01806032f7 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181800022 Counts the number of micro-ops retired umask=0x20,period=200003,event=0xca umask=0x7f,period=200003,event=0xca Fixed Counter: Counts the number of unhalted reference clock cycles Counts the total D-side page walks that are completed or started. The page walks started in the speculative path will also be counted This event counts every cycle when an I-side (walks due to an instruction fetch) page walk is in progress umask=0x2,period=2000000,event=0x51 L1 data cache lines allocated L1 data cache read in E state L1 data cache read in I state (misses) umask=0x8,period=2000000,event=0x42 l1d_cache_prefetch_lock_fb_hit umask=0xf0,period=200000,event=0x26 L2 demand lock RFOs in M state umask=0x10,period=20000,event=0xb,ldlat=0x8 offcore_response.any_request.io_csr_mmio Offcore requests satisfied by the LLC Offcore requests satisfied by a remote cache or remote DRAM Offcore requests that HIT in a remote cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x122 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1022 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x708 Offcore writebacks to the LLC umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4708 offcore_response.data_ifetch.any_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3877 offcore_response.data_in.llc_hit_no_other_core Offcore demand data requests satisfied by the LLC or local DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F01 offcore_response.demand_ifetch.remote_cache_dram offcore_response.other.llc_hit_other_core_hitm Offcore other requests satisfied by a remote cache or remote DRAM offcore_response.pf_data_rd.remote_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x810 offcore_response.pf_ifetch.any_location offcore_response.pf_ifetch.remote_cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1820 fp_mmx_trans.to_mmx umask=0x8,period=200000,event=0x12 offcore_response.any_data.local_dram Offcore demand data requests that missed the LLC Offcore demand RFO requests that missed the LLC offcore_response.other.any_llc_miss umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2030 umask=0x2,period=2000000,event=0x80 umask=0x1,period=100000,event=0x3c Cycles when thread is not halted (fixed counter) umask=0x8,period=2000000,event=0x87 umask=0x2,period=2000000,event=0xc0 Loops that can't stream from the instruction queue inv=1,umask=0x3f,any=1,period=2000000,cmask=1,edge=1,event=0xb1 inv=1,umask=0x1f,any=1,period=2000000,cmask=1,event=0xb1 Cycles no Uops issued on ports 0, 1 or 5 Uops executed on port 1 uops_issued.fused Retirement slots used (Precise Event) itlb_miss_retired ITLB miss page walks Core-originated cacheable demand requests that refer to L3 Spec update: SKL057 umask=0x40,period=100007,event=0xd1 umask=0x4,period=100007,event=0xd4 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400408000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200048000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0400002 offcore_response.demand_rfo.l3_hit_s.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02001C0001 offcore_response.demand_data_rd.l3_hit_s.snoop_miss offcore_response.demand_data_rd.l3_hit_s.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400080001 umask=0x1,period=100007,event=0xc6,frontend=0x400806 umask=0x10,period=100003,event=0xb0 offcore_response.other.l3_miss_local_dram.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000088000 offcore_response.other.l3_hit_m.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x203C400004 offcore_response.demand_code_rd.l3_miss_local_dram.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000400004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000002 offcore_response.demand_rfo.l3_miss_local_dram.snoop_none Number of PREFETCHT0 instructions executed Number of PREFETCHT1 or PREFETCHT2 instructions executed umask=0x1,period=2503,event=0x3c Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution Spec update: SKL091, SKL044 (Must be precise) Number of times a microcode assist is invoked by HW other than FP-assist. Examples include AD (page Access Dirty) and AVX* related assists rob_misc_events.pause_inst ( itlb_misses.walk_pending + dtlb_load_misses.walk_pending + dtlb_store_misses.walk_pending + ept.walk_pending ) / ( 2 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )) ) Counts page walks completed due to demand data loads whose address translations missed in the TLB and were mapped to 2M/4M pages. The page walks can end with or without a page fault Page walk completed due to a demand data store to a 2M/4M page rehabq.ld_splits This event counts the number of load ops retired that miss in L1 Data cache. Note that prefetch misses will not be counted This event counts the number of load ops retired that had UTLB miss Counts RFO requests generated by L2 prefetchers that hit in the other module where modified copies were found in other core's L1 cache offcore_response.corewb.l2_miss.no_snoop_needed Counts demand and DCU prefetch instruction cacheline that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Counts the number of cycles when no uops are allocated and a RATstall is asserted Counts the number of baclears This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a modified state, so the line had to be invalidated in that L2 cache and transferred to the requesting L2. (Precise Event - PEBS) (Precise event) Counts prefetch (that bring data to L2) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops sent to sibling cores return clean response offcore_response.demand_rfo.llc_hit_m.hitm REQUEST = PF_LLC_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_NO_OTHER_CORE REQUEST = ANY IFETCH and RESPONSE = IO_CSR_MMIO REQUEST = ANY_REQUEST and RESPONSE = REMOTE_CACHE_HITM REQUEST = CORE_WB and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = DEMAND_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = OTHER and RESPONSE = IO_CSR_MMIO REQUEST = OTHER and RESPONSE = REMOTE_CACHE_HITM umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1050 REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM REQUEST = PF_RFO and RESPONSE = REMOTE_CACHE_HITM REQUEST = PREFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT umask=0x1,period=100000,event=0xb7,offcore_rsp=0xf877 umask=0x1,period=100000,event=0xb7,offcore_rsp=0xf804 umask=0x1,period=100000,event=0xb7,offcore_rsp=0xf802 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3070 umask=0x80,period=200000,event=0x49 umask=0x4,period=2000000,event=0x85 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x27FF umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2780 Retired load instructions whose data sources was forwarded from a remote cache Supports address when precise (Precise event) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x083FC00001 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063FC00002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x103FC00020 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063B800080 offcore_response.pf_l3_rfo.l3_miss.remote_hit_forward offcore_response.all_pf_rfo.l3_miss.remote_hit_forward offcore_response.all_rfo.l3_miss.any_snoop umask=0x10,period=2000003,event=0xef inv=1,umask=0x2,cmask=1,period=2000003,event=0xb1 unc_cha_requests.reads_local read requests from remote home agent. Unit: uncore_cha Rsp*WB Snoop Responses Received. Unit: uncore_cha Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.mem_write.part0 event=0x26 Counts when messages were sent direct to the Intel Ultra Path Interconnect (bypassing the CHA) unc_m2m_directory_update.a2i umask=0x1,event=0x2e Partial Non-Isochronous writes to the iMC. Unit: uncore_m2m unc_m2m_prefcam_demand_promotions Counts clockticks of the fixed frequency clock controlling the Intel Ultra Path Interconnect (UPI). This clock runs at1/8th the 'GT/s' speed of the UPI link. For example, a 9.6GT/s link will have a fixed Frequency of 1.2 Ghz unc_upi_txl0p_power_cycles umask=0x10,cmask=1,period=100003,event=0x8 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100080 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F804007F7 offcore_response.pf_l1d_and_sw.l3_hit_s.snoop_miss This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED period=100007,umask=0x4,event=0xd4 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0490 offcore_response.demand_rfo.l3_hit_e.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040010 This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.SNOOP_MISS This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100010 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400080 offcore_response.all_pf_rfo.l3_hit_e.hit_other_core_fwd offcore_response.demand_data_rd.l3_hit_e.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C8000 offcore_response.all_data_rd.pmm_hit_local_pmm.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020122 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040001 offcore_response.pf_l1d_and_sw.supplier_none.any_snoop offcore_response.pf_l1d_and_sw.l3_hit_s.hitm_other_core This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020010 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100020 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020002 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040400 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED period=200003,umask=0xe4,event=0x24 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040002 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080080 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040122 period=2000003,umask=0x82,event=0xd0 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040002 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020004 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100080 offcore_response.pf_l2_data_rd.l3_hit.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040004 period=200003,umask=0xd8,event=0x24 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080004 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED offcore_response.all_pf_rfo.l3_hit_m.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020491 offcore_response.all_pf_rfo.l3_hit_e.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040400 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040122 period=100007,umask=0x1,event=0xc6,frontend=0x410006 offcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.snoop_none This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP offcore_response.demand_code_rd.l3_miss_remote_hop1_dram.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F840007F7 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800100 Counts all demand code reads DEMAND_CODE_RD & L3_MISS & REMOTE_HIT_FORWARD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000100 ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.snoop_miss Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS & NO_SNOOP_NEEDED ALL_PF_DATA_RD & L3_MISS & HITM_OTHER_CORE ocr.pf_l3_data_rd.l3_miss.snoop_none This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.SNOOP_NONE offcore_response.pf_l3_data_rd.l3_miss_local_dram.hitm_other_core This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD ocr.other.l3_miss.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000120 Counts all demand data writes (RFOs) DEMAND_RFO & L3_MISS_REMOTE_HOP1_DRAM & ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000122 period=2000003,umask=0x8,event=0x54 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000002 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000020 ocr.demand_code_rd.l3_miss_local_dram.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000010 ocr.other.l3_miss_local_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED ALL_RFO & L3_MISS_REMOTE_HOP1_DRAM & HITM_OTHER_CORE ocr.demand_data_rd.l3_miss.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000001 Counts all demand code reads DEMAND_CODE_RD & L3_MISS_REMOTE_HOP1_DRAM & ANY_SNOOP This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS & REMOTE_HITM ocr.demand_code_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd ocr.demand_data_rd.l3_miss.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000080 ocr.other.l3_miss.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD ocr.pf_l2_data_rd.l3_miss_local_dram.hitm_other_core This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED ocr.pf_l2_rfo.l3_miss.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000122 ocr.other.l3_miss_local_dram.hit_other_core_no_fwd Counts all demand data writes (RFOs) DEMAND_RFO & L3_MISS & HITM_OTHER_CORE ocr.pf_l3_rfo.l3_miss.remote_hitm This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED ocr.pf_l2_rfo.l3_miss.remote_hitm ocr.other.supplier_none.hitm_other_core ALL_DATA_RD & L3_HIT_S & HITM_OTHER_CORE ALL_DATA_RD & PMM_HIT_LOCAL_PMM & ANY_SNOOP ocr.pf_l2_data_rd.l3_hit.snoop_hit_with_fwd ocr.all_rfo.l3_hit_s.hit_other_core_no_fwd ocr.pf_l3_rfo.l3_hit_e.no_snoop_needed ocr.all_pf_data_rd.l3_hit_s.hit_other_core_no_fwd ocr.all_pf_data_rd.l3_hit_f.hitm_other_core ocr.pf_l3_rfo.l3_hit_f.hit_other_core_no_fwd Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT & SNOOP_NONE ocr.pf_l1d_and_sw.supplier_none.snoop_miss Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_S & ANY_SNOOP ocr.pf_l2_data_rd.l3_hit_s.hitm_other_core ALL_PF_RFO & L3_HIT_M & NO_SNOOP_NEEDED ocr.all_data_rd.supplier_none.snoop_none ocr.all_pf_rfo.l3_hit.hitm_other_core Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDED Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_M & ANY_SNOOP ocr.demand_rfo.l3_hit_f.hitm_other_core ALL_READS & L3_HIT & SNOOP_NONE ALL_PF_DATA_RD & SUPPLIER_NONE & NO_SNOOP_NEEDED ocr.all_pf_data_rd.l3_hit_m.snoop_none Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT & HITM_OTHER_CORE ALL_READS & SUPPLIER_NONE & NO_SNOOP_NEEDED Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_E & HITM_OTHER_CORE ALL_PF_RFO & L3_HIT & SNOOP_HIT_WITH_FWD ocr.pf_l3_rfo.l3_hit_f.any_snoop Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_E & ANY_SNOOP ocr.pf_l3_rfo.l3_hit_m.no_snoop_needed Counts demand data reads DEMAND_DATA_RD & L3_HIT_S & ANY_SNOOP ocr.pf_l2_rfo.l3_hit_e.hit_other_core_fwd Counts L1 data cache hardware prefetch requests and software prefetch requests hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores Counts all demand code reads DEMAND_CODE_RD & L3_HIT_M & HIT_OTHER_CORE_FWD ocr.pf_l2_rfo.l3_hit_s.any_snoop Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_S & HIT_OTHER_CORE_FWD All commands for Intel Optane DC persistent memory Underfill read commands for Intel Optane DC persistent memory. Unit: uncore_imc FaST wire asserted; Horizontal. Unit: uncore_cha fc_mask=0x07,ch_mask=0x01,umask=0x02,event=0xc0 Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part0 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_data_req_of_cpu.peer_read.part2 Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus AD Egress (to CMS) Allocations. Unit: uncore_m2m unc_upi_txl_flits.data period=100003,umask=0x10,event=0x85 period=2000003,umask=0x8,event=0x8 Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path umask=0x1,period=100007,event=0xc6,frontend=0x501006 Counts the number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer Number of times an instruction execution caused the transactional nest count supported to be exceeded Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into stravation periods (e.g. branch mispredictions or i-cache misses) Counts end of periods where the Reservation Station (RS) was empty Counts taken conditional branch instructions retired (Precise event) fc_mask=0x07,ch_mask=0x80,umask=0x04,event=0x83 fc_mask=0x07,ch_mask=0x40,umask=0x01,event=0x83 event=0x8a ic_fetch_stall.ic_stall_dq_empty l2_request_g1.ls_rd_blk_c_s l2_request_g2.bus_locks_originator LS to L2 WCB cache line zeroing requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) cache line zeroing requests L3 Cache Miss Latency. Total cycles for all transactions divided by 16. Ignores SliceMask and ThreadMask. Unit: uncore_l3pmc ex_ret_brn_misp event=0xc9 Retired Near Returns Mispredicted event=0xd1 umask=0x2,event=0x1cf df_ccm_reqa.node3.wrsizedfullzero df_ccm_reqa.node2.wrsizedfullnc df_ccm_reqa.node3.rdvlkl df_ccm_reqb.node2.vicblkfull. umask=0x0C,event=0x8c umask=0xAC,event=0x8c df_ccm_reqb.node4.vicblkcln umask=0xA9,event=0x8c df_ccm_reqb.node6.wrsizednc df_ccm_reqb.node6.rdsized umask=0x01,event=0x8d df_ioms_reqa.node5.ios_resp df_ioms_reqa.node3.flush df_ioms_reqa.node0.anydramtransaction df_ioms_reqa.node6.anydramtransaction df_ioms_reqb.node1.pieiorequest umask=0xAF,event=0x109 umask=0x2D,event=0x109 df_ioms_reqb.node0.ioanyatomic df_ioms_reqb.node5.ioanyatomic df_ioms_reqb.node0.ioanynon-postedwrsized=64b df_ioms_reqb.node1.ioanynon-postedwrsized>32band<64b umask=0x49,event=0x109 df_ioms_reqb.node1.ioanynon-postedwrsized=32b df_ioms_reqb.node0.ioanypostedwrsized=32 df_ioms_reqb.node5.ioanypostedwrsized=32 df_ioms_reqb.node7.iolargeread The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to all pipes umask=0x8,event=0 This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes. Number of Scalar Ops optimized The number of serializing Ops retired. x87 control word mispredict traps due to mispredictions in RC or PC, or changes in mask bits fp_retired_ser_ops.x87_bot_ret l3_request_g1.t7.s2.wrsizednc l3_request_g1.t6.s3.wrsized l3_request_g1.t2.s0.rdsizednc l3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x20,event=0x1 l3_request_g1.t1.s3.caching l3fillvicreq.t1.s3.vicblk l3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x02,event=0x3 l3fillvicreq.t7.s3.chgtox l3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x04,event=0x3 l3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x04,event=0x3 l3fillvicreq.t4.s2.rdblkc_s_vic l3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x04,event=0x3 l3fillvicreq.t1.s1.rdblkc_s l3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x08,event=0x3 l3fillvicreq.t5.s1.rdblkx_vic l3fillvicreq.t3.s2.rdblkx_vic l3fillvicreq.t0.s0.rdblkx l3fillvicreq.t1.s1.rdblkl l3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x80,event=0x3 l3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x80,event=0x3 l3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x80,event=0x3 l3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x01,event=0x9 l3victimstate.t2.s0.nol3victimline l3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x01,event=0x9 l3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x02,event=0x9 l3victimstate.t1.s2.none_nol3victimline l3victimstate.t4.s3.none_nol3victimline l3victimstate.t2.s0.f_s l3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x04,event=0x9 l3victimstate.t3.s0.o l3victimstate.t2.s3.o l3victimstate.t1.s0.e_fe l3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x10,event=0x9 l3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x10,event=0x9 l3victimstate.t4.s3.m l3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x20,event=0x9 l3victimstate.t3.s1.d l3victimstate.t0.s2.d l3victimstate.t5.s3.d l3victimstate.t4.s2.od umask=0x40,event=0x45 de_dis_dispatch_token_stalls0.alsq2_token_stall The number of instruction fetches that hit in the L1 ITLB. Instruction fetches to a 4KB page bp_l1_tlb_miss_l2_tlb_miss fp_ret_sse_avx_ops.div_flops umask=0x10,event=0x59 Hardware Prefetch Data Cache Fills by Data Source. From another cache (home node local) Cycles where a dispatch group is valid but does not get dispatched due to a token stall. FP scheduler resource stall. Applies to ops that use the FP scheduler CPU_CLK_UNHALTED_CORE FR_TAKEN_HARDWARE_INTERRUPTS CID_WRITE FLOATING_POINT_INSTR_RENAMED EXC_TRAP_IRQ TAGCACHE_EVICT STORE_MISS STORE_COND_FAILED ALU_CYCLES_STALLED L2_MISS_CYCLES COREXTEND_STALL_CYCLES IFETCH_BUFFER_FULL JR_31_NO_PREDICTIONS L2_CACHE_MISSES CACHE_HIT_PREFETCH_INSNS SYSTEM_EVENT_0 MC FPU_RENORMALIZATION LD_ST_TRUE_ALIAS_STALL LWARX_INSTR_COMPLETED L1_DATA_TOUCH_MISS L3SQ_FULL_CYCLES FXU0_BUSY_FXU1_BUSY LSU_MARKED_INSTR_FINISH WRITE_THROUGH_STORES_TRANSLATED CRIT_INPUT_INTR_TAKEN L2_HIT_CACHE_ACCESSES FPU_FINISH LOAD_RETRIES TSC- os store dram-controller-interface-bypass P4 MIPS_74K PPC_E500 GENERIC ARMV7_CORTEX_A17 BRANCH_INSTRUCTION_RETIRED {"type": "procexit" BAClear_Cost Memory-Level-Parallelism (average number of L1 miss demand load when there is at least 1 such miss) cpu_clk_unhalted.ref_tsc / msr@tsc@ (cstate_core@c3\-residency@ / msr@tsc@) * 100 l2_rqsts.code_rd_miss l2_rqsts.all_rfo umask=0xe7,period=200003,event=0x24 Core-originated cacheable demand requests missed L3 L1D miss oustandings duration in cycles Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore Spec update: BDM76 This event counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS Spec update: BDM76 umask=0x2,period=100003,event=0xb0 umask=0x81,period=2000003,event=0xd0 All retired load uops. (Precise Event - PEBS) Supports address when precise (Precise event) This event counts L2 fill requests that access L2 cache umask=0x4,period=100003,event=0xf1 Clean L2 cache lines evicted by demand This event counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable Spec update: BDM30 Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element This event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetches umask=0x2,period=2000003,event=0x5d rtm_retired.aborted uops_issued.flags_merge edge=1,inv=1,umask=0x1,cmask=1,period=200003,event=0x5e umask=0x81,period=200003,event=0x88 Speculative and retired indirect return branches br_inst_exec.all_direct_near_call This event counts taken speculative and retired mispredicted macro conditional branch instructions uops_dispatched_port.port_0 uops_executed_port.port_0 Cycles per core when uops are dispatched to port 7 This event increments by 1 for every cycle where there was no execute for this thread Execution stalls while L1 cache miss demand load is outstanding inst_retired.any_p machine_clears.count umask=0x1,period=400009,event=0xc4 Mispredicted conditional branch instructions retired. (Precise Event - PEBS) (Precise event) umask=0x4,period=400009,event=0xc5 umask=0x3,event=0x35,filter_opc=0x191 ItoM write misses (as part of fast string memcpy stores) + PCIe full line writes. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox llc_references.streaming_full Streaming stores (partial cache line). Derived from unc_c_tor_inserts.opcode. Unit: uncore_cbox umask=0x2,event=0x21 unc_p_power_state_occupancy.cores_c3 unc_p_freq_max_power_cycles dtlb_load_misses.miss_causes_a_walk umask=0x8,period=2000003,event=0x8 Store misses in all DTLB levels that cause completed page walks Spec update: BDM69 umask=0x2,period=100003,event=0x85 Store miss in all TLB levels causes a page walk that completes. (1G) Spec update: BDM69 umask=0x24,period=2000003,event=0xbc DTLB flush attempts of the thread-specific entries This category represents fraction of slots where the processor's Frontend undersupplies its Backend. SMT version; use when SMT is enabled and measuring per logical CPU This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum 4 uops retired per cycle has been achieved. Maximizing Retiring typically increases the Instruction-Per-Cycle metric. Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Microcode assists are categorized under Retiring. They hurt performance and can often be avoided SLOTS_SMT L3 cache true misses per kilo instruction for retired demand loads umask=0x1,any=1,period=2000003,cmask=1,event=0x48 umask=0x8,period=2000003,cmask=1,event=0x60 This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache Spec update: BDM100. Supports address when precise (Precise event) offcore_response.demand_data_rd.l3_hit.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0020 Counts all prefetch (that bring data to LLC only) code reads offcore_response.pf_l3_data_rd.supplier_none.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0080 offcore_response.pf_l3_rfo.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020100 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0100 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020200 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400028000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020090 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020120 offcore_response.all_pf_rfo.supplier_none.snoop_hit_no_fwd offcore_response.all_pf_rfo.supplier_none.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020120 offcore_response.all_pf_rfo.l3_hit.snoop_miss offcore_response.all_pf_code_rd.l3_hit.snoop_not_needed Counts all demand & prefetch data reads have any response type offcore_response.all_rfo.supplier_none.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0122 offcore_response.demand_code_rd.l3_miss_local_dram.snoop_miss offcore_response.demand_code_rd.l3_miss_local_dram.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0010 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000010 offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000080 offcore_response.pf_l3_code_rd.l3_miss_local_dram.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000120 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000122 umask=0x2,period=2000003,cmask=4,event=0xb1 L3 Lookup any request that access cache and found line in MESI-state unc_clock.socket ( itlb_misses.walk_duration + dtlb_load_misses.walk_duration + dtlb_store_misses.walk_duration + 7 * ( dtlb_store_misses.walk_completed + dtlb_load_misses.walk_completed + itlb_misses.walk_completed ) ) / ( 2 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )) ) This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K) Supports address when precise (Precise event) Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram offcore_response.all_reads.llc_miss.any_response umask=0x4,event=0 umask=0x40,period=200000,event=0x23 umask=0x70,period=200000,event=0x27 umask=0x42,period=200000,event=0x2d l2_rqsts.self.any.e_state l2_reject_busq.self.prefetch.mesi SIMD saturated arithmetic micro-ops executed umask=0x80,period=2000000,event=0xb1 SIMD saturated arithmetic micro-ops retired simd_uop_type_exec.shift.ar simd_uop_type_exec.arithmetic.s umask=0x8,period=2000000,event=0xc7 misalign_mem_ref.st_split.ar umask=0xe0,period=200000,event=0x69 Burst (full cache-line) bus transactions umask=0x2b,period=200000,event=0x77 reissue.any br_inst_type_retired.ind Only taken macro conditional branch instructions DTLB misses due to store operations Number of D-side only page walks Locked load uops retired (Precise event capable) Supports address when precise (Must be precise) offcore_response.partial_streaming_stores.l2_miss.any Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required offcore_response.sw_prefetch.l2_miss.snoop_miss_or_no_snoop_needed umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200001000 Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200000004 Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand cacheable data reads of full cache lines that miss the L2 cache offcore_response.demand_data_rd.l2_miss.hitm_other_core Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is not in the ICache (miss). The event strives to count on a cache line basis, so that multiple accesses which miss in a single cache line count as one ICACHE.MISS. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is not in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture umask=0x2,period=200003,event=0xca Counts the number of floating point divide uops retired (Must be precise) umask=0x4,period=200003,event=0xc3 umask=0xf9,period=200003,event=0xc4 Counts mispredicted branch instructions retired that were near indirect call or near indirect jmp, where the target address taken was not what the processor predicted (Must be precise) BACLEARs asserted for conditional branch umask=0x13,period=200003,event=0xd0 Counts data reads generated by L1 or L2 prefetchers hit the L2 cache Counts data reads generated by L1 or L2 prefetchers hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data reads (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem Page walk completed due to an instruction fetch in a 1GB page This event counts requests originating from the core that reference a cache line in the last level cache Demand data read requests that access L2 cache Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00122 offcore_response.demand_rfo.l3_miss.any_response Execution stalls due to memory subsystem Counts number of cycles no uops were dispatched to be executed on this thread Spec update: HSD144, HSD30, HSM31 umask=0x21,event=0x22 Unit: uncore_cbox An external snoop hits a modified line in some processor core This event counts load operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks Completed page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G) Counts the number of Extended Page Table walks from the DTLB that hit in the L3 page_walker_loads.ept_itlb_l1 page_walker_loads.ept_itlb_l3 Retired load uops missed L3. Excludes unknown data source Supports address when precise. Spec update: HSD74, HSD29, HSD25, HSM26, HSM30 (Precise event) Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI) Supports address when precise. Spec update: HSD29, HSM30 (Precise event) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063F800091 Number of near taken branches retired (Precise event) l2_l1d_wb_rqsts.hit_e Miss in last-level (L3) cache. Excludes Unknown data-source (Precise event) mem_load_uops_llc_hit_retired.xsnp_hit umask=0x2,period=100003,event=0xf2 umask=0x20,period=100003,event=0xc1 offcore_response.data_in_socket.llc_miss.local_dram Cycles with pending L2 miss loads. Set AnyThread to count per core unc_cbo_xsnp_response.inval unc_cbo_cache_lookup.i Unit: uncore_cbox LLC lookup request that access cache and found line in I-state Filter on any IRQ or IPQ initiated requests including uncacheable, non-coherent requests Demand load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page size umask=0x82,period=100003,event=0x8 mem_load_uops_llc_miss_retired.remote_fwd Counts demand & prefetch data reads that hit in the LLC and sibling core snoop returned a clean response offcore_response.all_pf_data_rd.llc_hit.hit_other_core_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0080 Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded umask=0x1,period=100003,event=0xb7,offcore_rsp=0x107fc00010 LLC misses - Uncacheable reads. Derived from unc_c_tor_inserts.miss_opcode.uncacheable. Unit: uncore_cbox LLC prefetch misses for code reads. Derived from unc_c_tor_inserts.miss_opcode.code. Unit: uncore_cbox Occupancy for all LLC misses that are addressed to local memory. Unit: uncore_cbox l2_l1d_wb_rqsts.hit_s This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes unchacheable accesses Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x600400077 umask=0x2,period=2000003,event=0xa2 This event counts the number of Uops issued by the front-end of the pipeilne to the back-end Number of cases where any load ends up with a valid block-code written to the load buffer (including blocks due to Memory Order Buffer (MOB), Data Cache Unit (DCU), TLB, but load has no DCU miss) ld_blocks_partial.all_sta_block mem_uops_retired.l1_miss_loads umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000080044 Counts any request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode offcore_response.pf_l1_data_rd.l2_hit_far_tile_m Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state umask=0x1,period=100007,event=0xb7,offcore_rsp=0x00020032f7 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000004 Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in E state umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000044 Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses which hit its own tile's L2 with data in S state offcore_response.pf_software.l2_hit_this_tile_s umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008008000 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008000044 offcore_response.pf_software.l2_hit_this_tile_f offcore_response.demand_code_rd.l2_hit_far_tile Counts all instruction fetches that miss the instruction cache or produce memory requests. An instruction fetch miss is counted only once and not once for every cycle it is outstanding Counts Demand code reads and prefetch code read requests that accounts for data responses from DRAM Far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080201000 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200020 offcore_response.demand_data_rd.mcdram_near Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Far offcore_response.partial_writes.mcdram Counts the number of mispredicted branch instructions retired that were near indirect CALL or near indirect JMP (Precise event) Counts the number of vector SSE, AVX, AVX2, AVX-512 micro-ops retired. More specifically, it counts packed SSE, AVX, AVX2, AVX-512 micro-ops (both floating point and integer) except for loads (memory-to-register mov-type micro-ops), packed byte and word multiplies br_misp_retired.rel_call umask=0x1,period=100003,edge=1,event=0x5 L1 data cache reads l1d_prefetch.miss l2_data_rqsts.prefetch.s_state umask=0x2,period=100000,event=0xf1 L2 lines evicted L2 demand store RFOs in I state (misses) umask=0x1,period=2000000,event=0xb Memory instructions retired above 4096 clocks (Precise Event) Offcore data reads satisfied by any cache or DRAM offcore_response.any_data.any_location Offcore code reads satisfied by the IO, CSR, MMIO unit offcore_response.any_ifetch.remote_cache Offcore requests satisfied by the LLC and not found in a sibling core offcore_response.any_rfo.any_location Offcore RFO requests satisfied by the LLC and HIT in a sibling core umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4722 Offcore writebacks to the LLC and HITM in a sibling core All offcore code or data read requests Offcore code or data read requests satisfied by the LLC or local DRAM Offcore code or data read requests that HIT in a remote cache offcore_response.demand_data.any_location offcore_response.demand_data_rd.llc_hit_other_core_hitm Offcore demand code reads satisfied by the LLC umask=0x1,period=100000,event=0xb7,offcore_rsp=0x804 Offcore demand RFO requests satisfied by a remote cache offcore_response.pf_data.llc_hit_other_core_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x8010 offcore_response.pf_data_rd.local_cache Offcore prefetch data reads satisfied by a remote cache offcore_response.pf_rfo.local_cache Offcore prefetch requests satisfied by any cache or DRAM Offcore prefetch requests satisfied by the LLC umask=0x40,period=2000000,event=0x10 umask=0x2,period=200000,event=0x12 128 bit SIMD integer unpack operations SIMD integer 64 bit pack operations Offcore writebacks to any DRAM Offcore prefetch data requests satisfied by any DRAM Offcore prefetch data reads satisfied by the local DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0x6070 L1I instruction fetch hits umask=0x7,period=2000000,event=0x13 br_misp_exec.near_calls br_misp_exec.taken Regen stall cycles umask=0x1,period=2000000,event=0x18 umask=0x80,period=2000000,event=0xa2 Uops executed on ports 0-4 (core count) inv=1,umask=0x3f,any=1,period=2000000,cmask=1,event=0xb1 Uops executed on port 2 (core count) umask=0x8,any=1,period=2000000,event=0xb1 umask=0x1,any=1,period=2000000,cmask=1,event=0xe uops_retired.active_cycles umask=0x2,period=2000000,event=0xc2 ITLB miss umask=0x38,period=200003,event=0x24 Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM Counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, etc. Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core cache Supports address when precise (Precise event) mem_load_misc_retired.uc offcore_response.other.l4_hit_local_l4.snoop_hit_no_fwd offcore_response.other.l3_hit_s.any_snoop offcore_response.other.l3_hit_s.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0048000 offcore_response.demand_code_rd.l4_hit_local_l4.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC01C0004 offcore_response.demand_code_rd.l3_hit_e.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200400002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00401C0002 offcore_response.demand_rfo.l3_hit_s.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080080002 offcore_response.demand_rfo.l3_hit_m.snoop_hit_no_fwd offcore_response.demand_data_rd.l4_hit_local_l4.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10001C0001 Retired Instructions who experienced decode stream buffer (DSB - the decoded instruction-cache) miss. Precise Event (Precise event) umask=0x1,period=100007,event=0xc6,frontend=0x13 Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops (Precise event) Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.) Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles (Must be precise) offcore_response.demand_code_rd.l3_miss.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0044000004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000100004 offcore_response.demand_rfo.l3_miss.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000100002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C400001 Loads blocked by overlapping with store buffer that cannot be forwarded Cycles the issue-stage is waiting for front-end to fetch from resteered path following branch misprediction or machine clear events Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6 Counts cycles during which no uops were executed on all ports and Reservation Station (RS) was not empty Cycles total of 1 uop is executed on all ports and Reservation Station was not empty exe_activity.3_ports_util Retirement slots used This is a precise version (that is, uses PEBS) of the event that counts conditional branch instructions retired Spec update: SKL091 (Precise event) This is a precise version (that is, uses PEBS) of the event that counts far branch instructions retired Spec update: SKL091 (Precise event) Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 1G pages. The page walks can end with or without a page fault Counts the number of DTLB flush attempts of the thread-specific entries This event counts the number of load ops retired that got data from the other core or from the other module (Precise event) umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000000044 Counts RFO requests generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded REL_CALL counts the number of near relative CALL branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) Counts the number of RETURN baclears Retired load uops with unknown information as data source in cache serviced the load. (Precise Event - PEBS) (Precise event) offcore_response.all_code_rd.llc_hit.hitm_other_core Counts demand data reads that hit in the LLC and the snoops sent to sibling cores return clean response REQUEST = DEMAND_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_NO_OTHER_CORE umask=0x1,period=100000,event=0xb7,offcore_rsp=0x8ff umask=0x1,period=100000,event=0xb7,offcore_rsp=0x208 REQUEST = DATA_IFETCH and RESPONSE = ANY_LOCATION REQUEST = DEMAND_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = DEMAND_DATA and RESPONSE = IO_CSR_MMIO offcore_response.demand_rfo.all_local_dram_and_remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x450 offcore_response.pf_data.local_dram_and_remote_cache_hit offcore_response.data_ifetch.other_local_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0xf880 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3050 REQUEST = PREFETCH and RESPONSE = REMOTE_DRAM snoopq_requests.code umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2701 Retired loads that hit remote socket in modified state (Precise Event) TBD TBD TBD Counts all demand data writes (RFOs) TBD umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0604000002 offcore_response.pf_l2_rfo.l3_miss.remote_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBC000400 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063FC00120 umask=0x4,period=100003,event=0xfe umask=0x1,cmask=1,period=2000003,event=0x14 umask=0x1,event=0x4 Counts CAS (Column Access Select) regular read commands issued to DRAM on a per channel basis. CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every regular read. This event only counts regular reads and does not includes underfill reads due to partial write requests. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not uncore other unc_cha_hitme_hit.ex_rds fc_mask=0x07,ch_mask=0x04,umask=0x04,event=0xc0 Write request of 4 bytes made to IIO Part3 by the CPU . Unit: uncore_iio Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part3 by a unit on the main die (generally a core). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus Write request of up to a 64 byte transaction is made to IIO Part1 by the CPU. Unit: uncore_iio Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part3 by a unit on the main die (generally a core). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus Read request for up to a 64 byte transaction is made by IIO Part2 to Memory. Unit: uncore_iio Write request of up to a 64 byte transaction is made by IIO Part1 to Memory. Unit: uncore_iio Counts every write request of up to a 64 byte transaction of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus Multi-socket cacheline Directory update from/to Any state . Unit: uncore_m2m unc_m2m_directory_update.i2a unc_m2m_imc_writes.all Count cases where flow control queue that sits between the Intel Ultra Path Interconnect (UPI) and the mesh spawns a prefetch to the iMC (Memory Controller) period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020491 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040400 offcore_response.all_rfo.l3_hit_f.hitm_other_core This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080002 offcore_response.demand_data_rd.pmm_hit_local_pmm.snoop_not_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200100 offcore_response.all_reads.l3_hit_s.hitm_other_core offcore_response.pf_l2_rfo.l3_hit_f.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100120 offcore_response.pf_l1d_and_sw.l3_hit_f.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0491 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS offcore_response.all_pf_rfo.l3_hit_e.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01004007F7 offcore_response.all_pf_rfo.l3_hit_e.no_snoop_needed offcore_response.pf_l2_data_rd.pmm_hit_local_pmm.snoop_none This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE offcore_response.all_data_rd.l3_hit_e.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C07F7 offcore_response.other.l3_hit_f.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080208000 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.SNOOP_MISS This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.ANY_SNOOP offcore_response.pf_l1d_and_sw.l3_hit_s.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080490 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040002 period=200003,umask=0x24,event=0x24 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400080 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.SNOOP_NONE offcore_response.pf_l3_data_rd.l3_hit.hit_other_core_fwd offcore_response.pf_l1d_and_sw.l3_hit_s.snoop_none This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040002 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200100 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02000207F7 offcore_response.demand_code_rd.l3_hit_e.hit_other_core_fwd offcore_response.pf_l3_rfo.pmm_hit_local_pmm.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080002 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED offcore_response.all_reads.l3_hit_f.hitm_other_core This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED offcore_response.demand_rfo.l3_hit_f.hit_other_core_fwd cmask=1,period=2000003,umask=0x1,event=0x9c cmask=2,period=2000003,umask=0x1,event=0x9c cmask=4,period=2000003,umask=0x18,event=0x79 ALL_READS & L3_MISS_LOCAL_DRAM & SNOOP_MISS_OR_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000120 offcore_response.pf_l3_rfo.l3_miss.hitm_other_core ALL_DATA_RD & L3_MISS & HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000080 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000400 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000010 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE ALL_RFO & L3_MISS_REMOTE_DRAM & SNOOP_MISS_OR_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000400 offcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.no_snoop_needed offcore_response.demand_code_rd.l3_miss.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000002 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000002 Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000001 ocr.demand_rfo.l3_miss.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00020 Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_NO_FWD offcore_response.all_reads.l3_miss.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000122 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000080 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD ocr.pf_l2_data_rd.l3_miss.remote_hit_forward ocr.all_reads.l3_miss_remote_hop1_dram.hitm_other_core Counts all demand code reads DEMAND_CODE_RD & L3_MISS_LOCAL_DRAM & ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000080 Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS & NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000120 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000020 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00002 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000120 offcore_response.all_data_rd.l3_miss_remote_hop1_dram.any_snoop ocr.other.l3_miss.snoop_miss ocr.other.l3_miss_local_dram.snoop_miss_or_no_fwd This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD ocr.pf_l3_data_rd.l3_miss_local_dram.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000120 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000004 Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS & SNOOP_NONE ocr.all_rfo.l3_miss_local_dram.hit_other_core_fwd Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_NO_FWD Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISS_OR_NO_FWD This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD Counts any other requests OTHER & L3_MISS & ANY_SNOOP ocr.demand_data_rd.l3_miss_local_dram.hit_other_core_fwd ocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.hitm_other_core ocr.all_data_rd.l3_miss_local_dram.hit_other_core_fwd ocr.demand_rfo.l3_miss_local_dram.snoop_none ocr.all_data_rd.l3_miss_local_dram.any_snoop Counts all demand code reads DEMAND_CODE_RD & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_NO_FWD ocr.demand_data_rd.l3_miss_local_dram.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED ocr.other.l3_miss.hit_other_core_fwd ocr.all_data_rd.l3_hit.snoop_hit_with_fwd ocr.other.l3_hit_s.any_snoop ALL_DATA_RD & SUPPLIER_NONE & SNOOP_MISS Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDED ALL_READS & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWD ocr.demand_data_rd.l3_hit.hit_other_core_fwd Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDED ocr.all_pf_data_rd.l3_hit_f.any_snoop ocr.demand_rfo.l3_hit.snoop_miss ocr.pf_l2_rfo.supplier_none.any_snoop ocr.pf_l1d_and_sw.supplier_none.no_snoop_needed ALL_DATA_RD & L3_HIT & NO_SNOOP_NEEDED ALL_DATA_RD & SUPPLIER_NONE & SNOOP_NONE Counts all demand data writes (RFOs) DEMAND_RFO & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDED ocr.pf_l3_rfo.l3_hit_s.hitm_other_core Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT & HIT_OTHER_CORE_FWD ocr.all_pf_rfo.l3_hit_f.no_snoop_needed ocr.other.pmm_hit_local_pmm.snoop_not_needed Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_S & HIT_OTHER_CORE_NO_FWD ALL_READS & L3_HIT_S & NO_SNOOP_NEEDED Counts all demand code reads DEMAND_CODE_RD & SUPPLIER_NONE & ANY_SNOOP ocr.all_pf_rfo.supplier_none.hitm_other_core Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & SUPPLIER_NONE & NO_SNOOP_NEEDED ocr.pf_l3_data_rd.l3_hit_e.snoop_none ocr.pf_l3_rfo.l3_hit.hit_other_core_no_fwd ocr.all_pf_data_rd.l3_hit_s.snoop_miss Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_M & HIT_OTHER_CORE_FWD Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_S & NO_SNOOP_NEEDED ocr.all_pf_data_rd.l3_hit.snoop_none Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_M & HIT_OTHER_CORE_NO_FWD ocr.demand_code_rd.l3_hit_m.hit_other_core_fwd This event counts taken branch instructions retired Spec update: SKL091 (Precise event) period=2000003,umask=0x1,event=0xb1 period=2000003,umask=0x40,event=0xcc period=400009,umask=0x1,event=0xc5 period=2000003,umask=0x2,event=0xa6 Cycles where DRAM ranks are in power down (CKE) mode+C37. Unit: uncore_imc Read Pending Queue Occupancy of all read requests for Intel Optane DC persistent memory. Unit: uncore_imc unc_m_tagchk.miss_clean unc_m_tagchk.miss_dirty umask=0x04,event=0x37 Snoop filter capacity evictions for E-state entries. Unit: uncore_cha Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part0. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.peer_write.part0 unc_iio_txn_req_by_cpu.peer_write.part2 Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus fc_mask=0x07,ch_mask=0x02,umask=0x02,event=0x84 BL Ingress (from CMS) Occupancy unc_m2m_txc_bl_occupancy.all period=100003,umask=0x1,event=0x85 period=100003,umask=0x2,event=0x85 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall (Precise event) umask=0x1,period=100007,event=0xc6,frontend=0x520006 Counts the number of PREFETCHT0 instructions executed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x000000003F04000001 period=200003,event=0xc4 umask=0xC8A7FE01,event=0x35 uncore_m2pcie Clockticks in the UBOX using a dedicated 48-bit Fixed Counter. Unit: uncore_ubox IC line invalidated due to L2 invalidating probe (external or LS). The number of instruction cache lines invalidated. A non-SMC event is CMC (cross modifying code), either from the other thread of the core or another core l2_request_g1.l2_hw_pf umask=0x40,event=0x63 umask=0x4,event=0x64 umask=0x2,event=0x64 l3_comb_clstr_state.other_l3_miss_typs event=0xc5 ex_tagged_ibs_ops.ibs_count_rollover df_ccm_reqa.node0.anydram df_ccm_reqa.node2.anydram umask=0xAE,event=0x8b umask=0x6D,event=0x8b df_ccm_reqa.node4.wrsized Data Fabric CCM Performance Monitor Event DF CCM Request Ordered anyrdblk umask=0x4A,event=0x8c umask=0x29,event=0x8c umask=0xC9,event=0x8c df_ccm_reqb.node6.anywrsized umask=0xC5,event=0x8c df_ccm_reqb.node3.wrsizedfullncposted df_ioms_reqa.node1.flush umask=0x26,event=0x108 df_ioms_reqa.node0.anywrsized>32band<64b df_ioms_reqa.node0.anywrsized=32b umask=0x24,event=0x108 umask=0x63,event=0x108 umask=0x02,event=0x108 df_ioms_reqa.node1.largeread umask=0x21,event=0x108 df_ioms_reqb.node4.pieinterrupt df_ioms_reqb.node7.anyiotransaction df_ioms_reqb.node7.ioanynon-postedwrsized=64b Total number of fp uOps on pipe 2 Double precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes. Number of Ops that are candidates for optimization (have Z-bit either set or pass) SSE bottom-executing uOps retired l3_request_g1.t2.s2.wrsizednc l3_request_g1.t3.s1.wrsized l3_request_g1.t7.s1.wrsized l3_request_g1.t7.s2.wrsized l3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x04,event=0x1 l3_request_g1.t4.s0.rdsized l3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x40,event=0x1 l3_request_g1.t4.s3.rdsized l3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x40,event=0x1 l3_request_g1.t7.s3.rdsized l3_request_g1.t3.s2.caching l3_request_g1.t7.s3.caching l3fillvicreq.t7.s1.vicblk l3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x01,event=0x3 l3fillvicreq.t6.s0.chgtox l3fillvicreq.t0.s2.chgtox l3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x02,event=0x3 l3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x02,event=0x3 l3fillvicreq.t6.s0.rdblkc_s_vic l3fillvicreq.t3.s3.rdblkc_s_vic l3fillvicreq.t5.s1.rdblkc_s l3fillvicreq.t4.s2.rdblkc_s l3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x10,event=0x3 l3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x10,event=0x3 l3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x10,event=0x3 l3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x20,event=0x3 l3fillvicreq.t6.s3.rdblkx l3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x40,event=0x3 l3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x01,event=0x9 l3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x01,event=0x9 l3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x01,event=0x9 l3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x02,event=0x9 l3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x02,event=0x9 l3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x02,event=0x9 l3victimstate.t5.s0.f_s l3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x04,event=0x9 l3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x04,event=0x9 l3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x04,event=0x9 l3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x08,event=0x9 l3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x08,event=0x9 l3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x10,event=0x9 l3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x10,event=0x9 l3victimstate.t3.s1.m l3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x20,event=0x9 l3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x40,event=0x9 l3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x40,event=0x9 l3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x40,event=0x9 l3victimstate.t2.s0.od l3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x80,event=0x9 l3victimstate.t7.s3.od umask=0xc,event=0x46 Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 2 Tokens unavailable l2_pf_miss_l2_hit_l3 umask=0xff,event=0x71 The number of instruction fetches that miss in both the L1 and L2 TLBs. Instruction fetches to a 4KB page Multiply-add FLOPS. Multiply-add counts as 2 FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15 LS MAB Allocates by Type. Loads L1 DTLB Miss. DTLB reload to a 2M page that hit in the L2 TLB umask=0x1,event=0xaa Count of dispatched Ops from Decoder FR_DISPATCH_STALL_FOR_SERIALIZATION MEM_ERROR TTBR_WRITE L1_DCACHE_HASH_MISS L1_DCACHE_NEON_CACHEABLE MAIN_EXECUTION_UNIT_PIPE L2D_CACHE_LD L1I_TLB MEM_CAP_WRITE L2CACHEMASTER_WRITE_REQ INTEGER_MULDIV_COMPLETED L2_IMISS_STALL_CYCLES CPO_READ_STALLS REQUEST_COUNT KILLED_FETCH_SLOTS MDU_DSP_SATURATION_INSNS GRADUATION_REPLAYS REFRESHED_DSTS FP_LOAD_SINGLE_INSTR_COMPLETED_IN_LSU LOAD_INSTR_COMPLETED FIRST_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLY FPR_ISSUE_QUEUE_ENTRIES MARKED_GROUP_COMPLETED CR_MARKED_INSTR_FINISH FXU_MARKED_INSTR_FINISHED LOAD_UOPS_COMPLETED CYCLES_SU2_SCHED_STALLED MISALIGNED_LOAD_STORE_ACCESS_TRANSLATED BIU_MASTER_DATA_SIDE_REQUESTS DLFB_LOAD_MISS_CYCLES STORE_RETRIES DVT1_DETECTED unhalted-cycles edge low-op-pos-2 SOFT-CLOCK.HARD INTERRUPT TAGGING INTEL_XSCALE "0x%016jx", v10 GenuineIntel-6-55-[01234] 1 / inst_retired.any / cycles (cstate_pkg@c6\-residency@ / msr@tsc@) * 100 umask=0x44,period=200003,event=0x24 This event counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches Requests from L2 hardware prefetchers This event counts the number of WB requests that hit L2 cache umask=0x1,any=1,cmask=1,period=2000003,event=0x48 This event counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS Spec update: BDM76 offcore_response mem_load_uops_retired.l1_hit umask=0x2,period=100003,event=0xd1 umask=0x2,period=20011,event=0xd2 This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches. This is a precise event Supports address when precise. Spec update: BDE70, BDM100 mem_load_uops_l3_miss_retired.remote_dram l2_trans.all_requests L2 cache lines in S state filling L2 Split locks in SQ Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ? fp_arith_inst_retired.packed This event counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention This event counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ idq.ms_mite_uops umask=0x40,period=2000003,event=0x54 Loads with latency value being above 4 Spec update: BDM100, BDM35 (Must be precise) This event counts the number of Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) umask=0x1,period=1000003,event=0x58 This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk br_inst_exec.all_direct_jmp umask=0x10,any=1,period=2000003,event=0xa1 Cycles per core when uops are exectuted in port 4 uops_executed.cycles_ge_4_uops_exec umask=0x2,cmask=3,period=2000003,event=0xb1 This event counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two) Spec update: BDM61 umask=0x20,period=400009,event=0xc5 1 llc_references.pcie_read umask=0xC,event=0x1 llc_misses.mem_read freq_max_power_cycles % Code miss in all TLB levels causes a page walk that completes. (2M/4M) Spec update: BDM69 umask=0x8,period=100003,event=0x85 This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example ( uops_issued.any - uops_retired.retire_slots + 4 * int_misc.recovery_cycles ) / (4 * cycles) Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache) IpL Floating Point Operations Per Cycle Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor) Miss in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS) Spec update: BDM100, BDE70. Supports address when precise (Precise event) This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches. This is a precise event Spec update: BDE70, BDM100. Supports address when precise umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020001 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0001 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0001 Counts all demand code reads umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010008 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020008 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0008 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010020 offcore_response.pf_l2_code_rd.supplier_none.snoop_hit_no_fwd offcore_response.pf_l3_data_rd.l3_hit.snoop_hit_no_fwd offcore_response.pf_l3_rfo.supplier_none.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020100 Counts any other requests have any response type umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080028000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100028000 offcore_response.all_pf_rfo.l3_hit.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020091 offcore_response.all_data_rd.l3_hit.snoop_none umask=0x1,period=2000003,cmask=3,event=0x9c Counts randomly selected loads with latency value being above four Spec update: BDM100, BDM35 (Must be precise) Randomly selected loads with latency value being above 16 Spec update: BDM100, BDM35 (Must be precise) Counts randomly selected loads with latency value being above 16 Spec update: BDM100, BDM35 (Must be precise) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000008 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000008 offcore_response.pf_l2_data_rd.l3_miss.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000080 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000080 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000100 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104008000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84008000 offcore_response.all_pf_data_rd.l3_hit.snoop_non_dram offcore_response.all_pf_rfo.l3_hit.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000120 offcore_response.all_data_rd.l3_miss_local_dram.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000122 Unit: uncore_cbox L3 Lookup read request that access cache and found line in I-state umask=0x02,event=0x81 Unit: uncore_arb Number of Writes allocated - any write transactions: full/partials writes and evictions This event counts store uops retired to the architected path with a filter on bits 0 and 1 applied.
Note: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement Supports address when precise (Precise event) offcore_response.demand_rfo.llc_hit.hitm_other_core Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache offcore_response.all_data_rd.llc_miss.remote_hit_forward umask=0x1,period=100003,event=0xb7,offcore_rsp=0x087FC00091 offcore_response.pf_llc_rfo.llc_miss.any_response Actually retired uops Supports address when precise (Precise event) Retirement slots used (Precise event) Direct and indirect near call instructions retired (Precise event) L2 cache misses l2_lines_in.self.demand L2 cache reads umask=0x78,period=200000,event=0x29 l2_ld.self.demand.e_state umask=0x41,period=200000,event=0x29 umask=0x41,period=200000,event=0x2c umask=0x41,period=200000,event=0x30 l1d_cache.all_ref umask=0x48,period=200000,event=0x40 fp_assist.ar SIMD micro-ops executed (excluding stores) umask=0x4,period=2000000,event=0xb3 Memory references that cross an 8-byte boundary (At Retirement) Nonzero segbase 1 bubble umask=0x81,period=200000,event=0x7 segment_reg_loads.any Number of thermal trips umask=0x21,period=200000,event=0x77 Bus queue is empty IO requests waiting in the bus queue br_inst_type_retired.dir_call br_inst_retired.mispred data_tlb_misses.dtlb_miss_st umask=0x42,period=200003,event=0xd0 Memory uops retired that split a cache-line (Precise event capable) Supports address when precise (Must be precise) Memory uops retired (Precise event capable) Supports address when precise (Must be precise) Counts load uops retired that hit in the L2 cache Supports address when precise (Must be precise) Counts reads for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required offcore_response.streaming_stores.l2_miss.any umask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600004800 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600004000 offcore_response.full_streaming_stores.l2_miss.hitm_other_core Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required offcore_response.demand_data_rd.l2_hit MS decode starts Cycles code-fetch stalled due to any reason Cycles pending interrupts are masked umask=0x8,period=2000003,event=0xc2 Machine clears due to memory disambiguation Counts Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired that were taken and does not count when the Jcc branch instruction were not taken (Must be precise) umask=0x1,period=200003,event=0xcd Counts every core cycle when a Instruction-side (walks due to an instruction fetch) page walk is in progress Counts demand reads for ownership (RFO) requests generated by a write to full data cache line miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts the number of writeback transactions caused by L1 or L2 cache evictions hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000013091 Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 2M or 4M pages. The page walks can end with or without a page fault umask=0x10,period=200003,event=0x49 Dirty L2 cache lines evicted by demand Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled Spec update: HSD135 Cycles with less than 3 uops delivered by the front end Spec update: HSD135 Number of times an HLE execution aborted due to incompatible memory type Spec update: HSD65 Number of times an RTM execution aborted due to incompatible memory type Spec update: HSD65 offcore_response.all_rfo.l3_miss.local_dram Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling Number of integer move elimination candidate uops that were not eliminated unc_cbo_xsnp_response.hitm_external umask=0x4f,event=0x34 unc_arb_coh_trk_occupancy.all Code miss in all TLB levels causes a page walk that completes. (2M/4M) Number of DTLB page walker loads that hit in the L3 Spec update: HSD25 umask=0x28,period=2000003,event=0xbc Number of ITLB page walker loads from memory Spec update: HSD25 umask=0x10,period=100003,event=0xd3 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00010 RFOs that miss cache lines Counts all demand & prefetch code reads that hit in the LLC umask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0001 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10800 Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s arith.fpu_div Counts total number of uops to be executed per-thread each cycle. Set Cmask = 1, INV =1 to count stall cycles Number of self-modifying-code machine clears detected Unit: uncore_cbox A snoop hits a modified line in some processor core Filter on cross-core snoops initiated by this Cbox due to LLC eviction Data forwarded from remote cache Counts prefetch data reads that hit in the LLC and sibling core snoop returned a clean response Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0080 Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3fffc20091 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x87f820001 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3fffc20010 Counts prefetch (that bring data to L2) data reads that miss in the LLC Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote dram ItoM write hits (as part of fast string memcpy stores). Derived from unc_c_tor_inserts.opcode.itom_write_hit. Unit: uncore_cbox Occupancy counter for LLC data reads (demand and L2 prefetch). Derived from unc_c_tor_occupancy.miss_opcode.llc_data_read. Unit: uncore_cbox Number of non data (control) flits transmitted . Unit: uncore_qpi unc_p_freq_band3_transitions Counts the number of cycles that the uncore transitioned to a frequency greater than or equal to the frequency that is configured in the filter. (filter_band3=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Derived from unc_p_freq_band3_cycles. Unit: uncore_pcu freq_max_current_cycles % unc_p_freq_ge_4000mhz_cycles Retired load uops that miss the STLB (Precise event) umask=0x2,period=2000003,event=0xac offcore_response.all_demand_mlc_pref_reads.llc_miss.local_dram insts_written_to_iq.insts Counts the number of cycles that the uncore transitioned to a frequency greater than or equal to the frequency that is configured in the filter. (filter_band2=XXX with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Derived from unc_p_freq_band2_cycles. Unit: uncore_pcu This event counts load operations that miss the first DTLB level but hit the second and do not cause any page walks. The penalty in this case is approximately 7 cycles umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400044 offcore_response.any_code_rd.any_response umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010044 offcore_response.any_request.l2_hit_near_tile_m Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state Counts Full streaming stores (WC and should be programmed on PMC1) that accounts for any response offcore_response.bus_locks.l2_hit_far_tile_m Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002000001 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002008000 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002000044 offcore_response.bus_locks.l2_hit_this_tile_e Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in S state Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in S state umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010003091 offcore_response.any_code_rd.l2_hit_near_tile umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800400040 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x00802032f7 offcore_response.any_data_rd.mcdram_near offcore_response.pf_software.ddr_near Counts Bus locks and split lock requests that accounts for data responses from DRAM Local Counts L2 code HW prefetches that accounts for data responses from DRAM Local offcore_response.pf_l2_rfo.ddr_near umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400004 Counts Demand cacheable data writes that accounts for data responses from MCDRAM Far or Other tile L2 hit far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000002 Counts demand cacheable data and L1 prefetch data reads that accounts for responses from MCDRAM (local and far) offcore_response.any_rfo.mcdram Counts the number of branch instructions retired that were conditional jumps and predicted taken (Precise event) Counts the number of near CALL branch instructions retired (Precise event) Counts the number of times that the machine clears due to program modifying data within 1K of a recently fetched code page umask=0x1,period=200000,event=0x4e l1d_wb_l2.e_state umask=0xff,period=200000,event=0x26 l2_data_rqsts.prefetch.e_state umask=0x1,period=100000,event=0xf2 L2 prefetch hits L1D writeback to L2 transactions umask=0x2,period=200000,event=0xf0 l2_write.lock.e_state l2_write.rfo.s_state umask=0x10,period=10000,event=0xf Memory instructions retired above 256 clocks (Precise Event) umask=0x10,period=3,event=0xb,ldlat=0x8000 Offcore data reads satisfied by the LLC and HIT in a sibling core umask=0x1,period=100000,event=0xb7,offcore_rsp=0x811 offcore_response.any_request.any_cache_dram offcore_response.any_request.llc_hit_other_core_hit Offcore RFO requests satisfied by a remote cache or remote DRAM Offcore demand data requests satisfied by the IO, CSR, MMIO unit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1803 Offcore demand RFO requests satisfied by the LLC or local DRAM Offcore other requests satisfied by the LLC or local DRAM Offcore other requests that HIT in a remote cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x130 Offcore prefetch data requests satisfied by a remote cache Offcore prefetch data reads that HIT in a remote cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4740 offcore_response.pf_rfo.remote_cache_hit offcore_response.prefetch.io_csr_mmio fp_comp_ops_exe.sse_fp_scalar SSE FP scalar Uops SSE* FP single precision Uops 128 bit SIMD integer pack operations umask=0x40,period=200000,event=0x12 macro_insts.decoded Offcore RFO requests satisfied by any DRAM Offcore demand code reads that missed the LLC offcore_response.demand_ifetch.local_dram Offcore demand code reads satisfied by a remote DRAM Offcore prefetch data reads that missed the LLC Offcore prefetch code reads satisfied by a remote DRAM Loads dispatched from stage 305 Partial register stall cycles Super Queue full stall cycles Mispredicted conditional branches executed ild_stall.mru resource_stalls.rob_full inv=1,umask=0x1,period=2000000,cmask=1,event=0xc2 dtlb_load_misses.pde_miss DTLB load miss caused by low part of address mem_load_retired.l1_miss umask=0x1,period=200003,event=0xf2 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02001C8000 offcore_response.other.l3_hit.spl_hit offcore_response.other.l3_hit_s.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200400004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100040004 offcore_response.demand_rfo.l4_hit_local_l4.spl_hit offcore_response.demand_rfo.l3_hit_e.snoop_none offcore_response.demand_data_rd.l3_hit_s.snoop_hit_no_fwd icache_64b.iftag_miss Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ cycle_activity.stalls_l3_miss Number of times an HLE execution aborted due to hardware timer expiration Core cycles the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event This event counts cycles during which the microcode scoreboard stalls happen Cycles total of 2 uops are executed on all ports and Reservation Station was not empty Cycles total of 3 uops are executed on all ports and Reservation Station was not empty Number of uops delivered to the back-end by the LSD(Loop Stream Detector) Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path Store misses in all TLB levels causes a page walk that completes. (All page sizes) Code miss in all TLB levels causes a page walk that completes. (1G) rehabq.st_splits Counts demand and DCU prefetch RFOs that hit in the other module where modified copies were found in other core's L1 cache This event counts the number of times that a program writes to a code section. Self-modifying code causes a severe penalty in all Intel? architecture processors This event counts retired load uops that hit in the last-level (L3) cache without snoops required. (Precise Event - PEBS) (Precise event) offcore_response.pf_llc_code_rd.llc_hit.hit_other_core_no_fwd Counts all prefetch (that bring data to L2) code reads that miss the LLC and the data returned from dram REQUEST = ANY_REQUEST and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM offcore_response.pf_l_ifetch.llc_miss_local.dram Mispredicted taken branch instructions retired. (Precise Event - PEBS) (Precise event) REQUEST = ANY_DATA read and RESPONSE = ANY_LOCATION REQUEST = ANY_REQUEST and RESPONSE = ANY_LOCATION REQUEST = DATA_IFETCH and RESPONSE = REMOTE_CACHE_HITM REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_CORE REQUEST = DEMAND_IFETCH and RESPONSE = ANY_LOCATION REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM REQUEST = PREFETCH and RESPONSE = IO_CSR_MMIO REQUEST = ANY_DATA read and RESPONSE = REMOTE_DRAM REQUEST = DEMAND_RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD offcore_response.prefetch.other_local_dram snoopq_requests_outstanding.code_not_empty umask=0x4,period=20000,event=0xc5 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5833 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5850 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5870 umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF850 mem_uncore_retired.local_dram_and_remote_cache_hit umask=0x2,period=100007,event=0xd3 offcore_response.pf_l3_data_rd.l3_hit.no_snoop_needed offcore_response.pf_l1d_and_sw.l3_hit.any_snoop offcore_response.demand_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd Counts demand instruction fetches and L1 instruction cache prefetches that TBD offcore_response.demand_code_rd.l3_miss.snoop_miss_or_no_fwd Counts all prefetch (that bring data to LLC only) RFOs TBD offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd Counts all CAS (Column Address Select) commands issued to DRAM per memory channel. CAS commands are issued to specify the address to read or write on DRAM, so this event increments for every read and write. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not umask=0x21,event=0x35,config1=0x40040e33 umask=0x21,event=0x35,config1=0x41833 UPI interconnect send bandwidth for payload. Derived from unc_upi_txl_flits.all_data. Unit: uncore_upi ll fc_mask=0x07,ch_mask=0x01,umask=0x01,event=0x83 umask=0x82,event=0x33 unc_cha_snoop_resp.rspifwd Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.mem_write.part0 fc_mask=0x07,ch_mask=0x08,umask=0x01,event=0xc1 Counts every read request for up to a 64 byte transaction of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus Counts cycles when direct to core mode (which bypasses the CHA) was disabled Writes to iMC issued. Unit: uncore_m2m Inserts into the Memory Controller Prefetch Queue. Unit: uncore_m2m umask=0x4,event=0x31 Counts null FLITs (80 bit FLow control unITs) transmitted via any of the 3 Intel Ulra Path Interconnect (UPI) slots on this UPI unit period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD offcore_response.pf_l2_rfo.l3_hit_f.hitm_other_core This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED offcore_response.demand_data_rd.l3_hit_s.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200020 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080120 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040120 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE offcore_response.pf_l3_rfo.supplier_none.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040400 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200080 offcore_response.all_rfo.l3_hit_s.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0002 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080122 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100010 offcore_response.pf_l1d_and_sw.l3_hit_m.hitm_other_core This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_MISS period=100003,umask=0x41,event=0xd0 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080400 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE offcore_response.other.l3_hit_e.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100088000 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020122 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.SNOOP_MISS This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP Counts retired load instructions with local Intel® Optane™ DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode). Precise event Supports address when precise (Precise event) This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.ALL_DATA_RD.ANY_RESPONSE This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE offcore_response.pf_l1d_and_sw.pmm_hit_local_pmm.snoop_none This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE offcore_response.pf_l2_rfo.supplier_none.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020002 offcore_response.all_rfo.pmm_hit_local_pmm.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100108000 offcore_response.all_data_rd.l3_hit_m.snoop_none This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080010 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020100 offcore_response.pf_l2_rfo.l3_hit.hit_other_core_fwd offcore_response.other.pmm_hit_local_pmm.snoop_not_needed This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400100 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element period=2000003,umask=0x20,event=0xc7 period=2000003,umask=0x4,event=0xc7 Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element period=100007,umask=0x1,event=0xc6,frontend=0x300206 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall (Precise event) Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops (Precise event) This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000100 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08100007F7 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000020 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000400 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000020 ocr.demand_rfo.l3_miss_remote_hop1_dram.hitm_other_core Counts all demand data writes (RFOs) DEMAND_RFO & L3_MISS_REMOTE_HOP1_DRAM & HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000001 Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS_LOCAL_DRAM & NO_SNOOP_NEEDED offcore_response.pf_l3_data_rd.l3_miss_local_dram.hit_other_core_no_fwd Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & HITM_OTHER_CORE Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS_REMOTE_DRAM & SNOOP_MISS_OR_NO_FWD This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD ocr.demand_rfo.l3_miss.remote_hitm Counts all demand data writes (RFOs) DEMAND_RFO & L3_MISS & REMOTE_HITM This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD period=1009,umask=0x1,event=0xcd,ldlat=0x80 period=2000003,umask=0x40,event=0x54 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP ALL_RFO & L3_MISS_LOCAL_DRAM & NO_SNOOP_NEEDED ALL_RFO & L3_MISS_LOCAL_DRAM & SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B808000 ocr.other.l3_miss.remote_hit_forward period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00491 ocr.demand_data_rd.l3_miss_local_dram.any_snoop ocr.demand_data_rd.l3_miss_remote_hop1_dram.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000020 ocr.pf_l3_data_rd.l3_miss_local_dram.hitm_other_core Counts demand data reads DEMAND_DATA_RD & L3_MISS & HITM_OTHER_CORE ALL_RFO & L3_MISS & REMOTE_HITM period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000491 ALL_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & SNOOP_NONE ocr.all_rfo.l3_miss.snoop_none This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.REMOTE_HITM offcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210008000 ALL_RFO & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_NO_FWD Counts demand data reads DEMAND_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & NO_SNOOP_NEEDED ALL_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & ANY_SNOOP Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS_REMOTE_HOP1_DRAM & HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE ocr.pf_l2_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C008000 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00004 Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS_REMOTE_DRAM & SNOOP_MISS_OR_NO_FWD offcore_response.demand_data_rd.l3_miss.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000400 This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS offcore_response.all_reads.l3_miss_remote_hop1_dram.snoop_none ALL_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & HITM_OTHER_CORE ocr.pf_l2_rfo.l3_miss_local_dram.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000004 offcore_response.demand_code_rd.l3_miss_remote_hop1_dram.snoop_miss Counts any other requests OTHER & L3_HIT_S & NO_SNOOP_NEEDED ocr.demand_rfo.l3_hit_e.any_snoop ocr.pf_l2_rfo.any_response ocr.pf_l2_data_rd.supplier_none.no_snoop_needed ALL_PF_DATA_RD & L3_HIT_S & HIT_OTHER_CORE_NO_FWD ALL_PF_DATA_RD & ANY_RESPONSE have any response type ocr.other.l3_hit_s.hit_other_core_fwd ocr.all_data_rd.l3_hit_s.snoop_miss ALL_PF_RFO & L3_HIT_E & NO_SNOOP_NEEDED ALL_RFO & PMM_HIT_LOCAL_PMM & SNOOP_NONE ocr.other.l3_hit.hit_other_core_fwd ocr.pf_l3_rfo.supplier_none.no_snoop_needed ocr.other.supplier_none.any_snoop ocr.all_reads.l3_hit.no_snoop_needed ocr.all_reads.any_response ocr.all_reads.l3_hit_s.hitm_other_core Counts demand data reads DEMAND_DATA_RD & L3_HIT_F & HIT_OTHER_CORE_FWD ocr.other.l3_hit_f.any_snoop ocr.demand_rfo.l3_hit_e.no_snoop_needed Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_E & HIT_OTHER_CORE_NO_FWD ocr.all_data_rd.l3_hit_m.any_snoop ALL_RFO & L3_HIT_E & NO_SNOOP_NEEDED ocr.all_rfo.l3_hit_s.hit_other_core_fwd ocr.pf_l2_rfo.l3_hit_m.hitm_other_core ocr.demand_rfo.l3_hit.snoop_none ocr.all_data_rd.l3_hit_f.hit_other_core_fwd ocr.demand_code_rd.l3_hit_e.hit_other_core_no_fwd ocr.all_data_rd.supplier_none.no_snoop_needed Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_S & NO_SNOOP_NEEDED Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_E & HIT_OTHER_CORE_FWD This event counts conditional branch instructions retired Spec update: SKL091 (Precise event) Counts the number of entries in the Write Pending Queue (WPQ) at each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule writes out to the memory controller and to track the requests. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC (memory controller). They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the 'not posted' filter, we can track how long writes spent in the iMC before completions were sent to the HA. The 'posted' filter, on the other hand, provides information about how much queueing is actually happenning in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts. Is there a filter of sorts??? Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part0. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part1. Unit: uncore_iio unc_iio_data_req_by_cpu.peer_write.part0 Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part2 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part0. In the general case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part1. Unit: uncore_iio fc_mask=0x07,ch_mask=0x08,umask=0x08,event=0xc1 Peer to peer write request of up to a 64 byte transaction is made to IIO Part1 by a different IIO unit. Unit: uncore_iio Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part1 to the MMIO space of an IIO target.In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus l2_rqsts.swpf_hit Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type Counts the number of cache lines replaced in L1 data cache Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache Supports address when precise (Precise event) assists.fp Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall (Precise event) Counts the number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts) Number of uops executed on port 2 and 3 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 2 and 3 Counts conditional branch instructions retired (Precise event) Counts number of near branch instructions retired that were mispredicted and taken Supports address when precise (Precise event) This event distributes cycle counts between active hyperthreads, i.e., those in C0. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If all other hyperthreads are inactive (or disabled or do not exist), all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread Counts the number of store uops retired Supports address when precise (Precise event) Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 unc_iio_data_req_of_cpu.mem_write.part7 branch L2 BTB Correction umask=0x2,event=0x61 LS to L2 WCB write requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) write requests Cycles with fill pending from L2. Total cycles spent with one or more fill requests in flight from L2 xi_sys_fill_latency ex_ret_brn ex_ret_brn_tkn umask=0x8D,event=0x8b df_ccm_reqa.node1.rdsizednc df_ccm_reqa.node4.specdramrd umask=0xE6,event=0x8b df_ccm_reqa.node6.rdvlkx umask=0xE3,event=0x8b df_ccm_reqa.node6.rdvlks umask=0x2C,event=0x8c df_ccm_reqb.node6.wbinvblkall umask=0x26,event=0x8c df_ccm_reqb.node7.anywrsized df_ccm_reqb.node5.wrsizedfullncposted df_ccm_reqb.node5.rdsized umask=0xC1,event=0x8c df_ccm_reqc.fasttprwrite umask=0x6A,event=0x108 df_ioms_reqa.node4.flush umask=0x87,event=0x108 umask=0xE7,event=0x108 df_ioms_reqa.node1.anywrsized<32b df_ioms_reqa.node3.largeread umask=0xCE,event=0x109 df_ioms_reqb.node7.pieinterrupt df_ioms_reqb.node7.ioanynon-postedwrsized=32b umask=0x67,event=0x109 df_ioms_reqb.node0.ioanyrdsized df_ioms_reqb.node4.ioanyrdsized umask=0xC2,event=0x109 df_ioms_reqb.node6.iolargeread The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to pipe 2 fp_ret_sse_avx_ops.dp_mult_add_flops fp_ret_sse_avx_ops.dp_mult_flops l3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x02,event=0x1 l3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x02,event=0x1 l3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x02,event=0x1 l3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x02,event=0x1 l3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x02,event=0x1 l3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x04,event=0x1 l3_request_g1.t5.s0.wrsized l3_request_g1.t4.s1.wrsized l3_request_g1.t0.s3.wrsized l3_request_g1.t3.s1.rdsizednc l3_request_g1.t6.s3.rdsizednc l3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x40,event=0x1 l3_request_g1.t2.s1.rdsized l3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x80,event=0x1 l3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x80,event=0x1 l3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x01,event=0x3 l3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x01,event=0x3 l3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x04,event=0x3 l3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x04,event=0x3 l3fillvicreq.t7.s3.rdblkc_s_vic l3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x08,event=0x3 l3fillvicreq.t1.s2.rdblkc_s l3fillvicreq.t4.s0.rdblkx_vic l3fillvicreq.t0.s3.rdblkx_vic l3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x20,event=0x3 l3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x40,event=0x3 l3fillvicreq.t4.s1.rdblkl_vic l3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x40,event=0x3 l3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x40,event=0x3 l3fillvicreq.t0.s2.rdblkl_vic l3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x40,event=0x3 l3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x80,event=0x3 l3fillvicreq.t2.s3.rdblkl l3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x80,event=0x3 l3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x01,event=0x9 l3victimstate.t5.s1.nol3victimline l3victimstate.t5.s0.none_nol3victimline l3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x02,event=0x9 l3victimstate.t1.s3.none_nol3victimline l3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x04,event=0x9 l3victimstate.t1.s2.f_s l3victimstate.t3.s1.o l3victimstate.t1.s2.e_fe l3victimstate.t1.s0.m l3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x20,event=0x9 l3victimstate.t1.s2.m l3victimstate.t1.s3.m l3victimstate.t5.s0.d l3victimstate.t2.s2.d l3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x80,event=0x9 l3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x80,event=0x9 l3victimstate.t2.s3.od ls_dc_accesses umask=0x8,event=0x46 de_dis_dispatch_token_stalls0.alsq3_0_token_stall fp_disp_faults.ymm_fill_fault Number of interrupts taken event=0x2d Demand Data Cache Fills by Data Source. Local L2 hit de_dis_uops_from_decoder.decoder_dispatched de_dis_dispatch_token_stalls1.fp_misc_rsrc_stall NB_SIZED_COMMANDS L2_CACHE_ACCESS DMB_SPEC EXC_DABORT STREX_SPEC DCACHE_WRITE_HIT L2CACHEMASTER_WRITE_REQ_FLIT TAGCACHEMASTER_WRITE_RSP ITLB_MISSES MISPREDICTED_BRANCH_INSNS_CYCLES DISSUE IUNA PMON_SIG VPU_INSTR_WAIT_CYCLES L1_DATA_PUSHES L2_TOUCH_HITS MARKED_GROUP_DISPATCH GCT_EMPTY_BY_BRANCH_MISS_PREDICT STORE_NO_REAL_ADDR STORES_TRANSLATED DATA_L1_CACHE_LOCKS DATA_MMU_BUSY_CYCLES INSTR_L1_CACHE_RELOADS BIU_MASTER_REQUESTS ILFB_FETCH_MISS_CYCLES CRIT_INPUT_INTR_PENDING_LATENCY_CYCLES INTV_ALLOCATIONS STASH_HIT_DLFB L2_CLEAN_LINE_INVALIDATIONS IAC2S_DETECTED DVT4_DETECTED FPU_FPSCR_FULL_STALL ds dc-fill data CASCADE INTEL_BROADWELL_XEON MIPS_OCTEON FREE DELETED ps->ps_len == 0 /usr/src/lib/libpmc/libpmc_pmu_util.c LLC-MISSES any {"type": "pmcattach" %s, "pid": "%d", "flags": "0x%08x", "pcomm": "%s"}
GenuineIntel-6-1A Instructions Per Cycle (per logical thread) DSB_Coverage l1d_pend_miss.pending / ( cpu@l1d_pend_miss.pending_cycles\,any\=1@ / 2) if #smt_on else l1d_pend_miss.pending_cycles SMT_2T_Utilization umask=0x24,period=200003,event=0x24 umask=0x3f,period=200003,event=0x24 Demand requests to L2 cache This event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace offcore_requests_outstanding.demand_data_rd_ge_6 umask=0x2,period=2000003,event=0x60 umask=0x8,period=2000003,event=0x60 offcore_requests_outstanding.cycles_with_data_rd umask=0x1,period=2000003,event=0xb2 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction mem_uops_retired.all_loads L2 or L3 HW prefetches that access L2 cache L1D writebacks that access L2 cache l2_lines_in.e L2 cache lines in E state filling L2 fp_arith_inst_retired.256b_packed_double edge=1,umask=0x10,cmask=1,period=2000003,event=0x79 idq.all_mite_cycles_any_uops icache.hit icache.misses Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow Number of times HLE aborted and was not due to the abort conditions in subevents 3-6 mem_trans_retired.load_latency_gt_16 uops_issued.any Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate) cpu_clk_unhalted.ref_xclk_any uop_dispatches_cancelled.simd_prf Counts the number of uops to be executed per-thread each cycle umask=0x1,cmask=4,period=2000003,event=0xb1 Direct and indirect macro near call instructions retired (captured in ring 3). (Precise Event - PEBS) (Precise event) Not taken branch instructions retired umask=0x1,event=0x35,filter_opc=0x18d read requests to remote home agent. Unit: uncore_ha (unc_p_freq_trans_cycles / unc_p_clockticks) * 100. dtlb_load_misses.walk_duration umask=0x10,period=100003,event=0x85 umask=0x20,period=100003,event=0x85 umask=0x60,period=100003,event=0x85 page_walker_loads.dtlb_memory This event counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on) inst_retired.any / mem_uops_retired.all_loads Branches;Instruction_Type ( cpu@itlb_misses.walk_duration\,cmask\=1@ + cpu@dtlb_load_misses.walk_duration\,cmask\=1@ + cpu@dtlb_store_misses.walk_duration\,cmask\=1@ + 7 * ( dtlb_store_misses.walk_completed + dtlb_load_misses.walk_completed + itlb_misses.walk_completed ) ) / (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )) L1 cache true misses per kilo instruction for retired demand loads This is a precise version (that is, uses PEBS) of the event that counts load uops with locked access retired to the architected path Spec update: BDM35. Supports address when precise (Precise event) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0001 offcore_response.demand_code_rd.l3_hit.snoop_hit_no_fwd Counts writebacks (modified to exclusive) have any response type offcore_response.pf_l2_rfo.supplier_none.snoop_hitm offcore_response.pf_l2_rfo.l3_hit.any_snoop offcore_response.pf_l2_code_rd.l3_hit.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0040 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0080 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0100 Counts prefetch (that bring data to LLC only) code reads have any response type umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020200 offcore_response.pf_l3_code_rd.l3_hit.snoop_not_needed offcore_response.other.l3_hit.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0090 output - Numeric Overflow, Numeric Underflow, Inexact Result (Precise Event) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0002 offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000080 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000100 offcore_response.pf_l3_rfo.l3_miss.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000120 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000122 offcore_response.all_rfo.l3_miss.snoop_hit_no_fwd Unit: uncore_cbox A cross-core snoop resulted from L3 Eviction which misses in some processor core Unit: uncore_cbox L3 Lookup write request that access cache and found line in MESI-state Unit: uncore_cbox L3 Lookup any request that access cache and found line in E or S-state umask=0x01,event=0x80 Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded offcore_response.all_rfo.llc_hit.hitm_other_core Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded offcore_response.all_rfo.llc_miss.any_response offcore_response.pf_llc_code_rd.llc_miss.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00100 unc_q_clockticks umask=0x40,period=200000,event=0x27 umask=0x41,period=200000,event=0x28 l2_ifetch.self.mesi umask=0x4f,period=200000,event=0x28 umask=0x48,period=200000,event=0x2a umask=0x44,period=200000,event=0x2b L2 locked accesses umask=0x42,period=200000,event=0x30 Cycles no L2 cache requests are pending mem_load_retired.l2_hit x87_comp_ops_exe.any.s SIMD micro-ops retired (excluding stores) (Must be precise) umask=0x10,period=2000000,event=0xb3 umask=0xa0,period=2000000,event=0xb3 Retired Streaming SIMD Extensions (SSE) scalar-single instructions prefetch.software_prefetch umask=0x20,period=200000,event=0x61 bus_trans_rfo.self ext_snoop.all_agents.hitm umask=0x1,period=2000000,event=0xc6 umask=0x81,period=200000,event=0x2 data_tlb_misses.l0_dtlb_miss_st page_walks.d_side_walks Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_read.l2_hit umask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600003010 Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cache lines requests by software prefetch instructions that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts reads for ownership (RFO) requests generated by L2 prefetcher that hit the L2 cache offcore_response.corewb.l2_miss.hit_other_core_no_fwd umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200000008 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000001 Counts demand cacheable data reads of full cache lines that true miss for the L2 cache with a snoop miss in the other processor module Counts the number of core cycles during which interrupts are masked (disabled). Increments by 1 each core cycle that EFLAGS.IF is 0, regardless of whether interrupts are pending or not umask=0x0,period=2000003,event=0xc2 Uops retired (Precise event capable) (Must be precise) umask=0x1,period=200003,event=0xc3 umask=0x0,period=200003,event=0xc4 br_misp_retired.return Retired mispredicted near indirect call instructions (Precise event capable) (Must be precise) Counts BACLEARS on Jcc (Jump on Conditional Code/Jump if Condition is Met) branches umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010002 Counts demand reads for ownership (RFO) requests generated by a write to full data cache line outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache hit the L2 cache offcore_response.demand_code_rd.l2_miss.hitm_other_core Counts the number of writeback transactions caused by L1 or L2 cache evictions have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.sw_prefetch.outstanding umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000012000 Counts any data writes to uncacheable write combining (USWC) memory region hit the L2 cache umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000022 ept.walk_pending Demand data read requests sent to uncore Spec update: HSD78 Retired load uops with locked access. (precise Event) Spec update: HSD76, HSD29, HSM30. Supports address when precise (Precise event) Retired store uops that split across a cacheline boundary. (precise Event) Spec update: HSD29, HSM30. Supports address when precise (Precise event) This event counts store uops retired which had memory addresses spilt across 2 cache lines. A line split is across 64B cache-lines which may include a page split (4K). This is a precise event Spec update: HSD29, HSM30. Supports address when precise (Precise event) umask=0x20,period=100003,event=0xd1 Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready Spec update: HSM30. Supports address when precise (Precise event) Counts all prefetch (that bring data to LLC only) code reads hit in the L3 Counts all demand code reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles icache.ifetch_stall Speculative cache-line split store-address uops dispatched to L1D offcore_response.all_code_rd.l3_miss.any_response This event counts the number of cycles spent waiting for a recovery after an event such as a processor nuke, JEClear, assist, hle/rtm abort etc arith.divider_uops umask=0x2,period=2000003,event=0x14 Number of SIMD move elimination candidate uops that were not eliminated This event counts cycles during which no instructions were allocated because no Store Buffers (SB) were available Code miss in all TLB levels causes a page walk that completes. (4K) page_walker_loads.ept_dtlb_l3 umask=0x44,period=2000003,event=0xbc Retired load uops that miss the STLB Supports address when precise. Spec update: HSD29, HSM30 (Precise event) Miss in last-level (L3) cache. Excludes Unknown data-source Supports address when precise. Spec update: HSD74, HSD29, HSD25, HSM26, HSM30 (Precise event) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x083FC00091 Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles Dirty L2 cache lines evicted by the MLC prefetcher offcore_response.demand_code_rd.llc_hit.no_snoop_needed Counts all demand data reads that hit in the LLC Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle Number of transitions from AVX-256 to legacy SSE when penalty applicable page_walks.llc_miss Loads with latency value being above 512 (Must be precise) Cycles which a Uop is dispatched on port 2 Cycles with pending L1 cache miss loads. Set AnyThread to count per core Unit: uncore_cbox Filter on processor core initiated cacheable read requests Misses in all TLB levels that cause a page walk of any page size from demand loads Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded umask=0x1,period=100003,event=0xb7,offcore_rsp=0x67f800001 llc_misses.pcie_non_snoop_read llc_references.pcie_partial_read freq_band2_cycles % unc_p_freq_ge_2000mhz_cycles Counts the number of cycles that the uncore was running at a frequency greater than or equal to 2Ghz. Derived from unc_p_freq_band1_cycles. Unit: uncore_pcu umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00010008 br_misp_exec.all_direct_near_call partial_rat_stalls.mul_single_uop br_misp_retired.near_call This event counts the number of load micro-ops retired Counts any Read request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002000020 offcore_response.demand_data_rd.l2_hit_this_tile_e Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in E state umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000020 Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in E state offcore_response.partial_reads.l2_hit_this_tile_s Counts UC code reads (valid only for Outstanding response type) that accounts for responses which hit its own tile's L2 with data in S state Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in F state umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000080 offcore_response.partial_writes.l2_hit_this_tile_f offcore_response.pf_l2_rfo.l2_hit_near_tile umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800180080 Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state offcore_response.any_rfo.l2_hit_near_tile offcore_response.any_read.l2_hit_near_tile Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400044 offcore_response.any_data_rd.ddr_far Counts any request that accounts for data responses from MCDRAM Far or Other tile L2 hit far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080801000 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000400 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800100 Counts demand code reads and prefetch code reads that accounts for data responses from MCDRAM Far or Other tile L2 hit far offcore_response.demand_data_rd.ddr_near umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180600200 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181800004 Counts L2 code HW prefetches that accounts for responses from DDR (local and far) Counts L1 data HW prefetches that accounts for responses from DDR (local and far) recycleq.lock recycleq.any_ld mcdram bandwidth read (CPU traffic only) (MB/sec). Unit: uncore_edc_eclk unc_e_wpq_inserts umask=0x3,period=100003,edge=1,event=0x5 l1d_prefetch.requests umask=0x7,period=100000,event=0xf1 L2 load misses mem_uncore_retired.local_dram Offcore L1 data cache writebacks umask=0x10,period=5,event=0xb,ldlat=0x4000 Offcore requests satisfied by the IO, CSR, MMIO unit offcore_response.any_request.remote_cache_dram offcore_response.any_request.remote_cache_hit Offcore requests that HITM in a remote cache offcore_response.corewb.any_cache_dram Offcore writebacks to a remote cache or remote DRAM offcore_response.data_in.local_cache_dram offcore_response.demand_data.remote_cache Offcore demand code reads satisfied by the LLC or local DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4780 Offcore prefetch data requests satisfied by the LLC Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core umask=0x1,period=100000,event=0xb7,offcore_rsp=0x710 offcore_response.pf_data_rd.local_cache_dram offcore_response.pf_data_rd.remote_cache offcore_response.pf_ifetch.io_csr_mmio offcore_response.pf_ifetch.remote_cache_hitm umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F70 umask=0x20,period=200000,event=0x12 128 bit SIMD integer arithmetic operations simd_int_64.packed_logical umask=0x1,period=200000,event=0xfd offcore_response.any_data.any_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF811 offcore_response.demand_ifetch.any_llc_miss umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF880 offcore_response.pf_data.any_llc_miss Offcore prefetch data reads satisfied by a remote DRAM rat_stalls.registers br_inst_exec.direct Unconditional branches executed Retired near call instructions (Precise Event) umask=0x4,period=2000000,event=0xc0 Total cycles (Precise Event) load_hit_pre Load operations conflicting with software prefetches umask=0x20,period=2000000,event=0xa2 umask=0x8,period=2000000,event=0xd1 Uops executed on any port (core count) Cycles no Uops issued on ports 0-4 (core count) umask=0x40,period=2000000,event=0xb1 Cycles no Uops were issued uops_retired.macro_fused dtlb_misses.stlb_hit umask=0x1,period=200000,event=0x85 Counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready Supports address when precise (Precise event) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080088000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100100004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000040004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040040004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000040002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400040002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0020001 Number of times RTM abort was triggered. (PEBS) (Precise event) Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles (Must be precise) offcore_response.demand_data_rd.l3_miss.any_snoop Core crystal clock cycles when the thread is unhalted Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5 umask=0x1,period=2000003,event=0xa6 Cycles total of 4 uops are executed on all ports and Reservation Station was not empty Counts all not taken macro branch instructions retired Spec update: SKL091 (Precise event) Increments whenever there is an update to the LBR array ( ((br_misp_retired.all_branches / ( br_misp_retired.all_branches + machine_clears.count )) * (( uops_issued.any - uops_retired.retire_slots + 4 * (( int_misc.recovery_cycles_any / 2 )) ) / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) ))))) + (4 * idq_uops_not_delivered.cycles_0_uops_deliv.core / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )))) * (( int_misc.clear_resteer_cycles + 9 * baclears.any ) / cycles) / (4 * idq_uops_not_delivered.cycles_0_uops_deliv.core / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )))) ) * (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) ))) / br_misp_retired.all_branches 1000 * mem_load_retired.l3_miss / inst_retired.any Counts any code reads (demand & prefetch) that miss L2 offcore_response.any_code_rd.l2_miss.hitm_other_core Counts any data read (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded This event counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time This event counts when a data (D) page walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks Counts prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoops sent to sibling cores return clean response offcore_response.pf_l2_data_rd.llc_miss.dram Counts all prefetch (that bring data to L2) RFOs that miss the LLC and the data returned from dram REQUEST = PF_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM REQUEST = ANY IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5022 REQUEST = ANY RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE REQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HIT offcore_response.demand_rfo.local_dram_and_remote_cache_hit REQUEST = OTHER and RESPONSE = LLC_HIT_NO_OTHER_CORE REQUEST = DEMAND_DATA and RESPONSE = ANY_DRAM AND REMOTE_FWD REQUEST = DEMAND_IFETCH and RESPONSE = REMOTE_DRAM REQUEST = DEMAND_RFO and RESPONSE = OTHER_LOCAL_DRAM Cycles snoop code requests queued Mispredicted conditional retired branches (Precise Event) DTLB misses caused by low part of address. Count also includes 2M page references because 2M pages do not use the PDE umask=0x2,cmask=1,period=2000003,event=0x60 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0604000004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x083FC00010 Counts prefetch (that bring data to L2) data reads TBD offcore_response.pf_l2_rfo.l3_miss.snoop_miss_or_no_fwd Counts L1 data cache hardware prefetch requests and software prefetch requests TBD offcore_response.all_pf_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd offcore_response.all_pf_rfo.l3_miss.snoop_miss_or_no_fwd umask=0x2,period=100003,event=0xfe (( 1 * ( fp_arith_inst_retired.scalar_single + fp_arith_inst_retired.scalar_double ) + 2 * fp_arith_inst_retired.128b_packed_double + 4 * ( fp_arith_inst_retired.128b_packed_single + fp_arith_inst_retired.256b_packed_double ) + 8 * ( fp_arith_inst_retired.256b_packed_single + fp_arith_inst_retired.512b_packed_double ) + 16 * fp_arith_inst_retired.512b_packed_single )) / cycles uncore_cha umask=0x02,event=0x50 uncore_iio unc_iio_data_req_of_cpu.mem_write.part0 Counts only multi-socket cacheline Directory state updates memory writes issued from the HA pipe. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines Counts when a normal (Non-Isochronous) read is issued to any of the memory controller channels from the CHA umask=0x20,event=0x50 fc_mask=0x07,ch_mask=0x08,umask=0x04,event=0xc0 unc_m2m_direct2core_taken event=0x27 Multi-socket cacheline Directory update from S to I. Unit: uncore_m2m Counts when the M2M (Mesh to Memory) promotes a outstanding request in the prefetch queue due to a subsequent demand read request that entered the M2M with the same address. Explanatory Side Note: The Prefecth queue is made of CAM (Content Addressable Memory) unc_upi_l1_power_cycles Counts incoming FLITs (FLow control unITs) which bypassed the TxL(transmit) FLIT buffer and pass directly out the UPI Link. Generally, when data is transmitted across the Intel Ultra Path Interconnect (UPI), it will bypass the TxQ and pass directly to the link. However, the TxQ will be used in L0p (Low Power) mode and (Link Layer Retry) LLR mode, increasing latency to transfer out to the link This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0100 offcore_response.pf_l1d_and_sw.l3_hit_e.hit_other_core_no_fwd offcore_response.pf_l1d_and_sw.l3_hit_e.any_snoop offcore_response.pf_l3_rfo.l3_hit_f.snoop_miss offcore_response.all_rfo.l3_hit_m.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.ANY_RESPONSE offcore_response.all_reads.supplier_none.hitm_other_core This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_NONE offcore_response.pf_l3_rfo.l3_hit_f.hit_other_core_fwd offcore_response.demand_code_rd.l3_hit_s.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020020 offcore_response.demand_rfo.supplier_none.no_snoop_needed This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00000107F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040490 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080048000 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000108000 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_MISS This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.ANY_RESPONSE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD offcore_response.demand_data_rd.l3_hit.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200010 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0020 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100120 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0020 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C07F7 offcore_response.all_reads.l3_hit_s.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.SNOOP_MISS This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD offcore_response.all_rfo.l3_hit_f.no_snoop_needed offcore_response.all_pf_data_rd.l3_hit_e.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080100 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED offcore_response.all_rfo.supplier_none.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800028000 This event is deprecated. Refer to new event OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080100 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED offcore_response.pf_l1d_and_sw.l3_hit_m.any_snoop This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200120 offcore_response.pf_l2_rfo.supplier_none.no_snoop_needed offcore_response.pf_l2_data_rd.l3_hit_s.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040122 offcore_response.all_rfo.supplier_none.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200004 offcore_response.pf_l3_rfo.l3_hit_s.no_snoop_needed This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.ANY_SNOOP offcore_response.all_pf_data_rd.l3_hit_f.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100490 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020120 offcore_response.other.l3_hit_f.any_snoop offcore_response.all_reads.l3_hit_e.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100001 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04002007F7 offcore_response.all_reads.l3_miss_local_dram.no_snoop_needed This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00004 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000001 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000002 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP offcore_response.all_reads.l3_miss.hit_other_core_fwd offcore_response.demand_data_rd.l3_miss_remote_hop1_dram.snoop_none ALL_PF_RFO & L3_MISS_LOCAL_DRAM & SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00010 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.ANY_SNOOP offcore_response.demand_data_rd.l3_miss_local_dram.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000120 ocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000020 offcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS_REMOTE_HOP1_DRAM & NO_SNOOP_NEEDED Counts all demand code reads DEMAND_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISS_OR_NO_FWD ocr.demand_code_rd.l3_miss.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000491 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800120 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000080 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00001 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD ocr.all_pf_rfo.l3_miss_remote_hop1_dram.snoop_none ocr.all_pf_data_rd.l3_miss.hit_other_core_no_fwd Counts all demand code reads DEMAND_CODE_RD & L3_MISS_LOCAL_DRAM & NO_SNOOP_NEEDED offcore_response.demand_code_rd.l3_miss.hit_other_core_fwd offcore_response.other.l3_miss_local_dram.no_snoop_needed offcore_response.pf_l3_data_rd.l3_miss.no_snoop_needed offcore_response.pf_l1d_and_sw.l3_miss_local_dram.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000490 ocr.all_pf_data_rd.l3_miss_remote_hop1_dram.any_snoop Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS & HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS ALL_PF_RFO & L3_MISS_LOCAL_DRAM & HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD ocr.pf_l3_data_rd.l3_miss_local_dram.snoop_miss This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_FWD ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000400 ocr.all_pf_data_rd.l3_miss_remote_hop1_dram.snoop_none Counts any other requests OTHER & L3_MISS & HIT_OTHER_CORE_FWD ALL_READS & L3_MISS_LOCAL_DRAM & SNOOP_NONE Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_S & HIT_OTHER_CORE_NO_FWD ocr.all_pf_data_rd.supplier_none.hitm_other_core ALL_RFO & L3_HIT_F & HITM_OTHER_CORE ocr.other.l3_hit_m.hit_other_core_fwd Counts demand data reads DEMAND_DATA_RD & L3_HIT_E & HITM_OTHER_CORE Counts demand data reads DEMAND_DATA_RD & L3_HIT_E & NO_SNOOP_NEEDED ocr.demand_code_rd.l3_hit_e.snoop_none ocr.all_pf_data_rd.pmm_hit_local_pmm.snoop_none Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_F & NO_SNOOP_NEEDED ocr.demand_rfo.pmm_hit_local_pmm.snoop_none ALL_PF_RFO & L3_HIT_E & ANY_SNOOP ALL_DATA_RD & L3_HIT & HIT_OTHER_CORE_NO_FWD ocr.pf_l1d_and_sw.l3_hit.hit_other_core_no_fwd ALL_PF_DATA_RD & L3_HIT & SNOOP_HIT_WITH_FWD Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_F & ANY_SNOOP ocr.pf_l2_rfo.supplier_none.hitm_other_core ocr.pf_l3_data_rd.any_response ocr.demand_data_rd.l3_hit.hitm_other_core ocr.all_rfo.l3_hit_s.hitm_other_core ocr.all_rfo.l3_hit.snoop_hit_with_fwd ALL_RFO & L3_HIT & SNOOP_HIT_WITH_FWD ALL_PF_RFO & L3_HIT_M & HIT_OTHER_CORE_NO_FWD ALL_PF_DATA_RD & L3_HIT_E & ANY_SNOOP ocr.demand_data_rd.l3_hit_e.snoop_miss ALL_READS & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDED ALL_PF_DATA_RD & L3_HIT_M & HITM_OTHER_CORE ALL_PF_RFO & SUPPLIER_NONE & NO_SNOOP_NEEDED ALL_RFO & L3_HIT_S & HIT_OTHER_CORE_FWD ALL_PF_RFO & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWD Counts all demand code reads DEMAND_CODE_RD & L3_HIT_S & HIT_OTHER_CORE_FWD ocr.demand_rfo.l3_hit_f.hit_other_core_no_fwd any=1,period=25003,umask=0x1,event=0x3c period=2000003,umask=0x1,event=0x87 period=2000003,umask=0x3,event=0 UNC_M_PMM_READ_LATENCY umask=0x1,event=0xea umask=0x4,event=0xea unc_cha_llc_victims.total_e Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in unc_cha_llc_victims.total_s Ingress (from CMS) Occupancy; IRQ. Unit: uncore_cha Write request of 4 bytes made to IIO Part3 by the CPU. Unit: uncore_iio unc_iio_data_req_of_cpu.peer_read.part1 fc_mask=0x07,ch_mask=0x04,umask=0x02,event=0xc1 Peer to peer write request of up to a 64 byte transaction is made by IIO Part0 to an IIO target. Unit: uncore_iio Counts all retired load instructions. This event accounts for SW prefetch instructions for loads Supports address when precise (Precise event) Counts all microcode FP assists Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element umask=0x30,period=2000003,cmask=1,edge=1,event=0x79 umask=0x1,period=100007,event=0xc6,frontend=0x504006 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall (Precise event) topdown.backend_bound_slots Issue slots where no uops were being issued due to lack of back end resources Core cycles the allocator was stalled due to recovery from earlier clear event for this thread Counts core crystal clock cycles when the thread is unhalted uops_executed.cycles_ge_3 number of branch instructions retired that were mispredicted and taken. Non PEBS Supports address when precise (Precise event) Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request Counts memory requests originating from the core that miss in the last level cache. If the platform has an L3 cache, last level cache is the L3, otherwise it is the L2 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 Instruction Pipe Stall. IC pipe was stalled during this clock cycle for any reason (nothing valid in pipe ICM1) umask=0x1,event=0x8c umask=0x2,event=0x60 l2_cache_req_stat.ls_rd_blk_cs Core to L2 cacheable request access status (not including L2 Prefetch). Data cache read hit on shared line in L2 ex_ret_near_ret_mispred ex_tagged_ibs_ops.ibs_tagged_ops_ret umask=0xCD,event=0x8b Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdsizednc umask=0xE8,event=0x8b df_ccm_reqa.node7.rdsized umask=0x46,event=0x8b df_ccm_reqa.node7.anyrdblk df_ccm_reqa.node2.rdvlkx df_ccm_reqa.node0.rdvlks umask=0xA2,event=0x8b df_ccm_reqa.node1.rdvlkl umask=0x02,event=0x8c umask=0x22,event=0x8c df_ioms_reqa.node6.ios_resp df_ioms_reqa.node1.fence umask=0x49,event=0x108 df_ioms_reqa.node0.anywrsized=64b df_ioms_reqa.node4.anywrsized>32band<64b umask=0xC4,event=0x108 umask=0x22,event=0x108 df_ioms_reqb.node3.pieinterrupt Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered anyiotransaction umask=0x2C,event=0x109 df_ioms_reqb.node3.ioanynon-postedwrsized=64b df_ioms_reqb.node3.ioanypostedwrsized=32 umask=0xA1,event=0x109 l3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x02,event=0x1 l3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x02,event=0x1 l3_request_g1.t6.s0.wrsized l3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x04,event=0x1 l3_request_g1.t2.s1.rdsizednc l3_request_g1.t2.s2.rdsizednc l3_request_g1.t0.s3.rdsizednc l3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x40,event=0x1 l3_request_g1.t1.s1.rdsized l3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x40,event=0x1 l3_request_g1.t2.s1.caching l3_request_g1.t5.s3.caching l3fillvicreq.t3.s0.vicblk l3fillvicreq.t3.s1.vicblk l3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x02,event=0x3 l3fillvicreq.t3.s2.chgtox l3fillvicreq.t4.s3.chgtox l3fillvicreq.t6.s2.rdblkc_s_vic l3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x04,event=0x3 l3fillvicreq.t5.s3.rdblkc_s l3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x10,event=0x3 l3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x20,event=0x3 l3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x20,event=0x3 l3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x40,event=0x3 l3fillvicreq.t2.s2.rdblkl l3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x80,event=0x3 l3victimstate.t1.s3.nol3victimline l3victimstate.t0.s0.f_s l3victimstate.t0.s0.o l3victimstate.t7.s0.o l3victimstate.t2.s1.o l3victimstate.t6.s2.o l3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x08,event=0x9 l3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x10,event=0x9 l3victimstate.t4.s0.e_fe l3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x20,event=0x9 l3victimstate.t2.s0.d l3victimstate.t5.s2.d l3victimstate.t1.s0.od l3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x80,event=0x9 l3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x80,event=0x9 Bus lock when a locked operations crosses a cache boundary or is done on an uncacheable memory type ls_stlf ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss L1 DTLB Reload of a page of 1G size OC Mode Switch. IC to OC mode switch bp_l1_tlb_fetch_hit.if4k Floating Point Dispatch Faults. XMM fill fault umask=0x2,event=0x25 ls_ret_cpuid Number of SMIs received LS MAB Allocates by Type. DC prefetcher Demand Data Cache Fills by Data Source. Hit in cache; local CCX (not Local L2), or Remote CCX and the address's Home Node is on this thread's die ls_refills_from_sys.ls_mabresp_lcl_l2 umask=0xff,event=0x4b umask=0x2,event=0x59 FP_DISPATCHED_FPU_OPS DC_MICROARCHITECTURAL_LATE_CANCEL DC_DISPATCHED_PREFETCH_INSTRUCTIONS DC_DCACHE_ACCESSES_BY_LOCKS PC_PROC_RETURN MEM_ACCESS AXI_WRITE L1_DCACHE_NEON_ACCESS RET_STACK_MISPREDICT JAZELLE_BACKWARD_BRANCH STREX_FAILED DATA_EVICTION ISB PLE_REQUEST_COMPLETED BUS_ACCESS_ST L1D_CACHE_LD L1D_CACHE_ST ICACHE_WRITE_MISS ICACHE_EVICT L2CACHE_SET_TAG_WRITE L2_ERR_CORRECTED IC_BLOCKED_CYCLES FSB_FULL_STALLS LDQ_OVER_50_FULL OCP_ALL_REQUESTS VFPU_INSTR_WAIT_CYCLES L1_DATA_SNOOP_HITS DSS_INSTR_COMPLETED LSU_ALIAS_VS_FSQ_WB0_WB1 FP_LOAD_DOUBLE_COMPLETED_IN_LSU LSU_COMPLETES_FP_STORE_SINGLE FPU_INSTR_COMPLETED L3_CACHE_HITS INTERVENTION INSTR_COMPLETED_WITH_ALL_THREADS_RUNNING SNOOP_PUSHES FPU_DOUBLE_PUMP k8-bu-cpu-clk-unhalted x87 low-op-pos-1 dram-controller-queue-bypass BERI INTEL_HASWELL INTEL_SKYLAKE_XEON topic: %s
cpu_clk_unhalted.thread longest_lat_cache.reference {"type": "closelog"}
%s, "version": "0x%08x", "arch": "0x%08x", "cpuid": "%s", "tsc_freq": "%jd", "sec": "%jd", "nsec": "%jd"}
%s, "pmcid": "0x%08x", "pid": "%d"}
%s, "pid": "%d", "start": "0x%016jx", "end": "0x%016jx"}
%s, "tid": "%d", "pid": "%d", "flags": "0x%08x", "tdname": "%s"}
v17 v1 GenuineIntel-6-3C GenuineIntel-6-25 uops_executed.thread / ( cpu@uops_executed.core\,cmask\=1@ / 2) if #smt_on else uops_executed.cycles_ge_1_uop_exec Fraction of cycles spent in Kernel mode umask=0x22,period=200003,event=0x24 This event counts the number of demand Data Read requests that hit L2 cache. Only not rejected loads are counted offcore_requests.demand_data_rd Retired load uops misses in L1 cache as data sources. Uses PEBS Supports address when precise (Precise event) umask=0x8,period=200003,event=0xf0 l2_lines_in.i umask=0x2,period=100003,event=0xf1 umask=0x20,period=2000003,event=0xc7 umask=0x4,period=100003,event=0xca idq.mite_uops idq.ms_dsb_occur umask=0x2,period=200003,event=0x80 umask=0x1,period=2000003,event=0xc8 Number of times a disallowed operation caused an HLE abort This event counts loads with latency value being above four Spec update: BDM100, BDM35 (Must be precise) mem_trans_retired.load_latency_gt_32 Loads with latency value being above 64 Spec update: BDM100, BDM35 (Must be precise) umask=0x1,period=1009,event=0xcd,ldlat=0x80 Loads with latency value being above 512 Spec update: BDM100, BDM35 (Must be precise) umask=0x1,period=2000003,event=0xe This event counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread move_elimination.simd_not_eliminated umask=0x84,period=200003,event=0x88 This event counts both taken and not taken speculative and retired macro-unconditional branch instructions, excluding calls and indirects This event counts taken speculative and retired mispredicted indirect branches that have a return mnemonic umask=0xc1,period=200003,event=0x89 uops_dispatched_port.port_1 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2 Cycles per thread when uops are executed in port 6 Number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event All (macro) branch instructions retired umask=0x10,period=400009,event=0xc4 br_inst_retired.far_branch br_misp_retired.all_branches_pebs baclears.any llc_misses.data_read LLC misses - Uncacheable reads (from cpu) . Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox llc_references.pcie_ns_partial_write M line forwarded from remote cache along with writeback to memory. Unit: uncore_ha (unc_m_power_critical_throttle_cycles / unc_m_dclockticks) * 100. event=0x4 dtlb_load_misses.stlb_hit umask=0x60,period=2000003,event=0x8 This category represents fraction of slots wasted due to incorrect speculations Instructions Per Cycle (per Logical Processor) FLOPc_SMT DRAM_BW_Use This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were HitM responses from a core on same socket (shared L3) Spec update: BDM100. Supports address when precise (Precise event) offcore_response.demand_code_rd.supplier_none.snoop_miss offcore_response.pf_l2_rfo.l3_hit.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0080 offcore_response.pf_l3_rfo.supplier_none.snoop_hitm offcore_response.pf_l3_rfo.supplier_none.any_snoop offcore_response.pf_l3_code_rd.supplier_none.snoop_none offcore_response.other.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010090 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0090 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0090 offcore_response.all_pf_code_rd.l3_hit.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400020091 Counts all demand & prefetch RFOs have any response type umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0122 Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element umask=0x4,period=2000003,cmask=1,event=0x79 offcore_response.demand_data_rd.l3_miss_local_dram.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000010 offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000010 offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0080 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000080 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000080 offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_hit_no_fwd offcore_response.pf_l3_data_rd.l3_miss.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000100 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020200 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000200 offcore_response.other.supplier_none.snoop_non_dram offcore_response.other.l3_miss_local_dram.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004008000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C008000 offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_none offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000090 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000090 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000090 offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_non_dram offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_hitm offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_non_dram offcore_response.all_data_rd.l3_miss_local_dram.snoop_none offcore_response.all_data_rd.l3_miss_local_dram.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000091 Unit: uncore_cbox L3 Lookup read request that access cache and found line in any MESI-state umask=0x16,event=0x34 L3 Lookup read request that access cache and found line in E or S-state uncore_arb Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic unc_arb_coh_trk_requests.all Memory_Lat Retired load uops which data sources were data hits in L3 without snoops required Supports address when precise. Spec update: BDM100 (Precise event) offcore_response.all_requests.llc_hit.any_response offcore_response.all_reads.llc_hit.hitm_other_core Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache Counts all demand & prefetch RFOs miss in the L3 qpi_ctl_bandwidth_tx l2_ld.self.any.i_state umask=0x41,period=200000,event=0x2a l2_lock.self.mesi umask=0x74,period=200000,event=0x2e Rejected L2 cache requests l2_reject_busq.self.demand.m_state umask=0x40,period=200000,event=0x32 umask=0xa1,period=2000000,event=0x40 umask=0x89,period=200000,event=0x5 misalign_mem_ref.st_bubble umask=0x8f,period=200000,event=0x7 umask=0x40,period=200000,event=0x60 bus_trans_ifetch.all_agents Instruction-fetch bus transactions umask=0x8,period=200000,event=0x77 cycles_int_masked.cycles_int_pending_and_masked Multiply operations executed umask=0x1,period=2000000,event=0x14 event=0x0,umask=0x03 page_walks.i_side_cycles Counts load uops retired that hit the L1 data cache Supports address when precise (Must be precise) Counts load uops retired that miss in the L2 cache Supports address when precise (Must be precise) umask=0x20,period=200003,event=0xd1 umask=0x40,period=200003,event=0xd1 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000003091 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000003010 Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts a load blocked from using a store forward, but did not occur because the store data was not available at the right time. The forward might occur subsequently when the data is available (Must be precise) umask=0x4,period=200003,event=0x3 umask=0x0,period=200003,event=0x9c machine_clears.all Retired mispredicted instructions of near indirect Jmp or near indirect call. (Precise event capable) (Must be precise) umask=0xfb,period=200003,event=0xc5 umask=0x10,period=200003,event=0xe6 Counts demand reads for ownership (RFO) requests generated by a write to full data cache line hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand reads for ownership (RFO) requests generated by a write to full data cache line outstanding, per cycle, from the time of the L2 miss to when any response is received Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000010008 Counts data cacheline reads generated by hardware L2 cache prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts bus lock and split lock requests have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.bus_locks.l2_miss.snoop_miss_or_no_snoop_needed Counts data cache line reads generated by hardware L1 data cache prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.streaming_stores.any_response Counts requests to the uncore subsystem miss the L2 cache with a snoop hit in the other processor module, data forwarding is required offcore_response.any_rfo.any_response offcore_response.any_read.outstanding Page walk completed due to an instruction fetch in a 4K page umask=0x4,period=2000003,event=0x85 Cycles in which the L1D is locked offcore_response.all_rfo.l3_hit.hitm_other_core Counts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00020 This event counts cycles when the Reservation Station ( RS ) is empty for the thread. The RS is a structure that buffers allocated micro-ops from the Front-end. If there are many cycles when the RS is empty, it may represent an underflow of instructions delivered from the Front-end Cycles per core when uops are executed in port 5 Cycles which a uop is dispatched on port 7 in this thread Cycles where at least 2 uops were executed per-thread Spec update: HSD144, HSD30, HSM31 Completed page walks due to misses in ITLB 2M/4M page entries Completed page walks in ITLB of any page size Number of ITLB page walker loads that hit in the L3 Spec update: HSD25 Retired load uops which data sources were data hits in L3 without snoops required Supports address when precise. Spec update: HSD74, HSD29, HSD25, HSM26, HSM30 (Precise event) offcore_response.demand_data_rd.llc_hit.hitm_other_core hsx metrics umask=0x40,period=200003,event=0x24 umask=0xc0,period=200003,event=0x24 Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle All retired store uops. (Precise Event) Retired load uops which data sources were hits in LLC without snoops required (Precise event) Counts all demand rfo's umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00010004 simd_fp_256.packed_double offcore_response.all_code_rd.llc_miss.dram Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.) Cycles per core when uops are dispatched to port 5 umask=0x80,event=0x81 Retired load uops whose data source was remote DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0090 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x803c8000 Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response ivt metrics Counts all demand & prefetch code reads that miss the LLC umask=0x1,period=100003,event=0xb7,offcore_rsp=0x87f800244 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x6004003f7 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x107fc003f7 offcore_response.demand_code_rd.llc_miss.remote_dram offcore_response.demand_code_rd.llc_miss.remote_hitm Counts demand data reads that miss the LLC and the data returned from remote dram unc_c_tor_occupancy.miss_local unc_m_act_count.rd unc_p_freq_band2_cycles All retired load uops (Precise event) Loads with latency value being above 4 (Must be precise) Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for Loads delayed due to SB blocks, preceding store operations with known addresses but unknown data umask=0x3,event=0x36 Counts the number of MEC requests from the L2Q that reference a cache line (cacheable requests) exlcuding SW prefetches filling only to L2 cache and L1 evictions (automatically exlcudes L2HWP, UC, WC) that were rejected - Multiple repeated rejects should be counted multiple times l2_requests.reference Counts Demand code reads and prefetch code read requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode Counts Demand code reads and prefetch code read requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state offcore_response.any_rfo.l2_hit_far_tile_m Counts Demand cacheable data write requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state offcore_response.any_request.l2_hit_far_tile_e_f offcore_response.uc_code_reads.l2_hit_near_tile_m Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for any response offcore_response.partial_reads.l2_hit_far_tile_m Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for any response offcore_response.pf_l2_rfo.l2_hit_far_tile_m offcore_response.pf_l2_rfo.l2_hit_near_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400001 offcore_response.any_data_rd.l2_hit_this_tile_m offcore_response.pf_l1_data_rd.l2_hit_this_tile_e umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004002000 Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in S state Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in F state umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000100 Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in F state Counts any Read request that accounts for responses which hit its own tile's L2 with data in F state umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800180020 Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state Counts any request that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode offcore_response.any_data_rd.l2_hit_far_tile offcore_response.any_read.ddr_near offcore_response.any_request.mcdram_far Counts L1 data HW prefetches that accounts for data responses from MCDRAM Local Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from any NON_DRAM system address. This includes MMIO transactions umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000040 offcore_response.pf_l2_rfo.non_dram umask=0x1,period=100007,event=0xb7,offcore_rsp=0x2000020020 offcore_response.pf_l2_rfo.mcdram_near offcore_response.any_read.mcdram Counts any Read request that accounts for responses from MCDRAM (local and far) offcore_response.uc_code_reads.ddr Counts the number of near relative CALL branch instructions retired (Precise event) Counts the number of mispredicted branch instructions retired that were conditional jumps and predicted taken (Precise event) Counts the number of core cycles when no micro-ops are allocated and the ROB is full no_alloc_cycles.all recycleq.ld_block_st_forward ddr bandwidth read (CPU traffic only) (MB/sec). Unit: uncore_imc uncore_edc_eclk l1d_cache_st.e_state L1 data cache stores in S state umask=0x4,period=100000,event=0x28 All L2 transactions umask=0x10,period=100000,event=0x27 Instructions retired which contains a load (Precise Event) mem_load_retired.hit_lfb mem_load_retired.other_core_l2_hit_hitm offcore_requests_sq_full Memory instructions retired above 0 clocks (Precise Event) umask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF11 Offcore data reads satisfied by the LLC offcore_response.data_ifetch.remote_cache_hit Offcore demand data requests satisfied by any cache or DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0x703 Offcore demand data requests satisfied by a remote cache or remote DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3801 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x801 offcore_response.demand_rfo.any_location umask=0x1,period=100000,event=0xb7,offcore_rsp=0x8002 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x280 offcore_response.other.local_cache offcore_response.pf_data_rd.llc_hit_other_core_hit offcore_response.prefetch.any_location umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3870 X87 Floating poiint assists for invalid input value (Precise Event) Offcore data reads satisfied by a remote DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0x6004 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2040 offcore_response.pf_rfo.any_llc_miss bpu_clears.early Scoreboard stall cycles seg_rename_stalls sq_full_stall_cycles Indirect non call branches executed umask=0x30,period=20000,event=0x88 br_misp_exec.cond umask=0x4,period=2000000,event=0x87 Reservation Station full stall cycles uops_decoded.esp_folding Uops decoded by Microcode Sequencer uops_decoded.stall_cycles uops_executed.core_active_cycles umask=0x2,period=200000,event=0x85 Number of times a request needed a FB (Fill Buffer) entry but there was no entry available for it. A request includes cacheable/uncacheable demands that are load, store or SW prefetch instructions Counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS Retired store instructions that miss the STLB. (Precise Event) Supports address when precise Retired load instructions that split across a cacheline boundary. (Precise Event) Supports address when precise Retired load instructions missed L1 cache as data sources Supports address when precise (Precise event) Retired instructions with at least 1 uncacheable load or lock Supports address when precise (Precise event) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00401C0004 offcore_response.demand_code_rd.l3_hit_s.snoop_miss offcore_response.demand_code_rd.l3_hit_e.snoop_not_needed offcore_response.demand_code_rd.l3_hit_m.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC01C0002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10001C0002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0100002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200100002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04001C0001 offcore_response.demand_data_rd.l3_hit_s.any_snoop Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss (Precise event) frontend_retired.stlb_miss frontend_retired.latency_ge_2 tx_mem.abort_capacity Demand Data Read requests who miss L3 cache Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles (Must be precise) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC408000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x007C400002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC400001 sw_prefetch_access.t0 Mispredicted direct and indirect near call instructions retired (Precise event) This event counts both taken and not taken retired mispredicted direct and indirect near calls, including both register and memory indirect (Precise event) ( itlb_misses.walk_pending + dtlb_load_misses.walk_pending + dtlb_store_misses.walk_pending + ept.walk_pending ) / ( 2 * cycles ) dtlb_store_misses.walk_active This event counts the number of retire loads that experienced cache line boundary splits (Precise event) Counts DCU hardware prefetcher data read that have any response type Counts data cacheline reads generated by L2 prefetchers that hit in the other module where modified copies were found in other core's L1 cache Counts demand and DCU prefetch RFOs that miss L2 with a snoop miss response offcore_response.demand_data_rd.l2_miss.snoop_miss This event counts all instruction fetches from the instruction cache Counts the number of mispredicted JCC branch instructions retired (Precise event) Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired (Precise event) This event counts the number of times that pipeline stalled due to FP operations needing assists Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS) (Precise event) offcore_response.pf_l2_code_rd.llc_hit.hitm_other_core umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0020 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400002 snb metrics REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE umask=0x1,period=100000,event=0xb7,offcore_rsp=0x50ff offcore_response.demand_data.local_dram_and_remote_cache_hit offcore_response.demand_data_rd.all_local_dram_and_remote_cache_hit REQUEST = OTHER and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT umask=0x1,period=100000,event=0xb7,offcore_rsp=0xff40 umask=0x1,period=100000,event=0xb7,offcore_rsp=0xf808 offcore_response.demand_data.other_local_dram REQUEST = PF_DATA and RESPONSE = OTHER_LOCAL_DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2050 offcore_response.pf_data_rd.any_dram_and_remote_fwd Snoop code requests snoopq_requests.data snoopq_requests_outstanding.code Cycles snoop data requests queued DTLB miss large page walks umask=0x4,period=2000000,event=0x49 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5811 Counts prefetch (that bring data to L2) data reads TBD TBD offcore_response.all_pf_data_rd.l3_hit.hitm_other_core Number of Packed Double-Precision FP arithmetic instructions (Use operation multiplier of 8) Number of Packed Single-Precision FP arithmetic instructions (Use operation multiplier of 16) offcore_response.pf_l1d_and_sw.l3_miss.any_snoop offcore_response.all_pf_data_rd.l3_miss.snoop_miss_or_no_fwd core_snoop_response.rsp_ihiti idi_misc.wb_downgrade unc_m_wpq_occupancy fc_mask=0x07,ch_mask=0x02,umask=0x04,event=0x83 Core Cross Snoops Issued; Multiple Eviction. Unit: uncore_cha unc_cha_dir_update.tor unc_cha_snoop_resp.rspsfwd Counts clockticks of the 1GHz trafiic controller clock in the IIO unit fc_mask=0x07,ch_mask=0x04,umask=0x01,event=0xc0 Read request for up to a 64 byte transaction is made by the CPU to IIO Part3. Unit: uncore_iio Write request of up to a 64 byte transaction is made to IIO Part3 by the CPU . Unit: uncore_iio Counts every read request for up to a 64 byte transaction of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus Number of reads in which direct to core transaction were overridden. Unit: uncore_m2m event=0x28 Multi-socket cacheline Directory lookups (cacheline found in A state) . Unit: uncore_m2m Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from I (Invalid) to S (Shared) umask=0x2,event=0x38 Counts when the M2M (Mesh to Memory) issues partial writes to the iMC (Memory Controller). It only counts normal priority non-isochronous writes event=0x56 AD Ingress (from CMS) Queue Inserts. Unit: uncore_m2m uncore_m3upi umask=0x97,event=0x2 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP any=1,cmask=1,period=2000003,umask=0x1,event=0x48 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02000807F7 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.ANY_RESPONSE This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400020 This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP offcore_response.all_pf_rfo.l3_hit_e.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040080 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00800207F7 offcore_response.all_rfo.pmm_hit_local_pmm.any_snoop This event is deprecated. Refer to new event OCR.PF_L2_RFO.ANY_RESPONSE offcore_response.pf_l3_rfo.l3_hit_f.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0120 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100122 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0080 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100122 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400040120 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD offcore_response.all_pf_data_rd.l3_hit_s.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080004 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED offcore_response.pf_l3_rfo.l3_hit_e.hit_other_core_fwd period=100003,umask=0x11,event=0xd0 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020100 period=200003,umask=0x21,event=0x24 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100400 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020120 This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080040020 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0001 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080004 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400120 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE offcore_response.all_reads.supplier_none.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0010 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C07F7 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080490 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080490 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0002 offcore_response.pf_l2_data_rd.supplier_none.no_snoop_needed This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD offcore_response.all_reads.l3_hit_f.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010100 ( ( 64 * imc@event\=0xe7@ / 1000000000 ) / duration_time ) if 1 if 0 == 1 else 0 else 0 period=100007,umask=0x1,event=0xc6,frontend=0x408006 period=200003,umask=0x1,event=0x83 period=2000003,umask=0x8,event=0x79 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall (Precise event) This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP ocr.demand_code_rd.l3_miss_remote_hop1_dram.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104008000 Counts any other requests OTHER & L3_MISS_LOCAL_DRAM & NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000020 offcore_response.all_reads.l3_miss_local_dram.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000100 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000010 Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS & HIT_OTHER_CORE_FWD ocr.all_pf_data_rd.l3_miss.remote_hitm ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.hitm_other_core ocr.all_pf_data_rd.l3_miss.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000080 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00122 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000004 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD ocr.all_pf_data_rd.l3_miss.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02040007F7 ocr.all_pf_data_rd.l3_miss_local_dram.no_snoop_needed This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000010 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90008000 ocr.other.l3_miss_remote_hop1_dram.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01100007F7 Counts all demand code reads DEMAND_CODE_RD & L3_MISS & ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC0007F7 ocr.pf_l3_data_rd.l3_miss.any_snoop ALL_RFO & L3_MISS & SNOOP_MISS This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP ocr.all_rfo.l3_miss_remote_hop1_dram.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000020 ocr.demand_rfo.l3_miss.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000120 ALL_PF_RFO & L3_MISS_REMOTE_HOP1_DRAM & NO_SNOOP_NEEDED ALL_PF_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00010 ocr.all_pf_data_rd.l3_miss.snoop_none offcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd Counts all demand data writes (RFOs) DEMAND_RFO & L3_MISS & ANY_SNOOP This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP ocr.all_reads.l3_miss_local_dram.no_snoop_needed offcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.hitm_other_core Counts all demand data writes (RFOs) DEMAND_RFO & L3_MISS & REMOTE_HIT_FORWARD This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISS This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED offcore_response.demand_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE ocr.pf_l2_data_rd.l3_miss.any_snoop offcore_response.all_data_rd.l3_miss.hitm_other_core offcore_response.pf_l2_rfo.l3_miss_local_dram.hitm_other_core This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.SNOOP_MISS ocr.demand_data_rd.l3_hit_e.hitm_other_core ocr.pf_l2_data_rd.supplier_none.hit_other_core_no_fwd ALL_PF_DATA_RD & L3_HIT_E & SNOOP_MISS ALL_RFO & L3_HIT_E & HIT_OTHER_CORE_FWD Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & SUPPLIER_NONE & HITM_OTHER_CORE ocr.pf_l3_rfo.l3_hit_f.hit_other_core_fwd ALL_PF_DATA_RD & L3_HIT_F & SNOOP_MISS ocr.all_rfo.l3_hit_f.hit_other_core_fwd ocr.demand_code_rd.l3_hit_e.hitm_other_core Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_E & ANY_SNOOP Counts all demand code reads DEMAND_CODE_RD & L3_HIT_E & HIT_OTHER_CORE_FWD ocr.pf_l2_data_rd.l3_hit_e.snoop_none ALL_PF_RFO & L3_HIT_F & SNOOP_NONE Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_F & HITM_OTHER_CORE Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_S & HITM_OTHER_CORE Counts any other requests OTHER & SUPPLIER_NONE & NO_SNOOP_NEEDED ALL_RFO & L3_HIT_F & SNOOP_MISS ocr.all_data_rd.l3_hit_e.hitm_other_core ocr.all_reads.l3_hit.any_snoop ocr.all_reads.supplier_none.snoop_miss ALL_DATA_RD & L3_HIT_E & HIT_OTHER_CORE_NO_FWD ocr.demand_data_rd.l3_hit.any_snoop ALL_RFO & L3_HIT & ANY_SNOOP ocr.pf_l2_data_rd.l3_hit_e.no_snoop_needed Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT_E & NO_SNOOP_NEEDED ocr.pf_l2_rfo.supplier_none.no_snoop_needed ocr.pf_l3_data_rd.supplier_none.hit_other_core_fwd ALL_RFO & L3_HIT_E & ANY_SNOOP ocr.all_pf_rfo.l3_hit.snoop_none ocr.all_pf_data_rd.l3_hit_s.no_snoop_needed ocr.demand_data_rd.l3_hit_s.snoop_none Counts all demand data writes (RFOs) DEMAND_RFO & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWD ocr.pf_l1d_and_sw.l3_hit_f.snoop_none ocr.other.l3_hit.hitm_other_core Counts all demand code reads DEMAND_CODE_RD & L3_HIT_F & NO_SNOOP_NEEDED ALL_PF_DATA_RD & L3_HIT_E & HIT_OTHER_CORE_FWD period=2000003,umask=0x10,event=0xa6 unc_cha_fast_asserted.horz umask=0x80,event=0x19 Counts number of entries in the specified Ingress queue in each cycle umask=0x02,event=0x3d Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.peer_read.part2 Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part2 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus Counts incoming FLITs (FLow control unITs) which bypassed the slot1 RxQ buffer (Receive Queue) and passed directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency cmask=1,period=100003,umask=0x10,event=0x8 Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle umask=0x1,period=100007,event=0xc6,frontend=0x510006 Counts the number of times we could not allocate Lock Buffer Counts the number of times HLE commit succeeded Supports address when precise Number of times an HLE execution aborted due to any reasons (multiple categories may count as one) Counts the number of times an RTM execution aborted due to incompatible memory type misc_retired.lbr_inserts Counts all demand reads for ownership (RFO) requests and software based prefetches for exclusive ownership (PREFETCHW) that have any response type machine_clears.any Counts all machine clears due to, but not limited to memory ordering, memory disambiguation, SMC, page faults and FP assist umask=0x04,event=0x2 Clockticks of the integrated IO (IIO) traffic controller umask=0x4,event=0x60 umask=0x80,event=0x61 Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache hit clean line in L2 umask=0x1,event=0x6d l3_request_g1.caching_l3_cache_accesses umask=0x8C,event=0x8b umask=0xCC,event=0x8b df_ccm_reqa.node7.wrsized umask=0xCB,event=0x8b umask=0xE9,event=0x8b Data Fabric CCM Performance Monitor Event DF CCM Request Ordered specdramrd df_ccm_reqa.node7.rdvlkx umask=0x81,event=0x8b df_ccm_reqb.node1.vicblkfullzero df_ccm_reqb.node0.wrsizedncposted df_ioms_reqa.node1.masterabort umask=0x0A,event=0x108 df_ioms_reqa.node5.fence umask=0x06,event=0x108 umask=0xC6,event=0x108 df_ioms_reqa.node3.anywrsized>32band<64b umask=0xA5,event=0x108 df_ioms_reqa.node2.anywrsized=32b Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Any DRAM transaction umask=0x6D,event=0x109 df_ioms_reqb.node4.ioanyatomic df_ioms_reqb.node4.ioanynon-postedwrsized=32b umask=0xC8,event=0x109 Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized=64b umask=0xf0,event=0 fp_retx87_fp_ops.all The number of x87 floating-point Ops that have retired. The number of events logged per cycle can vary from 0 to 8 umask=0x8,event=0x4 l3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x02,event=0x1 l3_request_g1.t0.s1.wrsizednc l3_request_g1.t2.s1.wrsizednc l3_request_g1.t3.s3.wrsizednc l3_request_g1.t4.s0.wrsized l3_request_g1.t5.s0.rdsizednc l3_request_g1.t5.s3.rdsized l3fillvicreq.t5.s0.vicblk l3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x01,event=0x3 l3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x01,event=0x3 l3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x01,event=0x3 l3fillvicreq.t1.s1.chgtox l3fillvicreq.t1.s1.rdblkc_s_vic l3fillvicreq.t5.s1.rdblkc_s_vic l3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x08,event=0x3 l3fillvicreq.t0.s2.rdblkc_s l3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x08,event=0x3 l3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x10,event=0x3 l3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x10,event=0x3 l3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x10,event=0x3 l3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x10,event=0x3 l3fillvicreq.t1.s1.rdblkx l3fillvicreq.t6.s1.rdblkx l3fillvicreq.t3.s2.rdblkx l3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x40,event=0x3 l3fillvicreq.t0.s0.rdblkl l3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x80,event=0x3 l3fillvicreq.t2.s0.rdblkl l3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x80,event=0x3 l3fillvicreq.t7.s0.rdblkl l3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x80,event=0x3 l3victimstate.t6.s1.nol3victimline l3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x04,event=0x9 l3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x10,event=0x9 l3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x20,event=0x9 l3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x20,event=0x9 l3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x40,event=0x9 l3victimstate.t5.s1.d l3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x40,event=0x9 l3victimstate.t6.s0.od l3victimstate.t3.s3.od umask=0x1,event=0x25 Counts the number of operations dispatched to the LS unit. Unit Masks ADDed. Load-op-Stores LS MAB allocates by type - stores L1 DTLB Miss or Reload off all sizes ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit umask=0x2,event=0xaf umask=0x2,event=0x85 The number of micro-ops retired. This count includes all processor activity (instructions, exceptions, interrupts, microcode assists, etc.). The number of events logged per cycle can vary from 0 to 8 All FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15 SSE bottom-executing uOps retired. The number of serializing Ops retired event=0x37 L1 DTLB Miss. DTLB reload to a 2M page that miss in the L2 TLB L1 DTLB Miss. DTLB reload to a 4K page that miss the L2 TLB Software Prefetch Data Cache Fills by Data Source. From another cache (home node remote) ls_hw_pf_dc_fill.ls_mabresp_lcl_dram event=0x78 IC_MICROARCHITECTURAL_RESYNC_BY_SNOOP IC_RETURN_STACK_OVERFLOW L1_CACHE_PAGECOL_ALIAS COHERENT_LINEFILL_HITC INSTR_MAIN_TLB_MISS_STALL L1D_CACHE L2D_CACHE_REFILL_ST LD_SPEC BUS_ACCESS_NOT_SHARED L1D_TLB_WR ICACHE_READ_HIT DCACHE_READ_MISS EJTAG_ITRIGGER WBB_QUARTER_TO_HALF CYCLES JR_31_MISPREDICTIONS NO_INSN_CYCLES J WBUFLD L1_DATA_TOTAL_MISSES FALL_THROUGH_BRANCHES_PROCESSED BRANCH_UNIT_STALL_ON_CTR_DEPENDENCY DSSALL_INSTR_COMPLETED SUCCESSFUL_STWCX L2_CACHE_CASTOUTS L2SQ_FULL_CYCLES BR_MARKED_INSTR_FINISH MARKED_STORE_WITH_INTR GROUP_DISPATCH_REJECT INSTR_COMPLETED_RUNNING TOUCHES_TRANSLATED CACHEOPS_TRANSLATED LOAD_MISS_DLFB_FULL_CYCLES L2MMU_MISSES L2_CACHE_DIRTY_REDUNDANT_UPDATES FPU_PIPE_SYNC_STALLS STWCX_FAILURES branch-mispredicts cycles-in-request read-to-write-turnaround nop USER ARMV7_CORTEX_A8 SS ps->ps_state != PL_STATE_ERROR ERROR: unrecognized event type: %d
{"type": "initialize" v5 core Total number of retired Instructions MLP Giga Floating Point Operations Per Second C2_Pkg_Residency l2_rqsts.rfo_hit l2_demand_rqsts.wb_hit Demand Data Read requests sent to uncore mem_uops_retired.all_stores (null) L2 fill requests that access L2 cache Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses umask=0x1,cmask=4,period=2000003,event=0x9c Unfriendly TSX abort triggered by a vzeroupper instruction umask=0x1,period=503,event=0xcd,ldlat=0x100 Unhalted core cycles when the thread is in ring 0 This event counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the hardware prefetch Cycles when Reservation Station (RS) is empty for the thread Speculative and retired macro-conditional branches umask=0xc2,period=200003,event=0x88 umask=0x41,period=200003,event=0x89 Cycles per core when uops are dispatched to port 3 Counts number of cycles no uops were dispatched to be executed on this thread uops_executed.core umask=0x2,cmask=2,period=2000003,event=0xb1 Cycles at least 4 micro-op is executed from any thread on physical core llc_misses.code_llc_prefetch umask=0x1,event=0x35,filter_opc=0x18c unc_h_snoop_resp.rspsfwd Cycles where DRAM ranks are in power down (CKE) mode. Unit: uncore_imc Cycles all ranks are in critical thermal throttle. Unit: uncore_imc (unc_m_power_self_refresh / unc_m_dclockticks) * 100. uncore_pcu Counts the number of cycles when temperature is the upper limit on frequency. Unit: uncore_pcu Number of DTLB page walker hits in the L1+FB Spec update: BDM69, BDM98 BpTB inst_retired.any / br_inst_retired.all_branches IpMispredict Page_Walks_Utilization_SMT 1000 * mem_load_uops_retired.l2_miss / inst_retired.any Retired load uops with locked access. (Precise Event - PEBS) Spec update: BDM35. Supports address when precise (Precise event) offcore_response.demand_rfo.any_response offcore_response.pf_l2_data_rd.any_response offcore_response.pf_l2_rfo.supplier_none.snoop_none Counts all prefetch (that bring data to LLC only) code reads have any response type umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0080 Counts prefetch (that bring data to LLC only) code reads umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0200 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010091 offcore_response.all_data_rd.l3_hit.snoop_hit_no_fwd offcore_response.all_data_rd.l3_hit.any_snoop offcore_response.demand_data_rd.l3_miss.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000008 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000008 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000010 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000010 offcore_response.pf_l2_rfo.l3_miss.snoop_hit_no_fwd offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000200 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000090 offcore_response.all_pf_rfo.l3_miss_local_dram.any_snoop offcore_response.all_data_rd.supplier_none.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000091 offcore_response.all_rfo.l3_miss_local_dram.any_snoop This event counts resource-related stall cycles umask=0x6,period=2000003,cmask=6,event=0xa3 umask=0x48,event=0x22 unc_arb_trk_requests.all bdx metrics Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches Retired load uop whose Data Source was: forwarded from remote cache Supports address when precise. Spec update: BDE70 (Precise event) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C8FFF umask=0x1,period=100003,event=0xb7,offcore_rsp=0x103FC007F7 Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram Counts all demand & prefetch data reads miss in the L3 This event counts the number of retirement slots used (Precise event) 8Bytes (unc_m_power_critical_throttle_cycles / unc_m_clockticks) * 100. L2 cache lines evicted Modified lines evicted from the L2 cache umask=0x42,period=200000,event=0x28 l2_ld.self.demand.m_state umask=0x58,period=200000,event=0x29 l2_rqsts.self.demand.e_state l2_rqsts.self.demand.s_state umask=0x72,period=200000,event=0x30 l2_reject_busq.self.demand.e_state l2_reject_busq.self.prefetch.i_state FXCH uops executed umask=0x10,period=2000000,event=0xc7 Retired computational Streaming SIMD Extensions (SSE) packed-single instructions Store splits umask=0x0,period=200000,event=0x3a bus_drdy_clocks.this_agent umask=0xe0,period=200000,event=0x7e Cycles the divider is busy umask=0x4,period=200000,event=0x89 br_missp_type_retired.ind_call br_inst_retired.mispred_taken umask=0xc,period=2000000,event=0xc4 umask=0x41,period=200003,event=0x2e umask=0x4f,period=200003,event=0x2e umask=0x80,period=200003,event=0xd1 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x36000032b7 offcore_response.any_rfo.l2_miss.snoop_miss_or_no_snoop_needed Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400004000 Counts the number of demand write requests (RFO) generated by a write to partial data cache line, including the writes to uncacheable (UC) and write through (WT), and write protected (WP) types of memory that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand data partial reads, including data in uncacheable (UC) or uncacheable write combining (USWC) memory types that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that are outstanding, per cycle, from the time of the L2 miss to when any response is received Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache offcore_response.demand_rfo.l2_miss.hitm_other_core umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000040002 decode_restriction.predecode_wrong Uops requested but not-delivered to the back-end per cycle umask=0xbf,period=200003,event=0xc4 umask=0xfb,period=200003,event=0xc4 umask=0x1,period=200003,event=0xe6 Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes outstanding, per cycle, from the time of the L2 miss to when any response is received Counts data cache line reads generated by hardware L1 data cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000013010 Counts data reads generated by L1 or L2 prefetchers have any transaction responses from the uncore subsystem Counts reads for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Instructions retired - using Reduced Skid PEBS feature (Must be precise) umask=0x2,period=200003,event=0x8 itlb_misses.walk_completed_1gb Counts STLB flushes. The TLBs are flushed on instructions like INVLPG and MOV to CR3 Counts the number of store RFO requests that hit the L2 cache Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore Spec update: HSD62, HSD61 All retired store uops. (precise Event) Spec update: HSD29, HSM30. Supports address when precise (Precise event) This event counts retired load uops in which data sources were data hits in the L3 cache without snoops required. This does not include hardware prefetches. This is a precise event Spec update: HSD74, HSD29, HSD25, HSM26, HSM30. Supports address when precise (Precise event) This event count the number of undelivered (unallocated) uops from the Front-end to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalled. The Front-end can allocate up to 4 uops per cycle so this event can increment 0-4 times per cycle depending on the number of unallocated uops. This event is counted on a per-core basis Spec update: HSD135 Cycles in which the L1D and L2 are locked, due to a UC lock or split lock Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch Cycles at least 1 micro-op is executed from any thread on physical core Spec update: HSD30, HSM31 Cycles no executable uops retired on core (Precise event) umask=0x24,event=0x22 Number of DTLB page walker hits in Memory Spec update: HSD25 Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready Supports address when precise. Spec update: HSM30 (Precise event) offcore_response.pf_l2_code_rd.llc_hit.any_response l2_store_lock_rqsts.miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0091 offcore_response.demand_data_rd.llc_hit.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3004003f7 Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not Cycles with pending memory loads. Set AnyThread to count per core Unit: uncore_arb Number of requests allocated in Coherency Tracker itlb_misses.large_page_walk_completed offcore_response.all_pf_data_rd.llc_hit.hitm_other_core Counts all prefetch (that bring data to L2) code reads that hit in the LLC Counts all demand & prefetch code reads that miss the LLC and the data forwarded from remote cache Counts prefetch (that bring data to L2) data reads that miss the LLC the data is found in M state in remote cache and forwarded from there LLC prefetch misses for data reads. Derived from unc_c_tor_inserts.miss_opcode.data_read. Unit: uncore_cbox (unc_p_freq_band2_cycles / unc_p_clockticks) * 100. dtlb_load_misses.demand_ld_walk_completed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC20077 Valid instructions written to IQ per cycle Resource stalls due to Rob being full, FCSW, MXCSR and OTHER unc_c_tor_occupancy.miss_all offcore_response.any_read.l2_hit_far_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000044 offcore_response.any_request.l2_hit_far_tile_m offcore_response.pf_software.l2_hit_far_tile_m offcore_response.uc_code_reads.outstanding offcore_response.partial_writes.l2_hit_far_tile_e_f offcore_response.partial_reads.l2_hit_near_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400020 Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in M state offcore_response.any_request.l2_hit_this_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000040 offcore_response.any_code_rd.l2_hit_this_tile_e Counts any Read request that accounts for responses which hit its own tile's L2 with data in E state Counts L2 code HW prefetches that accounts for responses which hit its own tile's L2 with data in F state offcore_response.pf_l1_data_rd.l2_hit_this_tile_f offcore_response.partial_writes.l2_hit_near_tile Counts Bus locks and split lock requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state offcore_response.any_data_rd.l2_hit_near_tile umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800403091 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200070 Counts Demand code reads and prefetch code read requests that accounts for data responses from DRAM Local umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101001000 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800020 Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Local offcore_response.demand_rfo.mcdram offcore_response.demand_data_rd.ddr Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from DDR (local and far) umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181800200 umask=0x8,period=200003,event=0x4 Counts the number of load micro-ops retired that cause a DTLB miss Supports address when precise (Precise event) cache_lock_cycles.l1d_l2 All references to the L1 data cache umask=0x4,period=2000000,event=0x40 L1 data cache read in M state umask=0x80,period=200000,event=0x26 umask=0x20,period=200000,event=0x26 l2_write.lock.hit umask=0xe0,period=100000,event=0x27 umask=0x41,period=100000,event=0x2e Longest latency cache miss mem_load_retired.llc_unshared_hit umask=0x10,period=100,event=0xb,ldlat=0x400 umask=0x10,period=2000,event=0xb,ldlat=0x40 offcore_response.any_data.any_cache_dram offcore_response.any_ifetch.remote_cache_hit offcore_response.data_ifetch.io_csr_mmio offcore_response.demand_data.local_cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1003 Offcore demand data reads satisfied by a remote cache or remote DRAM offcore_response.demand_ifetch.llc_hit_no_other_core umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4704 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1804 Offcore demand RFO requests satisfied by the LLC and not found in a sibling core offcore_response.demand_rfo.remote_cache_dram offcore_response.other.llc_hit_other_core_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1080 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3830 Offcore prefetch data reads satisfied by the LLC Offcore prefetch requests that HITM in a remote cache MMX Uops Transitions from MMX to Floating Point instructions simd_int_128.pack simd_int_128.packed_logical Instructions decoded offcore_response.corewb.any_dram Offcore demand data requests satisfied by any DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2004 umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF802 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x6080 Offcore prefetch data requests that missed the LLC umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4030 offcore_response.prefetch.any_llc_miss L1I instruction fetch stall cycles l1i.hits Loads dispatched that bypass the MOB br_inst_exec.any Conditional branch instructions executed ild_stall.regen Load buffer stall cycles resource_stalls.mxcsr umask=0x4,period=200000,event=0xc7 Cycles no Uops are decoded umask=0x3f,any=1,period=2000000,cmask=1,event=0xb1 Cycles no Uops were issued on any thread Cycles Uops were issued on either thread Uops retired (Precise Event) umask=0x10,period=2000000,event=0x8 DTLB second level hit Counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted offcore_response.other.l3_hit_m.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04001C0004 offcore_response.demand_code_rd.l3_hit_m.snoop_miss offcore_response.demand_rfo.l4_hit_local_l4.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0080002 offcore_response.demand_rfo.supplier_none.spl_hit offcore_response.demand_data_rd.l3_hit_e.snoop_hit_no_fwd umask=0x2,period=200003,event=0x83 Counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4 Retired Instructions who experienced iTLB true miss. Precise Event (Precise event) frontend_retired.latency_ge_2_bubbles_ge_2 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall. Precise Event (Precise event) umask=0x1,period=100007,event=0xc6,frontend=0x408006 Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall (Precise event) hle_retired.aborted_unfriendly Number of times we entered an RTM region. Does not count nested transactions Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency (Must be precise) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x203C400002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C400002 offcore_response.demand_rfo.l3_hit_m.snoop_non_dram offcore_response.demand_data_rd.l3_miss.snoop_hitm Counts the number of x87 uops dispatched This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired Spec update: SKL091 (Must be precise) Counts the number of far branch instructions retired Spec update: SKL091 (Precise event) Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake This event counts the number of load ops retired that miss in the L2 (Precise event) Counts any request that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Counts any request that have any response type Counts code reads generated by L2 prefetchers that miss L2 with a snoop miss response umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680000020 Counts RFO requests generated by L2 prefetchers that miss L2 offcore_response.demand_code_rd.l2_miss.snoop_miss This event counts all instruction fetches that miss the Instruction cache or produce memory requests. This includes uncacheable fetches. An instruction fetch miss is counted only once and not once for every cycle it is outstanding JCC counts the number of mispredicted conditional branches (JCC) instructions retired. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa. When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event) The BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end. The BACLEARS.ANY event counts the number of baclears for any type of branch Retired load uops which data sources were HitM responses from shared LLC. (Precise Event - PEBS) (Precise event) Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores Counts all demand rfo's umask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400120 Offcore demand code read requests Cycles offcore demand data read busy REQUEST = ANY_DATA read and RESPONSE = REMOTE_CACHE_HITM REQUEST = CORE_WB and RESPONSE = ANY_LOCATION REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE REQUEST = DEMAND_DATA and RESPONSE = LOCAL_CACHE umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5001 REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM REQUEST = PF_RFO and RESPONSE = IO_CSR_MMIO offcore_response.prefetch.all_local_dram_and_remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f70 REQUEST = ANY RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD offcore_response.corewb.any_dram_and_remote_fwd offcore_response.data_ifetch.any_dram_and_remote_fwd REQUEST = DEMAND_RFO and RESPONSE = REMOTE_DRAM offcore_response.pf_data.any_dram_and_remote_fwd REQUEST = PF_DATA_RD and RESPONSE = ANY_LLC_MISS Snoop data requests Snoop invalidate requests offcore_requests.uncached_mem umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2744 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x6050 inv=1,umask=0x3f,period=2000000,cmask=1,edge=1,event=0xb1 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063B800010 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x083FC00080 offcore_response.pf_l3_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x083FC00400 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063B800491 Core cycles the core was throttled due to a pending power level request 1000000000 * ( cha@event\=0x36\\\,umask\=0x21@ / cha@event\=0x35\\\,umask\=0x21@ ) / ( cha_0@event\=0x0@ / duration_time ) unc_m_cas_count.rd_underfill umask=0x2,event=0x4 umask=0x01,event=0x50 read requests from local home agent. Unit: uncore_cha write requests from home agent. Unit: uncore_cha LLC_MISSES.PCIE_READ PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0. Unit: uncore_iio unc_iio_data_req_of_cpu.mem_write.part0 +unc_iio_data_req_of_cpu.mem_write.part1 +unc_iio_data_req_of_cpu.mem_write.part2 +unc_iio_data_req_of_cpu.mem_write.part3 fc_mask=0x07,ch_mask=0x01,umask=0x04,event=0x83 PCI Express bandwidth reading at IIO, part 0. Unit: uncore_iio umask=0x42,event=0x33 unc_cha_snoop_resp.rsp_fwd_wb unc_cha_snoop_resp.rsp_wbwb Write request of up to a 64 byte transaction is made to IIO Part2 by the CPU . Unit: uncore_iio umask=0x2,event=0x22 Messages sent direct to the Intel UPI. Unit: uncore_m2m Multi-socket cacheline Directory update from A to I. Unit: uncore_m2m Multi-socket cacheline Directory update from I to A. Unit: uncore_m2m FLITs received which bypassed the Slot0 Receive Buffer. Unit: uncore_upi ll Cycles in which the Tx of the Intel Ultra Path Interconnect (UPI) is in L0p power mode. Unit: uncore_upi ll period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0004 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200001 offcore_response.all_reads.pmm_hit_local_pmm.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040001 offcore_response.demand_rfo.pmm_hit_local_pmm.snoop_none This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.SNOOP_MISS offcore_response.other.supplier_none.hitm_other_core period=100007,umask=0x10,event=0xd3 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400001 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200020 offcore_response.all_pf_rfo.l3_hit_m.hit_other_core_fwd This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD This event is deprecated. Refer to new event OCR.ALL_RFO.ANY_RESPONSE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010001 offcore_response.demand_rfo.l3_hit_s.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400100 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020010 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080120 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED offcore_response.all_rfo.l3_hit_s.snoop_miss offcore_response.demand_data_rd.l3_hit_f.snoop_none offcore_response.all_reads.pmm_hit_local_pmm.snoop_not_needed offcore_response.pf_l3_rfo.l3_hit_s.hit_other_core_fwd This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l2_data_rd.l3_hit_m.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200001 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080490 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100491 period=200003,umask=0xe2,event=0x24 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400491 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100491 offcore_response.pf_l1d_and_sw.l3_hit_f.snoop_miss offcore_response.pf_l2_data_rd.l3_hit_s.hit_other_core_fwd offcore_response.demand_rfo.l3_hit_m.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.SNOOP_MISS This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.SNOOP_NONE cmask=1,period=2000003,umask=0x2,event=0x60 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000208000 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.SNOOP_NONE offcore_response.all_data_rd.l3_hit_f.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE offcore_response.demand_code_rd.l3_hit_f.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0100 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020002 offcore_response.demand_code_rd.l3_hit_f.hitm_other_core This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD offcore_response.demand_data_rd.supplier_none.no_snoop_needed This event is deprecated. Refer to new event OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0020 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040002 offcore_response.other.pmm_hit_local_pmm.any_snoop This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080010 offcore_response.pf_l2_rfo.l3_hit_e.snoop_none This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400004 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE period=100003,umask=0x8,event=0xb0 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040100 Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall (Precise event) cmask=1,period=2000003,umask=0x30,event=0x79 period=100007,umask=0x1,event=0xc6,frontend=0x401006 Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE ocr.demand_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd ALL_RFO & L3_MISS & HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00840007F7 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD ocr.all_reads.l3_miss_remote_hop1_dram.any_snoop This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD period=2000003,umask=0x2,event=0xc8 offcore_response.demand_data_rd.l3_miss_remote_hop1_dram.snoop_miss This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000100 Counts all demand data writes (RFOs) DEMAND_RFO & L3_MISS_LOCAL_DRAM & SNOOP_MISS_OR_NO_FWD offcore_response.all_pf_data_rd.l3_miss.hit_other_core_no_fwd ALL_READS & L3_MISS_LOCAL_DRAM & SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000122 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08040007F7 offcore_response.all_rfo.l3_miss.hit_other_core_fwd This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE ALL_PF_RFO & L3_MISS & SNOOP_NONE This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD offcore_response.all_reads.l3_miss_remote_hop1_dram.snoop_miss This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS_REMOTE_HOP1_DRAM & NO_SNOOP_NEEDED ocr.all_rfo.l3_miss_local_dram.hit_other_core_no_fwd period=2000003,umask=0x2,event=0x54 ocr.all_pf_data_rd.l3_miss_remote_hop1_dram.hitm_other_core This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE period=2003,umask=0x1,event=0xcd,ldlat=0x40 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.REMOTE_HITM ocr.demand_rfo.l3_miss_local_dram.any_snoop ocr.pf_l3_data_rd.l3_miss.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD ocr.pf_l2_data_rd.l3_miss_local_dram.no_snoop_needed period=2000003,umask=0x10,event=0x60 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED offcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd Counts all demand code reads DEMAND_CODE_RD & L3_MISS & HITM_OTHER_CORE offcore_response.pf_l3_rfo.l3_miss.hit_other_core_fwd ocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hitm_other_core ocr.all_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd Counts any other requests OTHER & L3_HIT_E & ANY_SNOOP Counts demand data reads DEMAND_DATA_RD & L3_HIT_S & HIT_OTHER_CORE_FWD ocr.demand_rfo.l3_hit_m.hitm_other_core Counts any other requests OTHER & L3_HIT_S & HIT_OTHER_CORE_FWD ocr.all_pf_rfo.l3_hit.snoop_miss Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & SUPPLIER_NONE & HITM_OTHER_CORE ALL_RFO & ANY_RESPONSE have any response type ALL_PF_DATA_RD & L3_HIT_F & ANY_SNOOP ocr.all_pf_rfo.supplier_none.snoop_miss ocr.all_pf_rfo.l3_hit.hit_other_core_fwd Counts all demand code reads DEMAND_CODE_RD & SUPPLIER_NONE & HITM_OTHER_CORE ocr.pf_l2_data_rd.l3_hit_e.any_snoop ocr.demand_rfo.l3_hit.hitm_other_core ocr.pf_l2_rfo.l3_hit_f.snoop_miss ocr.demand_code_rd.supplier_none.snoop_miss ocr.all_reads.l3_hit.hit_other_core_fwd ocr.demand_rfo.pmm_hit_local_pmm.snoop_not_needed Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT & SNOOP_MISS ocr.pf_l2_data_rd.l3_hit_f.hit_other_core_fwd ocr.pf_l2_rfo.l3_hit.hit_other_core_no_fwd ocr.all_pf_rfo.l3_hit.hit_other_core_no_fwd ocr.pf_l2_rfo.l3_hit.snoop_none ALL_RFO & L3_HIT_S & HITM_OTHER_CORE ocr.other.supplier_none.hit_other_core_fwd ocr.pf_l3_data_rd.l3_hit_f.hitm_other_core ocr.pf_l1d_and_sw.l3_hit.hitm_other_core ALL_DATA_RD & L3_HIT & SNOOP_NONE ocr.other.l3_hit_s.hit_other_core_no_fwd ocr.demand_code_rd.l3_hit.no_snoop_needed ocr.demand_rfo.supplier_none.snoop_none period=200003,umask=0x18,event=0x28 ocr.demand_rfo.l3_hit_f.any_snoop period=203,umask=0x1,event=0xcb ocr.pf_l1d_and_sw.l3_hit_m.no_snoop_needed ALL_RFO & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDED period=25003,umask=0x1,event=0x3c period=2000003,umask=0x40,event=0xa1 unc_cha_rxc_occupancy.irq fc_mask=0x07,ch_mask=0x01,umask=0x08,event=0xc0 Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part3 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part2. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus fc_mask=0x07,ch_mask=0x01,umask=0x08,event=0x84 umask=0x02,event=0x2c Dirty line underfill read hits to Near Memory(DRAM cache) in Memory Mode. Unit: uncore_m2m unc_m2m_txc_bl_inserts.all period=100003,umask=0x1,event=0x49 l1d_pend_miss.fb_full_periods Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element idq.mite_cycles_ok umask=0x1,period=2000003,cmask=5,event=0x9c Counts the number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.) Counts the number of times RTM abort was triggered Supports address when precise uops_dispatched.port_2_3 resource_stalls.scoreboard Cycles where the Store Buffer was full and no loads caused an execution stall Cycles when at least one PMH is busy with a page walk for a store Counts the number of load uops retired that miss in the level 1 data cache Supports address when precise (Precise event) Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The event continues counting during hardware interrupts, traps, and inside interrupt handlers. This is an architectural performance event. This event uses a Programmable general purpose perfmon counter. *This event is Precise Event capable: The EventingRIP field in the PEBS record is precise to the address of the instruction which caused the event (Precise event) Clockticks in the UBOX using a dedicated 48-bit Fixed Counter Instruction Pipe Stall. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to DQ empty All L2 Cache Requests (Breakdown 2 - Rare). Self-modifying code invalidates Other L3 Miss Request Types. Unit: uncore_l3pmc umask=0x01,event=0x6 The number of uOps retired. This includes all processor activity (instructions, exceptions, interrupts, microcode assists, etc.). The number of events logged per cycle can vary from 0 to 4 umask=0x8B,event=0x8b umask=0x67,event=0x8b df_ccm_reqa.node2.anyrdblk df_ccm_reqa.node3.anyrdblk umask=0x65,event=0x8b umask=0x85,event=0x8b df_ccm_reqa.node5.anyrdblk umask=0x03,event=0x8b umask=0x2E,event=0x8c umask=0x49,event=0x8c umask=0x69,event=0x8c df_ccm_reqb.node5.anywrsized df_ccm_reqb.node1.wrsizedfullnc umask=0x81,event=0x8c umask=0x29,event=0x108 df_ioms_reqa.node2.fence df_ioms_reqa.node7.anywrsized=64b df_ioms_reqa.node1.anywrsized>32band<64b umask=0xE5,event=0x108 umask=0xE3,event=0x108 df_ioms_reqa.node6.anyrdsized umask=0xA1,event=0x108 df_ioms_reqb.node5.pieinterrupt umask=0x4C,event=0x109 df_ioms_reqb.node6.ioanyatomic umask=0x29,event=0x109 umask=0x69,event=0x109 umask=0xA5,event=0x109 Double precision divide/square root FLOPS This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Single-precision multiply FLOPS fp_num_mov_elim_scal_op.optimized x87 control word mispredict traps due to mispredictions in RC or PC, or changes in mask bits x87 bottom-executing uOps retired SSE control word mispredict traps due to mispredictions in RC, FTZ or DAZ, or changes in mask bits l3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x02,event=0x1 l3_request_g1.t5.s2.wrsizednc l3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x04,event=0x1 l3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x20,event=0x1 l3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x40,event=0x1 l3_request_g1.t4.s1.rdsized l3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x40,event=0x1 l3_request_g1.t7.s0.caching l3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x80,event=0x1 l3fillvicreq.t2.s1.vicblk l3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x01,event=0x3 l3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x02,event=0x3 l3fillvicreq.t7.s0.chgtox l3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x02,event=0x3 l3fillvicreq.t2.s1.rdblkc_s l3fillvicreq.t6.s2.rdblkc_s l3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x10,event=0x3 l3fillvicreq.t0.s1.rdblkx_vic l3fillvicreq.t2.s2.rdblkx l3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x20,event=0x3 l3fillvicreq.t3.s0.rdblkl_vic l3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x40,event=0x3 l3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x01,event=0x9 l3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x02,event=0x9 l3victimstate.t2.s1.f_s l3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x04,event=0x9 l3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x04,event=0x9 l3victimstate.t7.s2.f_s l3victimstate.t2.s2.o l3victimstate.t7.s2.e_fe l3victimstate.t3.s2.m l3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x20,event=0x9 l3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x20,event=0x9 l3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x40,event=0x9 l3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x40,event=0x9 Misaligned loads umask=0x4,event=0xaf fp_disp_faults.ymm_spill_fault umask=0x1,event=0xe ls_st_commit_cancel2.st_commit_cancel_wcb_full ls_refills_from_sys.ls_mabresp_rmt_cache L1 DTLB Miss. DTLB reload to a 1G page that miss in the L2 TLB umask=0x2,event=0x5a Cycles where the Micro-Op Queue is empty de_dis_dispatch_token_stalls1.fp_sch_rsrc_stall Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ3_0_TokenStall INSTR_RETIRED_ANY DC_COPYBACK L1_ICACHE_ACCESS CYCLES_STALLED_NEON_FULLQ PREDICTABLE_FUNCTION_RETURN BR_IMMED_RETIRED L1D_CACHE_REFILL_ST BR_RETIRED L2_WRITEBACK ALU_EMPTY_CYCLES AGEN_BUBBLE_CYCLES UNCACHED_STORE_INSNS FAILED_SC_INSNS MISPREDICTION_STALLS VIU1_INSTR_COMPLETED FP_LOAD_INSTR_COMPLETED_IN_LSU VTQ_LINE_FETCH_MISS L3_STORE_HITS EXTERNAL_INTERVENTIONS BUS_WRITES_NOT_RETRIED PREFETCH_ENGINE_COLLISION_VS_STORE GROUP_MARKED_IDU MARKED_GROUP_ISSUED ADDER PART2_MISALIGNED_CACHE_ACCESS_CYCLES SYSCALL_TRAP_INTR STASH_REQUESTS L2_CACHE_DATA_ACCESSES L2_CACHE_INSTR_ALLOCATIONS dc-misses IAP INTEL_IVYBRIDGE pmclog_get_event tsc-tsc %s, "pid": "%d"}
%s, "userdata": "0x%08x"}
GenuineIntel-6-5C ILP ( cpu@itlb_misses.walk_duration\,cmask\=1@ + cpu@dtlb_load_misses.walk_duration\,cmask\=1@ + cpu@dtlb_store_misses.walk_duration\,cmask\=1@ + 7*(dtlb_store_misses.walk_completed+dtlb_load_misses.walk_completed+itlb_misses.walk_completed)) / ( cpu_clk_unhalted.thread_any / 2 ) if #smt_on else cycles GFLOPs cpu_clk_unhalted.ref_tsc:k / cpu_clk_unhalted.ref_tsc C7 residency percent per package umask=0x4f,period=100003,event=0x2e l1d_pend_miss.fb_full Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore Spec update: BDM76 This event counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS Spec update: BDM76 lock_cycles.cache_lock_duration This event counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore mem_uops_retired.stlb_miss_loads mem_load_uops_retired.l2_miss Miss in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS) Supports address when precise. Spec update: BDM100, BDE70 (Precise event) Retired load uops which data sources were HitM responses from shared L3. (Precise Event - PEBS) Supports address when precise. Spec update: BDM100 (Precise event) sq_misc.split_lock This event counts the number of split locks in the super queue Number of transitions from SSE to AVX-256 when penalty applicable Spec update: BDM30 Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired. Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element Number of SIMD FP assists due to Output values This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE umask=0x80,period=2000003,event=0xc8 umask=0x2,period=2000003,event=0xc9 umask=0x1,period=101,event=0xcd,ldlat=0x200 event=0x3c Cycles checkpoints in Resource Allocation Table (RAT) are recovering from JEClear or machine clear int_misc.recovery_cycles_any cpu_clk_unhalted.thread_p This event counts not taken macro-conditional branch instructions umask=0xc4,period=200003,event=0x89 This event counts both taken and not taken mispredicted indirect branches excluding calls and returns Cycles per thread when uops are executed in port 5 umask=0x1,cmask=1,period=2000003,event=0xa3 uops_executed.cycles_ge_2_uops_exec umask=0x1,cmask=2,period=2000003,event=0xb1 uops_executed.core_cycles_none umask=0x1,period=2000003,event=0xc0 Direct and indirect near call instructions retired. (Precise Event - PEBS) (Precise event) This is a precise version (that is, uses PEBS) of the event that counts taken branch instructions retired (Precise event) All mispredicted macro branch instructions retired llc_misses.mmio_read unc_c_tor_occupancy.llc_data_read unc_m_pre_count.wr event=0x80,occ_sel=3 Load misses in all DTLB levels that cause page walks Spec update: BDM69 umask=0x1,period=100003,event=0x49 itlb_misses.walk_completed This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example. SMT version; use when SMT is enabled and measuring per logical CPU (( 1 * ( fp_arith_inst_retired.scalar_single + fp_arith_inst_retired.scalar_double ) + 2 * fp_arith_inst_retired.128b_packed_double + 4 * ( fp_arith_inst_retired.128b_packed_single + fp_arith_inst_retired.256b_packed_double ) + 8 * fp_arith_inst_retired.256b_packed_single )) / cycles FLOPS_SMT 64 * l2_lines_in.all / 1000000000 / duration_time Average per-core data fill bandwidth to the L3 cache [GB / sec] offcore_response.demand_data_rd.any_response offcore_response.demand_data_rd.supplier_none.snoop_not_needed offcore_response.demand_data_rd.l3_hit.snoop_miss offcore_response.corewb.l3_hit.snoop_hit_no_fwd offcore_response.pf_l2_data_rd.l3_hit.snoop_hit_no_fwd offcore_response.pf_l3_rfo.l3_hit.snoop_hitm offcore_response.all_pf_data_rd.supplier_none.snoop_none offcore_response.all_pf_code_rd.supplier_none.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0091 offcore_response.all_rfo.supplier_none.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0122 Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element umask=0x1e,period=100003,cmask=1,event=0xca Randomly selected loads with latency value being above 8 Spec update: BDM100, BDM35 (Must be precise) offcore_response.demand_data_rd.l3_miss_local_dram.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000004 offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000080 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0100 offcore_response.pf_l3_rfo.l3_miss.snoop_none offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000120 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000240 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000091 This is a precise version (that is, uses PEBS) of the event that counts cycles without actually retired uops Counts all not taken macro branch instructions retired. (Precise Event) Counts the number of far branch instructions retired.(Precise Event) Spec update: BDW98 umask=0x41,event=0x22 Unit: uncore_cbox A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core Unit: uncore_ncu This 48-bit fixed counter counts the UCLK cycles Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache Supports address when precise. Spec update: BDM100 (Precise event) offcore_response.all_code_rd.llc_hit.hit_other_core_no_fwd Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram offcore_response.all_data_rd.llc_miss.any_response This event counts mispredicted return instructions retired (Precise event) uncore interconnect umask=0x2,event=0 l2_ads.self l2_lines_in.self.prefetch l2_data_rqsts.self.m_state umask=0x54,period=200000,event=0x30 umask=0x5f,period=200000,event=0x30 FXCH uops retired (Must be precise) umask=0x84,period=2000000,event=0xb3 Saturated arithmetic instructions retired misalign_mem_ref.split Nonzero segbase load 1 bubble umask=0x86,period=200000,event=0x7 Bus cycles when a LOCK signal is asserted bus_trans_wb.self bus_trans_burst.all_agents bus_hitm_drv.all_agents Cycles during which interrupts are pending and disabled div.s umask=0x2,period=2000000,event=0x88 Instructions retired (precise event) (Must be precise) Micro-ops retired Cycles no micro-ops retired umask=0x0,period=200000,event=0xc5 page_walks.d_side_cycles mem_load_retired.dtlb_miss offcore_response.any_pf_data_rd.l2_miss.snoop_miss_or_no_snoop_needed umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000008000 Counts partial cache line data writes to uncacheable write combining (USWC) memory region that hit the L2 cache Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cache lines requests by software prefetch instructions that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that true miss for the L2 cache with a snoop miss in the other processor module Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required offcore_response.pf_l2_rfo.l2_hit offcore_response.demand_code_rd.l2_hit References per ICache line. This event counts differently than Intel processors based on Silvermont microarchitecture Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line. The event strives to count on a cache line basis, so that multiple fetches to a single cache line count as one ICACHE.ACCESS. Specifically, the event counts when accesses from straight line code crosses the cache line boundary, or when a branch target is to a new line.
This event counts differently than Intel processors based on Silvermont microarchitecture misalign_mem_ref.load_page_split ld_blocks.data_unknown Counts the number of integer divide uops retired (Must be precise) Retired taken branch instructions (Precise event capable) (Must be precise) br_inst_retired.return Counts demand cacheable data reads of full cache lines have any transaction responses from the uncore subsystem Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache outstanding, per cycle, from the time of the L2 miss to when any response is received Counts the number of writeback transactions caused by L1 or L2 cache evictions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000800 Counts requests to the uncore subsystem hit the L2 cache umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000003010 Counts data reads (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Page walk completed due to a demand load to a 1GB page Counts once per cycle for each page walk occurring due to a demand data store. Includes cycles spent traversing the Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of walks All requests that missed L2 Spec update: HSD78 Counts any demand and L1 HW prefetch data load requests to L2 Spec update: HSD78 This event counts all store uops retired. This is a precise event Spec update: HSD29, HSM30. Supports address when precise (Precise event) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Counts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer Randomly selected loads with latency value being above 8 Spec update: HSD76, HSD25, HSM26 (Must be precise) Counts all demand code reads miss the L3 and the data is returned from local dram Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch Execution stalls due to L2 cache misses Misses in all TLB levels that cause a page walk of any page size umask=0x80,period=100003,event=0x8 Store misses in all DTLB levels that cause completed page walks Completed page walks due to misses in ITLB 4K page entries Retired load uops with locked access Supports address when precise. Spec update: HSD76, HSD29, HSM30 (Precise event) Retired store uops that split across a cacheline boundary Supports address when precise. Spec update: HSD29, HSM30 (Precise event) Retired load uops missed L1 cache as data sources Supports address when precise. Spec update: HSM30 (Precise event) offcore_response.demand_data_rd.llc_miss.any_response offcore_response.pf_l2_rfo.llc_miss.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00040 Counts the number of conditional branch instructions retired (Precise event) umask=0x20,period=200003,event=0x24 Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore Counts all demand & prefetch RFOs that hit in the LLC other_assists.avx_store Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles Counts all demand & prefetch data reads that miss the LLC and the data returned from dram offcore_response.demand_code_rd.llc_miss.dram Cycles which a Uop is dispatched on port 4 umask=0x40,event=0x34 Unit: uncore_cbox Filter on any IRQ or IPQ initiated requests including uncacheable, non-coherent requests Counts load operations that missed 1st level DTLB but hit the 2nd level mem_load_uops_llc_miss_retired.remote_hitm offcore_response.all_pf_data_rd.llc_hit.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0010 Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores offcore_response.pf_llc_data_rd.llc_hit.no_snoop_needed rxl0p_power_cycles % unc_p_freq_band0_cycles (unc_p_freq_ge_3000mhz_cycles / unc_p_clockticks) * 100. Retired load uops that split across a cacheline boundary (Precise event) This event counts retired load uops that hit in the last-level (L3) cache without snoops required Cycles when 1 or more uops were delivered to the by the front end jkt metrics This event counts all remote cache-to-cache transfers (includes HITM and HIT-Forward) for all demand and L2 prefetches. LLC prefetches are excluded This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers br_misp_exec.taken_direct_near_call This event counts the number of retirement slots used each cycle. There are potentially 4 slots that can be used each cycle - meaning, 4 micro-ops or 4 instructions could retire each cycle. This event is used in determining the 'Retiring' category of the Top-Down pipeline slots characterization (Precise event) Uops dispatched from any thread offcore_response.any_pf_l2.l2_hit_far_tile_e_f Counts any Read request that accounts for any response offcore_response.any_rfo.l2_hit_far_tile_e_f offcore_response.demand_data_rd.l2_hit_far_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002000004 Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in M state offcore_response.any_code_rd.l2_hit_this_tile_m offcore_response.any_read.l2_hit_this_tile_e umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008000200 Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in S state umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800180200 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800181000 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x18004032f7 offcore_response.any_pf_l2.l2_hit_far_tile Counts all instruction fetches, including uncacheable fetches Counts any Prefetch requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080208000 offcore_response.demand_code_rd.ddr_near umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800001 offcore_response.bus_locks.ddr Counts Bus locks and split lock requests that accounts for responses from DDR (local and far) offcore_response.any_code_rd.ddr uops_retired.packed_simd Counts the number of core cycles when no micro-ops are allocated and the alloc pipe is stalled waiting for a mispredicted branch to retire Counts the total number of core cycles for all the D-side page walks. The cycles for page walks started in speculative path will also be included l1d_cache_ld.mesi L1 data cache read in S state umask=0x2,period=2000000,event=0x42 L1D load lock accepted in fill buffer l2_data_rqsts.demand.m_state umask=0x8,period=200000,event=0x26 umask=0xf,period=200000,event=0x26 L2 data demand requests l2_rqsts.ifetches l2_rqsts.ld_miss L2 RFO hits L2 fill transactions L2 instruction fetch transactions umask=0x20,period=100000,event=0x27 mem_uncore_retired.remote_cache_local_home_hit mem_inst_retired.latency_above_threshold_32768 offcore_response.any_data.remote_cache_hitm offcore_response.any_ifetch.any_cache_dram Offcore code reads satisfied by the LLC and not found in a sibling core Offcore code reads satisfied by the LLC or local DRAM Offcore code reads satisfied by a remote cache offcore_response.any_request.local_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x8FF offcore_response.corewb.any_location umask=0x1,period=100000,event=0xb7,offcore_rsp=0x777 offcore_response.data_ifetch.remote_cache_hitm Offcore request = all data, response = local cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3833 All offcore demand data requests umask=0x1,period=100000,event=0xb7,offcore_rsp=0x103 Offcore demand data requests that HITM in a remote cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1002 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x480 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x880 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x830 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1010 offcore_response.pf_rfo.any_cache_dram offcore_response.pf_rfo.any_location offcore_response.pf_rfo.remote_cache Offcore prefetch requests satisfied by the IO, CSR, MMIO unit offcore_response.prefetch.remote_cache fp_comp_ops_exe.mmx simd_int_64.shuffle_move offcore_response.any_data.remote_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2044 umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF877 offcore_response.data_in.local_dram offcore_response.demand_data.any_llc_miss Offcore demand data reads satisfied by the local DRAM Offcore demand RFO requests satisfied by any DRAM offcore_response.demand_rfo.local_dram Offcore other requests that missed the LLC offcore_response.pf_data.any_dram offcore_response.pf_rfo.any_dram umask=0x2,period=2000000,event=0xe8 All RAT stall cycles BACLEAR asserted with bad target address umask=0x8,period=20000,event=0x88 Mispredicted near retired calls (Precise Event) inst_retired.total_cycles ssex_uops_retired.vector_integer uops_executed.core_stall_cycles_no_port5 mem_inst_retired.all_loads mem_load_l3_hit_retired.xsnp_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080408000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200088000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400048000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080100004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000080004 Counts demand instruction fetches and L1 instruction cache prefetches that have any response type umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000400002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0020002 offcore_response.demand_rfo.supplier_none.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC01C0001 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0100001 Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles (Must be precise) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC400004 offcore_response.demand_data_rd.l3_hit_m.snoop_non_dram Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty umask=0x10,period=2000003,event=0xa6 Direct and indirect near call instructions retired Spec update: SKL091 (Precise event) inst_retired.any / ( br_inst_retired.far_branch / 2 ) Page walk completed due to a demand data load to a 2M/4M page Counts completed page walks (2M and 4M page sizes) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB. The page walk can end with or without a fault Cross core or cross module hitm (Precise event) This event counts the number of load ops retired Counts any rfo reads (demand & prefetch) that have any response type umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680004800 Counts data cacheline reads generated by L2 prefetchers that miss L2 Counts data cacheline reads generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded umask=0x3f,period=200003,event=0x86 MSROM micro-ops retired Cycles the divider is busy.This event counts the cycles when the divide unit is unable to accept a new divide UOP because it is busy processing a previously dispatched UOP. The cycles will be counted irrespective of whether or not another divide UOP is waiting to enter the divide unit (from the RS). This event might count cycles while a divide is in progress even if the RS is empty. The divide instruction is one of the longest latency instructions in the machine. Hence, it has a special event associated with it to help determine if divides are delaying the retirement of instructions Retired load uops that miss the STLB. (Precise Event - PEBS) (Precise event) offcore_response.all_code_rd.llc_hit.snoop_miss Counts all prefetch RFOs that miss the LLC and the data returned from dram offcore_response.pf_l2_code_rd.llc_miss.dram Counts all prefetch (that bring data to LLC only) code reads that miss the LLC and the data returned from dram This event counts the number of cycles with at least one slow LEA uop being allocated. A uop is generally considered as slow LEA if it has three sources (for example, two sources and immediate) regardless of whether it is a result of LEA instruction or not. Examples of the slow LEA uop are or uops with base, index, and offset source operands using base and index reqisters, where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel® 64 and IA-32 Architectures Optimization Reference Manual for more details about slow LEA instructions umask=0x10,period=100000,event=0xb0 umask=0x4,period=100000,event=0xb0 Offcore demand RFO requests umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4ff REQUEST = OTHER and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5010 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x20ff REQUEST = DATA_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD REQUEST = OTHER and RESPONSE = ANY_DRAM AND REMOTE_FWD umask=0x2,period=100000,event=0xb4 Outstanding snoop code requests offcore_response.pf_l3_data_rd.l3_hit.hit_other_core_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0400 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0491 offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd Counts all prefetch (that bring data to LLC only) data reads TBD offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd offcore_response.all_pf_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd offcore_response.all_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd offcore_response.all_rfo.l3_miss.remote_hitm umask=0x14,cmask=20,period=2000003,event=0xa3 Streaming stores (partial cache line). Derived from unc_cha_tor_inserts.ia_miss. Unit: uncore_cha umask=0x0C,event=0x50 fc_mask=0x07,ch_mask=0x04,umask=0x01,event=0xc1 Write request of up to a 64 byte transaction is made by IIO Part2 to Memory. Unit: uncore_iio Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state , and found the cacheline marked in the S (Shared) state indicating the cacheline is either stored in another socket in the S(hared) state , and so there is no need to snoop the other sockets for the latest data. The data may be stored in any state in the local socket Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from S (Shared) to A (SnoopAll) period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400002 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200004 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200122 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080122 offcore_response.all_pf_rfo.supplier_none.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400048000 period=100003,umask=0x42,event=0xd0 offcore_response.pf_l2_data_rd.supplier_none.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400491 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C8000 offcore_response.pf_l3_data_rd.l3_hit_e.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080001 This event is deprecated. Refer to new event OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP offcore_response.pf_l2_rfo.supplier_none.hitm_other_core This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C8000 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD offcore_response.other.l3_hit_s.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS offcore_response.pf_l3_data_rd.l3_hit_f.any_snoop This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE offcore_response.pf_l3_rfo.l3_hit_m.hitm_other_core This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP cmask=1,period=2000003,umask=0x1,event=0x60 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD offcore_response.pf_l3_rfo.l3_hit_m.snoop_miss offcore_response.all_pf_rfo.pmm_hit_local_pmm.snoop_not_needed offcore_response.all_pf_data_rd.l3_hit_e.hit_other_core_no_fwd offcore_response.pf_l3_data_rd.l3_hit_e.any_snoop This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_MISS offcore_response.all_reads.supplier_none.any_snoop This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD offcore_response.demand_data_rd.supplier_none.hit_other_core_no_fwd offcore_response.other.l3_hit_f.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0002 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0400 offcore_response.pf_l1d_and_sw.l3_hit.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100120 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040122 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00801007F7 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200491 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100080 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04000207F7 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040490 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040001 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010120 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080080020 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200120 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200002 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0020 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040020 Retired Instructions who experienced STLB (2nd level TLB) true miss (Precise event) ocr.all_reads.l3_miss_local_dram.snoop_miss_or_no_fwd This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000010 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800002 period=2000003,umask=0x4,event=0x54 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0804000120 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000004 period=2000003,umask=0x10,event=0x5d This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000400 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000004 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000010 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd Counts any other requests OTHER & L3_MISS & SNOOP_NONE offcore_response.all_data_rd.l3_miss.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000491 This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604000490 ocr.all_reads.l3_miss_local_dram.snoop_miss ocr.demand_data_rd.l3_miss_local_dram.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000490 offcore_response.all_pf_data_rd.l3_miss.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084008000 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS offcore_response.all_reads.l3_miss.remote_hit_forward Counts all demand code reads DEMAND_CODE_RD & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000400 offcore_response.all_reads.l3_miss_local_dram.hit_other_core_fwd Counts all demand code reads DEMAND_CODE_RD & L3_MISS_LOCAL_DRAM & HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000490 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS Counts any other requests OTHER & L3_MISS_REMOTE_HOP1_DRAM & HITM_OTHER_CORE ALL_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NONE period=2000003,umask=0x10,event=0xc8 Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS_REMOTE_HOP1_DRAM & NO_SNOOP_NEEDED ALL_PF_RFO & L3_MISS_REMOTE_DRAM & SNOOP_MISS_OR_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000491 ALL_DATA_RD & L3_MISS & SNOOP_MISS Counts demand data reads DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC000491 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONE ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.snoop_miss This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS ocr.other.l3_miss.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103FC00020 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS ocr.all_data_rd.l3_miss_local_dram.hitm_other_core This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000080 ocr.pf_l3_data_rd.l3_miss_local_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP offcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd ocr.all_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED ocr.demand_code_rd.l3_miss_remote_hop1_dram.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000400 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD ocr.all_pf_rfo.l3_miss.remote_hitm ocr.all_reads.l3_miss.hit_other_core_fwd Counts demand data reads DEMAND_DATA_RD & L3_HIT_S & NO_SNOOP_NEEDED ocr.demand_data_rd.l3_hit_s.hit_other_core_no_fwd ALL_PF_DATA_RD & SUPPLIER_NONE & HITM_OTHER_CORE ocr.all_rfo.l3_hit_f.hitm_other_core Counts all demand data writes (RFOs) DEMAND_RFO & SUPPLIER_NONE & HIT_OTHER_CORE_FWD ocr.all_reads.l3_hit_e.hit_other_core_fwd ocr.demand_rfo.l3_hit.any_snoop ocr.all_pf_data_rd.any_response ocr.all_pf_rfo.l3_hit_e.no_snoop_needed ocr.demand_data_rd.l3_hit_m.snoop_miss ALL_RFO & L3_HIT_M & HIT_OTHER_CORE_NO_FWD ocr.all_rfo.l3_hit_m.hit_other_core_fwd ocr.all_pf_rfo.l3_hit_e.any_snoop ocr.all_data_rd.l3_hit_m.hitm_other_core ocr.pf_l2_data_rd.l3_hit_m.snoop_none ocr.pf_l1d_and_sw.pmm_hit_local_pmm.snoop_not_needed ALL_READS & L3_HIT_S & HIT_OTHER_CORE_NO_FWD ocr.all_reads.l3_hit_e.no_snoop_needed Counts demand data reads DEMAND_DATA_RD & L3_HIT_F & NO_SNOOP_NEEDED ocr.other.l3_hit_e.hitm_other_core ALL_READS & ANY_RESPONSE have any response type ocr.all_data_rd.l3_hit.hit_other_core_fwd ALL_READS & L3_HIT_E & HIT_OTHER_CORE_NO_FWD ocr.pf_l3_data_rd.l3_hit.any_snoop Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT & ANY_SNOOP ocr.pf_l2_rfo.l3_hit.no_snoop_needed ALL_PF_RFO & L3_HIT_F & SNOOP_MISS ocr.demand_rfo.l3_hit_s.hit_other_core_fwd Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_M & HIT_OTHER_CORE_NO_FWD ocr.pf_l3_data_rd.pmm_hit_local_pmm.snoop_none ALL_DATA_RD & L3_HIT_F & NO_SNOOP_NEEDED ocr.all_pf_data_rd.l3_hit.hit_other_core_no_fwd Counts all demand code reads hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores ALL_PF_DATA_RD & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDED ocr.all_pf_rfo.l3_hit_m.snoop_miss ALL_PF_DATA_RD & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWD Counts any other requests OTHER & L3_HIT_S & HITM_OTHER_CORE Counts all demand code reads DEMAND_CODE_RD & SUPPLIER_NONE & NO_SNOOP_NEEDED ocr.demand_data_rd.l3_hit_s.any_snoop ocr.pf_l1d_and_sw.supplier_none.snoop_none ocr.pf_l3_data_rd.l3_hit_m.hit_other_core_no_fwd ocr.pf_l2_data_rd.l3_hit_f.hitm_other_core Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_S & ANY_SNOOP Counts demand data reads DEMAND_DATA_RD & L3_HIT_M & NO_SNOOP_NEEDED Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_E & HIT_OTHER_CORE_FWD period=2000003,umask=0x8,event=0xa2 Lines Victimized; Lines in M state. Unit: uncore_cha Peer to peer write request of 4 bytes made to IIO Part2 by a different IIO unit. Unit: uncore_iio Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part2 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus Peer to peer write request of up to a 64 byte transaction is made by IIO Part1 to an IIO target. Unit: uncore_iio fc_mask=0x07,ch_mask=0x08,umask=0x02,event=0x84 Tag Hit; Underfill Rd Hit from NearMem, Clean Line SW prefetch requests that miss L2 cache Number of cycles a demand request has waited due to L1D due to lack of L2 resources Counts return instructions retired (Precise event) Counts the number of load uops retired. This event is Precise Event capable Supports address when precise (Precise event) unc_cha_tor_inserts.ia_miss_crd_pref TOR Inserts; Code read prefetch from local IA that misses in the snoop filter TOR Inserts; RFO misses from local IA. Unit: uncore_cha Clockticks of the integrated IO (IIO) traffic controller. Unit: uncore_iio bp_l2_btb_correct Instruction Pipe Stall. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure l2_wcb_req.zero_byte_store l2_wcb_req.cl_zero Caching: L3 cache accesses. Unit: uncore_l3pmc event=0xc8 MMX instructions The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. MMX instructions Tagged IBS Ops. Number of times an op could not be tagged by IBS because of a previous tagged op that has not retired Tagged IBS Ops. Number of Ops tagged by IBS that retired Tagged IBS Ops. Number of Ops tagged by IBS df_ccm_reqa.node4.wrsizedfullzero Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsized umask=0xA7,event=0x8b umask=0x06,event=0x8b umask=0x64,event=0x8b umask=0xA3,event=0x8b umask=0xC1,event=0x8b umask=0xED,event=0x8c umask=0x4B,event=0x8c umask=0x6B,event=0x8c umask=0x0A,event=0x8c umask=0x2A,event=0x8c Data Fabric CCM Performance Monitor Event DF CCM Request Ordered anyiorequest df_ccm_reqb.node5.anyiorequest. df_ccm_reqb.node2.anywrsized df_ccm_reqb.node4.wrsizedfullnc df_ccm_reqb.node5.wrsizednc umask=0xA4,event=0x8c umask=0x63,event=0x8c df_ccm_reqc.apicaccess umask=0xEB,event=0x108 df_ioms_reqa.node2.anydramtransaction df_ioms_reqa.node2.largeread umask=0x0E,event=0x109 df_ioms_reqb.node1.piesystemmanagement umask=0xCC,event=0x109 df_ioms_reqb.node1.ioanynon-postedwrsized=64b df_ioms_reqb.node4.ioanynon-postedwrsized=64b umask=0x47,event=0x109 df_ioms_reqb.node0.ioanypostedwrsized=64b umask=0x84,event=0x109 fpu_pipe_assignment.total3 fpu_pipe_assignment.total0 umask=0x8,event=0x5 l3_request_g1.t7.s0.wrsizednc l3_request_g1.t7.s0.wrsized l3_request_g1.t5.s1.wrsized l3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x04,event=0x1 l3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x04,event=0x1 l3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x20,event=0x1 l3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x20,event=0x1 l3_request_g1.t1.s0.rdsized l3_request_g1.t5.s0.rdsized l3_request_g1.t6.s0.rdsized l3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x40,event=0x1 l3_request_g1.t2.s3.rdsized l3_request_g1.t3.s1.caching l3fillvicreq.t7.s2.vicblk l3fillvicreq.t0.s3.chgtox l3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x04,event=0x3 l3fillvicreq.t1.s3.rdblkc_s_vic l3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x04,event=0x3 l3fillvicreq.t0.s2.rdblkx_vic l3fillvicreq.t6.s1.rdblkl_vic l3fillvicreq.t4.s3.rdblkl_vic l3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x80,event=0x3 l3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x01,event=0x9 l3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x01,event=0x9 l3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x01,event=0x9 l3victimstate.t3.s2.none_nol3victimline l3victimstate.t3.s3.none_nol3victimline l3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x02,event=0x9 l3victimstate.t5.s3.o l3victimstate.t6.s0.e_fe l3victimstate.t6.s1.e_fe l3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x10,event=0x9 l3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x10,event=0x9 l3victimstate.t4.s0.m l3victimstate.t4.s0.d l3victimstate.t1.s1.d l3victimstate.t7.s2.d l3victimstate.t4.s3.d l3victimstate.t4.s0.od l3victimstate.t0.s3.od umask=0x8,event=0x45 umask=0x2,event=0x45 L1 DTLB Reload of a page of 4K size ls_tablewalker.ic_type0 Total Page Table Walks DC Type 0 umask=0x1,event=0xaf The number of instruction fetches that hit in the L1 ITLB. Instruction fetches to a 1GB page L2 prefetcher hits in L3. Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit the L3 L2 prefetcher misses in L3. All L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches fp_disp_faults.xmm_fill_fault Retired lock instructions. Bus lock when a locked operations crosses a cache boundary or is done on an uncacheable memory type. Comparable to legacy bus lock ls_ret_cl_flush DC_ONE_BIT_ECC_ERROR IC_RETURN_STACK_HIT NB_PROBE_RESULT CYCLES_STALLED_NEON_MRC PMUEXTIN1_EVT CRYPTO_SPEC EXC_UNDEF L2D_TLB_RD INST DTLB_MISS DCACHE_EVICT RETURN_MISPRED JTLB_IMISS UNCACHED_LOAD MFTC_COMPLETED FSB_GT_HALF PREDICTED_JR_31 UNCACHED_IFETCH_STALLS ALCB_FULL_DR_STALLS DCACHE_MISSES JR_NON_31_INSNS COREEXTEND_EVENTS OCP_WRITE_CACHEABLE_REQUESTS VSCR_SAT_SET BRANCHES_COMPLETED LSU_LOAD_MISS_LINE_ALIAS_VS_CSQ0 LSU_STORE_QUEUE_INDEX_ALIAS MFSPR_INSTR_COMPLETED L1_DATA_CACHE_RELOADS GPR_RENAME_BUFFER_ENTRIES_OVER_THRESHOLD EXTERNAL_PUSHES BUS_TAS_FOR_READS BRANCH_MISPREDICTED PREFETCHED_INSTRS_DISCARDED LOAD_MISS_DLFB_FULL DATA_MMU_MISS_CYCLES IAC1S_DETECTED DAC1S_DTECTED modified load nta mmx-3dnow SOFT AMD_K7 PPC_970 LONGEST_LAT_CACHE.REFERENCE GenuineIntel-6-1C GenuineIntel-6-45 GenuineIntel-6-46 GenuineIntel-6-37 GenuineIntel-6-2C CLKS Page_Walks_Utilization (cstate_pkg@c2\-residency@ / msr@tsc@) * 100 l2_rqsts.l2_pf_hit l1d_pend_miss.pending_cycles offcore_requests_outstanding.demand_data_rd offcore_requests.all_data_rd umask=0x1,period=100003,event=0xb7 Retired load uops that miss the STLB. (Precise Event - PEBS) Supports address when precise (Precise event) mem_load_uops_l3_hit_retired.xsnp_none This event counts Demand Data Read requests that access L2 cache, including rejects This event counts Read for Ownership (RFO) requests that access L2 cache idq_uops_not_delivered.cycles_le_3_uop_deliv.core umask=0x1,period=2000003,event=0x54 tx_mem.abort_capacity_write umask=0x8,period=2000003,event=0x54 tx_exec.misc5 umask=0x2,period=2000003,event=0xc8 Number of times the TSX watchdog signaled an HLE abort Cycles when L1 and L2 are locked due to UC or split lock Number of flags-merge uops being allocated. Such uops considered perf sensitive
added by GSR u-arch cpu_clk_thread_unhalted.one_thread_active umask=0x88,period=200003,event=0x88 br_inst_exec.all_conditional Mispredicted indirect branches excluding calls and returns uops_executed_port.port_1 Cycles per core when uops are exectuted in port 5 uops_executed_port.port_7_core umask=0x8,period=2000003,event=0xa2 This event counts ROB full stall cycles. This counts cycles that the pipeline backend blocked uop delivery from the front end Execution stalls while L2 cache miss demand load is outstanding lsd.cycles_4_uops umask=0x1,period=2000003,event=0xb1 br_inst_retired.conditional umask=0x1,event=0x35,filter_opc=0x181 read requests to memory controller. Derived from unc_m_cas_count.rd. Unit: uncore_imc This event counts load misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault Spec update: BDM69 This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault Spec update: BDM69 umask=0x1,period=100003,event=0x85 umask=0x40,period=100003,event=0x85 This category represents fraction of slots where the processor's Frontend undersupplies its Backend ( ((br_misp_retired.all_branches / ( br_misp_retired.all_branches + machine_clears.count )) * (( uops_issued.any - uops_retired.retire_slots + 4 * int_misc.recovery_cycles ) / (4 * cycles))) + (4 * idq_uops_not_delivered.cycles_0_uops_deliv.core / (4 * cycles)) * (12 * ( br_misp_retired.all_branches + machine_clears.count + baclears.any ) / cycles) / (4 * idq_uops_not_delivered.cycles_0_uops_deliv.core / (4 * cycles)) ) * (4 * cycles) / br_misp_retired.all_branches umask=0xd0,period=200003,event=0x24 This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required Spec update: BDM100. Supports address when precise (Precise event) offcore_response.demand_data_rd.supplier_none.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020008 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0040 offcore_response.other.supplier_none.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0090 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020240 offcore_response.all_pf_code_rd.supplier_none.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0240 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0240 offcore_response.all_data_rd.supplier_none.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020122 umask=0x30,period=2000003,cmask=1,event=0x79 umask=0x1,period=2000003,cmask=2,event=0x9c Counts randomly selected loads with latency value being above 512 Spec update: BDM100, BDM35 (Must be precise) offcore_response.demand_rfo.l3_miss.snoop_hit_no_fwd offcore_response.demand_code_rd.supplier_none.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000004 offcore_response.corewb.l3_miss_local_dram.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000008 offcore_response.pf_l2_rfo.supplier_none.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000040 offcore_response.pf_l2_code_rd.l3_miss.snoop_none offcore_response.pf_l3_data_rd.l3_miss.snoop_hit_no_fwd offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_hitm offcore_response.pf_l3_code_rd.l3_miss.snoop_none offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_hitm offcore_response.all_pf_rfo.l3_miss.snoop_none L3 Lookup any request that access cache and found line in M-state L3 Lookup write request that access cache and found line in MESI-state unc_arb_trk_requests.drd_direct cbox@event\=0x36\,umask\=0x3\,filter_opc\=0x182@ / cbox@event\=0x36\,umask\=0x3\,filter_opc\=0x182\,thresh\=1@ offcore_response.all_reads.llc_miss.remote_hit_forward Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache offcore_response.demand_rfo.llc_miss.remote_hitm l2_dbus_busy_rd.self L2 cache demand requests from this core that missed the L2 simd_inst_retired.packed_single simd_comp_inst_retired.packed_single umask=0x3,period=200000,event=0x80 This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ Store splits (Ar Retirement) misalign_mem_ref.rmw_bubble RFO bus transactions umask=0x40,period=200000,event=0x69 umask=0x40,period=200000,event=0x6e Reference cycles when core is not halted All indirect branches that are not calls umask=0x8,period=2000000,event=0x88 Self-Modifying Code detected page_walks.i_side_walks umask=0x4,period=200000,event=0x82 umask=0x1,period=100007,event=0xb7 umask=0x82,period=200003,event=0xd0 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000000022 Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts any data writes to uncacheable write combining (USWC) memory region that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cache line reads generated by hardware L1 data cache prefetcher that hit the L2 cache umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000040008 Counts the number of writeback transactions caused by L1 or L2 cache evictions that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes. This will include cycles due to an ITLB miss, ICache miss and other events This event used to measure front-end inefficiencies. I.e. when front-end of the machine is not delivering uops to the back-end and the back-end has is not stalled. This event can be used to identify if the machine is truly front-end bound. When this event occurs, it is an indication that the front-end of the machine is operating at less than its theoretical peak performance. Background: We can think of the processor pipeline as being divided into 2 broader parts: Front-end and Back-end. Front-end is responsible for fetching the instruction, decoding into uops in machine understandable format and putting them into a uop queue to be consumed by back end. The back-end then takes these uops, allocates the required resources. When all resources are ready, uops are executed. If the back-end is not ready to accept uops from the front-end, then we do not want to count these as front-end bottlenecks. However, whenever we have bottlenecks in the back-end, we will have allocation unit stalls and eventually forcing the front-end to wait until the back-end is ready to receive more uops. This event counts only when back-end is requesting more uops and front-end is not able to provide them. When 3 uops are requested and no uops are delivered, the event counts 3. When 3 are requested, and only 1 is delivered, the event counts 2. When only 2 are delivered, the event counts 1. Alternatively stated, the event will not count if 3 uops are delivered, or if the back end is stalled and not requesting any uops at all. Counts indicate missed opportunities for the front-end to deliver a uop to the back end. Some examples of conditions that cause front-end efficiencies are: ICache misses, ITLB misses, and decoder restrictions that limit the front-end bandwidth. Known Issues: Some uops require multiple allocation slots. These uops will not be charged as a front end 'not delivered' opportunity, and will be regarded as a back end problem. For example, the INC instruction has one uop that requires 2 issue slots. A stream of INC instructions will not count as UOPS_NOT_DELIVERED, even though only one instruction can be issued per clock. The low uop issue rate for a stream of INC instructions is considered to be a back end issue Counts uops which retired (Must be precise) Retired near call instructions (Precise event capable) (Must be precise) br_inst_retired.ind_call Retired conditional branch instructions that were taken (Precise event capable) (Must be precise) umask=0x7e,period=200003,event=0xc5 mem_uops_retired.dtlb_miss_loads Load uops retired that missed the DTLB (Precise event capable) Supports address when precise (Must be precise) Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts reads for ownership (RFO) requests (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) umask=0x10,period=200003,event=0x8 Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore Spec update: HSD62, HSD61 Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles Spec update: HSD62, HSD61 offcore_response.demand_rfo.l3_hit.hitm_other_core Any input SSE* FP Assist (Precise event) Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery Number of uops delivered to IDQ from any path Cycles with less than 2 uops delivered by the front end Spec update: HSD135 ( itlb_misses.walk_duration + dtlb_load_misses.walk_duration + dtlb_store_misses.walk_duration ) / cycles Number of times an RTM execution started offcore_response.all_reads.l3_miss.any_response offcore_response.pf_l3_rfo.l3_miss.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC00004 Counts all demand code reads miss in the L3 This event counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling Cycles with pending L1 data cache miss loads. Set Cmask=8 to count cycle All (macro) branch instructions retired (Must be precise) Load misses in all DTLB levels that cause page walks Load miss in all TLB levels causes a page walk that completes. (1G) Number of cache load STLB hits. No page walk umask=0x42,period=2000003,event=0xbc Retired load uops with L1 cache hits as data sources Supports address when precise. Spec update: HSD29, HSM30 (Precise event) Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache Supports address when precise. Spec update: HSD29, HSD25, HSM26, HSM30 (Precise event) Retired load uops which data sources were HitM responses from shared L3 Supports address when precise. Spec update: HSD29, HSD25, HSM26, HSM30 (Precise event) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x083FC007F7 Counts the number of micro-ops retired. Use Cmask=1 and invert to count active cycles or stalled cycles Supports address when precise (Precise event) umask=0x8,period=200003,event=0x27 Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle Offcore outstanding Demand Code Read transactions in SQ to uncore. Set Cmask=1 to count cycles offcore_response.all_code_rd.llc_hit.no_snoop_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x000105B3 umask=0x10,period=2000003,event=0x10 umask=0x1,period=2000003,event=0xab umask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400244 Count XClk pulses when this thread is unhalted and the other is halted Cycles per core when uops are dispatched to port 0 umask=0x30,period=2000003,event=0xa1 uops_dispatched_port.port_4_core Number of instructions retired. General Counter - architectural event unc_cbo_xsnp_response.miss umask=0x10,event=0x22 unc_cbo_xsnp_response.xcore_filter Unit: uncore_cbox Filter on cross-core snoops initiated by this Cbox due to processor core memory request Unit: uncore_cbox Filter on cross-core snoops initiated by this Cbox due to LLC eviction LLC lookup request that access cache and found line in E-state Unit: uncore_cbox Filter on processor core initiated cacheable write requests umask=0x80,event=0x34 unc_arb_trk_occupancy.cycles_over_half_full umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0010 Counts prefetch (that bring data to LLC only) data reads that hit in the LLC umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3fffc00244 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x67f800004 Counts all demand code reads that miss the LLC and the data forwarded from remote cache umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3fffc20040 llc_misses.itom_write (unc_q_txl0p_power_cycles / unc_q_clockticks) * 100. umask=0x4,period=2000003,event=0x51 umask=0x2,period=200003,event=0x28 offcore_requests_outstanding.demand_data_rd_c6 umask=0xe,period=2000003,event=0xa2 Occupancy counter for all LLC misses; we divide this by UNC_C_CLOCKTICKS to get average Q depth. Unit: uncore_cbox umask=0x20,period=200003,event=0x4 Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode offcore_response.any_rfo.l2_hit_near_tile_m offcore_response.pf_software.outstanding umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400100 Counts demand code reads and prefetch code reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002000002 offcore_response.uc_code_reads.l2_hit_this_tile_m Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in M state Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in E state umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008001000 Counts Demand cacheable data write requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state Counts Demand code reads and prefetch code read requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode offcore_response.any_code_rd.ddr_far Counts Demand cacheable data write requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far offcore_response.any_rfo.ddr_far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800022 offcore_response.pf_l1_data_rd.mcdram_far offcore_response.pf_l1_data_rd.ddr_far Counts L1 data HW prefetches that accounts for data responses from DRAM Local offcore_response.partial_reads.non_dram Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from MCDRAM Far or Other tile L2 hit far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200002 Counts Software Prefetches that accounts for responses from MCDRAM (local and far) Counts Demand code reads and prefetch code read requests that accounts for responses from MCDRAM (local and far) Counts UC code reads (valid only for Outstanding response type) that accounts for responses from DDR (local and far) umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181800044 Counts the number of mispredicted branch instructions retired (Precise event) This event counts the number of micro-ops (uops) retired. The processor decodes complex macro instructions into a sequence of simpler uops. Most instructions are composed of one or two uops. Some instructions are decoded into longer sequences such as repeat instructions, floating point transcendental instructions, and assists Counts the number of floating operations retired that required microcode assists This event counts the number of instructions that retire. For instructions that consist of multiple micro-ops, this event counts exactly once, as the last micro-op of the instruction retires. The event continues counting while instructions retire, including during interrupt service routines caused by hardware interrupts, faults or traps Counts the number of times the front end resteers for any branch as a result of another branch handling mechanism in the front end umask=0x2,period=2000000,event=0x40 umask=0x1,period=2000000,event=0x42 umask=0x1,period=100000,event=0x28 l2_data_rqsts.demand.mesi l2_data_rqsts.demand.s_state L2 data demand loads in S state All L2 data prefetches l2_rqsts.loads l2_transactions.any L2 demand lock RFOs in I state (misses) umask=0x2,period=40000,event=0xf Load instructions retired that HIT modified data in sibling core (Precise Event) mem_uncore_retired.uncacheable store_blocks.l1d_block mem_inst_retired.latency_above_threshold_16384 umask=0x10,period=50,event=0xb,ldlat=0x800 Memory instructions retired above 2048 clocks (Precise Event) Offcore data reads satisfied by the LLC and not found in a sibling core Offcore data reads that HITM in a remote cache Offcore code reads satisfied by a remote cache or remote DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0x38FF Offcore RFO requests satisfied by any cache or DRAM Offcore RFO requests satisfied by the LLC and not found in a sibling core umask=0x1,period=100000,event=0xb7,offcore_rsp=0x722 offcore_response.corewb.remote_cache_hit offcore_response.data_ifetch.llc_hit_no_other_core Offcore data reads, RFO's and prefetches satisfied by the LLC and HITM in a sibling core umask=0x1,period=100000,event=0xb7,offcore_rsp=0x403 All offcore other requests Offcore other requests satisfied by the LLC and HIT in a sibling core Offcore other requests that HITM in a remote cache Offcore prefetch data requests satisfied by the LLC and not found in a sibling core umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1830 offcore_response.pf_data.remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x410 offcore_response.pf_ifetch.llc_hit_no_other_core Offcore prefetch code reads satisfied by a remote cache umask=0x2,period=20000,event=0xf7 SIMD integer 64 bit logical operations Offcore code reads satisfied by a remote DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0xF833 offcore_response.demand_data.remote_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4002 Offcore other requests satisfied by a remote DRAM offcore_response.pf_data.remote_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2070 umask=0x4,period=2000000,event=0x80 umask=0x1,period=2000000,event=0x80 Large ITLB hit False dependencies due to partial address aliasing umask=0x8,period=2000000,event=0xd2 lsd.active umask=0x10,period=2000000,event=0xa2 SIMD Packed-Single Uops retired (Precise Event) umask=0x2,period=200000,event=0x49 Counts the RFO (Read-for-Ownership) requests that miss L2 cache All retired load instructions. (Precise Event) Supports address when precise Retired load instructions with L1 cache hits as data sources Supports address when precise (Precise event) Retired load instructions which data sources were hits in L3 without snoops required Supports address when precise (Precise event) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200108000 offcore_response.other.l3_hit_m.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100048000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080048000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040028000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04001C0002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020002 offcore_response.demand_data_rd.l4_hit_local_l4.snoop_hitm offcore_response.demand_data_rd.l3_hit.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200080001 umask=0x1,period=200003,event=0x83 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall. Precise Event (Precise event) Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency (Must be precise) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C400004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C400004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000080004 offcore_response.demand_rfo.l3_miss.snoop_non_dram umask=0x2,period=2000003,event=0x32 umask=0x1,period=2000003,cmask=1,event=0x14 Counts when there is a transition from ring 1, 2 or 3 to ring 0 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1 Counts resource-related stall cycles Conditional branch instructions retired Spec update: SKL091 (Precise event) 64 * offcore_requests.all_requests / 1000000000 / duration_time Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions. ) Page walk completed due to a demand data load to a 1G page Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake dtlb_load_misses.walk_active umask=0x10,period=2000003,event=0x49 Counts 1 per cycle for each PMH that is busy with a EPT (Extended Page Table) walk for any request type This event counts the number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the IDI link. The XQ may reject transactions from the L2Q (non-cacheable requests), BBS (L2 misses) and WOB (L2 write-back victims) This event counts the number of store uops reissued from Rehabq umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680000044 offcore_response.pf_l2_data_rd.l2_miss.snoop_miss umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1680000002 Counts the number of JCC branch instructions retired (Precise event) This event counts every cycle when a data (D) page walk or instruction (I) page walk is in progress. Since a pagewalk implies a TLB miss, the approximate cost of a TLB miss can be determined from this event Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. (Precise Event - PEBS) (Precise event) offcore_response.all_pf_rfo.llc_hit.no_snoop_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0122 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0004 offcore_response.all_pf_rfo.llc_miss.dram offcore_response.all_rfo.llc_miss.dram REQUEST = DATA_IN_SOCKET and RESPONSE = LLC_MISS_LOCAL and SNOOP = ANY_LLC_HIT offcore_response.pf_data_rd.llc_miss_local.dram This event counts the number of cycles spent executing performance-sensitive flags-merging uops. For example, shift CL (merge_arith_flags). For more details, See the Intel® 64 and IA-32 Architectures Optimization Reference Manual Direct and indirect mispredicted near call instructions retired. (Precise Event - PEBS) (Precise event) sq_misc.lru_hints REQUEST = ANY IFETCH and RESPONSE = LOCAL_CACHE REQUEST = DATA_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_NO_OTHER_CORE REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_CACHE_DRAM REQUEST = DEMAND_DATA_RD and RESPONSE = REMOTE_CACHE_HITM REQUEST = DEMAND_IFETCH and RESPONSE = ANY_CACHE_DRAM REQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_CACHE offcore_response.pf_rfo.local_dram_and_remote_cache_hit REQUEST = CORE_WB and RESPONSE = ANY_DRAM AND REMOTE_FWD REQUEST = CORE_WB and RESPONSE = ANY_LLC_MISS umask=0x1,period=100000,event=0xb7,offcore_rsp=0xf850 REQUEST = PF_DATA and RESPONSE = REMOTE_DRAM offcore_response.pf_rfo.any_dram_and_remote_fwd umask=0x2,period=200000,event=0x3 snoopq_requests_outstanding.invalidate_not_empty Cycles snoop invalidate requests queued itlb_misses.large_walk_completed umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2702 offcore_response.pf_l2_rfo.l3_hit.hitm_other_core offcore_response.pf_l1d_and_sw.l3_hit.no_snoop_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0490 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBC000001 offcore_response.pf_l2_data_rd.l3_miss.snoop_miss_or_no_fwd offcore_response.pf_l1d_and_sw.l3_miss_local_dram.snoop_miss_or_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x103FC00120 offcore_response.all_data_rd.l3_miss.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x083FC00122 Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes (( 1 * ( fp_arith_inst_retired.scalar_single + fp_arith_inst_retired.scalar_double ) + 2 * fp_arith_inst_retired.128b_packed_double + 4 * ( fp_arith_inst_retired.128b_packed_single + fp_arith_inst_retired.256b_packed_double ) + 8 * ( fp_arith_inst_retired.256b_packed_single + fp_arith_inst_retired.512b_packed_double ) + 16 * fp_arith_inst_retired.512b_packed_single )) / (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )) All DRAM Read CAS Commands issued (does not include underfills) . Unit: uncore_imc Counts the number of entries in the Write Pending Queue (WPQ) at each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule writes out to the memory controller and to track the requests umask=0x0F,event=0x2 Core Cross Snoops Issued; Multiple Core Requests. Unit: uncore_cha unc_cha_dir_lookup.snp unc_cha_imc_reads_count.normal Counts every write request of up to a 64 byte transaction of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus fc_mask=0x07,ch_mask=0x08,umask=0x01,event=0x84 event=0x24 event=0x25 unc_m2m_direct2upi_taken unc_m2m_direct2upi_txn_override Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from I (Invalid) to A (SnoopAll) Counts when the M2M (Mesh to Memory) issues reads to the iMC (Memory Controller) Cycles Intel UPI is in L1 power mode (shutdown). Unit: uncore_upi ll Counts null FLITs (80 bit FLow control unITs) received from any of the 3 Intel Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unit This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP offcore_response.demand_rfo.l3_hit_f.snoop_none This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_MISS This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100048000 offcore_response.pf_l1d_and_sw.l3_hit_f.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200400 Retired load instructions with remote Intel® Optane™ DC persistent memory as the data source where the data request missed all caches. Precise event Supports address when precise (Precise event) offcore_response.all_reads.l3_hit_e.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10001007F7 offcore_response.pf_l2_rfo.l3_hit_f.snoop_none period=2000003,umask=0x1,event=0xb2 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE period=50021,umask=0x10,event=0xd1 offcore_response.pf_l3_rfo.l3_hit_f.no_snoop_needed offcore_response.demand_data_rd.l3_hit_f.no_snoop_needed offcore_response.pf_l2_data_rd.supplier_none.hitm_other_core This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD This event is deprecated. Refer to new event OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE offcore_response.pf_l1d_and_sw.l3_hit_m.snoop_none offcore_response.pf_l1d_and_sw.l3_hit_m.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080088000 offcore_response.pf_l3_data_rd.l3_hit_s.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200080 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040490 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200122 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400200400 offcore_response.other.l3_hit_f.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0001 offcore_response.all_pf_data_rd.l3_hit_e.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0122 Retired store instructions that miss the STLB Supports address when precise (Precise event) This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED offcore_response.pf_l2_rfo.l3_hit_m.snoop_miss offcore_response.demand_data_rd.supplier_none.hit_other_core_fwd offcore_response.pf_l3_rfo.l3_hit_m.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100020 Retired load instructions with local Intel® Optane™ DC persistent memory as the data source where the data request missed all caches. Precise event Supports address when precise (Precise event) period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040010 offcore_response.all_pf_rfo.l3_hit_f.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100020 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE offcore_response.all_reads.l3_hit_f.no_snoop_needed offcore_response.pf_l1d_and_sw.l3_hit_f.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04001007F7 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200001 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100001 offcore_response.all_reads.l3_hit_m.snoop_none offcore_response.demand_data_rd.l3_hit_e.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element cmask=3,period=2000003,umask=0x1,event=0x9c period=100003,umask=0x1,event=0xb7,offcore_rsp=0x06040007F7 ocr.all_data_rd.l3_miss.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01040007F7 Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS_LOCAL_DRAM & ANY_SNOOP ocr.demand_rfo.l3_miss_remote_hop1_dram.snoop_miss offcore_response.all_rfo.l3_miss_local_dram.no_snoop_needed This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083FC00400 Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS & REMOTE_HIT_FORWARD Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS & HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000120 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000122 ocr.pf_l2_data_rd.l3_miss.snoop_miss ocr.all_data_rd.l3_miss.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F90000120 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.ANY_SNOOP offcore_response.all_pf_data_rd.l3_miss_local_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_FWD Counts all demand data writes (RFOs) DEMAND_RFO & L3_MISS_LOCAL_DRAM & NO_SNOOP_NEEDED ALL_READS & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_NO_FWD cmask=6,period=2000003,umask=0x6,event=0xa3 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C008000 offcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.SNOOP_MISS This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM offcore_response.demand_data_rd.l3_miss_local_dram.no_snoop_needed This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD period=2000003,umask=0x20,event=0x54 offcore_response.all_data_rd.l3_miss_remote_hop1_dram.snoop_none Counts any other requests OTHER & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_NO_FWD Counts all demand code reads DEMAND_CODE_RD & L3_MISS_REMOTE_HOP1_DRAM & NO_SNOOP_NEEDED Counts demand data reads DEMAND_DATA_RD & L3_MISS_REMOTE_DRAM & SNOOP_MISS_OR_NO_FWD Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS_LOCAL_DRAM & NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000120 offcore_response.all_pf_data_rd.l3_miss.hitm_other_core offcore_response.all_rfo.l3_miss_local_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD period=100003,umask=0x10,event=0xb0 ocr.pf_l1d_and_sw.l3_miss.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP offcore_response.all_pf_rfo.l3_miss_local_dram.no_snoop_needed This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE ocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd ocr.demand_code_rd.l3_hit_m.any_snoop ALL_PF_RFO & L3_HIT_E & HIT_OTHER_CORE_FWD ocr.demand_data_rd.l3_hit_m.hit_other_core_fwd Counts demand data reads DEMAND_DATA_RD & L3_HIT & SNOOP_NONE ALL_RFO & L3_HIT_M & ANY_SNOOP ocr.all_data_rd.l3_hit_f.hit_other_core_no_fwd ALL_DATA_RD & L3_HIT_F & HIT_OTHER_CORE_NO_FWD ocr.other.l3_hit_e.hit_other_core_no_fwd ALL_PF_RFO & SUPPLIER_NONE & SNOOP_MISS Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_S & HIT_OTHER_CORE_NO_FWD ocr.demand_rfo.supplier_none.hitm_other_core ocr.pf_l2_rfo.pmm_hit_local_pmm.snoop_none ocr.pf_l1d_and_sw.l3_hit_m.any_snoop Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & SUPPLIER_NONE & ANY_SNOOP Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_S & HITM_OTHER_CORE ocr.all_pf_rfo.l3_hit_e.snoop_miss ocr.all_rfo.l3_hit_s.snoop_none ocr.pf_l2_rfo.l3_hit_e.snoop_none Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_F & HIT_OTHER_CORE_FWD ocr.all_pf_data_rd.supplier_none.any_snoop ocr.all_pf_data_rd.l3_hit_s.any_snoop ALL_PF_DATA_RD & L3_HIT_S & ANY_SNOOP Counts any other requests OTHER & L3_HIT_E & HITM_OTHER_CORE Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_E & HITM_OTHER_CORE ALL_READS & L3_HIT_M & ANY_SNOOP ocr.all_data_rd.l3_hit_m.no_snoop_needed ocr.all_pf_data_rd.l3_hit_f.hit_other_core_no_fwd ocr.all_data_rd.l3_hit_m.snoop_miss ocr.pf_l3_data_rd.l3_hit_m.snoop_none Counts demand data reads DEMAND_DATA_RD & SUPPLIER_NONE & HIT_OTHER_CORE_FWD ocr.pf_l3_data_rd.l3_hit_m.snoop_miss ocr.all_reads.pmm_hit_local_pmm.snoop_not_needed ocr.pf_l3_data_rd.supplier_none.no_snoop_needed ALL_DATA_RD & SUPPLIER_NONE & ANY_SNOOP ocr.all_data_rd.l3_hit_e.hit_other_core_fwd ocr.all_rfo.l3_hit_e.snoop_miss ocr.pf_l3_data_rd.supplier_none.snoop_none ocr.pf_l3_data_rd.l3_hit_e.no_snoop_needed ALL_DATA_RD & L3_HIT_M & HIT_OTHER_CORE_NO_FWD ocr.all_pf_data_rd.l3_hit_e.hit_other_core_no_fwd Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_M & NO_SNOOP_NEEDED ALL_DATA_RD & L3_HIT & SNOOP_MISS ocr.pf_l1d_and_sw.l3_hit_s.hitm_other_core period=2000003,umask=0x1,event=0xd period=2000003,umask=0x2,event=0xc2 Write requests allocated in the PMM Write Pending Queue for Intel Optane DC persistent memory. Unit: uncore_imc unc_m_pmm_wpq_inserts Intel Optane DC persistent memory bandwidth read (MB/sec). Derived from unc_m_pmm_rpq_inserts. Unit: uncore_imc Intel Optane DC persistent memory read latency (ns). Derived from unc_m_pmm_rpq_occupancy.all. Unit: uncore_imc Write Pending Queue Occupancy of all write requests for Intel Optane DC persistent memory. Unit: uncore_imc umask=0x01,event=0x37 Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part3. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus Counts every peer to peer write request of 4 bytes of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part0 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus fc_mask=0x07,ch_mask=0x08,umask=0x02,event=0xc1 fc_mask=0x07,ch_mask=0x02,umask=0x08,event=0x84 Shows legal flit time (hides impact of L0p and L0c).; Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting. period=100007,umask=0x20,event=0xbd period=2000003,umask=0x4,event=0x8 Number of L1D misses that are outstanding Counts all retired store instructions. This event account for SW prefetch instructions and PREFETCHW instruction for stores Supports address when precise (Precise event) umask=0x4,period=2000003,cmask=5,event=0x79 uops_dispatched.port_4_9 Number of uops executed on port 5 umask=0x11,period=400009,event=0xc4 Counts far branch instructions retired (Precise event) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x000000000000010002 period=200003,event=0xc5 TOR Inserts; Code read from local IA that misses in the snoop filter TOR Inserts; Read for ownership from local IA that misses in the snoop filter TOR Inserts; RFO pref misses from local IA. Unit: uncore_cha TOR Inserts; Data read from local IA that misses in the snoop filter unc_iio_data_req_of_cpu.mem_read.part5 fc_mask=0x07,ch_mask=0x40,umask=0x04,event=0x83 unc_iio_data_req_of_cpu.mem_read.part7 ic_fw32 umask=0x1,event=0x62 umask=0x00,event=0x90 event=0xc6 ex_ret_mmx_fp_instr.sse_instr df_ccm_reqa.node3.anydram df_ccm_reqa.node0.wrsized umask=0x43,event=0x8b Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdvlks df_ccm_reqb.node6.chgtox df_ccm_reqb.node5.vicblkfullzero df_ccm_reqb.node3.anywrsized df_ccm_reqb.node6.wrsizedfullnc umask=0x44,event=0x8c Data Fabric CCM Performance Monitor Event DF CCM Request Type C (PIE Requests)APIC ucode access Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) flush umask=0x69,event=0x108 df_ioms_reqa.node2.anywrsized=64b umask=0x68,event=0x109 df_ioms_reqb.node5.ioanynon-postedwrsized<32b df_ioms_reqb.node3.ioanypostedwrsized=64b umask=0x25,event=0x109 df_ioms_reqb.node4.ioanypostedwrsized<32 df_ioms_reqb.node7.ioanypostedwrsized<32 umask=0x21,event=0x109 umask=0x41,event=0x109 fpu_pipe_assignment.dual3 umask=0x10,event=0 All Ops fp_ret_sse_avx_ops.all Single precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS Single-precision divide/square root FLOPS l3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x02,event=0x1 l3_request_g1.t2.s2.wrsized l3_request_g1.t5.s3.wrsized l3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x40,event=0x1 l3_request_g1.t4.s0.caching l3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x80,event=0x1 l3_request_g1.t6.s2.caching l3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x01,event=0x3 l3fillvicreq.t3.s2.vicblk l3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x02,event=0x3 l3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x02,event=0x3 l3fillvicreq.t1.s0.rdblkc_s_vic l3fillvicreq.t2.s0.rdblkc_s_vic l3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x04,event=0x3 l3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x20,event=0x3 l3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x20,event=0x3 l3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x40,event=0x3 l3fillvicreq.t6.s0.rdblkl_vic l3fillvicreq.t3.s1.rdblkl l3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x80,event=0x3 l3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x02,event=0x9 l3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x02,event=0x9 l3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x08,event=0x9 l3victimstate.t1.s3.o l3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x10,event=0x9 l3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x10,event=0x9 l3victimstate.t0.s0.m l3victimstate.t2.s2.m l3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x20,event=0x9 l3victimstate.t4.s2.m l3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x20,event=0x9 l3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x80,event=0x9 l3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x80,event=0x9 umask=0x10,event=0x45 ls_pref_instr_disp.load_prefetch_w ls_inef_sw_pref.data_pipe_sw_pf_dc_hit Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 3_0 Tokens unavailable L2 prefetch hit in L2 umask=0x1,event=0x85 Add/subtract FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15 Number of retired CLFLUSH instructions ls_rdtsc ls_pref_instr_disp.prefetch DC_REFILL_FROM_SYSTEM L1_ICACHE_REFILL CPU_CYCLES L2_CACHE_NEON_HIT L2D_CACHE_WB_CLEAN UNALIGNED_ST_SPEC PC_WRITE_SPEC TAGCACHEMASTER_READ_RSP ICACHE_HIT EXCEPTIONS IFU_CYCLES_STALLED SYSTEM_EVENT_2 WBB_25_50_FULL SYNC VEC_LOAD_INSTR_COMPLETED L2_STORE_HITS FPU_LONG_INSTR_COMPLETION_STALL CQ_REDIRECTS TAKEN_BRANCHES_FINISHED BTB_HITS_PSEUDO_HITS CASTOUTS_RELEASED tsc probe-hit-dirty-with-memory-cancel WRITE INTEL_PIV INTEL_IVYBRIDGE_XEON ARMV7_CORTEX_A5 STANDALONE metric_name: %s
unrecognized kvpair: %s:%s
{"type": "procexec" %s, "pmcid": "0x%08x", "pid": "%d" "tid": "%d", "value": "0x%016jx"}
v15 Unknown_Branches Average Frequency Utilization relative nominal frequency All L2 requests This event counts core-originated cacheable demand requests that miss the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU This is a precise version (that is, uses PEBS) of the event that counts store uops true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault Supports address when precise (Precise event) mem_load_uops_retired.l3_hit umask=0x8,period=100003,event=0xd2 umask=0x5,period=100003,event=0xf2 umask=0x2,period=2000003,event=0xc7 umask=0x8,period=2000003,event=0xc7 fp_assist.any umask=0x24,cmask=4,period=2000003,event=0x79 umask=0x24,cmask=1,period=2000003,event=0x79 idq.ms_uops Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy misalign_mem_ref.loads Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts) umask=0x1,period=100003,event=0x7 Cycles while L2 cache miss demand load is outstanding Cycles at least 3 micro-op is executed from any thread on physical core umask=0x40,period=100007,event=0xc4 umask=0x3,event=0x35,filter_opc=0x18f,filter_nc=1 llc_references.pcie_write write requests to remote home agent. Unit: uncore_ha Shared line response from remote cache. Unit: uncore_ha dtlb_load_misses.walk_completed_1g dtlb_load_misses.stlb_hit_4k dtlb_store_misses.walk_completed_2m_4m umask=0x10,period=100003,event=0x49 This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-ops (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-ops (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPU Average data fill bandwidth to the L2 cache [GB / sec] 1000 * mem_load_uops_retired.l1_miss / inst_retired.any Retired load uops which data sources were hits in L3 without snoops required. (Precise Event - PEBS) Spec update: BDM100. Supports address when precise (Precise event) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020008 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020080 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020100 offcore_response.pf_l3_code_rd.any_response offcore_response.other.supplier_none.snoop_hit_no_fwd offcore_response.other.l3_hit.snoop_none offcore_response.all_pf_data_rd.supplier_none.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020120 offcore_response.all_pf_rfo.l3_hit.snoop_hitm offcore_response.all_pf_rfo.l3_hit.any_snoop offcore_response.all_data_rd.supplier_none.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020091 offcore_response.all_rfo.l3_hit.snoop_not_needed Counts randomly selected loads with latency value being above 256 Spec update: BDM100, BDM35 (Must be precise) offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000020 offcore_response.pf_l2_code_rd.l3_hit.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000040 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000080 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000100 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000200 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000028000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204008000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404008000 offcore_response.all_data_rd.l3_miss_local_dram.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000091 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020122 umask=0xc,period=2000003,cmask=12,event=0xa3 Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready Supports address when precise (Precise event) Retired load uop whose Data Source was: local DRAM either Snoop not needed or Snoop Miss (RspI) Supports address when precise. Spec update: BDE70, BDM100 (Precise event) Counts all requests hit in the L3 offcore_response.all_data_rd.llc_hit.hitm_other_core umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC08FFF Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram event=0x14 unc_m_clockticks umask=0x50,period=200000,event=0x27 l2_ifetch.self.i_state L2 store requests l2_reject_busq.self.any.m_state umask=0x78,period=200000,event=0x30 L1 Data reads and writes umask=0x8,period=200000,event=0x40 l1d_cache.evict SIMD packed micro-ops retired misalign_mem_ref.bubble prefetch.hw_prefetch umask=0x10,period=2000000,event=0x7 umask=0x0,period=200000,event=0x62 bus_trans_brd.all_agents umask=0xe0,period=200000,event=0x6f umask=0x1,period=200000,event=0x77 umask=0x2,period=200000,event=0x77 umask=0x0,period=200000,event=0xc8 cycles_div_busy umask=0x2,period=200000,event=0x89 umask=0x10,period=2000000,event=0xc2 umask=0x1,period=2000000,event=0xc4 umask=0x1,period=2000000,event=0xe6 Micro-op reissues on a store-load collision (At Retirement) data_tlb_misses.dtlb_miss_ld umask=0x1,period=2000000,event=0xc ITLB misses (Must be precise) Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required Counts data reads (demand & prefetch) that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts any data writes to uncacheable write combining (USWC) memory region that hit the L2 cache Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required offcore_response.sw_prefetch.l2_miss.hitm_other_core offcore_response.sw_prefetch.l2_hit Counts the number of demand write requests (RFO) generated by a write to partial data cache line, including the writes to uncacheable (UC) and write through (WT), and write protected (WP) types of memory that miss the L2 cache Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required Counts the number of writeback transactions caused by L1 or L2 cache evictions that hit the L2 cache Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required hw_interrupts.masked umask=0x8,period=200003,event=0x3 Machine clears due to FP assists umask=0xf7,period=200003,event=0xc4 Retired mispredicted near return instructions (Precise event capable) (Must be precise) br_misp_retired.taken_jcc Counts the number of times a BACLEAR is signaled for any reason, including, but not limited to indirect branch/call, Jcc (Jump on Conditional Code/Jump if Condition is Met) branch, unconditional branch/call, and returns Duration of D-side page-walks in cycles Counts demand cacheable data reads of full cache lines have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cache lines requests by software prefetch instructions true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts requests to the uncore subsystem miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data reads generated by L1 or L2 prefetchers true miss for the L2 cache with a snoop miss in the other processor module Counts data reads (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received Counts data reads (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts all L2 code requests Demand code read requests sent to uncore This event counts load uops retired which had memory addresses spilt across 2 cache lines. A line split is across 64B cache-lines which may include a page split (4K). This is a precise event Spec update: HSD29, HSM30. Supports address when precise (Precise event) offcore_response.pf_l3_code_rd.l3_hit.any_response offcore_response.pf_l2_rfo.l3_hit.any_response avx_insts.all Counts any FP_ASSIST umask was incrementing (Precise event) Randomly selected loads with latency value being above 64 Spec update: HSD76, HSD25, HSM26 (Must be precise) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100400122 offcore_response.pf_l3_data_rd.l3_miss.any_response loads blocked by overlapping with store buffer that cannot be forwarded Number of SIMD move elimination candidate uops that were eliminated Cycles which a uop is dispatched on port 2 in this thread Cycles with no micro-ops executed from any thread on physical core Spec update: HSD30, HSM31 L3 Lookup external snoop request that access cache and found line in I-state Completed page walks in any TLB of any page size due to demand load misses Completed page walks due to store misses in one or more TLB levels of 4K page structure offcore_response.demand_code_rd.llc_hit.hitm_other_core Number of transitions from AVX-256 to legacy SSE when penalty applicable Spec update: HSD56, HSM57 inv=1,umask=0x1,any=1,cmask=1,period=2000003,event=0xe umask=0x3,period=200003,event=0x24 umask=0x2,period=2000003,cmask=1,event=0x60 Dirty L2 cache lines evicted by L2 prefetch umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10400 Counts 256-bit packed double-precision floating-point instructions uops_dispatched_port.port_0_core uops_dispatched_port.port_1_core uops_dispatched_port.port_3_core umask=0x01,event=0x34 Unit: uncore_cbox LLC lookup request that access cache and found line in E-state unc_cbo_cache_lookup.s umask=0x01,cmask=10,event=0x80 offcore_response.all_reads.llc_hit.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c03f7 offcore_response.pf_llc_data_rd.llc_hit.hitm_other_core Counts all data/code/rfo reads (demand & prefetch) that hit the LLC umask=0x1,period=100003,event=0xb7,offcore_rsp=0x107fc00004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3fffc20001 LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derived from unc_c_tor_inserts.miss_opcode.demand. Unit: uncore_cbox umask=0x1,umask=0x3,event=0x1 unc_p_freq_band3_cycles freq_band3_cycles % Data from remote DRAM either Snoop not needed or Snoop Miss (RspI) l1d.allocated_in_m Cycles when dispatched loads are cancelled due to L1D bank conflicts with other load ports Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS) (Must be precise) Each cycle there was a MLC-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0 and 2 Resource stalls due to memory buffers or Reservation Station (RS) being fully utilized This event counts the number of cycles spent executing performance-sensitive flags-merging uops. For example, shift CL (merge_arith_flags). For more details, See the Intel? 64 and IA-32 Architectures Optimization Reference Manual Counts the number of MEC requests that were not accepted into the L2Q because of any L2 queue reject condition. There is no concept of at-ret here. It might include requests due to instructions in the speculative path Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state Counts L1 data HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800402000 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080400 offcore_response.uc_code_reads.l2_hit_near_tile_e_f Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode offcore_response.any_rfo.l2_hit_this_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000080 Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses which hit its own tile's L2 with data in E state umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000400 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x00040032f7 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008000100 Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in F state offcore_response.bus_locks.l2_hit_near_tile umask=0x1,period=100007,event=0xb7,offcore_rsp=0x18001832f7 Counts any Read request that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080803091 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101008000 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100400200 offcore_response.partial_writes.mcdram_far offcore_response.pf_l2_code_rd.mcdram_near Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Far or Other tile L2 hit far Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Local umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181808000 Fixed Counter: Counts the number of instructions retired Counts the number of occurences a retired load gets blocked because its address overlaps with a store whose data is not ready umask=0xfd,period=200003,event=0xc5 umask=0xbf,period=200003,event=0xc5 umask=0x8,period=2000000,event=0x40 l1d_cache_ld.s_state All L2 data requests umask=0x20,period=200000,event=0xf0 All L2 demand store RFOs umask=0x2,period=200000,event=0xcb Super Queue lock splits across a cache line offcore_response.any_data.llc_hit_no_other_core umask=0x1,period=100000,event=0xb7,offcore_rsp=0x111 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x80FF offcore_response.corewb.io_csr_mmio Offcore code or data read requests satisfied by the LLC and HIT in a sibling core offcore_response.data_in.any_cache_dram offcore_response.data_in.llc_hit_other_core_hit offcore_response.data_in.local_cache offcore_response.demand_data.io_csr_mmio offcore_response.demand_ifetch.local_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4702 Offcore other requests satisfied by the LLC umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3880 offcore_response.other.remote_cache_hitm offcore_response.pf_data.llc_hit_other_core_hitm umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4730 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x110 offcore_response.pf_data_rd.remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1020 umask=0x1,period=20000,event=0xf7 X87 Floating point assists for invalid output value (Precise Event) fp_comp_ops_exe.sse_double_precision fp_mmx_trans.to_fp offcore_response.data_ifetch.any_llc_miss umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4077 offcore_response.demand_data_rd.local_dram offcore_response.pf_ifetch.local_dram es_reg_renames arith.mul Taken branches executed umask=0x1,period=20000,event=0x89 SIMD Scalar-Double Uops retired (Precise Event) Stack pointer instructions decoded uops_decoded.esp_sync umask=0x10,any=1,period=2000000,event=0xb1 DTLB miss page walks Retired loads that miss the DTLB (Precise Event) Counts the RFO (Read-for-Ownership) requests that hit L2 cache Retired load instructions with L2 cache hits as data sources Supports address when precise (Precise event) Retired load instructions missed L3 cache as data sources Supports address when precise (Precise event) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100088000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000048000 offcore_response.demand_code_rd.l3_hit_s.snoop_hitm offcore_response.demand_code_rd.l3_hit_e.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040080002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040040002 Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. Counting includes uops that may 'bypass' the IDQ. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB) Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency (Must be precise) offcore_response.other.l3_miss.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x103C408000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000408000 offcore_response.demand_rfo.l3_miss_local_dram.snoop_non_dram offcore_response.demand_rfo.l3_miss_local_dram.snoop_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC4000001 umask=0x8,period=2000003,event=0x32 Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end Cycles where the Store Buffer was full and no outstanding load idq.dsb_uops / (idq.dsb_uops + idq.mite_uops + idq.ms_uops) L3_Cache_Access_BW Page walk completed due to a demand data store to a 1G page Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store itlb_misses.walk_active offcore_response.pf_l2_code_rd.l2_miss.any Counts the number of near indirect JMP and near indirect CALL branch instructions retired (Precise event) TAKEN_JCC counts the number of mispredicted taken conditional branch (JCC) instructions retired. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa. When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event) RETURN counts the number of mispredicted near RET branch instructions retired. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa. When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event) Counts the number of cycles the Alloc pipeline is stalled when any one of the RSs (IEC, FPC and MEC) is full. This event is a superset of all the individual RS stall event counts umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0244 offcore_response.demand_code_rd.llc_hit.snoop_miss offcore_response.pf_llc_rfo.llc_hit.no_snoop_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0100 Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops sent to sibling cores return clean response Counts all prefetch code reads that miss the LLC and the data returned from dram offcore_response.demand_rfo.llc_miss.dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400100 offcore_requests_outstanding.any.read Outstanding offcore demand data reads Super Queue LRU hints sent to LLC REQUEST = ANY RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = CORE_WB and RESPONSE = LLC_HIT_NO_OTHER_CORE umask=0x1,period=100000,event=0xb7,offcore_rsp=0x150 REQUEST = PF_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = PF_RFO and RESPONSE = ANY_LOCATION REQUEST = PF_IFETCH and RESPONSE = ANY_LOCATION REQUEST = PF_IFETCH and RESPONSE = LOCAL_CACHE REQUEST = CORE_WB and RESPONSE = OTHER_LOCAL_DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3010 umask=0x4,period=200000,event=0x8 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010491 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063B800020 offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0604000080 unc_iio_data_req_of_cpu.mem_read.part0 + unc_iio_data_req_of_cpu.mem_read.part1 + unc_iio_data_req_of_cpu.mem_read.part2 + unc_iio_data_req_of_cpu.mem_read.part3 PCI Express bandwidth writing at IIO, part 2. Unit: uncore_iio unc_iio_data_req_of_cpu.mem_read.part1 unc_iio_data_req_of_cpu.mem_read.part2 RspCnflct* Snoop Responses Received. Unit: uncore_cha fc_mask=0x07,ch_mask=0x01,umask=0x04,event=0xc0 Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus Read request for up to a 64 byte transaction is made by the CPU to IIO Part2. Unit: uncore_iio fc_mask=0x07,ch_mask=0x08,umask=0x04,event=0xc1 Read request for up to a 64 byte transaction is made by IIO Part0 to Memory. Unit: uncore_iio Cycles when direct to Intel UPI was disabled. Unit: uncore_m2m umask=0x4,event=0x2d unc_upi_rxl_bypassed.slot2 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE offcore_response.demand_data_rd.pmm_hit_local_pmm.any_snoop This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP This event is deprecated. Refer to new event OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400100122 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200122 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04003C0010 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080400 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080010 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010490 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100120 offcore_response.all_data_rd.l3_hit_s.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100491 This event is deprecated. Refer to new event OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010004 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE offcore_response.all_reads.l3_hit_m.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040400 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200490 This event is deprecated. Refer to new event OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010010 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100002 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD offcore_response.all_pf_data_rd.l3_hit_m.any_snoop offcore_response.demand_data_rd.l3_hit_e.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F800207F7 offcore_response.demand_code_rd.l3_hit_f.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.SNOOP_MISS offcore_response.all_rfo.l3_hit_f.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0010 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE offcore_response.all_rfo.l3_hit_m.hit_other_core_fwd Retired load instructions with locked access Supports address when precise (Precise event) All retired store instructions Supports address when precise (Precise event) This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED offcore_response.all_reads.l3_hit_e.no_snoop_needed This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200100010 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08002007F7 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040020 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200040490 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100400 period=100007,umask=0x40,event=0xd1 offcore_response.all_pf_rfo.l3_hit_f.hit_other_core_fwd offcore_response.all_pf_data_rd.l3_hit_e.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200490 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080491 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C8000 period=100007,umask=0x1,event=0xc6,frontend=0x200206 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS ocr.pf_l1d_and_sw.l3_miss_local_dram.hit_other_core_no_fwd Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS & HIT_OTHER_CORE_NO_FWD Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS & SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000001 offcore_response.demand_rfo.l3_miss.hit_other_core_fwd ocr.all_reads.l3_miss_local_dram.hit_other_core_no_fwd ocr.all_data_rd.l3_miss_local_dram.snoop_miss ocr.pf_l2_data_rd.l3_miss.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C0007F7 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0404000004 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000490 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004008000 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000400 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000120 ocr.other.l3_miss_remote_hop1_dram.snoop_none ocr.all_pf_rfo.l3_miss_local_dram.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000490 ocr.all_reads.l3_miss_remote_hop1_dram.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00900007F7 offcore_response.other.l3_miss_local_dram.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0084000490 This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0604008000 ocr.demand_data_rd.l3_miss.snoop_none Counts demand data reads DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE ocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed offcore_response.pf_l2_rfo.l3_miss.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000010 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000400 ocr.other.l3_miss_local_dram.snoop_miss offcore_response.demand_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed ocr.demand_code_rd.l3_miss_remote_hop1_dram.any_snoop ALL_DATA_RD & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_NO_FWD ocr.all_reads.l3_miss.snoop_none offcore_response.all_reads.l3_miss.any_snoop This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD offcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.SNOOP_NONE offcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE offcore_response.demand_rfo.l3_miss_remote_hop1_dram.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000001 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD offcore_response.demand_rfo.l3_miss.hit_other_core_no_fwd ocr.all_data_rd.l3_miss.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C000120 ALL_DATA_RD & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_FWD offcore_response.other.l3_miss_remote_hop1_dram.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000491 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD ocr.all_pf_data_rd.l3_hit_m.hit_other_core_no_fwd Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_E & ANY_SNOOP Counts any other requests OTHER & L3_HIT_M & HIT_OTHER_CORE_FWD ocr.all_data_rd.supplier_none.hit_other_core_no_fwd ocr.pf_l1d_and_sw.l3_hit_e.no_snoop_needed ALL_PF_DATA_RD & SUPPLIER_NONE & SNOOP_MISS ALL_PF_RFO & L3_HIT_M & HIT_OTHER_CORE_FWD ocr.all_reads.l3_hit_e.snoop_miss ocr.all_pf_rfo.any_response Counts all demand code reads DEMAND_CODE_RD & SUPPLIER_NONE & HIT_OTHER_CORE_FWD ocr.demand_rfo.supplier_none.no_snoop_needed Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & SUPPLIER_NONE & ANY_SNOOP ocr.all_pf_data_rd.l3_hit_f.no_snoop_needed Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_F & HITM_OTHER_CORE ocr.all_reads.l3_hit_s.snoop_none ocr.all_pf_data_rd.l3_hit_e.snoop_none ocr.pf_l2_rfo.l3_hit_s.snoop_miss ocr.pf_l1d_and_sw.l3_hit_s.any_snoop ocr.all_pf_data_rd.pmm_hit_local_pmm.any_snoop ALL_PF_DATA_RD & L3_HIT_E & NO_SNOOP_NEEDED ocr.other.l3_hit.any_snoop Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_F & HIT_OTHER_CORE_NO_FWD ocr.all_pf_data_rd.pmm_hit_local_pmm.snoop_not_needed ocr.all_rfo.supplier_none.any_snoop Counts demand data reads DEMAND_DATA_RD & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWD Counts all demand code reads DEMAND_CODE_RD & L3_HIT & ANY_SNOOP ocr.all_data_rd.pmm_hit_local_pmm.snoop_not_needed ocr.pf_l2_data_rd.l3_hit.any_snoop ocr.pf_l1d_and_sw.l3_hit_e.hit_other_core_no_fwd period=400009,umask=0x2,event=0xc5 cmask=8,period=2000003,umask=0x8,event=0xa3 cmask=4,period=2000003,umask=0x2,event=0xb1 Intel Optane DC persistent memory bandwidth total (MB/sec). Derived from unc_m_pmm_rpq_inserts. Unit: uncore_imc umask=0x1,event=0xe0 unc_m_pmm_read_latency unc_m_pmm_cmd1.rd umask=0x1,event=0xe4 All dirty line misses to Near Memory(DRAM cache) in Memory Mode. Unit: uncore_imc unc_iio_data_req_of_cpu.mem_write.part0 + unc_iio_data_req_of_cpu.mem_write.part1 + unc_iio_data_req_of_cpu.mem_write.part2 + unc_iio_data_req_of_cpu.mem_write.part3 unc_cha_rxc_inserts.irq Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit. Unit: uncore_iio unc_iio_data_req_of_cpu.peer_read.part3 unc_iio_data_req_of_cpu.peer_write.part3 Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part1. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus Peer to peer write request of up to a 64 byte transaction is made to IIO Part0 by a different IIO unit. Unit: uncore_iio period=100003,umask=0x20,event=0x49 l2_rqsts.swpf_miss Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall (Precise event) Number of occurrences where a microcode assist is invoked by hardware Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB) umask=0x4,period=200003,event=0xd1 Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line. The event strives to count on a cache line basis, so that multiple fetches to a single cache line count as one ICACHE.ACCESS. Specifically, the event counts when accesses from straight line code crosses the cache line boundary, or when a branch target is to a new line unc_iio_data_req_of_cpu.mem_read.part0 +unc_iio_data_req_of_cpu.mem_read.part1 +unc_iio_data_req_of_cpu.mem_read.part2 +unc_iio_data_req_of_cpu.mem_read.part3 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 Counts the number of times there was an ITLB miss and a new translation was filled into the ITLB umask=0x80,event=0x1 xi_ccx_sdp_req1.all_l3_miss_req_typs ex_ret_brn_resync Retired Indirect Branch Instructions Mispredicted umask=0x4,event=0x1cf umask=0x6E,event=0x8e df_ccm_reqa.node6.wrsizedfullzero df_ccm_reqb.node1.vicblkfull. df_ccm_reqb.node4.vicblkfull. df_ccm_reqb.node5.vicblkfull. umask=0x6C,event=0x8c df_ccm_reqb.node4.anyiorequest. umask=0xA7,event=0x8c df_ccm_reqb.node3.wrsizednc Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullncposted df_ccm_reqb.node1.wrsizedncposted Data Fabric CCM Performance Monitor Event DF CCM Request Type C (PIE Requests)Fast TPR write umask=0x8C,event=0x108 df_ioms_reqa.node1.anyatomic df_ioms_reqa.node5.anyatomic df_ioms_reqa.node3.anywrsized<32b umask=0x62,event=0x108 umask=0xEC,event=0x109 umask=0x4B,event=0x109 umask=0x08,event=0x109 df_ioms_reqb.node7.ioanynon-postedwrsized<32b This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Single precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Single-precision divide/square root FLOPS Single-precision add/subtract FLOPS l3_request_g1.t1.s0.wrsizednc l3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x04,event=0x1 l3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x20,event=0x1 l3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x20,event=0x1 l3_request_g1.t0.s1.rdsized l3_thread_mask=0x40,l3_slice_mask=0x04,umask=0x40,event=0x1 l3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x80,event=0x1 l3_request_g1.t0.s2.caching l3_request_g1.t4.s3.caching l3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x80,event=0x1 l3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x01,event=0x3 l3fillvicreq.t6.s3.chgtox l3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x04,event=0x3 l3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x04,event=0x3 l3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x04,event=0x3 l3fillvicreq.t0.s1.rdblkc_s l3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x08,event=0x3 l3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x08,event=0x3 l3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x08,event=0x3 l3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x10,event=0x3 l3fillvicreq.t6.s2.rdblkx_vic l3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x20,event=0x3 l3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x20,event=0x3 l3fillvicreq.t1.s2.rdblkl_vic l3fillvicreq.t4.s2.rdblkl_vic l3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x40,event=0x3 l3fillvicreq.t1.s3.rdblkl_vic l3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x80,event=0x3 l3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x01,event=0x9 l3victimstate.t3.s1.nol3victimline l3victimstate.t1.s2.nol3victimline l3victimstate.t4.s2.nol3victimline l3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x01,event=0x9 l3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x01,event=0x9 l3victimstate.t7.s1.f_s l3victimstate.t0.s3.f_s l3victimstate.t6.s3.f_s l3victimstate.t1.s1.o l3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x10,event=0x9 l3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x20,event=0x9 l3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x20,event=0x9 l3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x40,event=0x9 l3victimstate.t2.s3.d l3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x40,event=0x9 l3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x80,event=0x9 L1 DTLB Miss of a page of 32K size The number of software prefetches that did not fetch data outside of the processor core. Software PREFETCH instruction saw a match on an already-allocated miss request buffer umask=0x1,event=0x52 de_dis_dispatch_token_stalls0.retire_token_stall de_dis_dispatch_token_stalls0.agsq_token_stall umask=0x8,event=0xaf Total number of fp uOps. The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS ls_bad_status2.stli_other umask=0x8,event=0x25 de_dis_uop_queue_empty_di0 event=0xa9 de_dis_uops_from_decoder de_dis_dispatch_token_stalls1.taken_branch_buffer_rsrc_stall Cycles where a dispatch group is valid but does not get dispatched due to a token stall. SC AGU dispatch stall TSC FR_DISPATCH_STALLS FR_DISPATCH_STALL_WHEN_LS_IS_FULL NB_MEMORY_CONTROLLER_BYPASS_SATURATION EXC_TAKEN DATA_CACHE_DEPENDENT_STALL L1D_TLB ITLB_WALK L1D_TLB_RD L2D_TLB_REFILL_WR DCACHE_SET_TAG_READ DC_LOADSTORE ITLB_ACCESSES DDQ0_FULL_DR_STALLS LOAD_STORE_BLOCKED_CYCLES CP1_BRANCH_MISPREDICTIONS ONE_INSN_CYCLES SYSTEM_EVENT_4 LDS SPEC_BUFFER_CYCLES ITLB_HW_TABLE_SEARCH_CYCLES BRANCH_LINK_STACK_CORRECTLY_RESOLVED ITLB_HW_SEARCH_CYCLES_OVER_THRESHOLD L2_DATA_CACHE_MISSES SNOOP_MODIFIED BORDQ_FULL BUS_TAS_FOR_WRITES BUS_READS_WRITES_NOT_RETRIED PREFETCH_ENGINE_REQUEST FPU_MARKED_INSTR_COMPLETED CYCLES_WITH_ANY_THREAD_RUNNING BRANCHES_FINISHED LOAD_GUARDED_MISS_CYCLES BIU_MASTER_DATA_SIDE_CASTOUT_REQUESTS EXT_INPU_INTR_LATENCY_CYCLES mask= ARMV8 MIPS74K INTEL_WESTMERE_EX MIPS_24K ARMV7_CORTEX_A9 %s:
%s
frontend "0x%016jx"]}
GenuineIntel-6-1F UPI idq.dsb_uops / ( idq.dsb_uops + lsd.uops + idq.mite_uops + idq.ms_uops ) C6 residency percent per package C7_Pkg_Residency Cycles with L1D load Misses outstanding l1d.replacement umask=0x1,period=2000003,event=0x51 Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. (Precise Event - PEBS) Supports address when precise (Precise event) Number of transitions from AVX-256 to legacy SSE when penalty applicable Spec update: BDM30 umask=0x4,cmask=1,period=2000003,event=0x79 This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ tx_mem.abort_hle_elision_buffer_not_empty umask=0x1,period=2000003,event=0x5d Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details) This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers.
Notes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event.
Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions umask=0x1,period=100003,event=0x4c This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by asm inspection of the nearby instructions umask=0x2,period=1000003,event=0x58 Stalls caused by changing prefix length of the instruction This event counts taken speculative and retired macro-conditional branch instructions br_inst_exec.taken_direct_near_call umask=0xc8,period=200003,event=0x88 Cycles per thread when uops are executed in port 3 umask=0x1,cmask=4,period=2000003,event=0xa8 Cycles Uops delivered by the LSD, but didn't come from the decoder Cycles with less than 10 actually retired uops This event counts not taken branch instructions retired br_misp_retired.ret write requests to home agent. Unit: uncore_ha M line forwarded from remote cache with no writeback to memory. Unit: uncore_ha (unc_p_power_state_occupancy.cores_c0 / unc_p_clockticks) * 100. virtual memory Store miss in all TLB levels causes a page walk that completes. (4K) Spec update: BDM69 umask=0x4,period=100003,event=0x49 itlb_misses.miss_causes_a_walk This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend Backend_Bound_SMT PGO;IcMiss Cycles Per Instruction (per Logical Processor) L3MPKI umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0001 offcore_response.corewb.supplier_none.snoop_not_needed offcore_response.pf_l2_rfo.l3_hit.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020040 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0120 offcore_response.all_pf_code_rd.any_response offcore_response.all_pf_code_rd.supplier_none.snoop_hitm offcore_response.all_rfo.l3_hit.snoop_hit_no_fwd This is a precise version (that is, uses PEBS) of the event that counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid Counts randomly selected loads with latency value being above 64 Spec update: BDM100, BDM35 (Must be precise) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x013C000001 offcore_response.demand_code_rd.l3_miss.snoop_miss offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_non_dram offcore_response.pf_l2_code_rd.supplier_none.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020040 offcore_response.pf_l3_data_rd.l3_miss.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000200 offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_miss offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1004000122 umask=0x2,period=2000003,cmask=2,event=0xb1 umask=0x2f,event=0x34 Unit: uncore_arb Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic offcore_response.demand_rfo.llc_hit.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x06040007F7 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0604000244 This event counts conditional branch instructions retired (Precise event) This event counts the number of mispredicted ret instructions retired. Non PEBS (Precise event) l2_ld.self.any.m_state umask=0x42,period=200000,event=0x29 umask=0x44,period=200000,event=0x2c l2_data_rqsts.self.s_state umask=0x51,period=200000,event=0x2e umask=0x41,period=200000,event=0x2e l2_reject_busq.self.any.mesi umask=0x48,period=200000,event=0x30 umask=0xa3,period=2000000,event=0x40 L1 Data line replacements umask=0x2,period=10000,event=0xcb umask=0x80,period=2000000,event=0xb0 umask=0x81,period=2000000,event=0xb3 SIMD packed arithmetic micro-ops executed Retired Streaming SIMD Extensions (SSE) packed-single instructions umask=0x0,period=100000,event=0xcd Non-CISC nacro instructions decoded All Instructions decoded umask=0xf,period=200000,event=0x5 umask=0x94,period=200000,event=0x5 umask=0x82,period=200000,event=0x7 bus_request_outstanding.self bus_hitm_drv.this_agent umask=0x0,period=200000,event=0x7b busq_empty.self umask=0x1,period=200000,event=0x3c br_inst_type_retired.cond Branch instructions decoded L0 DTLB misses due to load operations page_walks.walks Counts data reads (demand & prefetch) that miss the L2 cache umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400003091 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200008000 offcore_response.partial_streaming_stores.l2_miss.hit_other_core_no_fwd umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400001000 offcore_response.partial_reads.l2_miss.any offcore_response.pf_l2_rfo.l2_miss.hit_other_core_no_fwd Counts demand cacheable data reads of full cache lines that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) umask=0x1,period=200003,event=0x80 Counts cycles that fetch is stalled due to an outstanding ITLB miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ITLB miss. Note: this event is not the same as page walk cycles to retrieve an instruction translation umask=0x1,period=200003,event=0x3 Loads blocked due to store data not ready (Precise event capable) (Must be precise) br_inst_retired.all_taken_branches Counts mispredicted near indirect CALL branch instructions retired, where the target address taken was not what the processor predicted (Must be precise) cycles_div_busy.fpdiv Cycles the FP divide unit is busy Counts data cacheline reads generated by hardware L2 cache prefetcher have any transaction responses from the uncore subsystem Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200004800 Counts any data writes to uncacheable write combining (USWC) memory region miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts requests to the uncore subsystem true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_read.any_response Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Machines clear due to a page fault umask=0x8,period=200003,event=0x8 Demand requests that miss L2 cache Spec update: HSD78 Counts all L2 HW prefetcher requests This event counts cycles during which the microcode sequencer assisted the Front-end in delivering uops. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance This event counts the number cycles during which the Front-end allocated exactly zero uops to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalled. This event is counted on a per-core basis Spec update: HSD135 Randomly selected loads with latency value being above 128 Spec update: HSD76, HSD25, HSM26 (Must be precise) Number of flags-merge uops allocated. Such uops add delay Unit: uncore_cbox A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core L3 Lookup external snoop request that access cache and found line in M-state Unit: uncore_arb Each cycle count number of valid entries in Coherency Tracker queue from allocation till deallocation. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access memory) Store misses in all DTLB levels that cause completed page walks (2M/4M) page_walker_loads.ept_dtlb_l1 Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache Supports address when precise. Spec update: HSD29, HSD25, HSM26, HSM30 (Precise event) Offcore outstanding Demand Data Read transactions in uncore queue Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore mem_load_uops_llc_hit_retired.xsnp_hitm Dirty L2 cache lines filling the L2 Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1003c0001 fp_comp_ops_exe.sse_scalar_single umask=0x1,period=2000003,event=0x11 number of GSSE-256 Computational FP single precision uops issued this cycle umask=0x1,period=100003,event=0xb7,offcore_rsp=0x300400004 Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.) Cycles per core when uops are dispatched to port 4 Cycles Allocation is stalled due to Resource Related reason umask=0x01,event=0x22 Filter on cross-core snoops initiated by this Cbox due to processor core memory request LLC lookup request that access cache and found line in M-state dtlb_load_misses.large_page_walk_completed Miss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M/1G) offcore_response.all_pf_data_rd.llc_hit.any_response Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores umask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c03f7 offcore_response.all_reads.llc_hit.snoop_miss Counts demand data reads that miss the LLC and the data returned from remote & local dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x600400010 umask=0x1,event=0x35,filter_opc=0x195 event=0xe,edge=1 Counts the number of cycles that the uncore was running at a frequency greater than or equal to 4Ghz. Derived from unc_p_freq_band3_cycles. Unit: uncore_pcu Allocated L1D data cache lines in M state Speculative and retired mispredicted direct near calls br_misp_retired.taken umask=0x2,period=100003,event=0xc1 This event counts the number of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this type offcore_response.any_pf_l2.l2_hit_near_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080070 Counts any Read request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state Counts Demand code reads and prefetch code read requests that accounts for any response Counts Demand cacheable data write requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800403091 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000014000 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080200 Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state offcore_response.demand_code_rd.l2_hit_far_tile_m Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800080001 Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in M state offcore_response.pf_l1_data_rd.l2_hit_this_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002000070 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000001 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000400 offcore_response.any_data_rd.l2_hit_this_tile_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800180400 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800182000 Counts demand code reads and prefetch code reads that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode Counts Bus locks and split lock requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800402000 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200044 Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from MCDRAM Local umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0101000100 Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800080 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080200004 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181800002 Counts the number of branch instructions retired that were near indirect CALL or near indirect JMP (Precise event) no_alloc_cycles.not_delivered umask=0x1f,period=200003,event=0xcb 6.4e-05MiB Counts the total number of core cycles for all the I-side page walks. The cycles for page walks started in speculative path will also be included L1 data cache stores in E state l2_data_rqsts.demand.i_state l2_data_rqsts.prefetch.m_state l2_lines_in.e_state L2 lines allocated in the E state umask=0x4,period=200000,event=0x6 Memory instructions retired above 16384 clocks (Precise Event) mem_inst_retired.latency_above_threshold_2048 mem_inst_retired.latency_above_threshold_4 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F11 Offcore data reads that HIT in a remote cache All offcore code reads umask=0x1,period=100000,event=0xb7,offcore_rsp=0x10FF offcore_response.any_request.remote_cache_hitm Offcore RFO requests that HITM in a remote cache offcore_response.demand_data.any_cache_dram offcore_response.demand_data.llc_hit_other_core_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x201 offcore_response.demand_data_rd.remote_cache offcore_response.demand_ifetch.any_cache_dram offcore_response.demand_rfo.io_csr_mmio offcore_response.demand_rfo.local_cache_dram Offcore prefetch data requests that HITM in a remote cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x140 All offcore prefetch RFO requests umask=0x1,period=100000,event=0xb7,offcore_rsp=0x820 offcore_response.prefetch.local_cache_dram Offcore requests that missed the LLC Offcore RFO requests satisfied by a remote DRAM Offcore demand data reads that missed the LLC offcore_response.demand_rfo.any_dram Offcore prefetch data reads satisfied by any DRAM offcore_response.pf_data_rd.local_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x6020 load_dispatch.any load_dispatch.mob umask=0x1,period=100000,event=0xb8 umask=0x2,period=20000,event=0x89 ROB full stall cycles umask=0x8,period=200000,event=0xc7 uops_executed.core_stall_count Counts the total number of requests from the L2 hardware prefetchers offcore_response.other.l3_hit_s.snoop_miss offcore_response.demand_code_rd.l3_hit_s.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400080002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0040002 offcore_response.demand_rfo.supplier_none.snoop_hitm offcore_response.demand_rfo.supplier_none.snoop_none umask=0x4,period=200003,event=0x83 Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops (Precise event) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFC408000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC4000002 Core crystal clock cycles when this thread is unhalted and the other thread is halted umask=0x10,period=2000003,cmask=16,event=0xa3 exe_activity.1_ports_util Number of cycles using an always true condition applied to PEBS instructions retired event. (inst_ret< 16) Spec update: SKL091, SKL044 (Must be precise) This is a precise version (that is, uses PEBS) of the event that counts return instructions retired Spec update: SKL091 (Precise event) uops_executed.thread / (( uops_executed.core_cycles_ge_1 / 2 ) if #smt_on else uops_executed.core_cycles_ge_1) l1d_pend_miss.pending / ( mem_load_retired.l1_miss + mem_load_retired.fb_hit ) Cycles when at least one PMH is busy with a page walk for a store. EPT page walk duration are excluded in Skylake Code miss in all TLB levels causes a page walk that completes. (All page sizes) Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake michroarchitecture Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.) rehabq.ld_block_st_forward Counts the number of mispredicted taken JCC branch instructions retired (Precise event) IND_CALL counts the number of mispredicted near indirect CALL branch instructions retired. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa. When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event) This event counts the number of micro-ops retired. The processor decodes complex macro instructions into a sequence of simpler micro-ops. Most instructions are composed of one or two micro-ops. Some instructions are decoded into longer sequences such as repeat instructions, floating point transcendental instructions, and assists. In some cases micro-op sequences are fused or whole instructions are fused into one micro-op. See other UOPS_RETIRED events for differentiating retired fused and non-fused micro-ops Stalls due to FP assists Counts the number of JCC baclears Loads missed DTLB (Precise event) offcore_response.all_pf_code_rd.llc_hit.hit_other_core_no_fwd offcore_response.all_pf_code_rd.llc_hit.hitm_other_core Counts demand & prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded Counts demand & prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded offcore_response.data_in.any_response REQUEST = PF_LLC_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1ff REQUEST = DATA_IN and RESPONSE = ANY_CACHE_DRAM offcore_response.pf_data.all_local_dram_and_remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f50 umask=0x2,period=200000,event=0x5 REQUEST = ANY IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD offcore_response.other.any_dram_and_remote_fwd umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4080 Outstanding snoop data requests umask=0x1,period=2000000,cmask=1,event=0xb3 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5844 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5804 offcore_response.pf_l2_data_rd.l3_hit.hit_other_core_no_fwd Counts all prefetch (that bring data to L2) RFOs TBD TBD umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0000010400 TBD offcore_response.demand_rfo.l3_miss.remote_hit_forward offcore_response.demand_rfo.l3_miss.remote_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBC000010 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBC000080 offcore_response.all_data_rd.l3_miss.remote_hitm umask=0x1,period=100003,event=0xb7,offcore_rsp=0x103FC00491 offcore_response.all_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule inv=1,umask=0x1,cmask=10,period=2000003,event=0xc0 DRAM Page Activate commands sent due to a write request. Unit: uncore_imc unc_cha_clockticks umask=0x04,event=0x50 fc_mask=0x07,ch_mask=0x04,umask=0x04,event=0x83 fc_mask=0x07,ch_mask=0x08,umask=0x04,event=0x83 unc_iio_data_req_by_cpu.mem_read.part2 Read request for up to a 64 byte transaction is made by IIO Part1 to Memory. Unit: uncore_iio fc_mask=0x07,ch_mask=0x04,umask=0x04,event=0x84 unc_m2m_bypass_m2m_egress.not_taken unc_m2m_directory_update.s2i unc_m3upi_upi_prefetch_spawn Counts cycles when the the receive side (Rx) of the Intel Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power Counts incoming FLITs (FLow control unITs) which bypassed the slot2 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency Counts cycles when the transmit side (Tx) of the Intel Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS offcore_response.demand_data_rd.l3_hit_f.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0080 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200010 offcore_response.pf_l2_rfo.l3_hit_f.any_snoop offcore_response.all_pf_rfo.l3_hit_m.snoop_miss This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100120 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED offcore_response.pf_l2_rfo.pmm_hit_local_pmm.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F803C0100 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0122 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200100 This event is deprecated. Refer to new event OCR.ALL_READS.ANY_RESPONSE This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NONE offcore_response.all_rfo.l3_hit_f.any_snoop period=200003,umask=0xc1,event=0x24 cmask=1,period=2000003,umask=0x8,event=0x60 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED Counts retired load instructions that split across a cacheline boundary Supports address when precise (Precise event) period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100400120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD offcore_response.all_rfo.l3_hit_m.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0001 offcore_response.pf_l1d_and_sw.supplier_none.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200080 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0010 offcore_response.demand_rfo.l3_hit_e.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000040001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE offcore_response.other.l3_hit_m.hitm_other_core offcore_response.demand_code_rd.supplier_none.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020010 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800020490 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080020100 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200122 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD offcore_response.pf_l1d_and_sw.pmm_hit_local_pmm.snoop_not_needed offcore_response.all_pf_rfo.l3_hit_f.snoop_none offcore_response.other.l3_hit_m.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE period=2000003,umask=0x2,event=0xc7 period=2000003,umask=0x30,event=0x79 period=100007,umask=0x1,event=0xc6,frontend=0x404006 cmask=1,edge=1,period=2000003,umask=0x30,event=0x79 ocr.pf_l3_rfo.l3_miss_local_dram.snoop_none This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD period=2000003,umask=0x8,event=0xc9 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONE ocr.pf_l1d_and_sw.l3_miss_local_dram.snoop_miss This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE ALL_READS & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS ALL_PF_DATA_RD & L3_MISS & REMOTE_HITM Counts all demand data writes (RFOs) DEMAND_RFO & L3_MISS & NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x063B800490 This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.SNOOP_MISS offcore_response.pf_l3_data_rd.l3_miss.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1004000004 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD Counts demand data reads DEMAND_DATA_RD & L3_MISS & SNOOP_NONE offcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.any_snoop ocr.demand_code_rd.l3_miss_local_dram.any_snoop This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD ocr.other.l3_miss_remote_hop1_dram.hitm_other_core This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS_LOCAL_DRAM & HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS ocr.pf_l1d_and_sw.l3_miss.snoop_none ocr.all_rfo.l3_miss.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000122 offcore_response.all_data_rd.l3_miss_local_dram.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD period=503,umask=0x1,event=0xcd,ldlat=0x100 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000100 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE ocr.pf_l2_data_rd.l3_miss.snoop_none period=2000003,umask=0x1,event=0xc9 ALL_PF_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & SNOOP_MISS Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISS_OR_NO_FWD This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD Counts any other requests OTHER & L3_MISS & NO_SNOOP_NEEDED ocr.demand_code_rd.l3_miss_remote_hop1_dram.no_snoop_needed ocr.all_pf_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd Counts any other requests OTHER & L3_MISS_LOCAL_DRAM & ANY_SNOOP Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS & HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM Counts all demand data writes (RFOs) DEMAND_RFO & L3_MISS_REMOTE_HOP1_DRAM & NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000491 ocr.pf_l1d_and_sw.l3_miss_local_dram.snoop_miss_or_no_fwd Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS_LOCAL_DRAM & SNOOP_MISS_OR_NO_FWD This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS & NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000490 offcore_response.all_rfo.l3_miss_remote_hop1_dram.snoop_miss This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP ocr.demand_data_rd.l3_hit_s.hit_other_core_fwd Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_S & ANY_SNOOP ocr.demand_code_rd.l3_hit_f.snoop_miss ocr.demand_data_rd.l3_hit_f.any_snoop ocr.all_reads.supplier_none.hit_other_core_no_fwd Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT & SNOOP_NONE Counts demand data reads DEMAND_DATA_RD & L3_HIT_E & HIT_OTHER_CORE_FWD Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_F & NO_SNOOP_NEEDED ocr.other.any_response ocr.all_pf_data_rd.l3_hit_m.hit_other_core_fwd ALL_READS & L3_HIT & HIT_OTHER_CORE_FWD ocr.pf_l2_data_rd.l3_hit_s.no_snoop_needed ALL_DATA_RD & L3_HIT_M & HITM_OTHER_CORE ocr.pf_l2_rfo.l3_hit_f.no_snoop_needed ALL_RFO & L3_HIT_S & ANY_SNOOP ocr.pf_l2_data_rd.l3_hit_m.hit_other_core_fwd ocr.pf_l2_rfo.l3_hit_f.hit_other_core_fwd ALL_PF_DATA_RD & L3_HIT & SNOOP_MISS ALL_READS & L3_HIT_S & SNOOP_NONE ocr.demand_code_rd.l3_hit_s.snoop_miss ALL_DATA_RD & L3_HIT_S & HIT_OTHER_CORE_NO_FWD ocr.pf_l2_data_rd.pmm_hit_local_pmm.any_snoop ocr.pf_l1d_and_sw.l3_hit_f.hit_other_core_no_fwd ocr.all_rfo.l3_hit.any_snoop ALL_DATA_RD & L3_HIT_E & HIT_OTHER_CORE_FWD Counts demand data reads DEMAND_DATA_RD & L3_HIT_M & HIT_OTHER_CORE_NO_FWD Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_HIT & HIT_OTHER_CORE_FWD ocr.pf_l3_data_rd.l3_hit.no_snoop_needed Counts all demand code reads DEMAND_CODE_RD & L3_HIT_M & HITM_OTHER_CORE ocr.all_data_rd.l3_hit_e.snoop_miss ocr.pf_l2_data_rd.l3_hit_m.hitm_other_core Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT_E & HIT_OTHER_CORE_NO_FWD ALL_READS & L3_HIT_S & SNOOP_MISS period=2000003,umask=0x20,event=0xe period=2000003,umask=0x20,event=0xcc cmask=1,period=2000003,umask=0x1,event=0xa8 cmask=3,period=2000003,umask=0x2,event=0xb1 unc_m_pmm_cmd1.ufill_rd umask=0x08,event=0x37 unc_iio_data_req_by_cpu.peer_write.part3 unc_iio_data_req_of_cpu.peer_write.part1 Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus Multi-socket cacheline Directory lookup (cacheline found in I state). Unit: uncore_m2m Write requests to Intel Optane DC persistent memory issued to the iMC from M2M. Unit: uncore_m2m unc_m2m_rxc_ad_occupancy BL Egress (to CMS) Allocations; All period=2000003,umask=0x2,event=0x8 Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache Supports address when precise (Precise event) Counts retired load instructions whose data sources were hits in L3 without snoops required Supports address when precise (Precise event) Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 RANGE FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element Number of switches from DSB or MITE to the MS Counts instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions umask=0x7,period=100003,event=0xc1 umask=0x2,period=25003,event=0x3c Number of instructions retired. General Counter - architectural event All miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch) Supports address when precise (Precise event) Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle umask=0x1,period=100003,event=0xb7,offcore_rsp=0x000000000000010001 Counts branch instructions retired for all branch types. This event is Precise Event capable. This is an architectural event (Precise event) umask=0xC86FFE01,event=0x35 Clockticks of the IO coherency tracker (IRP) ic_cache_fill_l2 All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache hit modifiable line in L2 umask=0xff,event=0x4 event=0xd4 ex_tagged_ibs_ops.ibs_tagged_ops df_ccm_reqa.node1.anydram Data Fabric CCM Performance Monitor Event DF CCM Request Ordered WrSizedFullZero df_ccm_reqa.node1.rdsized df_ccm_reqa.node1.specdramrd df_ccm_reqa.node5.rdvlkx Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdvlkl df_ccm_reqb.node3.vicblkfull. umask=0x4C,event=0x8c df_ccm_reqb.node7.wrsizedfullncposted df_ccm_reqb.node3.wrsizedncposted umask=0xAB,event=0x108 df_ioms_reqa.node4.anydramtransaction df_ioms_reqa.node7.anywrsized>32band<64b Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized=32b umask=0xA3,event=0x108 Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) largeread umask=0x61,event=0x108 umask=0xE1,event=0x108 df_ioms_reqb.node2.ioanyatomic df_ioms_reqb.node5.ioanynon-postedwrsized>32band<64b umask=0x48,event=0x109 umask=0xC5,event=0x109 umask=0xE5,event=0x109 df_ioms_reqb.node5.ioanyrdsized umask=0xA2,event=0x109 umask=0xC1,event=0x109 Total number of fp uOps on pipe 3 The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 1 fp_num_mov_elim_scal_op.opt_potential l3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x02,event=0x1 l3_request_g1.t1.s1.wrsized l3_request_g1.t6.s2.wrsized l3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x04,event=0x1 l3_request_g1.t2.s3.wrsized l3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x20,event=0x1 l3_request_g1.t6.s1.rdsizednc l3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x40,event=0x1 l3_request_g1.t5.s1.rdsized l3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x40,event=0x1 l3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x80,event=0x1 l3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x80,event=0x1 l3fillvicreq.t2.s0.chgtox l3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x02,event=0x3 l3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x02,event=0x3 l3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x02,event=0x3 l3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x04,event=0x3 l3fillvicreq.t7.s1.rdblkx_vic l3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x20,event=0x3 l3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x20,event=0x3 l3_thread_mask=0x02,l3_slice_mask=0x08,umask=0x20,event=0x3 l3fillvicreq.t7.s0.rdblkl_vic l3_thread_mask=0x01,l3_slice_mask=0x04,umask=0x40,event=0x3 l3fillvicreq.t7.s2.rdblkl_vic l3_thread_mask=0x08,l3_slice_mask=0x08,umask=0x40,event=0x3 l3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x40,event=0x3 l3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x80,event=0x3 l3fillvicreq.t2.s1.rdblkl l3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x01,event=0x9 l3victimstate.t5.s3.none_nol3victimline l3victimstate.t4.s0.f_s l3victimstate.t6.s0.f_s l3victimstate.t3.s1.f_s l3victimstate.t0.s1.o l3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x08,event=0x9 l3victimstate.t7.s3.e_fe l3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x20,event=0x9 l3victimstate.t7.s0.m l3victimstate.t5.s1.m l3victimstate.t7.s2.m l3_thread_mask=0x08,l3_slice_mask=0x01,umask=0x80,event=0x9 l3victimstate.t1.s1.od event=0x47 Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALU tokens total unavailable Retired Conditional Branch Instructions Mispredicted Total number uOps assigned to pipe 1 Multiply FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15 Number of Scalar Ops optimized. This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes Number of SSE Move Ops eliminated. This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes Number of stores dispatched. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed ls_smi_rx A non-cacheable store and the non-cacheable commit buffer is full umask=0x10,event=0x43 L1 DTLB Miss. DTLB reload to a 4K page that hit in the L2 TLB umask=0x8,event=0x59 umask=0x1,event=0x5a ls_tlb_flush umask=0x2,event=0xaa DC_MICROARCHITECTURAL_EARLY_CANCEL WRITE_BUF_FULL NEON_INSTRS_RENAMED L1I_CACHE_REFILL BR_INDIRECT_SPEC BR_RETURN_RETIRED DP_SPEC BR_MIS_PRED_RETIRED L2D_TLB L3_CACHE_RD UNREPRESENTABLE_CAPS L2CACHE_WRITE_MISS L2CACHE_SET_TAG_READ L2CACHEMASTER_WRITE_RSP TAGCACHEMASTER_WRITE_REQ CACHE_STALL_CYCLES WBB_GT_HALF REDIRECT_STALLS COND_BRANCH_INSNS GFIFO_BLOCKED_CYCLES CP1_CP2_STORE_INSNS IFI BRMIS LSU_ALIAS_VS_CSQ L1_DATA_CYCLES_USED FPR_ISSUE_STALLED TAKEN_BRANCHES_PROCESSED BRANCH_FLUSHES FPU_COMPLETION_STALL CACHE_LOAD_MISS LOADS_TRANSLATED_ALLOCATED_TO_DLFB STORES_COMPLETED_ALLOCATED_TO_DLFB STORE_TRANSLATE_WHEN_QUEUE_FULL_CYCLES L2_CACHE_DATA_DIRTY_HITS packed-sse-sse2 command INTEL_PIII INTEL_ATOM_SILVERMONT ARMV8_CORTEX_A76 RUNNING bad magic LLC_REFERENCE cmask config1 GenuineIntel-6-47 GenuineIntel-6-2F GenuineIntel-6-7E Fraction of Uops delivered by the DSB (aka Decoded Icache; or Uop Cache) 2* ( rs_events.empty_cycles - icache.ifdata_stall - ( 14 * itlb_misses.stlb_hit + cpu@itlb_misses.walk_duration\,cmask\=1@ + 7* itlb_misses.walk_completed ) ) / rs_events.empty_end Load_Miss_Real_Latency FLOPS;Summary umask=0x21,period=200003,event=0x24 umask=0xf8,period=200003,event=0x24 l2_rqsts.references This event counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM umask=0x11,period=100003,event=0xd0 umask=0x4,period=200003,event=0xf0 fp_arith_inst_retired.scalar_double umask=0x3,period=2000003,event=0xc7 mem_trans_retired.load_latency_gt_4 umask=0x1,period=50021,event=0xcd,ldlat=0x8 mem_trans_retired.load_latency_gt_256 mem_trans_retired.load_latency_gt_512 umask=0x1,period=2000003,event=0x5c This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access umask=0x0,period=2000003,event=0x3c This is a fixed-frequency event programmed to general counters. It counts when the core is unhalted at 100 Mhz br_inst_exec.all_indirect_near_return Speculative and retired direct near calls br_misp_exec.taken_indirect_jump_non_call_ret Taken speculative and retired mispredicted indirect branches excluding calls and returns uops_dispatched_port.port_3 umask=0x40,any=1,period=2000003,event=0xa1 umask=0x10,period=2000003,event=0xa2 FP operations retired. X87 FP operations that have no exceptions: Self-modifying code (SMC) detected All (macro) branch instructions retired. (Precise Event - PEBS) Spec update: BDW98 (Must be precise) uncore cache umask=0x1,event=0x35,filter_opc=0x1c8,filter_tid=0x3e Occupancy counter for LLC data reads (demand and L2 prefetch). Derived from unc_c_tor_occupancy.miss_opcode. Unit: uncore_cbox unc_h_snoop_resp.rsps prochot_external_cycles % unc_p_freq_max_os_cycles umask=0x40,period=2000003,event=0x8 Code miss in all TLB levels causes a page walk that completes. (4K) Spec update: BDM69 This category represents fraction of slots wasted due to incorrect speculations. SMT version; use when SMT is enabled and measuring per logical CPU br_inst_retired.all_branches / br_inst_retired.near_taken inst_retired.any / (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )) Actual Average Latency for L1 data-cache miss demand loads (in core cycles) This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required Spec update: BDM100. Supports address when precise (Precise event) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0002 offcore_response.corewb.supplier_none.snoop_none offcore_response.corewb.l3_hit.snoop_not_needed offcore_response.pf_l3_data_rd.l3_hit.snoop_not_needed Counts all prefetch (that bring data to LLC only) RFOs umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00803C0100 offcore_response.pf_l3_code_rd.supplier_none.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020200 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0090 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0090 Counts prefetch RFOs umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020120 offcore_response.all_pf_code_rd.l3_hit.snoop_hit_no_fwd offcore_response.all_pf_code_rd.l3_hit.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020122 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020122 This is a precise version (that is, uses PEBS) of the event that counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention umask=0x24,period=2000003,cmask=1,event=0x79 offcore_response.demand_data_rd.l3_miss_local_dram.snoop_not_needed offcore_response.corewb.l3_miss_local_dram.snoop_none offcore_response.pf_l2_rfo.l3_miss_local_dram.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000020 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0040 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000040 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0104000200 offcore_response.other.l3_miss.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0090 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000090 offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_not_needed offcore_response.all_pf_rfo.l3_miss.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x043C000120 offcore_response.all_pf_code_rd.l3_miss.snoop_not_needed umask=0x4,period=2000003,cmask=4,event=0xa3 unc_cbo_cache_lookup.read_m Unit: uncore_cbox L3 Lookup read request that access cache and found line in M-state unc_cbo_cache_lookup.any_m unc_arb_trk_occupancy.all Retired store uops that split across a cacheline boundary Supports address when precise (Precise event) Counts all demand & prefetch code reads miss in the L3 Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBFC00122 Counts all demand data writes (RFOs) miss in the L3 Mispredicted conditional branch instructions retired (Precise event) umask=0x40,period=200000,event=0x22 umask=0x40,period=200000,event=0x24 L2 cache line modifications umask=0x7f,period=200000,event=0x29 l2_ld.self.demand.s_state l2_st.self.e_state l2_reject_busq.self.demand.mesi simd_uops_exec.s umask=0x2,period=2000000,event=0xb3 umask=0x2,period=2000000,event=0xc7 macro_insts.non_cisc_decoded ld-op-st splits prefetch.prefetcht1 umask=0x88,period=200000,event=0x7 L1 hardware prefetch request bus_bnr_drv.all_agents umask=0xe0,period=200000,event=0x6b Bus stalled for snoops umask=0x2,period=2000000,event=0xc6 br_inst_type_retired.ret umask=0x10,period=2000000,event=0x88 umask=0x8,period=200000,event=0x89 Mispredicted and taken cond branch instructions retired Retired branch instructions that were predicted not-taken page_walks.cycles itlb.flush core_reject_l2q.all Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000040022 offcore_response.any_pf_data_rd.l2_hit offcore_response.pf_l2_rfo.l2_miss.snoop_miss_or_no_snoop_needed Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required umask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600000002 Unfilled issue slots per cycle umask=0x8,period=200003,event=0xc3 umask=0x80,period=200003,event=0xc4 Counts near return branch instructions retired (Must be precise) BACLEARs asserted for any branch type offcore_response.pf_l2_data_rd.outstanding Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes have any transaction responses from the uncore subsystem Counts data cache lines requests by software prefetch instructions hit the L2 cache umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000004800 Counts data reads (demand & prefetch) have any transaction responses from the uncore subsystem Counts reads for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) umask=0x10,period=200003,event=0x4f Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM All retired load uops. (precise Event) Spec update: HSD29, HSM30. Supports address when precise (Precise event) A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core This event counts load operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks Number of DTLB page walker hits in the L3 + XSNP Spec update: HSD25 Number of near branch instructions retired that were taken but mispredicted (Precise event) Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache (Precise event) Counts all demand & prefetch prefetch RFOs fp_comp_ops_exe.sse_packed_single number of AVX-256 Computational FP double precision uops issued this cycle Number of assists associated with 256-bit AVX store operations Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses Loads with latency value being above 256 (Must be precise) umask=0x2,period=2000003,event=0xcd LLC lookup request that access cache and found line in S-state unc_cbo_cache_lookup.any_request_filter umask=0x84,period=2000003,event=0x8 Cycle PMH is busy with a walk due to demand loads Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoop returned a clean response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x23ffc08000 Counts all demand & prefetch code reads that miss the LLC and the data returned from remote dram Counts all demand code reads that miss the LLC and the data returned from remote dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3fffc20200 umask=0x3,event=0x35,filter_opc=0x1e4 unc_p_freq_max_current_cycles (unc_p_freq_max_current_cycles / unc_p_clockticks) * 100. Counts the number of cycles that the uncore was running at a frequency greater than or equal to 1.2Ghz. Derived from unc_p_freq_band0_cycles. Unit: uncore_pcu Counts the number of cycles that the uncore transitioned to a frequency greater than or equal to 4Ghz. Derived from unc_p_freq_band3_cycles. Unit: uncore_pcu All retired store uops (Precise event) l1d.all_m_replacement Multiply packed/scalar single precision uops allocated resource_stalls2.bob_full Direct and indirect mispredicted near call instructions retired (Precise event) l2_requests_reject.all umask=0x10,period=200003,event=0x4 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x40000032f7 Counts any request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800088000 offcore_response.pf_l1_data_rd.l2_hit_near_tile_m Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode offcore_response.bus_locks.l2_hit_far_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000200 offcore_response.partial_writes.any_response umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400040 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0002000080 offcore_response.uc_code_reads.l2_hit_this_tile_e Counts Demand cacheable data write requests that accounts for responses which hit its own tile's L2 with data in E state umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0008000020 Counts UC code reads (valid only for Outstanding response type) that accounts for responses which hit its own tile's L2 with data in F state offcore_response.any_read.l2_hit_this_tile_f Counts the number of times the MSROM starts a flow of uops offcore_response.any_rfo.ddr_near Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from DRAM Far offcore_response.partial_reads.ddr_near offcore_response.demand_code_rd.mcdram_far offcore_response.demand_data_rd.mcdram_far umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0180603091 Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from DDR (local and far) umask=0x20,period=200003,event=0xc2 br_misp_retired.far_branch l1d_cache_lock.hit L2 RFO misses l2_transactions.wb mem_uncore_retired.remote_dram umask=0x10,period=2000000,event=0xb,ldlat=0x0 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x411 offcore_response.any_data.remote_cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x444 offcore_response.any_ifetch.local_cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x18FF umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F22 offcore_response.any_rfo.local_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x8033 Offcore request = all data, response = remote cache offcore_response.demand_data.remote_cache_hitm Offcore demand data reads satisfied by the LLC and HITM in a sibling core umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4701 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x404 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x704 Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F40 umask=0x20,period=2000000,event=0x10 umask=0x4,period=200000,event=0xfd Offcore data reads that missed the LLC umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4044 offcore_response.corewb.remote_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x4001 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2080 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x6040 io_transactions snoop_response.hitm Instruction queue forced BACLEAR Instructions written to instruction queue umask=0x1,period=200000,event=0x4c resource_stalls.other umask=0x1,period=2000000,event=0xb1 uops_executed.port1 umask=0x1,period=2000000,event=0xe dtlb_misses.any mem_store_retired.dtlb_miss mem_load_retired.l3_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040048000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080400002 offcore_response.demand_rfo.l3_hit_e.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FC0040001 Counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1 Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS Counts retired Instructions that experienced STLB (2nd level TLB) true miss (Precise event) Cycles while L3 cache miss demand load is outstanding umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084000002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20001C0002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000080002 offcore_response.demand_data_rd.l3_miss.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000400001 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20001C0001 Number of hardware interrupts received by the processor Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 7 Counts page walks completed due to demand data loads whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault Loads blocked due to store data not ready Uops with lock semantics offcore_response.any_data_rd.l2_miss.snoop_miss Counts streaming store that miss L2 Counts DCU hardware prefetcher data read that miss L2 Counts demand and DCU prefetch instruction cacheline that miss L2 Counts demand and DCU prefetch data read that have any response type This event counts the number of times that pipeline was cleared due to memory ordering issues Counts the number of branch instructions retired.. (Precise event) Counts all machine clears Cycles the divider is busy. Does not imply a stall waiting for the divider Counts the number of reference cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. Divide this event count by core frequency to determine the elapsed time while the core was not in halt state. Divide this event count by core frequency to determine the elapsed time while the core was not in halt state. This event is architecturally defined and is a designated fixed counter. CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.CORE_P use the core frequency which may change from time to time. CPU_CLK_UNHALTE.REF_TSC and CPU_CLK_UNHALTED.REF are not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. The fixed events are CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.REF_TSC and the programmable events are CPU_CLK_UNHALTED.CORE_P and CPU_CLK_UNHALTED.REF Counts demand & prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0240 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0120 Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded umask=0x1,period=100003,event=0xb7,offcore_rsp=0x4003c0122 Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded offcore_requests.demand.read_data offcore_requests_outstanding.demand.read_code REQUEST = ANY_REQUEST and RESPONSE = IO_CSR_MMIO umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f22 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7f08 REQUEST = CORE_WB and RESPONSE = LOCAL_CACHE REQUEST = CORE_WB and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT offcore_response.demand_ifetch.local_dram_and_remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5002 REQUEST = OTHER and RESPONSE = ANY_CACHE_DRAM REQUEST = ANY_DATA read and RESPONSE = ANY_LLC_MISS offcore_response.any_rfo.any_dram_and_remote_fwd REQUEST = DEMAND_DATA and RESPONSE = REMOTE_DRAM REQUEST = DEMAND_IFETCH and RESPONSE = ANY_LLC_MISS offcore_response.pf_l1d_and_sw.any_response offcore_response.all_pf_data_rd.l3_hit.hit_other_core_no_fwd offcore_response.all_pf_rfo.l3_hit.hitm_other_core offcore_response.pf_l3_rfo.l3_hit.snoop_hit_with_fwd offcore_response.all_pf_data_rd.l3_hit.snoop_hit_with_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x103FC00490 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063B800490 Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server michroarchtecture). This includes high current AVX 512-bit instructions L2_Evictions_Silent_PKI unc_cha_requests.writes PCI Express bandwidth writing at IIO, part 1. Unit: uncore_iio unc_cha_dir_update.ha unc_cha_snoop_resp.rspcnflcts unc_iio_data_req_by_cpu.mem_write.part0 unc_iio_data_req_by_cpu.mem_write.part2 fc_mask=0x07,ch_mask=0x01,umask=0x04,event=0xc1 Write request of up to a 64 byte transaction is made by IIO Part3 to Memory. Unit: uncore_iio unc_m2m_imc_reads.normal This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.SNOOP_MISS This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0004 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0000010002 offcore_response.pf_l3_data_rd.pmm_hit_local_pmm.snoop_not_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800080001 offcore_response.all_pf_data_rd.l3_hit_s.snoop_miss This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080200001 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020002 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020020 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80020400 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0490 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100080120 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800100080 offcore_response.demand_data_rd.l3_hit_f.hit_other_core_no_fwd offcore_response.all_rfo.l3_hit_s.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100122 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080408000 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00803C0080 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000100400 offcore_response.pf_l2_data_rd.l3_hit_f.hit_other_core_fwd This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE offcore_response.pf_l2_data_rd.l3_hit_s.no_snoop_needed offcore_response.pf_l2_rfo.l3_hit_s.snoop_miss offcore_response.all_pf_rfo.l3_hit_s.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200200001 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE offcore_response.all_pf_rfo.l3_hit_m.hit_other_core_no_fwd offcore_response.all_data_rd.l3_hit_s.hit_other_core_no_fwd offcore_response.pf_l2_data_rd.l3_hit_s.snoop_none This event is deprecated. Refer to new event OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED period=100003,umask=0x4f,event=0x2e This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l2_data_rd.l3_hit_m.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08003C0080 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD offcore_response.demand_code_rd.l3_hit_m.hit_other_core_fwd offcore_response.all_pf_data_rd.supplier_none.hitm_other_core This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE offcore_response.demand_data_rd.l3_hit_m.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800040080 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD offcore_response.all_pf_data_rd.supplier_none.hit_other_core_fwd This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD offcore_response.pf_l2_data_rd.l3_hit_e.snoop_miss This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE offcore_response.all_reads.l3_hit.snoop_hit_with_fwd offcore_response.all_pf_data_rd.l3_hit_m.snoop_miss This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE offcore_response.all_reads.l3_hit_e.snoop_none This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200080002 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.ANY_SNOOP clx metrics period=100007,umask=0x1,event=0xc6,frontend=0x11 cmask=1,period=2000003,umask=0x18,event=0x79 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000020 Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C000004 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS ocr.all_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd offcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd ocr.demand_code_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000010 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS ocr.demand_code_rd.l3_miss_local_dram.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0110000122 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C0007F7 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000020 Counts all demand data writes (RFOs) DEMAND_RFO & L3_MISS & HIT_OTHER_CORE_FWD Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x023C000100 ocr.demand_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd Counts demand data reads DEMAND_DATA_RD & L3_MISS & ANY_SNOOP ALL_PF_DATA_RD & L3_MISS_LOCAL_DRAM & NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000100 ALL_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISS_OR_NO_FWD ALL_PF_DATA_RD & L3_MISS_LOCAL_DRAM & HITM_OTHER_CORE Counts all demand data writes (RFOs) DEMAND_RFO & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_NO_FWD Counts any other requests OTHER & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_FWD Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS & HITM_OTHER_CORE Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS_LOCAL_DRAM & HIT_OTHER_CORE_NO_FWD ocr.all_pf_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000122 offcore_response.other.l3_miss_remote_hop1_dram.snoop_none ALL_READS & L3_MISS & REMOTE_HIT_FORWARD Counts all demand code reads DEMAND_CODE_RD & L3_MISS_REMOTE_DRAM & SNOOP_MISS_OR_NO_FWD offcore_response.pf_l1d_and_sw.l3_miss_local_dram.hit_other_core_no_fwd Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD offcore_response.all_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd ALL_PF_RFO & L3_MISS_LOCAL_DRAM & SNOOP_MISS_OR_NO_FWD This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.snoop_miss This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.hitm_other_core ocr.other.l3_miss.hitm_other_core Counts any other requests OTHER & L3_MISS & HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD ocr.pf_l1d_and_sw.l3_miss.hitm_other_core offcore_response.all_rfo.l3_miss_remote_hop1_dram.hitm_other_core Counts all demand code reads DEMAND_CODE_RD & L3_MISS & HIT_OTHER_CORE_FWD ocr.all_rfo.l3_miss.hitm_other_core ocr.other.l3_miss.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS ocr.all_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP ALL_RFO & L3_MISS_REMOTE_HOP1_DRAM & SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWD ocr.all_reads.l3_miss_remote_hop1_dram.no_snoop_needed This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l1d_and_sw.l3_miss.snoop_miss Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS_LOCAL_DRAM & HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD ALL_READS & L3_HIT_F & NO_SNOOP_NEEDED Counts demand data reads DEMAND_DATA_RD & L3_HIT_S & HIT_OTHER_CORE_NO_FWD period=100003,umask=0x4,event=0xfe Counts all demand code reads DEMAND_CODE_RD & L3_HIT & HITM_OTHER_CORE ocr.other.l3_hit.hit_other_core_no_fwd ALL_RFO & L3_HIT & SNOOP_MISS ocr.all_reads.supplier_none.hit_other_core_fwd ocr.all_rfo.any_response ocr.all_data_rd.l3_hit_s.no_snoop_needed Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_S & HITM_OTHER_CORE ocr.demand_rfo.l3_hit_m.any_snoop ocr.demand_data_rd.l3_hit.no_snoop_needed Counts all demand code reads DEMAND_CODE_RD & L3_HIT_F & HIT_OTHER_CORE_FWD ALL_PF_RFO & PMM_HIT_LOCAL_PMM & SNOOP_NONE ocr.pf_l2_rfo.l3_hit_f.hitm_other_core ocr.all_data_rd.l3_hit.hitm_other_core ALL_PF_DATA_RD & L3_HIT_M & SNOOP_NONE ocr.all_pf_rfo.l3_hit_m.hit_other_core_no_fwd ocr.pf_l1d_and_sw.l3_hit_s.snoop_none ocr.all_reads.l3_hit_f.snoop_none ocr.pf_l2_data_rd.l3_hit_f.no_snoop_needed ocr.all_pf_rfo.l3_hit_e.snoop_none ocr.demand_rfo.l3_hit_e.hit_other_core_no_fwd ocr.demand_code_rd.l3_hit_m.snoop_miss Counts demand data reads DEMAND_DATA_RD & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDED ocr.all_data_rd.l3_hit_e.hit_other_core_no_fwd ocr.pf_l3_rfo.supplier_none.snoop_none ocr.all_reads.l3_hit_m.hitm_other_core ocr.demand_rfo.l3_hit_s.snoop_miss ocr.all_pf_rfo.supplier_none.no_snoop_needed ocr.all_data_rd.l3_hit.snoop_miss Counts any other requests OTHER & L3_HIT_M & HIT_OTHER_CORE_NO_FWD ocr.pf_l3_rfo.l3_hit_e.hit_other_core_no_fwd ALL_RFO & L3_HIT_E & HITM_OTHER_CORE Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_E & HIT_OTHER_CORE_FWD ocr.pf_l1d_and_sw.l3_hit_e.hit_other_core_fwd period=2000003,umask=0x1,event=0xa1 cmask=20,period=2000003,umask=0x14,event=0xa3 DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode. Unit: uncore_imc All Reads - RPQ or Ufill Counts number of allocations per cycle into the specified Ingress queue unc_cha_sf_eviction.s_state Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus fc_mask=0x07,ch_mask=0x04,umask=0x08,event=0x83 fc_mask=0x07,ch_mask=0x08,umask=0x08,event=0x83 fc_mask=0x07,ch_mask=0x04,umask=0x08,event=0xc1 Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part1 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus Peer to peer read request of up to a 64 byte transaction is made by IIO Part2 to an IIO target. Unit: uncore_iio fc_mask=0x07,ch_mask=0x08,umask=0x08,event=0x84 unc_iio_txn_req_of_cpu.peer_write.part3 umask=0x08,event=0x2c period=100003,umask=0xe,event=0x8 Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 RANGE FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector) umask=0x1,period=100003,cmask=1,edge=1,event=0xc3 br_misp_retired.indirect Counts all miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch) Supports address when precise (Precise event) TOR Inserts; DRd Opt misses from local IA. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_rfo Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 uncore_ubox L1 BTB Correction ic_cache_fill_sys l2_request_g2.bus_locks_responses Core to L2 cacheable request access status (not including L2 Prefetch). Data cache read hit in L2 l2_cache_req_stat.ls_rd_blk_c All L3 Request Types. Unit: uncore_l3pmc ex_ret_instr event=0xc2 Retired Branch Instructions umask=0x2,event=0xcb umask=0xAA,event=0x8b umask=0x08,event=0x8b df_ccm_reqa.node4.rdsizednc umask=0x84,event=0x8b df_ccm_reqa.node2.rdvlks df_ccm_reqa.node0.rdvlkl Data Fabric CCM Performance Monitor Event DF CCM Request Ordered vicblkfullzero df_ccm_reqb.node6.vicblkfullzero umask=0x8A,event=0x8c umask=0x09,event=0x8c umask=0x04,event=0x8c umask=0x84,event=0x8c df_ccm_reqb.node0.wrsizedfullncposted df_ccm_reqb.node6.wrsizedncposted umask=0x01,event=0x8c umask=0x21,event=0x8c df_ccm_reqb.node3.rdsized df_ioms_reqa.node1.anydramtransaction Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized=64b df_ioms_reqa.node5.anywrsized=64b umask=0xA6,event=0x108 umask=0x84,event=0x108 umask=0xC3,event=0x108 umask=0x8F,event=0x109 umask=0xAE,event=0x109 df_ioms_reqb.node6.piesystemmanagement umask=0x89,event=0x109 umask=0xA9,event=0x109 df_ioms_reqb.node6.ioanynon-postedwrsized=32b df_ioms_reqb.node6.ioanynon-postedwrsized<32b umask=0xE6,event=0x109 umask=0x02,event=0x109 umask=0x40,event=0 Total number multi-pipe uOps assigned to pipe 0 The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to all pipes The number of x87 floating-point Ops that have retired. The number of events logged per cycle can vary from 0 to 8. Multiply Ops The number of x87 floating-point Ops that have retired. The number of events logged per cycle can vary from 0 to 8. Add/subtract Ops umask=0x80,event=0x3 l3_request_g1.t0.s0.wrsized l3_thread_mask=0x10,l3_slice_mask=0x01,umask=0x04,event=0x1 l3_request_g1.t3.s2.wrsized l3_request_g1.t1.s1.rdsizednc l3_thread_mask=0x04,l3_slice_mask=0x02,umask=0x20,event=0x1 l3_request_g1.t2.s0.rdsized l3_request_g1.t3.s1.rdsized l3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x80,event=0x1 l3_request_g1.t7.s1.caching l3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x80,event=0x1 l3_request_g1.t0.s3.caching l3_thread_mask=0x10,l3_slice_mask=0x08,umask=0x80,event=0x1 l3fillvicreq.t6.s2.vicblk l3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x02,event=0x3 l3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x02,event=0x3 l3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x04,event=0x3 l3_thread_mask=0x20,l3_slice_mask=0x08,umask=0x04,event=0x3 l3fillvicreq.t1.s2.rdblkx_vic l3fillvicreq.t4.s1.rdblkx l3fillvicreq.t4.s3.rdblkx l3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x20,event=0x3 l3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x40,event=0x3 L3 Cache Performance Monitor Counters L3 Victim State l3victimstate.t1.s1.nol3victimline l3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x01,event=0x9 l3victimstate.t7.s0.none_nol3victimline l3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x02,event=0x9 l3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x02,event=0x9 l3victimstate.t0.s2.f_s l3victimstate.t2.s2.f_s l3victimstate.t4.s3.f_s l3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x04,event=0x9 l3victimstate.t5.s1.e_fe l3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x10,event=0x9 l3victimstate.t0.s3.e_fe l3victimstate.t0.s2.m l3victimstate.t3.s0.d l3_thread_mask=0x10,l3_slice_mask=0x02,umask=0x40,event=0x9 l3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x40,event=0x9 l3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x40,event=0x9 l3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x40,event=0x9 l3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x80,event=0x9 l3victimstate.t4.s1.od l3victimstate.t1.s3.od umask=0x4,event=0x29 ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit Cycles not in Halt umask=0xff,event=0x72 Number of SSE Move Ops. This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes umask=0x2,event=0xe Number of loads dispatched. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed L1 DTLB Miss. DTLB reload coalesced page miss de_dis_dispatch_token_stalls1.load_queue_token_stall BU_CPU_CLK_UNHALTED IC_REFILL_FROM_L2 FR_DECODER_EMPTY CYCLES_NONIDLE_NEON_INT LOAD_STORE_PIPE DSB SW_INCR CHAIN LD_RETIRED L1D_CACHE_WB_VICTIM EXC_PABORT EXC_SMC EXC_TRAP_OTHER L3D_CACHE MEM_WORD_WRITE JTLB_IACCESS RF_CYCLES_STALLED DC_BLOCKED_CYCLES CP2_STALL_CYCLES LDQ_FULL_PIPELINE_STALLS SINGLE_ISSUE_CYCLES DCACHE_LINE_REFILL_REQUESTS LDQ_FULL_STALLS SC_INSNS TWO_INSNS_CYCLES LDQ_LESS_25_FULL L1_INSTR_CACHE_MISSES LOAD_MISS_ALIAS_ON_TOUCH L1_DATA_STORE_HIT LSU_CSQ_FORWARDING SYNC_INSTR_COMPLETED RUN_CYCLES GROUP_COMPLETED PM_EVENT_CYCLES BRANCH_INSTRS_COMPLETED CYCLES_LRU_SCHED_STALLED LOAD_MISS_LDQ_FULL_CYCLES INTERRUPTS_TAKEN L2_CACHE_DATA_HITS L2_CACHE_INSTR_ACCESSES FPU_INPUT_DATA_STALLS dirty-l2-victim scalar-sse-sse2 sse-retype-microfaults XSCALE OCTEON PPC970 E500 br_inst_retired.all_branches UNC_ uncore GenuineIntel-6-3D GenuineIntel-6-4F GenuineIntel-6-26 GenuineIntel-6-27 GenuineIntel-6-85 GenuineIntel-6-1E GenuineIntel-6-4C AuthenticAMD-23-[012][0-9A-F] C6 residency percent per core C7 residency percent per core offcore_requests_outstanding.cycles_with_demand_rfo offcore_requests.demand_code_rd Retired load uops with L1 cache hits as data sources. (Precise Event - PEBS) Supports address when precise (Precise event) This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data source were hits in the nearest-level (L1) cache.
Note: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. This event also counts SW prefetches independent of the actual data source Supports address when precise (Precise event) mem_load_uops_retired.hit_lfb This event counts the number of L2 cache accesses when fetching instructions l2_trans.all_pf This event counts the number of L2 cache lines in the Invalidate state filling the L2. Counting does not cover rejects fp_assist.simd_input idq.mite_cycles Cycles MITE is delivering any Uop idq.ms_cycles umask=0x30,cmask=1,period=2000003,event=0x79 Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts) Number of times RTM aborted and was not due to the abort conditions in subevents 3-6 This event counts loads with latency value being above 256 Spec update: BDM100, BDM35 (Must be precise) ld_blocks_partial.address_alias Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread umask=0x10,period=2000003,event=0xe uops_issued.single_mul This event counts the number of the divide operations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DIV_ACTIVE to get the number of the divide operations executed umask=0x2,period=100003,event=0x4c umask=0x41,period=200003,event=0x88 Speculative and retired macro-unconditional branches excluding calls and indirects This event counts both taken and not taken speculative and retired indirect branches that have a return mnemonic uops_executed_port.port_2 umask=0x10,period=2000003,event=0xa1 umask=0x80,period=2000003,event=0xa1 Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand* load request missing the L2 cache.(as a footprint) * includes also L1 HW prefetch requests that may or may not be required by demands umask=0xc,cmask=12,period=2000003,event=0xa3 lsd.uops This event counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread uops_retired.all This is a precise version (that is, uses PEBS) of the event that counts both direct and indirect macro near call instructions retired (captured in ring 3) (Precise event) br_inst_retired.near_taken br_misp_retired.near_taken LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox PCIe write references (full cache line). Derived from unc_c_tor_inserts.opcode. Unit: uncore_cbox umask=0x4,event=0x1 Conflict requests (requests for same address from multiple agents simultaneously). Unit: uncore_ha umask=0x8,event=0x21 Counts the number of cycles when power is the upper limit on frequency. Unit: uncore_pcu unc_p_freq_trans_cycles dtlb_store_misses.walk_completed_1g Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. SMT version; use when SMT is enabled and measuring per logical CPU IpB L2 cache true misses per kilo instruction for retired demand loads offcore_response.demand_data_rd.supplier_none.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F80020020 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C0040 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0040 Counts all prefetch (that bring data to LLC only) data reads umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0080 offcore_response.other.supplier_none.snoop_miss offcore_response.other.l3_hit.snoop_miss offcore_response.other.l3_hit.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100020090 Counts prefetch RFOs have any response type umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F803C0240 offcore_response.all_rfo.supplier_none.snoop_hitm offcore_response.all_rfo.l3_hit.any_snoop Number of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. (RSQRT for single-precision?) umask=0x10,period=2000003,cmask=1,event=0x79 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0204000004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000008 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x00BC000020 offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000020100 offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_hit_no_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3F84000200 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0084008000 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000090 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0120 offcore_response.all_pf_rfo.l3_miss.snoop_not_needed offcore_response.all_data_rd.l3_miss.snoop_none umask=0x3,period=2000003,cmask=1,event=0xd inv=1,umask=0x1,period=2000003,cmask=1,event=0xb1 unc_cbo_xsnp_response.hit_xcore unc_cbo_cache_lookup.write_mesi Unit: uncore_arb Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic umask=0x20,event=0x81 ( itlb_misses.walk_duration + dtlb_load_misses.walk_duration + dtlb_store_misses.walk_duration + 7 * ( dtlb_store_misses.walk_completed + dtlb_load_misses.walk_completed + itlb_misses.walk_completed ) ) / ( 2 * cycles ) Data from local DRAM either Snoop not needed or Snoop Miss (RspI) Supports address when precise. Spec update: BDE70, BDM100 (Precise event) Counts prefetch (that bring data to LLC only) code reads hit in the L3 Cycles the L2 transfers data to the core l2_ld.self.prefetch.mesi umask=0xa2,period=2000000,event=0x40 umask=0x1,period=200000,event=0xcb simd_uop_type_exec.unpack.ar umask=0x90,period=2000000,event=0xb3 CISC macro instructions decoded uops.ms_cycles umask=0x97,period=200000,event=0x5 Nonzero segbase store 1 bubble bus_data_rcv.self bus_trans_mem.self ext_snoop.all_agents.any All store forwards Retired branch instructions BACLEARS asserted Counts the number of demand and L1 prefetcher requests rejected by the L2Q due to a full or nearly full condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to ensure fairness between cores, or to delay a core's dirty eviction when the address conflicts with incoming external snoops umask=0x8,period=200003,event=0xd1 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200000022 Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required umask=0x1,period=100007,event=0xb7,offcore_rsp=0x3600000010 Counts the number of writeback transactions caused by L1 or L2 cache evictions that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) References per ICache line that are not available in the ICache (miss). This event counts differently than Intel processors based on Silvermont microarchitecture issue_slots_not_consumed.any umask=0x4,period=200003,event=0xcb Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1. You cannot collect a PEBs record for this event All machine clears Counts machine clears for any reason Retired far branch instructions (Precise event capable) (Must be precise) Counts near indirect call or near indirect jmp branch instructions retired (Must be precise) br_misp_retired.non_return_ind Counts the number of writeback transactions caused by L1 or L2 cache evictions true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts reads for ownership (RFO) requests generated by L2 prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts bus lock and split lock requests true miss for the L2 cache with a snoop miss in the other processor module offcore_response.bus_locks.outstanding Counts data cache lines requests by software prefetch instructions have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cache lines requests by software prefetch instructions outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts INST_RETIRED.ANY using the Reduced Skid PEBS feature that reduces the shadow in which events aren't counted allowing for a more unbiased distribution of samples across instructions retired (Must be precise) umask=0x21,period=100003,event=0xd0 Retired load uops that split across a cacheline boundary. (precise Event) Spec update: HSD29, HSM30. Supports address when precise (Precise event) offcore_response.demand_data_rd.l3_hit.hit_other_core_no_fwd input - Invalid Operation, Denormal Operand, SNaN Operand (Precise event) ( uops_executed.core / 2 / (( cpu@uops_executed.core\,cmask\=1@ / 2 ) if #smt_on else cpu@uops_executed.core\,cmask\=1@) ) if #smt_on else uops_executed.core / (( cpu@uops_executed.core\,cmask\=1@ / 2 ) if #smt_on else cpu@uops_executed.core\,cmask\=1@) Number of times an HLE execution aborted due to any reasons (multiple categories may count as one) (Precise event) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FFFC08FFF offcore_response.demand_rfo.l3_miss.local_dram inv=1,umask=0x1,any=1,period=2000003,cmask=1,event=0xe ild_stall.iq_full Cycles where at least 1 uop was executed per-thread Spec update: HSD144, HSD30, HSM31 Counts total number of uops to be executed per-core each cycle Spec update: HSD30, HSM31 An external snoop hits a modified line in some processor core unc_cbo_xsnp_response.hitm_eviction Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K) This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses umask=0x81,period=2000003,event=0xbc umask=0x88,period=2000003,event=0xbc Retired load uops that split across a cacheline boundary Supports address when precise. Spec update: HSD29, HSM30 (Precise event) umask=0x1,period=200003,event=0x24 Requests from the L2 hardware prefetchers that miss L2 cache Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.) offcore_requests_outstanding.cycles_with_demand_code_rd Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore Cases when offcore requests buffer cannot take more entries for core Retired load uops whose data source was local memory (cross-socket snoop not needed or missed) Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003c0002 dsb_fill.exceed_dsb_lines Counts demand data reads that miss the LLC and the data returned from dram unc_cbo_xsnp_response.hit unc_cbo_xsnp_response.eviction_filter Unit: uncore_arb Cycles weighted by number of requests pending in Coherency Tracker Misses in all ITLB levels that cause page walks Counts all prefetch data reads that hit the LLC offcore_response.all_reads.llc_hit.no_snoop_needed Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded umask=0x3,event=0x35,filter_opc=0x19c umask=0x3,event=0x35,filter_opc=0x1e6 PCIe non-snoop reads. Derived from unc_c_tor_inserts.opcode.pcie_read. Unit: uncore_cbox dtlb_load_misses.demand_ld_walk_duration This event counts the number of store uops retired (Precise event) umask=0x1,period=100003,event=0xb6 umask=0xf,period=2000003,event=0x5b Cycles with either free list is empty umask=0xf0,period=2000003,event=0xa2 Counts the total number of L2 cache references umask=0x40,period=200003,event=0x4 umask=0x80,period=200003,event=0x4 Counts the matrix events specified by MSR_OFFCORE_RESPx umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400070 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400022 Counts all streaming stores (WC and should be programmed on PMC1) that accounts for any response offcore_response.pf_l1_data_rd.l2_hit_near_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000081000 offcore_response.pf_software.l2_hit_near_tile_e_f Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in M state offcore_response.any_read.l2_hit_this_tile_m offcore_response.any_pf_l2.l2_hit_this_tile_m umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0004000070 offcore_response.bus_locks.l2_hit_this_tile_s Counts Demand code reads and prefetch code read requests that accounts for responses which hit its own tile's L2 with data in S state umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000044 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800400004 offcore_response.pf_l2_code_rd.l2_hit_far_tile offcore_response.any_pf_l2.ddr_near offcore_response.bus_locks.mcdram_far offcore_response.demand_rfo.ddr_far offcore_response.demand_data_rd.mcdram Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from DDR (local and far) offcore_response.pf_l1_data_rd.ddr Counts any request that accounts for responses from DDR (local and far) This event counts the number of core cycles when no uops are allocated, the instruction queue is empty and the alloc pipe is stalled waiting for instructions to be fetched umask=0x1,period=2000003,event=0xcd This event counts the number of retired store that experienced a cache line boundary split(Precise Event). Note that each spilt should be counted only once umask=0x80,period=200003,event=0x3 umask=0x01,event=0x1 L1D cache lines replaced in M state umask=0x4,period=2000000,event=0x42 umask=0x1,period=2000000,event=0x52 umask=0x2,period=2000000,event=0x41 umask=0x1,period=200000,event=0xf0 umask=0x8,period=200000,event=0xf0 Retired loads that hit the L1 data cache (Precise Event) Memory instructions retired above 64 clocks (Precise Event) umask=0x1,period=100000,event=0xb7,offcore_rsp=0x744 Offcore writebacks to any cache or DRAM Offcore code or data read requests satisfied by any cache or DRAM offcore_response.data_ifetch.llc_hit_other_core_hit Offcore code or data read requests satisfied by a remote cache or remote DRAM umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1077 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x233 offcore_response.demand_data_rd.any_cache_dram offcore_response.demand_data_rd.remote_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x780 offcore_response.other.local_cache_dram offcore_response.pf_data.local_cache_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF10 offcore_response.pf_rfo.remote_cache_hitm fp_assist.all fp_comp_ops_exe.sse2_integer umask=0x8,period=2000000,event=0x10 offcore_response.data_in.any_dram umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2002 offcore_response.other.remote_dram offcore_response.pf_data_rd.any_llc_miss umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2020 bpu_missed_call_ret L1I instruction fetch misses rat_stalls.any umask=0x4,period=2000000,event=0xd2 umask=0x1,period=2000000,event=0xa7 umask=0x8,period=2000,event=0x89 lsd.inactive inv=1,umask=0x1f,any=1,period=2000000,cmask=1,edge=1,event=0xb1 inv=1,umask=0x1,period=2000000,cmask=16,event=0xc2 umask=0x20,period=200000,event=0x8 DTLB misses Core-originated cacheable demand requests missed L3 Spec update: SKL057 Counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.Note: A prefetch promoted to Demand is counted from the promotion point Retired store instructions that split across a cacheline boundary. (Precise Event) Supports address when precise Counts L2 writebacks that access L2 cache offcore_response.demand_code_rd.l4_hit_local_l4.snoop_hitm offcore_response.demand_code_rd.l3_hit_s.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400080004 offcore_response.demand_code_rd.supplier_none.spl_hit umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0400400002 offcore_response.demand_rfo.l4_hit_local_l4.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x1000020002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200400001 offcore_response.demand_data_rd.l4_hit_local_l4.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080080001 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040080001 Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB) frontend_retired.dsb_miss frontend_retired.itlb_miss umask=0x1,period=100007,event=0xc6,frontend=0x14 frontend_retired.latency_ge_64 Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency (Must be precise) offcore_response.other.l3_miss.snoop_hitm offcore_response.demand_code_rd.l3_hit_m.snoop_non_dram offcore_response.demand_rfo.l3_miss_local_dram.snoop_not_needed offcore_response.demand_rfo.l3_hit_s.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x203C400001 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2000080001 sw_prefetch_access.t1_t2 arith.divider_active umask=0x14,period=2000003,cmask=20,event=0xa3 All (macro) branch instructions retired Spec update: SKL091 (Must be precise) Number of retired PAUSE instructions (that do not end up with a VMExit to the VMM; TSX aborted Instructions may be counted). This event is not supported on first SKL and KBL products Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake microarchitecture Loads hit L2 (Precise event) umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200000044 Counts any data read (demand & prefetch) that miss L2 Counts any request that miss L2 with a snoop miss response offcore_response.pf_l1_data_rd.l2_miss.snoop_miss Counts demand and DCU prefetch data read that miss L2 with a snoop miss response IND_CALL counts the number of near indirect CALL branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) D-side page-walks offcore_response.all_pf_rfo.llc_hit.hit_other_core_no_fwd Counts prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2003c0120 REQUEST = PF_RFO and RESPONSE = ANY_RESPONSE Number of any page walk that had a miss in LLC. Does not necessary cause a SUSPEND This event counts any requests that miss the LLC where the data was returned from local DRAM umask=0x1,period=100003,event=0xb7,offcore_rsp=0x17004001b3 This event counts the number of micro-ops retired. (Precise Event) (Precise event) umask=0x1,period=100000,event=0xb7,offcore_rsp=0x5011 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7fff umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7ff offcore_response.corewb.llc_hit_other_core_hit REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HIT REQUEST = DATA_IN and RESPONSE = REMOTE_CACHE_HITM REQUEST = DEMAND_RFO and RESPONSE = REMOTE_CACHE_HITM REQUEST = PF_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = PF_DATA and RESPONSE = REMOTE_CACHE_HITM umask=0x1,period=100000,event=0xb7,offcore_rsp=0xff10 REQUEST = ANY IFETCH and RESPONSE = ANY_LLC_MISS umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3022 REQUEST = CORE_WB and RESPONSE = REMOTE_DRAM REQUEST = DEMAND_DATA_RD and RESPONSE = OTHER_LOCAL_DRAM offcore_response.pf_data_rd.other_local_dram REQUEST = PREFETCH and RESPONSE = OTHER_LOCAL_DRAM Loads that partially overlap an earlier store umask=0x4,period=2000000,cmask=1,event=0xb3 ITLB miss page walk cycles umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2703 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F50 umask=0x4,period=40000,event=0xf mem_load_l3_miss_retired.remote_dram mem_load_l3_miss_retired.remote_fwd umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3FBC000004 Counts all prefetch (that bring data to L2) RFOs TBD offcore_response.all_pf_rfo.l3_miss.remote_hitm offcore_response.all_rfo.l3_miss.remote_hit_forward offcore_response.all_rfo.l3_miss.snoop_miss_or_no_fwd core_power.lvl0_turbo_license L2_Evictions_NonSilent_PKI umask=0x21,event=0x35,config1=0x40041e33 fc_mask=0x07,ch_mask=0x01,umask=0x01,event=0xc0 fc_mask=0x07,ch_mask=0x01,umask=0x01,event=0xc1 unc_iio_txn_req_of_cpu.mem_read.part3 Number of reads that a message sent direct2 Intel UPI was overridden. Unit: uncore_m2m unc_m2m_directory_update.s2a Counts when the M2M (Mesh to Memory) issues reads to the iMC (Memory Controller). It only counts normal priority non-isochronous reads Counts when the M2M (Mesh to Memory) issues writes to the iMC (Memory Controller) unc_upi_rxl_flits.all_null FLITs that bypassed the TxL Buffer. Unit: uncore_upi ll period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200491 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.SNOOP_NONE offcore_response.demand_data_rd.l3_hit_s.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400020491 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200120 offcore_response.all_data_rd.supplier_none.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10003C0122 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000200490 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100020120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE offcore_response.pf_l3_rfo.supplier_none.hit_other_core_fwd period=200003,umask=0xc2,event=0x24 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400080100 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80080100 offcore_response.pf_l2_data_rd.l3_hit_f.snoop_none period=100003,umask=0x1,event=0xb7,offcore_rsp=0x10000807F7 offcore_response.demand_code_rd.l3_hit_e.no_snoop_needed This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE offcore_response.demand_rfo.l3_hit_m.hitm_other_core offcore_response.demand_code_rd.l3_hit_s.hit_other_core_fwd This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE offcore_response.pf_l2_rfo.l3_hit_e.snoop_miss offcore_response.pf_l3_rfo.supplier_none.no_snoop_needed This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED offcore_response.pf_l3_rfo.l3_hit_e.snoop_none This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020490 offcore_response.all_rfo.l3_hit_e.snoop_none offcore_response.pf_l3_data_rd.l3_hit_s.no_snoop_needed This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD offcore_response.demand_code_rd.l3_hit_s.hitm_other_core This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l2_rfo.pmm_hit_local_pmm.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80400020 offcore_response.all_pf_rfo.supplier_none.hitm_other_core This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS offcore_response.all_pf_data_rd.l3_hit_s.snoop_none This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE Counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread. b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions). c. Instruction Decode Queue (IDQ) delivers four uops period=100007,umask=0x1,event=0xc6,frontend=0x420006 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x013C000100 ocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.any_snoop Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_MISS_REMOTE_HOP1_DRAM & ANY_SNOOP offcore_response.demand_code_rd.l3_miss.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000100 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD ocr.pf_l1d_and_sw.l3_miss.snoop_miss ocr.demand_data_rd.l3_miss_local_dram.snoop_none This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED ocr.demand_code_rd.l3_miss.remote_hit_forward period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0104000080 Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & L3_MISS & SNOOP_MISS ALL_RFO & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_NO_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0410000020 offcore_response.demand_rfo.l3_miss.hitm_other_core ocr.demand_code_rd.l3_miss_local_dram.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE ocr.pf_l2_rfo.l3_miss_local_dram.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000020 ocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.any_snoop Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS & NO_SNOOP_NEEDED ALL_PF_RFO & L3_MISS & SNOOP_MISS offcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.snoop_miss period=2000003,umask=0x4,event=0xc9 Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS_LOCAL_DRAM & SNOOP_MISS_OR_NO_FWD ocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM ocr.other.l3_miss_remote_hop1_dram.any_snoop offcore_response.pf_l3_data_rd.l3_miss.hit_other_core_fwd Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS & REMOTE_HIT_FORWARD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000020 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x103C008000 offcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd ALL_READS & L3_MISS_REMOTE_HOP1_DRAM & SNOOP_MISS This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP ocr.pf_l2_data_rd.l3_miss.remote_hitm ocr.all_rfo.l3_miss.hit_other_core_no_fwd ocr.all_pf_data_rd.l3_miss_local_dram.snoop_miss This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_NONE This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x083C008000 ocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hit_other_core_fwd ocr.all_data_rd.l3_miss_remote_hop1_dram.hitm_other_core offcore_response.all_rfo.l3_miss_remote_hop1_dram.any_snoop offcore_response.pf_l1d_and_sw.l3_miss_local_dram.hit_other_core_fwd ocr.all_pf_rfo.l3_hit_s.any_snoop Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & SUPPLIER_NONE & HIT_OTHER_CORE_NO_FWD Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_E & HIT_OTHER_CORE_NO_FWD ocr.demand_rfo.l3_hit_e.snoop_none Counts any other requests OTHER & L3_HIT & HIT_OTHER_CORE_NO_FWD ALL_PF_DATA_RD & L3_HIT_S & HIT_OTHER_CORE_FWD ocr.pf_l3_data_rd.l3_hit.snoop_none Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT & HITM_OTHER_CORE ocr.pf_l2_data_rd.l3_hit_m.no_snoop_needed Counts prefetch (that bring data to L2) data reads PF_L2_DATA_RD & SUPPLIER_NONE & NO_SNOOP_NEEDED ALL_PF_RFO & L3_HIT & SNOOP_MISS ocr.all_reads.supplier_none.snoop_none ALL_RFO & L3_HIT & HIT_OTHER_CORE_NO_FWD ocr.pf_l3_rfo.l3_hit_m.hitm_other_core ocr.pf_l1d_and_sw.l3_hit_m.snoop_none ocr.demand_rfo.l3_hit_m.snoop_none ocr.all_data_rd.l3_hit.hit_other_core_no_fwd Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_S & HIT_OTHER_CORE_NO_FWD ocr.pf_l1d_and_sw.supplier_none.hitm_other_core ocr.pf_l3_rfo.l3_hit_m.any_snoop Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT & SNOOP_NONE Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_HIT_F & HIT_OTHER_CORE_FWD ocr.all_reads.l3_hit_s.no_snoop_needed ALL_DATA_RD & L3_HIT & HIT_OTHER_CORE_FWD ocr.all_pf_rfo.l3_hit_f.snoop_miss Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT & HIT_OTHER_CORE_FWD ocr.pf_l3_rfo.l3_hit.any_snoop ocr.pf_l3_data_rd.l3_hit_f.snoop_none ocr.all_reads.supplier_none.hitm_other_core ALL_DATA_RD & L3_HIT_M & ANY_SNOOP Counts any other requests hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores ALL_PF_RFO & L3_HIT_F & HITM_OTHER_CORE period=2000003,umask=0x8,event=0x32 ocr.pf_l2_rfo.l3_hit_s.hit_other_core_fwd ALL_PF_DATA_RD & L3_HIT_E & HIT_OTHER_CORE_NO_FWD ocr.demand_code_rd.l3_hit_s.snoop_none ocr.all_pf_rfo.pmm_hit_local_pmm.snoop_not_needed This event counts both direct and indirect near call instructions retired Spec update: SKL091 (Precise event) cmask=1,period=2000003,umask=0x1,event=0x14 cmask=1,edge=1,inv=1,period=2000003,umask=0x1,event=0x5e period=2000003,umask=0x1,event=0xa8 period=2000003,umask=0x2,event=0xe period=100007,umask=0x8,event=0xc4 All hits to Near Memory(DRAM cache) in Memory Mode. Unit: uncore_imc Snoop filter capacity evictions for M-state entries. Unit: uncore_cha Snoop filter capacity evictions for S-state entries. Unit: uncore_cha Peer to peer write request of 4 bytes made to IIO Part1 by a different IIO unit. Unit: uncore_iio Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part3. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus Peer to peer read request of up to a 64 byte transaction is made by IIO Part1 to an IIO target. Unit: uncore_iio Peer to peer read request of up to a 64 byte transaction is made by IIO Part3 to an IIO target. Unit: uncore_iio BL Ingress (from CMS) Allocations l1d_pend_miss.l2_stall Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1 Supports address when precise (Precise event) Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 RANGE FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element Retired Instructions who experienced DSB miss (Precise event) Counts retired Instructions who experienced Instruction L2 Cache true miss (Precise event) Counts the number of times RTM commit succeeded umask=0x2,period=10000003,event=0xa4 Far branch instructions retired (Precise event) Number of page walks outstanding for an outstanding code request in the PMH each cycle cycles_div_busy.any umask=0xC001FE01,event=0x35,config1=0x40041e33 umask=0xC001FE01,event=0x35,config1=0x41a33 TOR Inserts; WCiLF misses from local IA. Unit: uncore_cha The number of 32B fetch windows tried to read the L1 IC and missed in the full tag event=0x99 All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized non-cacheable Total cycles spent waiting for L2 fills to complete from L3 or memory, divided by four. Event counts are for both threads. To calculate average latency, the number of fills from both threads must be used l2_cache_req_stat.ls_rd_blk_x SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX) umask=0x1,event=0x1cf umask=0x8F,event=0x8b umask=0x0C,event=0x8b df_ccm_reqa.node1.wrsized umask=0x2B,event=0x8b umask=0xC8,event=0x8b df_ccm_reqa.node0.rdvlkx umask=0xE1,event=0x8b df_ccm_reqb.node1.anyiorequest. df_ccm_reqb.node0.anywrsized Data Fabric CCM Performance Monitor Event DF CCM Request Ordered anywrsized umask=0xE4,event=0x8c umask=0xA3,event=0x8c umask=0x82,event=0x8c umask=0x41,event=0x8c umask=0xCA,event=0x108 df_ioms_reqa.node4.fence umask=0xC9,event=0x108 df_ioms_reqa.node6.anywrsized<32b umask=0x42,event=0x108 umask=0xCD,event=0x109 df_ioms_reqb.node3.ioanyatomic umask=0xAA,event=0x109 umask=0x09,event=0x109 df_ioms_reqb.node0.ioanynon-postedwrsized=32b df_ioms_reqb.node4.ioanypostedwrsized>32band<64b umask=0xC4,event=0x109 umask=0x43,event=0x109 Total number multi-pipe uOps assigned to pipe 3 umask=0x20,event=0 fpu_pipe_assignment.dual0 The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 2 fp_ret_sse_avx_ops.dp_add_sub_flops umask=0x1,event=0x3 Number of Scalar Ops optimized l3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x02,event=0x1 l3_request_g1.t1.s0.wrsized l3_thread_mask=0x20,l3_slice_mask=0x02,umask=0x04,event=0x1 l3_request_g1.t5.s2.wrsized l3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x04,event=0x1 l3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x04,event=0x1 l3_request_g1.t1.s3.rdsizednc l3_request_g1.t7.s0.rdsized l3_thread_mask=0x80,l3_slice_mask=0x08,umask=0x40,event=0x1 l3_request_g1.t0.s0.caching l3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x80,event=0x1 l3fillvicreq.t0.s1.vicblk l3_thread_mask=0x02,l3_slice_mask=0x02,umask=0x01,event=0x3 l3_thread_mask=0x80,l3_slice_mask=0x02,umask=0x01,event=0x3 l3fillvicreq.t4.s2.vicblk l3fillvicreq.t3.s3.vicblk l3_thread_mask=0x40,l3_slice_mask=0x02,umask=0x04,event=0x3 l3fillvicreq.t3.s2.rdblkc_s_vic l3fillvicreq.t7.s2.rdblkc_s_vic l3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x08,event=0x3 l3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x08,event=0x3 l3fillvicreq.t0.s0.rdblkx_vic l3fillvicreq.t6.s0.rdblkx_vic l3fillvicreq.t6.s1.rdblkx_vic l3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x10,event=0x3 l3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x20,event=0x3 l3fillvicreq.t1.s0.rdblkx l3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x20,event=0x3 l3fillvicreq.t4.s0.rdblkx l3fillvicreq.t6.s2.rdblkl l3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x01,event=0x9 l3victimstate.t3.s0.none_nol3victimline l3victimstate.t4.s2.f_s l3_thread_mask=0x20,l3_slice_mask=0x04,umask=0x04,event=0x9 l3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x08,event=0x9 l3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x08,event=0x9 l3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x10,event=0x9 l3victimstate.t0.s1.e_fe l3_thread_mask=0x10,l3_slice_mask=0x04,umask=0x10,event=0x9 l3_thread_mask=0x01,l3_slice_mask=0x08,umask=0x10,event=0x9 l3_thread_mask=0x80,l3_slice_mask=0x08,event=0x9 l3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x40,event=0x9 l3_thread_mask=0x80,l3_slice_mask=0x01,umask=0x40,event=0x9 l3victimstate.t6.s3.d l3_thread_mask=0x02,l3_slice_mask=0x01,umask=0x80,event=0x9 l3victimstate.t0.s1.od l3victimstate.t2.s1.od l3victimstate.t1.s2.od l3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x80,event=0x9 Counts the number of stores dispatched to the LS unit. Unit Masks ADDed ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss umask=0x1,event=0x45 umask=0x8,event=0x5a de_dis_dispatch_token_stalls1.int_phy_reg_file_token_stall BU_FILL_REQUEST_L2_MISS PC_WRITE MEM_UNALIGNED_ACCESS PC_BRANCH_PRED COHERENT_LINEFILL_MISSC PLD_STALL L3D_CACHE_REFILL ITLB_MISS DC_WRITEBACK JTLB_INSN_MISSES AGEN_EMPTY_CYCLES AGEN_OPERANDS_NOT_READY_CYCLES STORE_INSTR_COMPLETED FP_STORE_INSTR_COMPLETED_IN_LSU FPU_DENORMALIZATION LSU_MISALIGNED_LOAD_FINISH VTQ_STREAM_CANCELED_PREMATURELY VTQ_RESUMES_DUE_TO_CTX_CHANGE BPU_STALL_ON_LR_DEPENDENCY PREFETCH_ENGINE_COLLISION_VS_LOAD OVERFLOW FXU0_BUSY_FXU1_IDLE LSU_COMPLETION_STALL GCT_EMPTY_BY_ICACHE_MISS CYCLES_WITH_INSTRS_COMPLETED PM_EVENT_TRANSITIONS BTB_BRANCH_MISPRED_FROM_DIRECTION CYCLES_BU_SCHED_STALLED DATA_MMU_TLB4K_RELOADS L2_CACHE_CLEAN_REDUNDANT_UPDATES k8-fr-retired-x86-instructions UCF INTEL_WESTMERE ARMV7_CORTEX_A7 umask data fabric GenuineIntel-6-4D Uops Per Instruction Pipeline min( 1 , idq.mite_uops / ( uops_retired.retire_slots / inst_retired.any * 16 * ( icache.hit + icache.misses ) / 4.0 ) ) CPI SLOTS Turbo_Utilization (cstate_core@c6\-residency@ / msr@tsc@) * 100 C3 residency percent per package This event counts the number of requests from the L2 hardware prefetchers that miss L2 cache This event counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore Spec update: BDM76 This event counts the demand and prefetch data reads. All Core Data Reads include cacheable Demands and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache Supports address when precise. Spec update: BDM100 (Precise event) L2 writebacks that access L2 cache l2_lines_in.all l2_lines_out.demand_clean idq.empty umask=0x8,period=2000003,event=0x79 idq.dsb_cycles This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE idq_uops_not_delivered.cycles_0_uops_deliv.core Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded umask=0x2,period=100003,event=0xc3 rtm_retired.start rtm_retired.aborted_misc3 Loads with latency value being above 32 Spec update: BDM100, BDM35 (Must be precise) This event counts loads with latency value being above 64 Spec update: BDM100, BDM35 (Must be precise) This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3 lock_cycles.split_lock_uc_lock_duration move_elimination.int_eliminated This event counts both taken and not taken speculative and retired macro-conditional branch instructions Speculative and retired branches uops_executed_port.port_7 umask=0x8,cmask=8,period=2000003,event=0xa3 Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request missing the L1 data cache uops_executed.stall_cycles uops_executed.cycles_ge_1_uop_exec Number of uops executed on the core Cycles at least 1 micro-op is executed from any thread on physical core Cycles with no micro-ops executed from any thread on physical core This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0 This is a precise version (that is, uses PEBS) of the event that counts mispredicted conditional branch instructions retired (Precise event) unc_c_llc_victims.m_state umask=0x3,event=0x35,filter_opc=0x190 umask=0x3,event=0x35,filter_opc=0x1c8 umask=0x3,event=0x1 umask=0x4,event=0x21 event=0xa Counts the number of cycles when the OS is the upper limit on frequency. Unit: uncore_pcu dtlb_load_misses.walk_completed_2m_4m dtlb_load_misses.walk_completed Load operations that miss the first DTLB level but hit the second and do not cause page walks umask=0x2,period=100003,event=0x49 itlb_misses.stlb_hit_2m 1 / (inst_retired.any / cycles) TopDownL1_SMT ( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) ) l1d_pend_miss.pending / l1d_pend_miss.pending_cycles umask=0x4,period=2000003,cmask=1,event=0x60 offcore_response.demand_code_rd.l3_hit.snoop_none umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0004 offcore_response.pf_l2_data_rd.supplier_none.snoop_miss umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C0010 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0010 offcore_response.pf_l2_rfo.supplier_none.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0200020020 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x01003C0080 offcore_response.pf_l3_rfo.l3_hit.snoop_miss offcore_response.pf_l3_code_rd.supplier_none.snoop_hitm offcore_response.other.l3_hit.snoop_not_needed umask=0x1,period=100003,event=0xb7,offcore_rsp=0x02003C8000 Counts all prefetch data reads have any response type offcore_response.all_pf_rfo.l3_hit.snoop_hit_no_fwd Counts all prefetch code reads umask=0x1,period=100003,event=0xb7,offcore_rsp=0x10003C0240 offcore_response.all_data_rd.supplier_none.snoop_miss Counts any FP_ASSIST umask was incrementing (Precise Event) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000001 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x023C000004 offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_not_needed offcore_response.pf_l3_rfo.l3_hit.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0404000240 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x2004000091 offcore_response.all_rfo.l3_hit.snoop_non_dram umask=0x1,period=100003,event=0xb7,offcore_rsp=0x20003C0122 inv=1,umask=0x1,period=2000003,cmask=1,event=0xc2 Unit: uncore_arb Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.; Retired store uops that miss the STLB Supports address when precise (Precise event) All retired store uops Supports address when precise (Precise event) umask=0x1,period=100003,event=0xb7,offcore_rsp=0x04003C07F7 Number of times RTM abort was triggered (Precise event) Counts all data/code/rfo reads (demand & prefetch) miss in the L3 This event counts mispredicted conditional branch instructions retired (Precise event) Number of data flits transmitted . Derived from unc_q_txl_flits_g0.data. Unit: uncore_qpi l2_lines_out.self.prefetch l2_ifetch.self.m_state l2_ld.self.prefetch.s_state umask=0x58,period=200000,event=0x2e umask=0x1,period=2000000,event=0x10 Floating point computational micro-ops retired (Must be precise) Floating point assists for retired operations umask=0x0,period=2000000,event=0xb0 simd_uop_type_exec.mul.ar SIMD unpacked micro-ops retired Instruction fetches umask=0x1,period=2000000,event=0xaa misalign_mem_ref.ld_split.ar Load splits (At Retirement) umask=0x8c,period=200000,event=0x5 umask=0xe0,period=200000,event=0x6c umask=0x40,period=200000,event=0x6c umask=0xe0,period=200000,event=0x6d ext_snoop.all_agents.hit Divide operations retired Instructions retired umask=0x1,period=2000000,event=0xe4 umask=0x2,period=2000000,event=0xc itlb.hit Stores uops retired that split a cache-line (Precise event capable) Supports address when precise (Must be precise) Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache umask=0x1,period=100007,event=0xb7,offcore_rsp=0x04000032b7 offcore_response.any_rfo.l2_hit offcore_response.any_pf_data_rd.l2_miss.hit_other_core_no_fwd umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400003010 Counts data reads generated by L1 or L2 prefetchers that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts any data writes to uncacheable write combining (USWC) memory region that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.streaming_stores.l2_hit offcore_response.pf_l1_data_rd.l2_miss.hit_other_core_no_fwd offcore_response.pf_l2_data_rd.l2_miss.snoop_miss_or_no_snoop_needed umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000000008 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0400000004 Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that true miss for the L2 cache with a snoop miss in the other processor module umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0000040004 Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_rfo.l2_miss.hit_other_core_no_fwd umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000000001 References per ICache line that are available in the ICache (hit). This event counts differently than Intel processors based on Silvermont microarchitecture ld_blocks.4k_alias umask=0x10,period=2000003,event=0xc2 Retired near relative call instructions (Precise event capable) (Must be precise) BACLEARs asserted for return branch Counts every core cycle a page-walk is in progress due to either a data memory operation or an instruction fetch mem_uops_retired.dtlb_miss_stores Counts demand cacheable data reads of full cache lines hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts any data writes to uncacheable write combining (USWC) memory region miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts data reads generated by L1 or L2 prefetchers outstanding, per cycle, from the time of the L2 miss to when any response is received Counts data reads (demand & prefetch) hit the L2 cache Counts data reads (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module Counts data reads (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) umask=0x1,period=100007,event=0xb7,offcore_rsp=0x00000132b7 l2_lines_out.demand_dirty Number of transitions from AVX-256 to legacy SSE when penalty applicable Spec update: HSD56, HSM57 (Precise event) umask=0x7,period=2000003,event=0xc6 Number of times an RTM execution successfully committed Number of slow LEA or similar uops allocated. Such uop has 3 sources (for example, 2 sources + immediate) regardless of whether it is a result of LEA instruction or not Cycles which a uop is dispatched on port 3 in this thread This events counts the cycles where at least one uop was executed. It is counted per thread Spec update: HSD144, HSD30, HSM31 unc_cbo_cache_lookup.extsnp_mesi This event counts store operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks Misses at all ITLB levels that cause page walks Number of DTLB page walker hits in the L2 umask=0x48,period=2000003,event=0xbc offcore_response.demand_data_rd.llc_miss.local_dram offcore_response.pf_l2_data_rd.llc_miss.any_response umask=0x1,period=100003,event=0xb7,offcore_rsp=0x06004007F7 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063F8007F7 l2_l1d_wb_rqsts.all Any MLC or LLC HW prefetch accessing L2, including rejects umask=0x1,period=100003,event=0xf2 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x3f803c0091 Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded Sample stores and collect precise store operation via PEBS record. PMC3 only (Must be precise) uops_dispatched_port.port_2_core Counts prefetch (that bring data to L2) data reads that hit in the LLC umask=0x1,period=100003,event=0xb7,offcore_rsp=0x600400004 offcore_response.demand_code_rd.llc_miss.remote_hit_forward Counts prefetch (that bring data to L2) data reads that miss the LLC and the data forwarded from remote cache Memory page activates for reads and writes. Unit: uncore_imc event=0xc,edge=1,filter_band1=20 offcore_response.all_demand_mlc_pref_reads.llc_miss.remote_hitm_hit_forward umask=0x40,period=2000003,event=0x5b Cycles when Allocator is stalled if BOB is full and new branch needs it Cycles per core when load or STA uops are dispatched to port 2 Resource stalls due to load or store buffers all being in use Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...) umask=0x2,period=100003,event=0x8 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1000400070 offcore_response.uc_code_reads.l2_hit_far_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x4000000040 offcore_response.demand_code_rd.l2_hit_near_tile_e_f umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0800400002 offcore_response.demand_rfo.l2_hit_near_tile_m Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in M state Counts Demand code reads and prefetch code read requests that accounts for responses which hit its own tile's L2 with data in M state offcore_response.any_pf_l2.l2_hit_this_tile_e Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses which hit its own tile's L2 with data in S state Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in F state umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0010000022 umask=0x1,period=100007,event=0xb7,offcore_rsp=0x1800180100 Counts Demand cacheable data and L1 prefetch data read requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state Counts Demand cacheable data and L1 prefetch data read requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode Counts Demand cacheable data write requests that accounts for data responses from DRAM Local umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100408000 Counts any request that accounts for data responses from MCDRAM Local umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0100402000 offcore_response.bus_locks.ddr_far Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from DRAM Local umask=0x1,period=100007,event=0xb7,offcore_rsp=0x2000020080 Counts L2 code HW prefetches that accounts for data responses from DRAM Far offcore_response.demand_rfo.ddr_near umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0080800002 Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM Local Counts demand code reads and prefetch code reads that accounts for responses from MCDRAM (local and far) offcore_response.any_request.mcdram umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0181803091 Counts Demand cacheable data write requests that accounts for responses from DDR (local and far) Counts the number of occurences a retired load gets blocked because its address partially overlaps with a store Supports address when precise (Precise event) recycleq.ld_splits Counts any retired load that was pushed into the recycle queue for any reason umask=0x1,period=2000000,event=0x51 umask=0xf,period=2000000,event=0x40 umask=0x4,period=200000,event=0x26 L2 lines evicted by a prefetch request L2 prefetch misses umask=0x40,period=100000,event=0x27 l2_write.lock.mesi All demand L2 lock RFOs l2_write.lock.s_state umask=0x2,period=100000,event=0x27 Retired loads that miss the LLC cache (Precise Event) Retired loads that hit valid versions in the LLC cache (Precise Event) umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1044 offcore_response.any_request.remote_cache offcore_response.any_rfo.llc_hit_no_other_core offcore_response.data_in.remote_cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0xFF01 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x1801 offcore_response.demand_rfo.remote_cache_hitm Offcore demand RFO requests that HITM in a remote cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x430 offcore_response.pf_data.local_cache umask=0x1,period=100000,event=0xb7,offcore_rsp=0x7F10 offcore_response.pf_data_rd.llc_hit_no_other_core umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3810 Offcore prefetch code reads that HITM in a remote cache fp_comp_ops_exe.sse_fp umask=0x10,period=2000000,event=0x10 umask=0x3,period=2000000,event=0xcc umask=0x10,period=200000,event=0x12 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x6011 Offcore RFO requests satisfied by the local DRAM offcore_response.prefetch.remote_dram umask=0x1,period=2000000,event=0xe8 ES segment renames snoop_response.hit inv=1,umask=0x1,period=2000000,cmask=1,edge=1,event=0x14 baclear.clear umask=0x2,period=200000,event=0x88 Mispredicted non call branches executed umask=0x8,period=2000000,event=0xa2 SIMD Vector Integer Uops retired (Precise Event) umask=0x1,period=2000000,event=0xdb Cycles Uops executed on any port (core count) Uops issued on ports 0, 1 or 5 Uops issued umask=0x1,period=200000,event=0x8 DTLB load miss page walks complete Retired instructions that missed the ITLB (Precise Event) Counts L2 cache misses when fetching instructions Counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.Note: Writeback pending FIFO has six entries Retired load instructions with locked access. (Precise Event) Supports address when precise mem_load_retired.l1_hit Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0040080004 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0100080002 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0080020002 Counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency (Must be precise) offcore_response.demand_code_rd.l3_hit_s.snoop_non_dram offcore_response.demand_rfo.l3_miss.spl_hit offcore_response.demand_rfo.l3_hit_e.snoop_non_dram Counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased umask=0x0,edge=1,period=100007,cmask=1,event=0x3c Counts the cycles when 4 uops are delivered by the LSD (Loop-stream detector) umask=0x10,period=2000003,event=0xb1 All (macro) branch instructions retired Spec update: SKL091 skl metrics Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake microarchitecture This event counts the cases where a forward was technically possible, but did not occur because the store data was not available at the right time This event counts the number of load ops retired that hit in the L2 (Precise event) mem_uops_retired.utlb_miss offcore_response.any_rfo.l2_miss.snoop_miss umask=0x1,period=100007,event=0xb7,offcore_rsp=0x0200000040 FAR counts the number of far branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) ALL_BRANCHES counts the number of any mispredicted branch instructions retired. This umask is an architecturally defined event. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa. When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event) ALL_TAKEN_BRANCHES counts the number of all taken branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Must be precise) Total cycles for all the page walks. (I-side and D-side) Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS) (Precise event) Counts prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded offcore_response.pf_llc_rfo.llc_hit.hit_other_core_no_fwd umask=0x4,period=2000000,cmask=1,event=0x60 offcore_response.any_data.all_local_dram_and_remote_cache_hit REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT REQUEST = ANY IFETCH and RESPONSE = REMOTE_CACHE_HITM umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2ff offcore_response.any_rfo.all_local_dram_and_remote_cache_hit REQUEST = ANY RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT offcore_response.any_rfo.local_dram_and_remote_cache_hit offcore_response.corewb.all_local_dram_and_remote_cache_hit umask=0x1,period=100000,event=0xb7,offcore_rsp=0xff77 REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM REQUEST = DATA_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = DATA_IN and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = DEMAND_RFO and RESPONSE = ANY_CACHE_DRAM REQUEST = PF_IFETCH and RESPONSE = IO_CSR_MMIO REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT offcore_response.data_in.other_local_dram REQUEST = DEMAND_DATA_RD and RESPONSE = REMOTE_DRAM REQUEST = DEMAND_RFO and RESPONSE = ANY_LLC_MISS REQUEST = PF_DATA_RD and RESPONSE = ANY_DRAM AND REMOTE_FWD umask=0x1,period=100000,event=0xb7,offcore_rsp=0x3020 DTLB load miss page walk cycles umask=0x20,period=100000,event=0xb0 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x58FF umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2777 umask=0x1,period=100000,event=0xb7,offcore_rsp=0x2770 mem_uncore_retired.local_hitm Load instructions retired local dram and remote cache HIT data sources (Precise Event) Cycles thread is active umask=0x80,period=2000003,event=0xc7 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x0604000010 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063B800100 offcore_response.all_pf_data_rd.l3_miss.any_snoop umask=0x1,period=100003,event=0xb7,offcore_rsp=0x083FC00490 umask=0x1,period=100003,event=0xb7,offcore_rsp=0x063FC00122 umask=0x18,period=200003,event=0x28 umask=0x4,period=2000003,event=0xef core_snoop_response.rsp_sfwdm umask=0x20,period=2000003,event=0xef umask=0x03,event=0x50 unc_cha_requests.writes_local unc_iio_data_req_of_cpu.mem_read.part3 unc_cha_requests.invitoe_remote Counts when a a transaction with the opcode type RspIFwd Snoop Response was received which indicates a remote caching agent forwarded the data and the requesting agent is able to acquire the data in E (Exclusive) or M (modified) states. This is commonly returned with RFO (the Read for Ownership issued before a write) transactions. The snoop could have either been to a cacheline in the M,E,F (Modified, Exclusive or Forward) states unc_iio_data_req_by_cpu.mem_read.part0 unc_iio_txn_req_by_cpu.mem_read.part1 fc_mask=0x07,ch_mask=0x04,umask=0x04,event=0xc1 Read request for up to a 64 byte transaction is made by IIO Part3 to Memory. Unit: uncore_iio fc_mask=0x07,ch_mask=0x02,umask=0x01,event=0x84 unc_m2m_direct2upi_not_taken_credits umask=0x1,event=0x2d Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state , and found the cacheline marked in the I (Invalid) state indicating the cacheline is not stored in another socket, and so there is no need to snoop the other sockets for the latest data. The data may be stored in any state in the local socket umask=0x40,event=0x2e Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from A (SnoopAll) to S (Shared) umask=0x1,event=0x12 Null FLITs received from any slot. Unit: uncore_upi ll unc_upi_txl_bypassed umask=0x47,event=0x2 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED offcore_response.pf_l1d_and_sw.l3_hit_m.hit_other_core_fwd offcore_response.pf_l2_data_rd.l3_hit_f.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200048000 period=100003,umask=0x80,event=0xb0 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100200120 period=200003,umask=0xe1,event=0x24 offcore_response.all_reads.l3_hit_s.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200088000 offcore_response.pf_l2_rfo.pmm_hit_local_pmm.snoop_not_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0120 This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x08007C0400 This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0200020001 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040010 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000020400 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200010 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE offcore_response.all_data_rd.l3_hit_m.hit_other_core_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x01003C0100 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80108000 offcore_response.pf_l3_data_rd.l3_hit_m.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080100010 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0400088000 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP offcore_response.pf_l2_rfo.l3_hit_e.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200002 offcore_response.all_data_rd.l3_hit_s.snoop_miss period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1000080001 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE offcore_response.pf_l2_rfo.l3_hit_s.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x02003C0001 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.SNOOP_MISS period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0080400400 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100100002 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0800200491 offcore_response.other.l3_hit_e.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80040100 period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80100020 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0100040120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.ANY_RESPONSE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F80200120 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element period=100007,umask=0x1,event=0xc6,frontend=0x12 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall (Precise event) period=100003,umask=0x1,event=0xb7,offcore_rsp=0x043C000491 offcore_response.pf_l2_data_rd.l3_miss.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000491 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED period=100003,umask=0x1,event=0xb7,offcore_rsp=0x1010000004 Counts all demand code reads DEMAND_CODE_RD & L3_MISS_REMOTE_HOP1_DRAM & HITM_OTHER_CORE ocr.all_pf_data_rd.l3_miss.remote_hit_forward offcore_response.all_reads.l3_miss_remote_hop1_dram.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0810000004 Counts all demand code reads DEMAND_CODE_RD & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_FWD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0204000491 ALL_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISS This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD offcore_response.all_rfo.l3_miss.hitm_other_core period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0090000001 ocr.demand_data_rd.l3_miss.any_snoop period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3F84000400 ALL_RFO & L3_MISS & REMOTE_HIT_FORWARD Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS_REMOTE_HOP1_DRAM & HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP Counts any other requests OTHER & L3_MISS_REMOTE_DRAM & SNOOP_MISS_OR_NO_FWD This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE period=100003,umask=0x1,event=0xb7,offcore_rsp=0x0210000080 ocr.all_pf_rfo.l3_miss_local_dram.no_snoop_needed offcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.snoop_none ocr.demand_rfo.l3_miss_local_dram.no_snoop_needed period=100003,umask=0x1,event=0xb7,offcore_rsp=0x04100007F7 offcore_response.pf_l1d_and_sw.l3_miss_local_dram.snoop_miss This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD period=100003,umask=0x1,event=0xb7,offcore_rsp=0x3FBC000010 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD offcore_response.demand_code_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd period=100003,umask=0x1,event=0xb7,offcore_rsp=0x00BC0007F7 Counts all prefetch (that bring data to L2) RFOs PF_L2_RFO & L3_MISS_LOCAL_DRAM & ANY_SNOOP ocr.all_pf_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd offcore_response.pf_l3_rfo.l3_miss.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_MISS & SNOOP_MISS This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP ocr.demand_data_rd.l3_miss.no_snoop_needed ALL_PF_RFO & L3_MISS & REMOTE_HIT_FORWARD ocr.all_pf_rfo.l3_miss_remote_hop1_dram.snoop_miss period=2000003,umask=0x2,event=0xc9 ALL_READS & L3_MISS_LOCAL_DRAM & NO_SNOOP_NEEDED offcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_MISS & REMOTE_HITM ocr.demand_code_rd.l3_hit_s.hitm_other_core ocr.all_rfo.l3_hit_s.no_snoop_needed ocr.demand_rfo.l3_hit_m.no_snoop_needed ALL_PF_DATA_RD & L3_HIT & HITM_OTHER_CORE ALL_RFO & L3_HIT_F & HIT_OTHER_CORE_NO_FWD ALL_READS & L3_HIT_E & ANY_SNOOP Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & SUPPLIER_NONE & ANY_SNOOP ALL_READS & SUPPLIER_NONE & HIT_OTHER_CORE_FWD ocr.pf_l3_rfo.l3_hit.snoop_none ocr.all_rfo.l3_hit_m.hitm_other_core ocr.pf_l3_data_rd.supplier_none.hitm_other_core ALL_DATA_RD & L3_HIT_S & HIT_OTHER_CORE_FWD ocr.all_pf_data_rd.supplier_none.snoop_none ocr.pf_l2_data_rd.l3_hit_s.any_snoop ocr.demand_rfo.l3_hit_m.snoop_miss ocr.all_data_rd.l3_hit_s.any_snoop ALL_PF_RFO & ANY_RESPONSE have any response type ocr.pf_l2_data_rd.supplier_none.any_snoop ocr.all_pf_rfo.pmm_hit_local_pmm.snoop_none Counts all prefetch (that bring data to LLC only) RFOs PF_L3_RFO & L3_HIT_F & NO_SNOOP_NEEDED Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & PMM_HIT_LOCAL_PMM & SNOOP_NOT_NEEDED ocr.pf_l3_data_rd.l3_hit_e.any_snoop ALL_READS & L3_HIT & NO_SNOOP_NEEDED ocr.all_pf_data_rd.l3_hit.snoop_miss ALL_READS & L3_HIT_F & ANY_SNOOP Counts demand data reads DEMAND_DATA_RD & SUPPLIER_NONE & HITM_OTHER_CORE Counts all prefetch (that bring data to LLC only) data reads PF_L3_DATA_RD & L3_HIT_F & HITM_OTHER_CORE ocr.all_reads.l3_hit_m.snoop_none Counts all demand data writes (RFOs) DEMAND_RFO & L3_HIT_S & HIT_OTHER_CORE_FWD ocr.all_pf_rfo.l3_hit_m.hitm_other_core Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & SUPPLIER_NONE & HIT_OTHER_CORE_FWD ocr.all_pf_data_rd.l3_hit_m.snoop_miss ocr.all_pf_data_rd.l3_hit_e.no_snoop_needed ocr.demand_data_rd.pmm_hit_local_pmm.any_snoop ocr.all_data_rd.l3_hit_f.no_snoop_needed Counts L1 data cache hardware prefetch requests and software prefetch requests PF_L1D_AND_SW & L3_HIT & SNOOP_MISS ocr.all_rfo.l3_hit_e.no_snoop_needed ocr.demand_data_rd.l3_hit_m.snoop_none ocr.demand_data_rd.supplier_none.snoop_miss ocr.all_pf_rfo.l3_hit_f.any_snoop ocr.demand_rfo.l3_hit_e.snoop_miss period=400009,umask=0x1,event=0xc4 period=400009,event=0xc4 period=2000003,umask=0x8,event=0xa1 period=2000003,umask=0x1,event=0xe period=2000003,umask=0x1,event=0x59 6.103515625E-5MB/sec unc_iio_data_req_of_cpu.peer_read.part0 unc_m2m_imc_writes.to_pmm unc_m2m_tag_hit.nm_rd_hit_dirty Tag Hit; Underfill Rd Hit from NearMem, Dirty Line AD Egress (to CMS) Allocations AD Egress (to CMS) Occupancy Counts all microcode Floating Point assists Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB) idq.dsb_cycles_ok idq.dsb_cycles_any Counts instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall (Precise event) umask=0x4,period=100003,event=0x54 Number of machine clears due to memory ordering conflicts uops_dispatched.port_5 umask=0x40,period=2000003,cmask=2,event=0xa6 Taken conditional branch instructions retired (Precise event) Counts the number of load uops retired Supports address when precise (Precise event) Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is not in the ICache (miss). The event strives to count on a cache line basis, so that multiple accesses which miss in a single cache line count as one ICACHE.MISS. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is not in the ICache Counts demand data reads that was not supplied by the L3 cache Counts demand data reads that have any response type Clockticks of the power control unit (PCU) event=0x82 All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including hardware and software prefetch) Core to L2 cacheable request access status (not including L2 Prefetch). Data cache shared read hit in L2 l2_cache_req_stat.ls_rd_blk_l_hit_s umask=0xfe,event=0x6 ex_ret_cops ex_ret_near_ret x87 instructions df_ccm_reqa.node1.wrsizedfullzero df_ccm_reqa.node4.wrsizedfullnc df_ccm_reqa.node6.wrsizedfullnc umask=0x2C,event=0x8b umask=0x29,event=0x8b umask=0xC9,event=0x8b umask=0x28,event=0x8b df_ccm_reqa.node3.rdsizednc umask=0xE5,event=0x8b umask=0xC4,event=0x8b df_ccm_reqb.node5.vicblkcln df_ccm_reqb.node3.wrsizedfullnc umask=0x64,event=0x8c umask=0xC2,event=0x8c df_ccm_reqb.node7.wrsizedncposted umask=0xEC,event=0x108 df_ioms_reqa.node3.fence Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized>32band<64b df_ioms_reqa.node4.anywrsized<32b df_ioms_reqa.node5.anyrdsized df_ioms_reqb.node0.piesystemmanagement umask=0x0C,event=0x109 df_ioms_reqb.node5.anyiotransaction df_ioms_reqb.node1.ioanyatomic umask=0xA6,event=0x109 df_ioms_reqb.node6.ioanypostedwrsized=64b df_ioms_reqb.node3.ioanypostedwrsized>32band<64b df_ioms_reqb.node6.ioanypostedwrsized>32band<64b umask=0xA3,event=0x109 umask=0xE3,event=0x109 umask=0x42,event=0x109 df_ioms_reqb.node2.iolargeread Total number multi-pipe uOps assigned to pipe 1 umask=0x4,event=0x5 l3_request_g1.t0.s3.wrsizednc l3_request_g1.t5.s3.wrsizednc l3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x20,event=0x1 l3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x20,event=0x1 l3_request_g1.t4.s2.rdsizednc l3_request_g1.t5.s2.rdsizednc l3_thread_mask=0x80,l3_slice_mask=0x04,umask=0x20,event=0x1 l3_request_g1.t5.s3.rdsizednc l3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x40,event=0x1 l3_request_g1.t1.s0.caching l3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x80,event=0x1 l3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x01,event=0x3 l3_thread_mask=0x04,l3_slice_mask=0x01,umask=0x01,event=0x3 l3fillvicreq.t4.s0.vicblk l3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x01,event=0x3 l3fillvicreq.t6.s3.vicblk l3fillvicreq.t3.s0.chgtox l3fillvicreq.t2.s3.chgtox l3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x04,event=0x3 l3fillvicreq.t7.s0.rdblkc_s l3_thread_mask=0x04,l3_slice_mask=0x04,umask=0x08,event=0x3 l3fillvicreq.t3.s0.rdblkx_vic l3fillvicreq.t5.s0.rdblkx l3_thread_mask=0x04,l3_slice_mask=0x08,umask=0x20,event=0x3 l3_thread_mask=0x40,l3_slice_mask=0x01,umask=0x40,event=0x3 l3fillvicreq.t3.s3.rdblkl_vic l3fillvicreq.t6.s3.rdblkl_vic l3_thread_mask=0x40,l3_slice_mask=0x08,umask=0x40,event=0x3 l3victimstate.t4.s1.nol3victimline l3_thread_mask=0x08,l3_slice_mask=0x04,umask=0x01,event=0x9 l3victimstate.t5.s2.nol3victimline l3victimstate.t2.s0.none_nol3victimline l3victimstate.t5.s1.none_nol3victimline l3_thread_mask=0x01,l3_slice_mask=0x02,umask=0x08,event=0x9 l3victimstate.t5.s1.o l3victimstate.t3.s3.o l3victimstate.t6.s3.o l3_thread_mask=0x01,l3_slice_mask=0x01,umask=0x10,event=0x9 l3victimstate.t4.s1.e_fe l3_thread_mask=0x20,l3_slice_mask=0x01,umask=0x20,event=0x9 l3_thread_mask=0x08,l3_slice_mask=0x02,umask=0x20,event=0x9 l3victimstate.t0.s0.d l3victimstate.t7.s1.d l3victimstate.t3.s1.od l3victimstate.t6.s1.od l3_thread_mask=0x02,l3_slice_mask=0x04,umask=0x80,event=0x9 umask=0x1,event=0x29 Software Prefetch Instructions (PREFETCHNTA instruction) Dispatched LS MAB Allocates by Type. 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