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Mini Shell
Mini Shell
require '_h2ph_pre.ph';
no warnings qw(redefine misc);
unless(defined(&_VMM_DEV_H_)) {
eval 'sub _VMM_DEV_H_ () {1;}' unless defined(&_VMM_DEV_H_);
if(defined(&_KERNEL)) {
}
eval 'sub VM_MEMMAP_F_WIRED () {0x1;}' unless defined(&VM_MEMMAP_F_WIRED);
eval 'sub VM_MEMMAP_F_IOMMU () {0x2;}' unless defined(&VM_MEMMAP_F_IOMMU);
eval 'sub VM_MEMSEG_NAME {
my($m) = @_;
eval q((($m)-> $name[0] != ord(\'\\\\0\') ? ($m)-> &name : &NULL));
}' unless defined(&VM_MEMSEG_NAME);
eval 'sub MAX_VM_STATS () {64;}' unless defined(&MAX_VM_STATS);
eval 'sub VM_ACTIVE_CPUS () {0;}' unless defined(&VM_ACTIVE_CPUS);
eval 'sub VM_SUSPENDED_CPUS () {1;}' unless defined(&VM_SUSPENDED_CPUS);
eval 'sub VM_DEBUG_CPUS () {2;}' unless defined(&VM_DEBUG_CPUS);
eval("sub IOCNUM_ABIVERS () { 0; }") unless defined(&IOCNUM_ABIVERS);
eval("sub IOCNUM_RUN () { 1; }") unless defined(&IOCNUM_RUN);
eval("sub IOCNUM_SET_CAPABILITY () { 2; }") unless defined(&IOCNUM_SET_CAPABILITY);
eval("sub IOCNUM_GET_CAPABILITY () { 3; }") unless defined(&IOCNUM_GET_CAPABILITY);
eval("sub IOCNUM_SUSPEND () { 4; }") unless defined(&IOCNUM_SUSPEND);
eval("sub IOCNUM_REINIT () { 5; }") unless defined(&IOCNUM_REINIT);
eval("sub IOCNUM_MAP_MEMORY () { 10; }") unless defined(&IOCNUM_MAP_MEMORY);
eval("sub IOCNUM_GET_MEMORY_SEG () { 11; }") unless defined(&IOCNUM_GET_MEMORY_SEG);
eval("sub IOCNUM_GET_GPA_PMAP () { 12; }") unless defined(&IOCNUM_GET_GPA_PMAP);
eval("sub IOCNUM_GLA2GPA () { 13; }") unless defined(&IOCNUM_GLA2GPA);
eval("sub IOCNUM_ALLOC_MEMSEG () { 14; }") unless defined(&IOCNUM_ALLOC_MEMSEG);
eval("sub IOCNUM_GET_MEMSEG () { 15; }") unless defined(&IOCNUM_GET_MEMSEG);
eval("sub IOCNUM_MMAP_MEMSEG () { 16; }") unless defined(&IOCNUM_MMAP_MEMSEG);
eval("sub IOCNUM_MMAP_GETNEXT () { 17; }") unless defined(&IOCNUM_MMAP_GETNEXT);
eval("sub IOCNUM_GLA2GPA_NOFAULT () { 18; }") unless defined(&IOCNUM_GLA2GPA_NOFAULT);
eval("sub IOCNUM_SET_REGISTER () { 20; }") unless defined(&IOCNUM_SET_REGISTER);
eval("sub IOCNUM_GET_REGISTER () { 21; }") unless defined(&IOCNUM_GET_REGISTER);
eval("sub IOCNUM_SET_SEGMENT_DESCRIPTOR () { 22; }") unless defined(&IOCNUM_SET_SEGMENT_DESCRIPTOR);
eval("sub IOCNUM_GET_SEGMENT_DESCRIPTOR () { 23; }") unless defined(&IOCNUM_GET_SEGMENT_DESCRIPTOR);
eval("sub IOCNUM_SET_REGISTER_SET () { 24; }") unless defined(&IOCNUM_SET_REGISTER_SET);
eval("sub IOCNUM_GET_REGISTER_SET () { 25; }") unless defined(&IOCNUM_GET_REGISTER_SET);
eval("sub IOCNUM_GET_KERNEMU_DEV () { 26; }") unless defined(&IOCNUM_GET_KERNEMU_DEV);
eval("sub IOCNUM_SET_KERNEMU_DEV () { 27; }") unless defined(&IOCNUM_SET_KERNEMU_DEV);
eval("sub IOCNUM_GET_INTINFO () { 28; }") unless defined(&IOCNUM_GET_INTINFO);
eval("sub IOCNUM_SET_INTINFO () { 29; }") unless defined(&IOCNUM_SET_INTINFO);
eval("sub IOCNUM_INJECT_EXCEPTION () { 30; }") unless defined(&IOCNUM_INJECT_EXCEPTION);
eval("sub IOCNUM_LAPIC_IRQ () { 31; }") unless defined(&IOCNUM_LAPIC_IRQ);
eval("sub IOCNUM_INJECT_NMI () { 32; }") unless defined(&IOCNUM_INJECT_NMI);
eval("sub IOCNUM_IOAPIC_ASSERT_IRQ () { 33; }") unless defined(&IOCNUM_IOAPIC_ASSERT_IRQ);
eval("sub IOCNUM_IOAPIC_DEASSERT_IRQ () { 34; }") unless defined(&IOCNUM_IOAPIC_DEASSERT_IRQ);
eval("sub IOCNUM_IOAPIC_PULSE_IRQ () { 35; }") unless defined(&IOCNUM_IOAPIC_PULSE_IRQ);
eval("sub IOCNUM_LAPIC_MSI () { 36; }") unless defined(&IOCNUM_LAPIC_MSI);
eval("sub IOCNUM_LAPIC_LOCAL_IRQ () { 37; }") unless defined(&IOCNUM_LAPIC_LOCAL_IRQ);
eval("sub IOCNUM_IOAPIC_PINCOUNT () { 38; }") unless defined(&IOCNUM_IOAPIC_PINCOUNT);
eval("sub IOCNUM_RESTART_INSTRUCTION () { 39; }") unless defined(&IOCNUM_RESTART_INSTRUCTION);
eval("sub IOCNUM_BIND_PPTDEV () { 40; }") unless defined(&IOCNUM_BIND_PPTDEV);
eval("sub IOCNUM_UNBIND_PPTDEV () { 41; }") unless defined(&IOCNUM_UNBIND_PPTDEV);
eval("sub IOCNUM_MAP_PPTDEV_MMIO () { 42; }") unless defined(&IOCNUM_MAP_PPTDEV_MMIO);
eval("sub IOCNUM_PPTDEV_MSI () { 43; }") unless defined(&IOCNUM_PPTDEV_MSI);
eval("sub IOCNUM_PPTDEV_MSIX () { 44; }") unless defined(&IOCNUM_PPTDEV_MSIX);
eval("sub IOCNUM_PPTDEV_DISABLE_MSIX () { 45; }") unless defined(&IOCNUM_PPTDEV_DISABLE_MSIX);
eval("sub IOCNUM_VM_STATS () { 50; }") unless defined(&IOCNUM_VM_STATS);
eval("sub IOCNUM_VM_STAT_DESC () { 51; }") unless defined(&IOCNUM_VM_STAT_DESC);
eval("sub IOCNUM_SET_X2APIC_STATE () { 60; }") unless defined(&IOCNUM_SET_X2APIC_STATE);
eval("sub IOCNUM_GET_X2APIC_STATE () { 61; }") unless defined(&IOCNUM_GET_X2APIC_STATE);
eval("sub IOCNUM_GET_HPET_CAPABILITIES () { 62; }") unless defined(&IOCNUM_GET_HPET_CAPABILITIES);
eval("sub IOCNUM_SET_TOPOLOGY () { 63; }") unless defined(&IOCNUM_SET_TOPOLOGY);
eval("sub IOCNUM_GET_TOPOLOGY () { 64; }") unless defined(&IOCNUM_GET_TOPOLOGY);
eval("sub IOCNUM_ISA_ASSERT_IRQ () { 80; }") unless defined(&IOCNUM_ISA_ASSERT_IRQ);
eval("sub IOCNUM_ISA_DEASSERT_IRQ () { 81; }") unless defined(&IOCNUM_ISA_DEASSERT_IRQ);
eval("sub IOCNUM_ISA_PULSE_IRQ () { 82; }") unless defined(&IOCNUM_ISA_PULSE_IRQ);
eval("sub IOCNUM_ISA_SET_IRQ_TRIGGER () { 83; }") unless defined(&IOCNUM_ISA_SET_IRQ_TRIGGER);
eval("sub IOCNUM_ACTIVATE_CPU () { 90; }") unless defined(&IOCNUM_ACTIVATE_CPU);
eval("sub IOCNUM_GET_CPUSET () { 91; }") unless defined(&IOCNUM_GET_CPUSET);
eval("sub IOCNUM_SUSPEND_CPU () { 92; }") unless defined(&IOCNUM_SUSPEND_CPU);
eval("sub IOCNUM_RESUME_CPU () { 93; }") unless defined(&IOCNUM_RESUME_CPU);
eval("sub IOCNUM_RTC_READ () { 100; }") unless defined(&IOCNUM_RTC_READ);
eval("sub IOCNUM_RTC_WRITE () { 101; }") unless defined(&IOCNUM_RTC_WRITE);
eval("sub IOCNUM_RTC_SETTIME () { 102; }") unless defined(&IOCNUM_RTC_SETTIME);
eval("sub IOCNUM_RTC_GETTIME () { 103; }") unless defined(&IOCNUM_RTC_GETTIME);
eval("sub IOCNUM_SNAPSHOT_REQ () { 113; }") unless defined(&IOCNUM_SNAPSHOT_REQ);
eval("sub IOCNUM_RESTORE_TIME () { 115; }") unless defined(&IOCNUM_RESTORE_TIME);
eval 'sub VM_RUN () { &_IOWR(ord(\'v\'), &IOCNUM_RUN, \'struct vm_run\');}' unless defined(&VM_RUN);
eval 'sub VM_SUSPEND () { &_IOW(ord(\'v\'), &IOCNUM_SUSPEND, \'struct vm_suspend\');}' unless defined(&VM_SUSPEND);
eval 'sub VM_REINIT () { &_IO(ord(\'v\'), &IOCNUM_REINIT);}' unless defined(&VM_REINIT);
eval 'sub VM_ALLOC_MEMSEG_FBSD12 () { &_IOW(ord(\'v\'), &IOCNUM_ALLOC_MEMSEG, \'struct vm_memseg_fbsd12\');}' unless defined(&VM_ALLOC_MEMSEG_FBSD12);
eval 'sub VM_ALLOC_MEMSEG () { &_IOW(ord(\'v\'), &IOCNUM_ALLOC_MEMSEG, \'struct vm_memseg\');}' unless defined(&VM_ALLOC_MEMSEG);
eval 'sub VM_GET_MEMSEG_FBSD12 () { &_IOWR(ord(\'v\'), &IOCNUM_GET_MEMSEG, \'struct vm_memseg_fbsd12\');}' unless defined(&VM_GET_MEMSEG_FBSD12);
eval 'sub VM_GET_MEMSEG () { &_IOWR(ord(\'v\'), &IOCNUM_GET_MEMSEG, \'struct vm_memseg\');}' unless defined(&VM_GET_MEMSEG);
eval 'sub VM_MMAP_MEMSEG () { &_IOW(ord(\'v\'), &IOCNUM_MMAP_MEMSEG, \'struct vm_memmap\');}' unless defined(&VM_MMAP_MEMSEG);
eval 'sub VM_MMAP_GETNEXT () { &_IOWR(ord(\'v\'), &IOCNUM_MMAP_GETNEXT, \'struct vm_memmap\');}' unless defined(&VM_MMAP_GETNEXT);
eval 'sub VM_SET_REGISTER () { &_IOW(ord(\'v\'), &IOCNUM_SET_REGISTER, \'struct vm_register\');}' unless defined(&VM_SET_REGISTER);
eval 'sub VM_GET_REGISTER () { &_IOWR(ord(\'v\'), &IOCNUM_GET_REGISTER, \'struct vm_register\');}' unless defined(&VM_GET_REGISTER);
eval 'sub VM_SET_SEGMENT_DESCRIPTOR () { &_IOW(ord(\'v\'), &IOCNUM_SET_SEGMENT_DESCRIPTOR, \'struct vm_seg_desc\');}' unless defined(&VM_SET_SEGMENT_DESCRIPTOR);
eval 'sub VM_GET_SEGMENT_DESCRIPTOR () { &_IOWR(ord(\'v\'), &IOCNUM_GET_SEGMENT_DESCRIPTOR, \'struct vm_seg_desc\');}' unless defined(&VM_GET_SEGMENT_DESCRIPTOR);
eval 'sub VM_SET_REGISTER_SET () { &_IOW(ord(\'v\'), &IOCNUM_SET_REGISTER_SET, \'struct vm_register_set\');}' unless defined(&VM_SET_REGISTER_SET);
eval 'sub VM_GET_REGISTER_SET () { &_IOWR(ord(\'v\'), &IOCNUM_GET_REGISTER_SET, \'struct vm_register_set\');}' unless defined(&VM_GET_REGISTER_SET);
eval 'sub VM_SET_KERNEMU_DEV () { &_IOW(ord(\'v\'), &IOCNUM_SET_KERNEMU_DEV, \'struct vm_readwrite_kernemu_device\');}' unless defined(&VM_SET_KERNEMU_DEV);
eval 'sub VM_GET_KERNEMU_DEV () { &_IOWR(ord(\'v\'), &IOCNUM_GET_KERNEMU_DEV, \'struct vm_readwrite_kernemu_device\');}' unless defined(&VM_GET_KERNEMU_DEV);
eval 'sub VM_INJECT_EXCEPTION () { &_IOW(ord(\'v\'), &IOCNUM_INJECT_EXCEPTION, \'struct vm_exception\');}' unless defined(&VM_INJECT_EXCEPTION);
eval 'sub VM_LAPIC_IRQ () { &_IOW(ord(\'v\'), &IOCNUM_LAPIC_IRQ, \'struct vm_lapic_irq\');}' unless defined(&VM_LAPIC_IRQ);
eval 'sub VM_LAPIC_LOCAL_IRQ () { &_IOW(ord(\'v\'), &IOCNUM_LAPIC_LOCAL_IRQ, \'struct vm_lapic_irq\');}' unless defined(&VM_LAPIC_LOCAL_IRQ);
eval 'sub VM_LAPIC_MSI () { &_IOW(ord(\'v\'), &IOCNUM_LAPIC_MSI, \'struct vm_lapic_msi\');}' unless defined(&VM_LAPIC_MSI);
eval 'sub VM_IOAPIC_ASSERT_IRQ () { &_IOW(ord(\'v\'), &IOCNUM_IOAPIC_ASSERT_IRQ, \'struct vm_ioapic_irq\');}' unless defined(&VM_IOAPIC_ASSERT_IRQ);
eval 'sub VM_IOAPIC_DEASSERT_IRQ () { &_IOW(ord(\'v\'), &IOCNUM_IOAPIC_DEASSERT_IRQ, \'struct vm_ioapic_irq\');}' unless defined(&VM_IOAPIC_DEASSERT_IRQ);
eval 'sub VM_IOAPIC_PULSE_IRQ () { &_IOW(ord(\'v\'), &IOCNUM_IOAPIC_PULSE_IRQ, \'struct vm_ioapic_irq\');}' unless defined(&VM_IOAPIC_PULSE_IRQ);
eval 'sub VM_IOAPIC_PINCOUNT () { &_IOR(ord(\'v\'), &IOCNUM_IOAPIC_PINCOUNT, \'int\');}' unless defined(&VM_IOAPIC_PINCOUNT);
eval 'sub VM_ISA_ASSERT_IRQ () { &_IOW(ord(\'v\'), &IOCNUM_ISA_ASSERT_IRQ, \'struct vm_isa_irq\');}' unless defined(&VM_ISA_ASSERT_IRQ);
eval 'sub VM_ISA_DEASSERT_IRQ () { &_IOW(ord(\'v\'), &IOCNUM_ISA_DEASSERT_IRQ, \'struct vm_isa_irq\');}' unless defined(&VM_ISA_DEASSERT_IRQ);
eval 'sub VM_ISA_PULSE_IRQ () { &_IOW(ord(\'v\'), &IOCNUM_ISA_PULSE_IRQ, \'struct vm_isa_irq\');}' unless defined(&VM_ISA_PULSE_IRQ);
eval 'sub VM_ISA_SET_IRQ_TRIGGER () { &_IOW(ord(\'v\'), &IOCNUM_ISA_SET_IRQ_TRIGGER, \'struct vm_isa_irq_trigger\');}' unless defined(&VM_ISA_SET_IRQ_TRIGGER);
eval 'sub VM_SET_CAPABILITY () { &_IOW(ord(\'v\'), &IOCNUM_SET_CAPABILITY, \'struct vm_capability\');}' unless defined(&VM_SET_CAPABILITY);
eval 'sub VM_GET_CAPABILITY () { &_IOWR(ord(\'v\'), &IOCNUM_GET_CAPABILITY, \'struct vm_capability\');}' unless defined(&VM_GET_CAPABILITY);
eval 'sub VM_BIND_PPTDEV () { &_IOW(ord(\'v\'), &IOCNUM_BIND_PPTDEV, \'struct vm_pptdev\');}' unless defined(&VM_BIND_PPTDEV);
eval 'sub VM_UNBIND_PPTDEV () { &_IOW(ord(\'v\'), &IOCNUM_UNBIND_PPTDEV, \'struct vm_pptdev\');}' unless defined(&VM_UNBIND_PPTDEV);
eval 'sub VM_MAP_PPTDEV_MMIO () { &_IOW(ord(\'v\'), &IOCNUM_MAP_PPTDEV_MMIO, \'struct vm_pptdev_mmio\');}' unless defined(&VM_MAP_PPTDEV_MMIO);
eval 'sub VM_PPTDEV_MSI () { &_IOW(ord(\'v\'), &IOCNUM_PPTDEV_MSI, \'struct vm_pptdev_msi\');}' unless defined(&VM_PPTDEV_MSI);
eval 'sub VM_PPTDEV_MSIX () { &_IOW(ord(\'v\'), &IOCNUM_PPTDEV_MSIX, \'struct vm_pptdev_msix\');}' unless defined(&VM_PPTDEV_MSIX);
eval 'sub VM_PPTDEV_DISABLE_MSIX () { &_IOW(ord(\'v\'), &IOCNUM_PPTDEV_DISABLE_MSIX, \'struct vm_pptdev\');}' unless defined(&VM_PPTDEV_DISABLE_MSIX);
eval 'sub VM_INJECT_NMI () { &_IOW(ord(\'v\'), &IOCNUM_INJECT_NMI, \'struct vm_nmi\');}' unless defined(&VM_INJECT_NMI);
eval 'sub VM_STATS () { &_IOWR(ord(\'v\'), &IOCNUM_VM_STATS, \'struct vm_stats\');}' unless defined(&VM_STATS);
eval 'sub VM_STAT_DESC () { &_IOWR(ord(\'v\'), &IOCNUM_VM_STAT_DESC, \'struct vm_stat_desc\');}' unless defined(&VM_STAT_DESC);
eval 'sub VM_SET_X2APIC_STATE () { &_IOW(ord(\'v\'), &IOCNUM_SET_X2APIC_STATE, \'struct vm_x2apic\');}' unless defined(&VM_SET_X2APIC_STATE);
eval 'sub VM_GET_X2APIC_STATE () { &_IOWR(ord(\'v\'), &IOCNUM_GET_X2APIC_STATE, \'struct vm_x2apic\');}' unless defined(&VM_GET_X2APIC_STATE);
eval 'sub VM_GET_HPET_CAPABILITIES () { &_IOR(ord(\'v\'), &IOCNUM_GET_HPET_CAPABILITIES, \'struct vm_hpet_cap\');}' unless defined(&VM_GET_HPET_CAPABILITIES);
eval 'sub VM_SET_TOPOLOGY () { &_IOW(ord(\'v\'), &IOCNUM_SET_TOPOLOGY, \'struct vm_cpu_topology\');}' unless defined(&VM_SET_TOPOLOGY);
eval 'sub VM_GET_TOPOLOGY () { &_IOR(ord(\'v\'), &IOCNUM_GET_TOPOLOGY, \'struct vm_cpu_topology\');}' unless defined(&VM_GET_TOPOLOGY);
eval 'sub VM_GET_GPA_PMAP () { &_IOWR(ord(\'v\'), &IOCNUM_GET_GPA_PMAP, \'struct vm_gpa_pte\');}' unless defined(&VM_GET_GPA_PMAP);
eval 'sub VM_GLA2GPA () { &_IOWR(ord(\'v\'), &IOCNUM_GLA2GPA, \'struct vm_gla2gpa\');}' unless defined(&VM_GLA2GPA);
eval 'sub VM_GLA2GPA_NOFAULT () { &_IOWR(ord(\'v\'), &IOCNUM_GLA2GPA_NOFAULT, \'struct vm_gla2gpa\');}' unless defined(&VM_GLA2GPA_NOFAULT);
eval 'sub VM_ACTIVATE_CPU () { &_IOW(ord(\'v\'), &IOCNUM_ACTIVATE_CPU, \'struct vm_activate_cpu\');}' unless defined(&VM_ACTIVATE_CPU);
eval 'sub VM_GET_CPUS () { &_IOW(ord(\'v\'), &IOCNUM_GET_CPUSET, \'struct vm_cpuset\');}' unless defined(&VM_GET_CPUS);
eval 'sub VM_SUSPEND_CPU () { &_IOW(ord(\'v\'), &IOCNUM_SUSPEND_CPU, \'struct vm_activate_cpu\');}' unless defined(&VM_SUSPEND_CPU);
eval 'sub VM_RESUME_CPU () { &_IOW(ord(\'v\'), &IOCNUM_RESUME_CPU, \'struct vm_activate_cpu\');}' unless defined(&VM_RESUME_CPU);
eval 'sub VM_SET_INTINFO () { &_IOW(ord(\'v\'), &IOCNUM_SET_INTINFO, \'struct vm_intinfo\');}' unless defined(&VM_SET_INTINFO);
eval 'sub VM_GET_INTINFO () { &_IOWR(ord(\'v\'), &IOCNUM_GET_INTINFO, \'struct vm_intinfo\');}' unless defined(&VM_GET_INTINFO);
eval 'sub VM_RTC_WRITE () { &_IOW(ord(\'v\'), &IOCNUM_RTC_WRITE, \'struct vm_rtc_data\');}' unless defined(&VM_RTC_WRITE);
eval 'sub VM_RTC_READ () { &_IOWR(ord(\'v\'), &IOCNUM_RTC_READ, \'struct vm_rtc_data\');}' unless defined(&VM_RTC_READ);
eval 'sub VM_RTC_SETTIME () { &_IOW(ord(\'v\'), &IOCNUM_RTC_SETTIME, \'struct vm_rtc_time\');}' unless defined(&VM_RTC_SETTIME);
eval 'sub VM_RTC_GETTIME () { &_IOR(ord(\'v\'), &IOCNUM_RTC_GETTIME, \'struct vm_rtc_time\');}' unless defined(&VM_RTC_GETTIME);
eval 'sub VM_RESTART_INSTRUCTION () { &_IOW(ord(\'v\'), &IOCNUM_RESTART_INSTRUCTION, \'int\');}' unless defined(&VM_RESTART_INSTRUCTION);
eval 'sub VM_SNAPSHOT_REQ () { &_IOWR(ord(\'v\'), &IOCNUM_SNAPSHOT_REQ, \'struct vm_snapshot_meta\');}' unless defined(&VM_SNAPSHOT_REQ);
eval 'sub VM_RESTORE_TIME () { &_IOWR(ord(\'v\'), &IOCNUM_RESTORE_TIME, \'int\');}' unless defined(&VM_RESTORE_TIME);
}
1;
Zerion Mini Shell 1.0