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Mini Shell
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| Current File : //usr/sbin/cxgbetool |
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xM M ; M : SGE_PF_KDOORBELL QueuesPerPagePF2 QueuesPerPagePF0 perr_pd_fifo1 perr_ulptx_fifo0 err_itp_time_paused SGE_INT_ENABLE3 RspCreditEn2 SGE_STAT_TOTAL SGE_CTXT_MASK0 Ingress2_Log2Size SGE_LA_RDPTR_7 SGE_LA_RDDATA_9 SGE_LA_RDDATA_14 DReqPerr StateAReq PCIE_PIO_FIFO_CFG VecBase CH2 CH1_SOP SRD3 SRD6 RCEP RNPI PMC4 NoSoftReset GPIO15_Out_Val GPIO7_CHG_DET GPIO15 ARM_ERROR_OUT_int_cause DBG_GPIO_ACT_LOW DBG_TRACE0_DATA_OUT dtu_err_b6 MC_PCTL_DTUPRD2 MC_PCTL_TINIT pvt_upd_req_en phy_upd_trig_type MC_PCTL_PHYTUPDON MC_DDR3PHYAC_GCR OCOEN MC_PVT_REG_IN_DRVP MC_PVT_REG_SAMPLE_WAIT_CLKS THRESHOLD0 MA_TP_TH1_DEBUG_CNT MEM_WRAP_CLIENT_NUM CL4_PAR_WRQUEUE_ERROR_EN CL8_PAR_RDQUEUE_ERROR_EN CL7_PAR_RDQUEUE_ERROR BlkRdBootIntEn RspOvrLookupInt BlkWrBootInt IbqDbgWr CIM_PI_LA_DEBUGDATA CIM_DEBUG_UP_UPACC_CAUSE_MASK TcpOptParserDisCh2 CrcPassPrt3 CrcPassPrt0 CChecksumCheckIP EQfcDmac SYNCookieParams IPChecksumOffload RxMaxOpCnt WindowScaleMode AutoState3 TP_PARA_REG3 RxDdpOffInit CngCtrlMode TP_INIT_SRTT RowIndex ULPType0Field TNL2tupEnIpv6 TNL2tupEnIpv4 UdpEnable TP_RSS_CONFIG_OFD TP_PIO_DATA TP_SYNC_TIME_HI OfdRate3 Pbl_bound_err_ch2 pbl_fifo_perr_set0 cmd_fifo_perr_set0 ULP_TX_FPGA_CMD_15 SOP_CNT_ALG_IN EOP_CNT_ALG_IN ULP_TX_LA_RDPTR_9 PM_RX_STAT_LSB iespi2_Tx_framing_error ocspi1_ofifo2x_Tx_framing_error PM_TX_STAT_COUNT PLInt CH_MAP0 DA MPS_PFVF_ATRB_FLTR9 MPS_TX_PERR_INJECT ValidPt3 ValidPt2 TfMinPktSize LpbkErrStat MPS_PORT_STAT_LB_PORT_256B_511B_H MPS_PORT_STAT_RX_PORT_BCAST_L MPS_PORT_STAT_RX_PORT_LEN_ERROR_L MPS_PORT_STAT_RX_PORT_1519B_MAX_H MPS_PF_STAT_TX_PF_BCAST_BYTES_H MPS_PF_STAT_TX_PF_BCAST_FRAMES_L MPS_PORT_CLS_HASH_CTL MultiListen2 sge_enable SlvFifoPerrEn MI_CFG ENABLE_DDPMF_0 ULP_RX_STAG_LLIMIT EOP_CNT_OUT1 ELOOKDUMEN IPv4ONLYEN LE_DB_MASK_IPV6 bmc_drop_non_bc NCSI_BUS_DEBUG RetryTest LinkChange NCSI_MACB_FCS_ERR Rx_Byte_Swap AuxExt_Reset XGMAC_PORT_BUILD_REVISION FltCtrl HSSPLL_LOCK HSSPRBSErr TXAOBS RXAPRBSEN HSSPLLLOCK XGMAC_PORT_XGM_TX_PAUSE_QUANTA CopyPreamble EnExtMatch XGMAC_PORT_PCSR_CTRL rx_prbs31_en rx_tst_dat_sel XGMAC_PORT_AN_NP_LOWER_TRANSMIT XGMAC_PORT_AE_REG_MODE FSM_TR_ACT MC_RX_RDY IDAC RAEOFF SIGDET XGMAC_PORT_HSS_RXA_DFE_CTRL D11AMP XGMAC_PORT_HSS_RXA_DFE_E0_E1_OFFSET ADSN EMBUMP XGMAC_PORT_HSS_RXA_DFE_H1 FROTO XGMAC_PORT_HSS_RXB_DFE_D10_D11_OFFSET XGMAC_PORT_HSS_TXC_MODE_CFG XGMAC_PORT_HSS_TXC_EXT_ADDR XGMAC_PORT_HSS_TXD_TAP1_COEFF XGMAC_PORT_HSS_RXC_DFE_CTRL XGMAC_PORT_HSS_RXD_DACA_MIN XGMAC_PORT_HSS_RXD_DIGITAL_EYE_METRICS RXBEN LFREQ2 XGMAC_PORT_HSS_RX_DDC dbfifo_hp_int_low perr_pointer_data_fifo1 SGE_DBP_FETCH_THRESHOLD_QUEUE SGE_DBFIFO_STATUS3 debug_PC_Req_SOP0_cnt debug_PD_RdReq_EOP2_cnt debug_M_rd_req_outstanding_IMSG debug_st_dbp_dbfifo_main Ingress1_Size EnableSKPParityFix HoldCplEnteringL1 PH0 VC0_NPD_Credits PostCursor VFID_SleepStatus VC1_SleepReq LnB_RxPwrState GPIO16_IN DBG_T5_STATIC_M_PLL_CONF5 T5_STATIC_KR_PLL_ANALOGTUNE T5_STATIC_KX_PLL_CCALCVHOLD STATIC_C_DFS_FFTUNE4 STATIC_U_DFS_ENABLE GPIO16_PE_En DBG_EFUSE_BYTE44_47 EXT_MEM0_BASE MA_PCIE_RDDATA_CNT MA_EXT_MEMORY1_RDDATA_CNT1 CL5_WR_CMD_TO_EN CL8_WR_DATA_TO_ERROR CL11_RD_CMD_TO_EN CL9_RD_CMD_TO_EN CL5_RD_CMD_TO_EN CL11_IF_PAR_ERROR VLANExtEnPort0 IssFromCplEnable ma_intf_sdc_err TxOutMAC1_CGEN MPS_STAT_STOP_UPD_PF MPS_STAT_STOP_UPD_RX_VF_64_95 MPS_PORT_STAT_RX_PORT_MAC_ERROR_H SMAC_TCAM_SEL cpl_map_tbl_idx CHANNEL_CGEN atomic_req_len PL_BusPerr AEC0Reset MAC_PORT_MAGIC_MACID_HI HSSPLLLOCKA TXCQUIET_STATUS TXDREFRESH_STATUS sd2_CGEN sd1_CGEN MAC_PORT_PTP_TIMER_RD0_LO MAC_PORT_IFOUTBROADCASTPKTSHI MAC_PORT_AMACCONTROLFRAMESTRANSMITTEDHI PS1 MAC_PORT_MTIP_MDIO_DATA MAC_PORT_MTIP_VLAN_TPID_0 MAC_PORT_MTIP_PCS_PKG_ID1 TECH_ABILITY_1 XNP MAC_PORT_LP_BEAN_XNP_0_LANE1 MAC_PORT_FEC_ABILITY T5_AE2_RXSTAT_RDY MAC_PORT_AE_REG_MODE_2 MAC_PORT_AE_RX_COEF_REQ_3 MAC_PORT_AE_PRBS_CTL_3 AET_STAT MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_3 MAC_PORT_BANDGAP_CONTROL REFVALIDD RXCLKSEL MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_1 T5C2BUFDCEN ASEGEN C0MAX MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTE_4 MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_APPLIED MAC_PORT_TX_LINKC_TRANSMIT_DCC_OVERRIDE MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_DATA MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_4 MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_3 MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 MAC_PORT_RX_LINKA_RECEIVER_CONFIGURATION_MODE T5_RX_LINKRST T5_RX_ASAMPQ SNUL MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 MAC_PORT_RX_LINKA_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC MAC_PORT_RX_LINKA_DYNAMIC_DATA_CENTERING_DDC LOFE3S_ReadOnly H2OSN_ReadWrite H4ESN_ReadWrite H9GS MAC_PORT_RX_LINKB_RECEIVER_INTERNAL_STATUS MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_1 MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_1 MAC_PORT_RX_LINKC_DFE_TAP_ENABLE MAC_PORT_RX_LINKC_DFE_H8_AND_H9 MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS MC_DDRPHY_PC_AD32S_PLL_LOCK_STATUS REFRESH_CONTROL ERROR_DIGITAL_EYE BIT_ENABLE_0_11 MC_ADR_DDRPHY_ADR_DIFFPAIR_ENABLE MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN1 ADR_LANE_0_11_PD VREG_VREGSPARE ADR_RX_PD MC_DDRPHY_DP18_SYSCLK_PR MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR MC_DDRPHY_DP18_RD_ERROR_MASK0 TWO_CYCLE_ADDR_EN MC_DDRPHY_SEQ_ODT_WR_CONFIG0 GLOBAL_PHY_OFFSET RD_CNTL_ERROR_MASK MC_UPCTL_LPDDR2ZQCFG t_rp MC_UPCTL_DFIODTCFG MC_UPCTL_DFIODTCFG1 dfi_rdlvl_gate_mode PHY_DRAM_WL MC_P_ECC_CTRL MC_CE_ADDR MC_UE_ADDR MC_P_DEEP_SLEEP err_th2_max_fetch fatal_outp_drdy Ingress0_Base imsg_gts_sel debug_bar2_eop_cnt dbg_tbuf_used0 thread_st_cimfl MARspUE LnI_CMD Lane9FS Lane12FS PCIE_FLR_VF4_STATUS PCIe_WARM_RST_MODE1_STATE_flag PF2_DState STATIC_M_PLL_RANGEPRE DBG_STATIC_C_PLL_CONF2 STATIC_U_PLL_STOPCLKB STATIC_U_PLL_FFBYPASS DBG_CUST_EFUSE_PROGRAM HMA_WRT_EN FUTURE_CEXPANSION_WTS ULPType1Length edma_in_fifo_perr_set1 HASH_EN_MAC Outer_IPv6_n_Inner_IPv4 non_runt_frame Err_IP_Payload_Len MPS_STAT_STOP_UPD_RX_VF_160_191 MPS_CLS_MATCH_CNT_PROM LE_DB_MAX_NUM_HASH_ENTRIES ClCamCrcParErr an_data_ctl pcs40g_reset_rxclk CTL_FSM_CUR_STATE Perr_rx8_pcs100g Perr_tx2_pcs40g Perr_rx2_fec40g MAC_PORT_PTP_PERIODIC_ALARM Hold_time_setting Port_PHY_Addr MAC_PORT_MTIP_1G10G_CL01_PAUSE_QUANTA MAC_PORT_MTIP_1G10G_CL23_PAUSE_QUANTA MAC_PORT_MTIP_1G10G_CL23_QUANTA_THRESH CL7_QUANTA_THRESH MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_4 PWR_DWN 100BasexFullDplx TX_LPI_ACTIVE Receive_Fault MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_0 MAC_PORT_MTIP_KR4_SPEED_ABILITY MAC_PORT_MTIP_KR4_CONTROL_2 ERR_BLK_CNTR MAC_PORT_MTIP_KR4_CORE_REVISION VSD_2_PRESENT MAC_PORT_MTIP_CR4_PKG_ID1 MAC_PORT_MTIP_CR4_BASE_R_TEST_ERR_CNT LANE_ALIGN_STAT Lane_0_blck_lck Lane_13_blck_lck MAC_PORT_MTIP_RS_FEC_SYMBLERR1_LO T5_TXREQ_C3 FRCERR AS1X0 OS4X7 MAC_PORT_TX_LINKB_TRANSMIT_APPLIED_TUNE_REGISTER MAC_PORT_TX_LINKB_TRANSMIT_AE_C0_LIMIT_EXTENDED MAC_PORT_TX_LINKC_TRANSMIT_AE_C3_LIMIT_EXTENDED MAC_PORT_TX_LINKD_TRANSMIT_TAP_SIGN_APPLIED_REGISTER MAC_PORT_TX_LINKD_TRANSMIT_AE_C3_INIT_EXTENDED MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_5_4 MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C1_LIMIT_EXTENDED FVOFFSKP WGAIN ACCPLASTEP OVRTAILV DCDSTEP QCCOVRDEN ASYNCDIR MAC_PORT_RX_LINKB_RECEIVER_IQAMP_CONTROL_1 MAC_PORT_RX_LINKB_DFE_OFFSET_VALUE MAC_PORT_RX_LINKD_RECEIVER_DACAP_AND_DACAN_SELECTION MAC_PORT_RX_LINKD_DFE_TAP_CONTROL ADDR_MIRROR_BA0_BA1 WIDTH0 MIRROR MC_LMC_INITSEQ0 MC_LMC_CMD14 REFI MC_LMC_SDTR2 T_SYS_RDLAT T_CCD_L T_PHY_WRLAT TDQS CWL BCmdLen Edram0RdEnLo EDC_H_DBG_BIST_WR_DAT_CYC_CNT dead_cycle0 TPH PAGE_SIZE3 MPS_VF_STAT_TX_VF_BCAST_BYTES_H MPS_VF_STAT_RX_VF_UCAST_BYTES_H PL_VF_REV CIM_VF_EXT_MAILBOX_STATUS quit %*u:%u %-47s %#-10x %u
tp DIP , vlan=rewrite(%x) %d fcoe dip action switch queue unknown vlan parameter "%s"; must be one of "none", "=<vlan>", "+<vlan>" IPv4 ReschedulePending: QueueType: InterruptIDX: CongMode: invalid tid "%s" do not SN %s
SMM8 CHELSIO_T4_LOAD_CFG TF_TX_PACE_FIXED TF_ASK_MODE rx_frag2_len_raw IRS modulo marker_interval when enterring iWARP mode cq_idx_rq STAG TF_DDP_BUF1_VALID OPT_0_TX_CHANNEL %-12s (%-2u), %s, lock_tid %u, init %u
timer %u, dack_timer %u
NAT_seq_check Tag for DDP buffer QueuesPerPagePF1 perr_mc_pc perr_align_ctl_fifo0 perr_edma_fifo1 SGE_FL_BUFFER_SIZE7 LL_Read_Wait_Disable Ingress1_Log2Size TC0_Stamp LinkDnRstEn PIOPauseDone PCIE_SYS_CFG_READY PCIE_HMA_REQ_CNT PCIE_MSI_EN_7 PCIE_MSIX_EN_7 SWD7 SRD2 RCCI IN0H OC2T ALEI CPM1 Offset DBG_DBG1_CFG GPIO14_OEn GPIO12_OEn GPIO5_Out_Val STATIC_M_PLL_TUNE STATIC_KX_PLL_N3 STATIC_KX_PLL_BYPASS U_OCLK_MUXSEL DBG_PVT_REG_IN_TERMN REG_IN_DRVN_B start_cmd rank1_odt_write_nsel rank0_odt_default rank0_odt_read_sel rank0_odt_read_nsel dtu_err_b4 bank_addr_width MC_PCTL_TCL MC_PCTL_TDQS MC_PCTL_ECCTST dtu_wr_col dtu_wr_multi_rd MC_PCTL_DTUECTL wr_multi_rd_rst run_error_reports phy_upd_req_en MC_PCTL_PHYPVTSTAT dyn_soc_odt_aten PHYINIT MC_DDR3PHYDATX8_WLDPR MC_DDR3PHYDATX8_WDBDR8 MC_DDR3PHYDATX8_WDBDMR MC_DDR3PHYDATX8_RDBDR2 MC_PVT_REG_UPDATE_CTL MC_STATIC_CFG_STATUS MA_LE_DEBUG_CNT CL4_PAR_RDQUEUE_ERROR_EN CL3_PAR_RDQUEUE_ERROR uPCRst TieQOutParErrIntEn OBQULP2ParErr Timer1Int MstPlIntEn LADbgEn CIM_MEM_ZONE2_VA Timer1En MBOwner TP_IN_CONFIG EPriority TCAMServerUse TimestampsMode CMCacheDisable EnableMaxRcvWnd TimerBackoffIndex6 EmptyRqEnable DisablePDURxmt TP_ENG_CONFIG TP_PACE_TABLE OFDLkpEn KeyWrAddr TP_RSS_CONFIG_CNG ETpOutTcpFifoPerr ETpOutEthFifoPerr RxRcvWndLtMss TxRxmFin EnableHdrFull1 DbgLaEnable ULP_TX_PERR_INJECT Ch2Size1 Ch0Size1 EOP_CNT_ULP2TP ULP_TX_LA_RDPTR_10 iespi3_Tx_framing_error icspi2_Tx_framing_error oespi3_Rx_framing_error RxIntEnb MPS_TX_PAUSE_RETRANS_BUF_GRP0 oVlanSelMac3 USED MPS_RX_PAUSE_GEN_TH_3 ADDR MAC_CNT3 Ch3_Prty CFI MPS_STAT_PERR_INT_CAUSE_TX_FIFO MPS_PORT_STAT_LB_PORT_65B_127B_L MPS_PORT_STAT_RX_PORT_FRAMES_H MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L Replicate MPS_PORT_CLS_PROMISCUOUS_CTL VLAN_Mask Priority3 SlvAddrCfg MstTxFifoParEn SubsystemDeviceID St RegAddr MI_OP CAUSE_MPARC_0 PERR_ENABLE_FF PERR_ENABLE_DDPDF_1 ULP_RX_RQUDP_LLIMIT SOP_CNT_OUT0 SOP_CNT_MR0 PMU DBGICMDTYPE LE_RSP_DEBUG_LA_TCAM_WRPTR CH3_SADDR_EN NC2CIM_SOP_CNT CIM_DM_prty_err NCSI_MACB_NETWORK_CTRL XGM_Tx_Disable_Pre RXFIFO_Reset XGMAC_PORT_FPGA_PAUSE_CTL ClearMatch MAC_Link_Up TXBPRBSRST CfgClkSpeed XGMAC_PORT_XGM_RX_HASH_HIGH XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_3 TxErrFIFO XGMAC_PORT_XGM_MDIO_CTRL test_cnt_125us Transmitted_Nonce XGMAC_PORT_HSS_TXA_DRIVER_MODE XGMAC_PORT_HSS_TXA_TDM_BIASGEN_PWRON_TIMER XGMAC_PORT_HSS_TXA_PWR XWR XGMAC_PORT_HSS_TXB_TAP0_COEFF SIGNSD FRCH NONRND HBND0 XGMAC_PORT_HSS_RXA_DFE_H4 DACCMP XGMAC_PORT_HSS_RXC_DFE_H2 TCDIS XGMAC_PORT_HSS_BAND_GAP_CTRL XGMAC_PORT_HSS_TX_MODE_CFG uPCutoffThreshLp HintDepthCtlFL Force_Ordering EDMA1_Sleep_Status Throttle_Threshold_fl debug_UD_Rx_EOP1_cnt debug_PC_Req_SOP1_cnt debug_CPLSW_EOP0_cnt debug_st_dbp_thread1_cimfl debug_st_flm_dbptr INTVFAllMSIDisErr CfgdMaxPyldSz MaxReqSize CookieA PCIE_VC1_CDTS1 PCIE_CORE_ACK_FREQUENCY_L0L1_ASPM_CONTROL PCIE_CORE_QUEUE_STATUS RspEOPMatchSOP IP_RxPerr IP_FrontTxPerr PCIE_PHY_REQRXPWR LnC_CMD CoeffStart DBG_GPIO_IN_NEW FUSE_DONE_SENSE T5_STATIC_M_PLL_MULTFRAC DBG_T5_STATIC_KR_PLL_CONF2 DBG_GPIO_PE_EN DBG_EFUSE_BYTE48_51 MA_PARITY_ERROR_ENABLE1 MA_PARITY_ERROR_STATUS1 MA_PMRX_THROTTLE MA_TP_TH0_WRDATA_CNT MA_EXT_MEMORY0_WRDATA_CNT0 CLR DIR FUTURE_CEXPANSION CL8_RD_DATA_TO_ERROR CL5_IF_PAR_EN DEBUG_RPT EnableXoffPdu SOF_FS3 ULP_TX_CGEN_Storage MPS_TX_PAUSE_DURATION_BUF_GRP_TH0 MPS_TX_PAUSE_DURATION_BUF_GRP_TH12 MPS_TX_PAUSE_RETRANS_BUF_GRP_TH12 MPS_RX_CGEN_OUT SE_CNT_MISMATCH_1 rdma_pbl_pref_en SRCHHADDR MtipSd2TxRst MtipSd1RxRst MtipSd0RxRst AEC3_TX_WIDTH MAC_PORT_LINK_STATUS MAC_PORT_HSS_CFG0 HSSREFCLKVALIDA RXACONFIGSEL MAC_PORT_HSS_PL_CTL MAC_PORT_PTP_OFFSET_ADJUST_FINE B MAC_PORT_MTIP_FRM_LENGTH MAC_PORT_AFRAMESTRANSMITTEDOK MAC_PORT_VLANRECEIVEDOKHI MAC_PORT_IFOUTUCASTPKTSHI MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3 MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6 MAC_PORT_MTIP_SGMII_STATUS JabberDetect PS2 USE_SGMII_AN read LP_BEAN_ABILITY MAC_PORT_BEAN_ABILITY_2_LANE1 MAC_PORT_BEAN_XNP_0_LANE3 MAC_PORT_BEAN_XNP_2_LANE3 MAC_PORT_FEC_CERR_CNT_0 T5_AE0_RXSTAT_C1 MAC_PORT_AE_FSM_CTL EN_H1T_EQ MAC_PORT_AET_ZFE_LIMITS_1 RCRST JTAGMD HSSACJPC MAC_PORT_PLLA_EYE_METRICS_INTERVAL_CONTROL T5_TX_LINKEN MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_4 MAC_PORT_TX_LINKB_TRANSMIT_AMPLITUDE MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED MAC_PORT_TX_LINKC_TRANSMIT_DCLK_DRIFT_TOLERANCE MAC_PORT_TX_LINKD_TRANSMIT_DCLK_DRIFT_TOLERANCE MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_MODE_CONTROL MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_1 FWSNAP T5_RX_TRAINEN DPCMD T5DPCCMP T5E1AMP OFFAMP ISTRIMS SM2RDY H5ESN_ReadWrite H11GS SDLSSD ACJZPT MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PATTERN_LENGTH MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 MAC_PORT_RX_LINKC_DFE_H10_AND_H11 MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_3 MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_1 MAC_PORT_RX_LINKD_DFE_H3 RANK_PAIR2_PRI RANK_OVERRIDE_VALUE VREFDQ0D ERROR_WR_LEVEL_MASK ERROR_INITIAL_PAT_WRITE_MASK MC_ADR_DDRPHY_ADR_DELAY3 ADR_TEST_CLEAR_ERROR EN_SLICE_N_WR_3 SLICE_SEL_REG_BITS8_9 SLEW_CTL_SEL_BITS8_9 SLEW_EARLY_SAMPLE QUAD0_CLK16_BIT0 CLK18_SINGLE_ENDED_BIT11 DQ_WR_OFFSET_N3 PEAK_AMP_CTL_SIDE0 INITIAL_DQS_ROT_N0_N2 MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR DRIFT_ERROR MC_DDRPHY_DP18_RD_DIA_CONFIG5 TRFC_CYCLES FORCE_ON_CLK_GATE clock_stop MC_UPCTL_DTUNA MC_UPCTL_DTUAWDT MC_UPCTL_TRCD dfi_rdlvl_rank_sel dfi_dram_clk_disable_en_dpd MC_UPCTL_DFISTPARCLR MC_P_PERFORMANCE_CTRL deq_ll_perr db_dbg_en SGE_CONM_CTRL2 SGE_DBG_BAR2_PKT_CNT debug_idma1_idma2imsg_cmp_out_rss PfEQsPerPage PF5_DState STATIC_C_PLL_FFSLEWRATE STATIC_U_PLL_FFSLEWRATE STATIC_KR_PLL_CCALFMAX DBG_CUST_EFUSE_BYTE24_27 DBG_CUST_EFUSE_BYTE32_35 MA_DDR_DEVICE_CFG FUTURE_DEXPANSION_WTS EnableFcoeCheck ULPType6Offset ULPType4Length map_fifo_perr_set3 bypass_first MPS_RX_FIFO_3_CTL Outer_IPv4_n_Double_VLAN_NVGRE Outer_IPv4_n_Double_VLAN_GENEVE MPS_TX_NCSI2MPS_CNT DisEncapOuterRplct ClsTrcLkpType ClsTrcIndex ClsTrcVF_Vld MPS_CLS_DIPIPV4_MASK_TABLE rdma_version_0 CMDLIMIT NUMHASHBKT LE_DB_RSP_CODE_0 HPRI_FILT_HIT DBGIRspTid pcs100g_gate_cgmii_rxclk pcs100g_gate_sd_rx_clk AEC_RX_LANE_ID_O MAC_PORT_AEC_DEBUG_HI_2 mac1g10g_mii_ena_10 mac1g10g_tx_ts_frm_out blk_stb_val Perr_tx1_fec40g Perr_rx0_fec40g Clk_divisor CL7_PAUSE_QUANTA MAC_PORT_MTIP_1G10G_CL45_QUANTA_THRESH MAC_PORT_MTIP_1G10G_TS_TIMESTAMP MAC_PORT_MTIP_1G10G_STATN_CONFIG MAC_PORT_MTIP_1G10G_RX_AALIGNMENTERRORSHI MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS128TO255OCTETSHI MAC_PORT_MTIP_1G10G_RX_AINRANGELENGTHERRORSHI MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_6 100BasexHalfDplx PRBS9_Pttrn_Tstng_Ability MAC_PORT_MTIP_KR4_DEVICE_ID0 MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_1 MAC_PORT_MTIP_CR4_LANE_0_MAPPING MAC_PORT_MTIP_RS_FEC_VENDOR_CONTROL MAC_PORT_MTIP_FEC0_CERR_CNT_0 MAC_PORT_PLLA_PLL_MICELLANEOUS_CONTROL AS4X4 AS2X2 MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_1X_OVERRIDE MAC_PORT_TX_LINKB_TRANSMIT_AE_C1_LIMIT_EXTENDED MAC_PORT_TX_LINKB_TRANSMIT_AE_V2_LIMIT_EXTENDED MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_4X_OVERRIDE MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_4X_OVERRIDE MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C1_INIT2_EXTENDED FACCPLDYN ACCPLSTEP UNPKVGA HBISTMAN INTDACGS H1EDELTA DCCAOVRDEN MAC_PORT_RX_LINKD_RECEIVER_INTERNAL_STATUS_2 MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_3 APPROACH_ALIGNMENT PARITY_A17_MASK ECC_COR EN_MULTI_RANK_SEL MC_LMC_CMD2 MC_LMC_CMD6 T_WTR_S QOFF RD_PRE MC_P_PHY_ADR_CK_EN MC_UE_ERR_ECC_DATA1 MCmdWr BCmdWr rddq_rdcnt INV_ALL HMA_TLB_DESC_5_L MPS_VF_STAT_TX_VF_MCAST_FRAMES_H --help reg64 regdump SPORT %02x/%02x %3s dip-dp-sp cong DCACPUID: SP_TPHint: CongEn: loadfw: incorrect number of arguments. CHELSIO_T4_LOAD_FW memdump: invalid length "%s" disable DWDM-SFP/SFP+ invalid type parameter "%s" absolute sched params "channel" missing invalid MSS specification "%s". "mss" needs a positive integer value ulp TF_RCV_COALESCE_HEARTBEAT rx_compact snd_scale Page pointer for first byte in send buffer Offset of highest sequence acked from rcv_nxt stag Current FPDU command Retransmit is out of FPDU sync rx_ddp_flags ddp_buf0_indicate ddp_push_disable_0 ddp_buf1_unused OPT_1_RSS_INFO OPT_1_CONNECTION_POLICY OPT_0_ACCEPT_MODE OPT_0_L2T_IX t_srtt %u, t_rttvar %u
tx_pace_auto %u, tx_pace_fixed %u, tx_queue %u qp_id %u, pd_id %u, stag %u
Hit_byte_cnt_high rx_tls_buf_len QueuesPerPagePF3 perr_flm_CreditFifo SGE_INT_ENABLE1 perr_hint_delay_fifo1 dbfifo_hp_int HintsAllowedHdr SGE_CTXT_MASK5 SGE_LA_RDPTR_1 SGE_LA_WRPTR_13 SGE_LA_RESERVED_14 CReqPerr MSIAddrHPerr MemReq DMAStopEn Device Function PCIE_DMA32_RSP_FREE PCIE_CORE_OUTBOUND_POSTED_HEADER_BUFFER_ALLOCATION VRB2 PTOM PME5 DBG_DBG0_CFG GPIO15_OEn IBM_FDL_FAIL_int_enbl GPIO8 STATIC_M_PLL_PREDIV STATIC_KX_PLL_V dbg_trace_operate_with_trg THRESHOLD_TERMP_MAX_SYNC DBG_PVT_REG_HISTORY_DRVP DBG_PVT_REG_HISTORY_DRVN rkinf_en rank3_odt_write_sel rank3_odt_read_sel MC_PCTL_DWLCFG1 MC_PCTL_DTURACTL dtu_wr_byte13 dtu_rd_byte6 i_pvt_upd_trig MC_PCTL_PHYTUPDDLY MC_PCTL_PVTTUPDWAIT MDLEN WLERR WLINC PLLPD MC_DDR3PHYDATX8_WDBDPR DDRSELINV RANK MC_PVT_REG_OUT_TERMP ECC_UE_PAR_ENABLE MC_BIST_USER_WDATA0 MC_BIST_USER_WDATA1 MA_CLIENT11_WR_LATENCY_THRESHOLD DIS_PAGE_HINT CL4_PAR_RDQUEUE_ERROR EDC_INST_NUM EDC_INT_CAUSE ExtMem2BaseAddr MBuPParErr IBQULPParErr PrefDropIntEn BlkRdCtlIntEn TimeOutMAInt BlkRdPlInt IllWrBEInt CIM_MEM_ZONE1_LEN CIM_MEM_ZONE3_VA RssLoopbackEnable SACKRx EnableOfdoVLAN EnableEPCMDAFull TnlErrorAny TP_FAST_FINWAIT2_TIMER Port2MTUValue MaskSize ChnUndFlow0 TP_LA_TABLE_1 RxChannelWeight1 ArpLutPerr CmCachePerr ETpOutCplFifoPerr ETpInEthFifoPerr TxRcvAdvZero sge2ulp_fifo_perr_set2 pbl_fifo_perr_set1 lso_hdr_sram_perr_set3 ULP_TX_LA_RDPTR_0 ch1_input cong_thresh1 icspi1_Rx_framing_error VFDirectAccess MPS_VF_TX_CTL_95_64 CTL_P0 MPS_RX_PERR_INT_CAUSE PG_TH_INT5 MAC_CNT2 RSS_CTRL MPS_TX_PERR_ENABLE MPS_TX_LPBK_DROP_BP_CTL_CH3 SizeCh3 DataPt1 MPS_TX_SGE_CH_PAUSE_IGNR MPS_PORT_TX_LPBK_RELOAD_CH4 TrcEn TrcMultiFilter TfPktTooLarge MPS_TRC_FILTER0_MATCH MPS_STAT_PERR_INT_CAUSE_RX_FIFO MPS_STAT_RX_BG_3_LB_DROP_FRAME_H MPS_PORT_STAT_LB_PORT_128B_255B_H MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H MatchBoth CimNoPromiscuous MacParity1 zero_switch_error SlvNoRepStartEn ArpCommandCode ENABLE_FF CAUSE_CTX_1 CAUSE_APF_0 CAUSE_AF_1 CAUSE_TPTCF_1 Hpz3 ULP_RX_TDDP_TAGMASK ULP_RX_RQ_ULIMIT PERR_ENABLE_DDPCF_0 EOP_CNT_IN1 PortxMap UART EDC1 XGMAC0 PL_INT_CAUSE PL_INT_ENABLE InvalidAccess Rgn ReqQParErr hw_arb_en NCSI_CH2_SADDR_LOW BUS_STATE_MPS_IN MACInt NoFCS NCSI_MACB_TX_STATUS XGMAC_PORT_HSS_SIGDET_STATUS CTL XGMAC_PORT_FPGA_LA_CTL MatchedFilter AutoNeg_Done MAC_Link_Down RXBPRBSRST HSSPRTREADY EnNon802_3Preamble XGMAC_PORT_XGM_RX_HASH_LOW XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_7 FrameType ModuleID XGMAC_PORT_XGM_STAT_TX_FRAME_HIGH XGMAC_PORT_XGM_STAT_RX_JABBER_FRAMES ACK_2 BP_From_LP TXSTAT_C1 TWDP SPEN VLINC XGMAC_PORT_HSS_TXB_TAP1_IDAC_APP TSOEN SDLVL BLKAZ XGMAC_PORT_HSS_RXB_TEST_CTRL XGMAC_PORT_HSS_TXC_TAP0_IDAC_OVR XGMAC_PORT_HSS_TXC_EXT_ADDR_DATA XGMAC_PORT_HSS_TXD_TEST_CTRL XGMAC_PORT_HSS_TXD_POLARITY XGMAC_PORT_HSS_RXC_TEST_CTRL XGMAC_PORT_HSS_RXD_DDC CCCMP FMIN RXBRST XGMAC_PORT_HSS_RX_PH_ROTATOR_POSITION1 SGE_PERR_ENABLE5 FLM_Reschedule_Mode debug_U_Rx_SOP1_cnt debug_U_Tx_EOP0_cnt debug_st_edma0_align debug_idma1_qid MAWrEOPErr GenPME CS2 MemOfst NPD0 PCIE_CORE_ACK_LATENCY_TIMER_REPLAY_TIMER AtmReqSOPCnt HMA_Dynamic_CGEN MAReqTimerEn IP_BackTxPerr LnF_RxStateReq MCIMPED1_out DBG_FERSEL T5_STATIC_C_PLL_RANGEB T5_STATIC_C_PLL_MULT GPIO13_PE_En GPIO11_PE_En GPIO17_PS_En GPIO9_PS_En ARB4_PAR_RDQUEUE_ERROR_EN ARB4_PAR_WRQUEUE_ERROR FL_ENABLE MA_PCIE_WRDATA_CNT MA_WRITE_TIMEOUT_ERROR_ENABLE CL12_WR_CMD_TO_EN FUTURE_DEXPANSION CL11_WR_CMD_TO_ERROR CL3_WR_DATA_TO_ERROR CL10_RD_DATA_TO_ERROR ChnErrEnable DropErrorFPMA HashXor VfFwEn ULP_TX_INT_ENABLE_2 t10_pi_sram_perr_set1 TP2MPS_Ch1 MPS_TRC_FILTER3_RSS_HASH LPBK_TCAM_PRIORITY EDC0_Part_CGEn SE_CNT_MISMATCH_0 Rdma_DataPath_CGEN PF_PBL_0 ULP_RX_INT_CAUSE_2 VfParErr RDWR MAC_PORT_CFG3 align_done Perr1_rx_mix Perr0_rx_mix RXDCONFIGSEL TXBQUIET_STATUS MAC_PORT_HSS_SIGDET_STATUS CGEN PCSSEG3_CGEN En wake_cnt MAC_PORT_MTIP_SCRATCH MAC_PORT_AINRANGELENGTHERRORSHI MAC_PORT_ETHERSTATSJABBERS MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0 PWRDWN blocklock Lane17 AMLOCK2 AMLOCK0 MAC_PORT_MTIP_PCS_BIP_ERR_CNT_0 MAC_PORT_MTIP_PCS_LANE_MAP_6 TECH_ABILITY_2 MAC_PORT_AE_TX_COEF_STAT MAC_PORT_AE_RX_COEF_REQ_1 MAC_PORT_AE_REG_MODE_3 MAC_PORT_AET_STATUS_3 RCAMPEN MAC_PORT_RESISTOR_CALIBRATION_STATUS_3 MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_3 VCOSEL MAC_PORT_PLLB_PCLK_CONTROL AMMODE T5DCCEN RPOS MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_4 MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_MODE_CONTROL MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED T5_RX_CFGPTR FREQFW H1O2 T5OCCMP T5SMQM T5EMBUMP APDF MAC_PORT_RX_LINKA_DFE_H4 MAC_PORT_RX_LINKC_PHASE_ROTATOR_CONTROL MAC_PORT_RX_LINKC_DFE_CONTROL MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PDF_EYE_COUNT RANK_PAIR1_PRI RANK_PAIR3_PRI_V MC_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE MC_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE PER_NEXT_RANK_PAIR DDR4_VLEVEL_BANK_GROUP MC_DDRPHY_PC_INIT_CAL_CONFIG0 REFRESH_INTERVAL ERROR_CUSTOM_RD MC_DDRPHY_PC_IO_PVT_FET_STATUS ADR_TEST_GEN_EN EN_SLICE_N_WR_FFE SLEW_CTL1 MC_DDRPHY_ADR_SYSCLK_CNTL_PR MRS_CMD_DATA_N1 ATEST_MUX_CTL2 DISABLE_TERMINATION MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR REFERENCE_BITS1_7 MC_DDRPHY_DP18_READ_TIMING_REFERENCE1 COARSE_PATTERN_ERR_N3 INCOMPLETE_RD_CAL_N2_MASK DONE WL_ERR_CLK18 INVALID_NS_BIG_R_MASK EN_TERM_P_WR MC_DDRPHY_DP18_IO_TX_CONFIG0 MEMINTD09_POS MEMINTD20_POS MC_DDRPHY_SEQ_ODT_WR_CONFIG2 BIG_STEP MC_DDRPHY_RC_CONFIG0 MC_UPCTL_POWCTL MC_UPCTL_CMDTSTAT lpddr2_s4 MC_UPCTL_TRP MC_UPCTL_TRTP MC_UPCTL_ECCLOG dfi_data_byte_disable_en dfi_lp_en_pd MC_P_FPGA_BONUS L_SEL gts_dbg_timer_reg SGE_IDMA0_DROP_CNT Req_LnF_RxStateDone Req_LnA_RxStateDone Req_LnL_RxPwrState LnJ_CMD PCIE_VF_INT_INDIR_DATA PCIE_DEBUG_ADDR_RANGE1 DBG_STATIC_M_PLL_CONF1 STATIC_C_PLL_FFTUNE STATIC_U_PLL_DIVCHANGE STATIC_U_PLL_FFTUNE STATIC_KR_PLL_CCALMETHOD DBG_CUST_EFUSE_BYTE48_51 BRBC_MODE SEQ_UPDATE_EN edma_in_fifo_perr_set3 flush_first SpeedMode MPS_VF_RX_CTL_255_224 IVLAN_ETYPE SAP_VALUE EN_IP_PAYLOAD_LEN_CHK MPS_RX_CNT_TNL_ERR_PKT_LPBK1 MPS_PORT_RX_VF_MAP4 MPS_STAT_STOP_UPD_TX_VF_160_191 MPS_STAT_STOP_UPD_RX_VF_192_223 ClsTrcMatch LE_TCAM_SIZE ERR_CID Aec_pat_data PCS10G_RESET REF_Clk_Sel pcs100g_reset_sd1_rx_clk mac1g10g_gate_txclk aec_rx an_clk_enable CUF_C0_UPDATE AlmostEmpty MAC_PORT_MTIP_1G10G_RX_OCTETSOK MAC_PORT_MTIP_1G10G_RX_APAUSEMACCTRLFRAMESHI MAC_PORT_MTIP_1G10G_RX_IFINERRORS MAC_PORT_MTIP_1G10G_TX_APAUSEMACCTRLFRAMES MAC_PORT_MTIP_1G10G_TX_IFUCASTPKTSHI MAC_PORT_MTIP_KR_VENDOR_SPECIFIC_PCS_STATUS MAC_PORT_MTIP_KR4_VL_INTVL MAC_PORT_MTIP_CR4_STATUS_2 MAC_PORT_MTIP_CR4_PKG_ID0 Lane_5_blck_lck Lane_16_blck_lck MAC_PORT_MTIP_RS_FEC_NCCW_HI amps_lock MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_KEY MAC_PORT_MTIP_FEC_STATUS2 FEC_REQUEST VBGENDOC MAC_PORT_PLLB_POWER_CONTROL AS2X3 SEGSEL C3PRESET MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C2_INIT2_EXTENDED SERVREF PILOCK DACCLIP DPCWPK DCCIND LOFCH HCOMP MAC_PORT_RX_LINKA_AC_COUPLING_CURRENT_SOURCE_ADJUST MAC_PORT_RX_LINKB_DFE_H1H2H3_LOCAL_OFFSET MAC_PORT_RX_LINKB_DFE_H12_13 MAC_PORT_RX_LINKC_RECEIVER_POWER_MANAGEMENT_CONTROL MAC_PORT_RX_LINKC_PEAKED_INTEGRATOR MAC_PORT_RX_LINKC_RECEIVER_LOFF_CONTROL_REGISTER MAC_PORT_RX_LINKD_RECEIVER_AC_COUPLING_VALUE MAC_PORT_RX_LINKD_H_COEFFICIENBT_BIST MC_DDRPHY_AD32S_POWERDOWN_1 ADVANCE_PR_VALUE DQS_QUAD_CONFIG QUAD1_PWR_CTL DM_ENABLE MC_LMC_INITSEQ4 T_RTW_ADJ T_PL STATIC_PP64 MRspRdy rdsideq_notfull MPS_VF_STAT_TX_VF_BCAST_FRAMES_L CIM_VF_EXT_MAILBOX_DATA_38 pmtx list trailing arguments after "list" ignored. vnic_id fl invalid context id "%s" StatusPgRO: FetchRO: DropRSS: ID: %s
QSFP ddp migrating TF_DACK_MSS tx_pace_auto TF_MOD_SCHD_REASON1 rdma_error TF_RECV_TSTMP TF_CCTRL_ECN Offset of snd_max from tx_max rx_frag2_ptr_raw Current MSN (modulo 8K, further check in ULP_RX) ddp_active_buf rx_ddp_buf1_len t_rtt_ts_recent_age %u t_rttseq_recent %u
frag1_idx %-10u length %-10u rcv_wnd %u. (snd_scale %u, recv_scaleflag = %u)
rx_flow_ctrl_ddp %u
MISCELANEOUS:
NAT_Mode perr_edma_fifo2 perr_idma2imsg_fifo0 err_data_cpl_on_high_qid1 dbfifo_lp_int ingress_size_err SGE_FL_BUFFER_SIZE14 SGE_INT_CAUSE4 err_bad_upfl_inc_credit1 SGE_CTXT_DATA4 SGE_CTXT_MASK7 SGE_LA_WRPTR_12 PCIEPINT HReqPerr BypassMSIXCache IPLaneSwap LocalCfg Window GBIF_MAX_WRSIZE PCIE_CDEBUG_DATA_LOW PCIE_RSP_ERR_STAT_3 CRMC OP1H TDUE RDPS ALER CPM6 CLIDecEn DBG_GPIO_EN GPIO10_OEn GPIO0_OEn GPIO9_IN GPIO6_IN GPIO4 DBG_DBG0_RST_VALUE DBG_OVERWRSERCFG_EN ExPHYClk_sel_en STATIC_KR_PLL_BYPASS DBG_TRACE_CONF DBG_PVT_REG_CALIBRATE_CTL THRESHOLD_DRVN_MAX_SYNC DBG_PVT_REG_IN_TERMP DBG_PVT_REG_IN_DRVN DBG_PVT_REG_OUT_TERMN pd_type ecc_intr_en MC_PCTL_ECCLOG dtu_row_increments dtu_wr_byte11 MC_PCTL_PHYIOCRV1 ACCAL MC_DDR3PHYAC_PSCR PHYHRST RSTCLKS POND MC_DDR3PHYDATX8_RDBDR7 MC_DDRPHY_RST_CTRL MC_PERFORMANCE_CTRL ECC_UECNT STATIC_DEN MA_CLIENT0_RD_LATENCY_THRESHOLD MA_CLIENT0_WR_LATENCY_THRESHOLD MA_CLIENT6_RD_LATENCY_THRESHOLD DBG_WRITE_DATA_CNT EDRAM0_ENABLE MA_TP_THREAD1_MAPPER CL6_PAR_RDQUEUE_ERROR CIM_BOOT_CFG uPGen BootSdram CIM_SDRAM_ADDR_SIZE OBQULP0ParErr BlkRdPlIntEn OBQSelect PILADbgRdPtr CIM_PO_LA_PIFSMDEBUGDATA CChecksumInsertTCP TP_GLOBAL_CONFIG CxMaxOpCnt AutoCareful DisableWindowPSH DisableHeldFIN EnableUDP4TupRss SwsTimer TnlErrorAttack ChnCount0 ChnOvrFlow0 CmOpExtFifoPerr TP_FLM_FREE_PS_CNT CommitReset2 ForceCong2 TxChnXoff1 TP_PROTOCOL_DATA1 TP_PROTOCOL_DATA2 TP_PROTOCOL_DATA4 cmd_fifo_perr_set3 ULP_TX_ERR_CNT_CH0 ULP_TX_ERR_CNT_CH3 ULP_TX_FPGA_CMD_6 ULP_TX_LA_RESERVED_2 ULP_TX_LA_WRPTR_6 ULP_TX_LA_RDDATA_10 PM_RX_INT_CAUSE icspi3_Tx_framing_error MPS_INT_CAUSE ClsInt MPS_PORT_PAUSE_CTL RegSendOn RxSending Prty3 MPS_RX_PG_SHR_BG1 MPS_RX_PG_HYST_BG0 PGME MPS_RX_PT_ARB1 VLAN_EN MPS_PFVF_ATRB_FLTR14 MPS_VF_RPLCT_MAP0 MPS_TX_INT_CAUSE TfDropInpCount MPS_TRC_TIMESTAMP_L MPS_PORT_STAT_TX_PORT_64B_H MPS_PORT_STAT_TX_PORT_PPP1_H MPS_PF_STAT_RX_PF_UCAST_FRAMES_H VLAN_Valid CPL_SWITCH_TBL_DATA MstFifoDbgClr MstTxFifoPerrEn SMB_COMMAND_CODE2 ENABLE_PRSDF_0 CAUSE_PCMDF_0 ULP_RX_SE_CNT_CH0 SOP_CNT_AL0 SOP_CNT_IN1 Lock SWIntCIM MAP7 LE_DB_HASH_TABLE_BASE DropFilterHit ParityErr FullDuplex TxBufUnderrun MgmtFrameSent NCSI_MACB_TX_UNDERRUN_ERR MagicEn AEC_PMA_RX_READY RxEop XGMAC_PORT_LA_RX_0 stop XGMAC_PORT_EPIO_DATA1 XGMAC_PORT_EPIO_OP RemoteFault TXDOBS TXBPRBSEN TXAPRBSEN XGMAC_PORT_XGM_RX_TYPE_MATCH_2 Lane3_CTC_Status ScrLoopEn ber_cnt_rst FEC_Enable RX_Pause_Okay RXSTAT_RDY RXSTAT_C1 AEINVPOL BW810 FDWRAP FILTCTL EXTEL RAOOFF NONRNF H1OSN H3EMAG XGMAC_PORT_HSS_RXA_DFE_FUNC_CTRL XGMAC_PORT_HSS_TXC_8023AP_AE_CMD LDET RXDRST ENCPIS XGMAC_PORT_HSS_TX_8023AP_AE_CMD XGMAC_PORT_HSS_TX_TAP2_IDAC_OVR perr_edma_input_fifo1 CGEN_IDMA EDMA0_Sleep_Status SGE_DEBUG_DATA_HIGH_INDEX_1 debug_PD_WrReqAFull_d debug_flm_idma1_cache_data_active debug_st_dbp_upcp_main debug_st_edma2_align_sub debug_st_edma2_align debug_st_edma1_req LinkReqRstPCIeCRstMode MSTPause ExpdCookie NPH1 Flow_Control_Timer_Modifier PCIE_CORE_FILTER_MASK2 VC4_WRR Sel_DeEmphasis PhyTxSwing WinAperture_CMins1 NPH_CreditsAvailVC1 PCIE_PB_CTL Lane1LF PCIE_PHY_PRESET_REQ GPIO18_OEn GPIO19_IN T5_STATIC_M_PLL_FFSLEWRATE T5_STATIC_KR_PLL_CCALCVHOLD STATIC_U_DFS_RANGEA GPIO19_PS_En GPIO7_PS_En GPIO1_PS_En BRC_MODE1 EXT_MEM_PAGE_SIZE1 MA_CIM_WRDATA_CNT MA_EXT_MEMORY1_WRDATA_CNT0 CL11_WR_DATA_TO_EN CL5_WR_DATA_TO_EN CL0_WR_DATA_TO_EN CL2_RD_CMD_TO_EN CL0_RD_DATA_TO_EN CL6_RD_CMD_TO_ERROR CL9_IF_PAR_ERROR NCSI2CIMIntfParErr CIM_CIM_IBQ_ERR_CODE CIM_SGE1_PKT_ERR_CODE CIM_IBQ_DBG_WAIT_COUNTER CIM_PIO_UP_MST_CFG_SEL CIM_CGEN ospi_overflow0 MTU_ERR_INT2 MPS_RX_PAUSE_GEN_TH_2_0 MPS_RX_LPBK_CLS_DROP_CNT0 MacPadEnPt0 TfInsertActLen TfInsertTimer LPBK_TCAM0_HIT_PRIORITY ULP_RX_CH0_CGEN clear_ctx_err_cnt1 atomic_op_msn_check_enable MAC0 MAC_PORT_CFG Perr2_rx_mix MAC_PORT_PERR_ENABLE HSSPRTREADYA MACSEG2_CGEN LPI_TXHOLD MAC_PORT_MTIP_TX_IPG_LENGTH MAC_PORT_IFINBROADCASTPKTSHI MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3HI MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0HI MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4HI CuDplxStatus MAC_PORT_MTIP_SGMII_EXTENDED_STATUS mdio_busy LoPwrAbl MAC_PORT_MTIP_PCS_BASER_STATUS2 RxTestPatEn MAC_PORT_MTIP_PCS_BIP_ERR_CNT_13 MAC_PORT_BEAN_STATUS MAC_PORT_BEAN_XNP_2 rx_status MAC_PORT_AE_RX_COEF_REQ AET_ENABLE T5_AE2_RXSTAT_C0 MAC_PORT_AE_TX_COEF_STAT_2 MAC_PORT_AE_KR_CTRL EN_GAIN_TOG EN_AMIN_TH MAC_PORT_AET_SIGNAL_LOSS_DETECTION_2 MAC_PORT_AET_ZFE_LIMITS_2 T5_TX_CFGPTR MAC_PORT_TX_LINKA_TRANSMIT_POLARITY DCCASTEP MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_3 BSOUT JTAGTS MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C1_INIT_EXTENDED C1MAX MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED MAC_PORT_TX_LINKB_TRANSMIT_TEST_CONTROL MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_MODE_CONTROL MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C2_INIT_EXTENDED MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_APPLIED MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED T5_RX_CFGWRT T5_RX_CFGEXT T5VGAIN DTHR FINTCAL MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_ERROR_COUNT GBOFSTLSSD MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_2 MAC_PORT_RX_LINKB_DFE_OFFSET_ODD3_ODD4 MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_1 MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_1 MAC_PORT_RX_LINK_BCST_DFE_E0_AND_E1_OFFSET MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PDF_EYE_COUNT START_PER_CAL ENA_CUSTOM_RD ERROR_INITIAL_PAT_WRITE ERROR_CUSTOM_WR_MASK MC_ADR_DDRPHY_ADR_DELAY5 EN_SLICE_N_WR_0 MC_DDRPHY_ADR_PLL_VREG_CONFIG_1 PLL_TUNEATST MC_DDRPHY_DP18_DATA_BIT_DIR1 DATA_BIT_DIR_16_23 MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR DQS_GATE_DELAY_N1 COARSE_PATTERN_ERR_N0 EYE_CLIPPING MIN_EYE_MASK BIG_STEP_RIGHT VALID_NS_BIG_R_MASK SYSCLK_RDCLK_OFFSET ANALOG_OUTPUT_STAB INVALID_REQ_SOURCE MC_DDRPHY_SEQ_MEM_TIMING_PARAM1 DQ_SEL_LANE MC_UPCTL_DFITPHYUPDTYPE0 MC_UPCTL_DFISTCFG1 MC_UPCTL_DFILPCFG0 STATIC_LAT MC_CE_COR_DATA_RDATA MC_P_BIST_USER_WDATA0 MC_P_BIST_USER_WDATA1 ECC_CE_INT0_CAUSE HMA_TABLE_LINE2 deq_out_perr 100ns_timer SGE_QBASE_MAP1 fl_deq_cnt debug_idma0_idma2imsg_cmp_out_srdy VfWCOffEn Req_LnC_RxStateDone KDB_VF_BaseAddr Lane10FS PHY0_RTune_Req STATIC_M_PLL_FFTUNE STATIC_M_PLL_DIVCHANGE STATIC_M_PLL_VREGTUNE DBG_STATIC_C_PLL_CONF1 EnableMibVfPld EnableRdmaFix align_ctl_fifo_perr_set1 PROT_TYPE_EN MPS_RX_CNT_NVGRE_PKT_MAC0 MPS_RX_CNT_VXLAN_PKT_LPBK0 Outer_IPv4_n_VLAN_VXLAN Outer_IPv6_n_Double_VLAN_VXLAN REPL_VECT_SEL ULP_RX_TLS_CTL LE_DB_NORM_FILT_TABLE_START_INDEX UNKNOWN_CMD SRAM_SRVR_HIT_ACTF ClCamIntPerr LE_DB_SRVR_SRAM_CONFIG pcs40g_reset_sd_tx_clk pcs40g_reset_sd0_rx_clk pcs100g_reset_tx_clk pcs100g_reset_sd2_rx_clk MAC_PORT_AEC_DEBUG_LO_2 debug_sel MAC_PORT_MAC_AN_STATE_STATUS CL6_PAUSE_QUANTA MAC_PORT_MTIP_1G10G_RX_PAUSE_STATUS MAC_PORT_MTIP_1G10G_RX_AALIGNMENTERRORS MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1519TOMAXHI MAC_PORT_MTIP_1G10G_TX_VLANOK MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS65TO127OCTETSHI MAC_PORT_MTIP_KR_PCS_SPEED_ABILITY Clause_22_Reg_Present BERBER_Counter MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_1 High_BER MAC_PORT_MTIP_KR4_BASE_R_TEST_CONTROL MAC_PORT_MTIP_CR4_CONTROL_2 Lane10_algn_mrkr_lck MAC_PORT_MTIP_RS_FEC_VENDOR_INFO_2 100GKR4 EN_RETRY AS4X5 MAC_PORT_TX_LINKA_TRANSMIT_AE_VM_LIMIT_EXTENDED C3MAX MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED MAC_PORT_TX_LINKB_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE MAC_PORT_TX_LINKC_TRANSMIT_AE_STEP_SIZE_EXTENDED MAC_PORT_TX_LINKC_TRANSMIT_AE_C1_INIT_EXTENDED MAC_PORT_TX_LINKD_TRANSMIT_TAP_3_COEFFICIENT MAC_PORT_TX_LINKD_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE MAC_PORT_TX_LINKD_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE MAC_PORT_TX_LINK_BCST_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER ROTA LOAD2 UNPKPKA ACCCMP LCURR RX_OVRDIVPD FDDC5 FPRBSOFF MAC_PORT_RX_LINKB_RECEIVER_INTERNAL_STATUS_2 MAC_PORT_RX_LINKB_AC_COUPLING_CURRENT_SOURCE_ADJUST MAC_PORT_RX_LINKC_RECEIVER_AC_COUPLING_CONTROL MAC_PORT_RX_LINKD_RECEIVER_POWER_MANAGEMENT_CONTROL MAC_PORT_RX_LINKD_DFE_OFFSET_VALUE MAC_PORT_RX_LINK_BCST_DFE_H1H2H3_LOCAL_OFFSET_VALUE EN_ANALOG_PD MC_DDRPHY_AD32S_PLL_VREG_CONFIG_0 MC_DDRPHY_AD32S_SYSCLK_CNTL_PR DP18_WRAPSEL QUAD2_EDGES QUAD2_CAVEAT MT_ADR32_PLL_LOCK_SUM SELF_REF_EN MCIF_COMP_PTY_EN ADDR_MODE MC_LMC_INITSEQ10 MC_LMC_INITSEQ14 T_LEADOFF ODT_WIDTH MC_LMC_T_PHYUPD3 dead_cycle0_rmw HMA_REG2_MIN OTF_INT_CAUSE PCIEMST_INT_CAUSE MPS_VF_STAT_TX_VF_UCAST_BYTES_L MPS_VF_STAT_RX_VF_UCAST_FRAMES_H context hash %s "%s"; must be "0" or "1". Hits TOS Action parameter "%s" has bad "value[:mask]" %s uPFLCreditEn: CngDBPHdr: ReschedulePending_1: raw SMM4 QSFP+(CIMS) config ch-rl sched params "weight" missing or invalid (not 1-99) for weighted-round-robin level unbind random /usr/src/usr.sbin/cxgbetool/tcb_common.c LISTEN %4d:%4d %31s: %10u (0x%1x) rx_quiesce TF_IP_VERSION cctrl_ecn rcv_wnd rx_frag3_start_idx_offset_raw ISS modulo marker_interval when entering iWARP mode tx_pdu_len rx_ddp_buf0_offset Length of DDP buffer 0 TF_DDP_WAIT_FRAG TF_DDP_PUSH_DISABLE_0 Current offset into DDP buffer 1 OPT_1_LISTEN_INTERFACE OPT_1_SYN_DEFENSE OPT_0_MAX_RCV_BUFFER last_ack_sent %-10u rx_compact %u
Data being DDP'ed to buf 1, 0 length Indicate buffers IngPadBoundary perr_flm_HintFifo perr_edma_fifo0 perr_ulptx_fifo1 perr_flm_l1Cache err_cpl_exceed_iqe_size SGE_FL_BUFFER_SIZE6 SGE_CONM_CTRL err_physaddr_len0_idma1 err_flm_invalid_pkt_drop0 SGE_INGRESS_QUEUES_PER_PAGE_PF SGE_PC0_REQ_BIST_CMD CtxtType SGE_QUEUE_BASE_MAP_LOW SGE_LA_RDPTR_4 SGE_LA_RESERVED_13 VPDRspErr TagDrop PCIEOfst BIR GBIF_MAX_RDSIZE SendFLRRsp PCIE_DMA10_RSP_FREE PCIE_RSP_ERR_STAT_1 PCIE_MSI_EN_1 PCIE_MSI_EN_6 PTRP PCIE_CORE_INBOUND_POSTED_DATA_BUFFER_ALLOCATION ON1H RTOS PCIE_CORE_UTL_PCI_EXPRESS_PORT_ERROR_SEVERITY PLDS RLNE PADI PC4S TOAK OPM5 GPIO5_OEn GPIO8_ACT_LOW STATIC_KR_PLL_P STATIC_M_PLL_SLEEP STATIC_LVDS_CLKOUT_SEL STATIC_C_PLL_BYPASS DBG_TRACE1_CONF_MASKREG1 Counter1 LAST_MEASUREMENT_RESULT_BANK_A page_policy rank0_odt_write_sel MC_PCTL_TOGCNT1U MC_PCTL_TWR MC_PCTL_TEXSR dtu_rd_byte9 ea_rank MC_DDR3PHYDATX8_WDBDR4 MC_DDR3PHYDATX8_RDBDR3 MC_DDR3PHYDATX8_GSR MC_PVT_REG_TERMN MC_PAR_ENABLE ECC_CE_INT_CAUSE MC_PHY_CTRL MA_CLIENT11_RD_LATENCY_THRESHOLD MEM_PERR_INT_ENABLE ARB1_PAR_WRQUEUE_ERROR_EN ARB2_PAR_WRQUEUE_ERROR COHERANCY_THREAD_NUM MA_ERROR_ENABLE OBQULP1ParErr TieQOutParErrInt PrefDropInt ReqOvrLookupIntEn BlkRdEEPROMIntEn SglWrFlashInt CIM_DEBUGSTS CIM_MEM_ZONE2_LEN CIM_GLB_TIMER_TICK CIM_DEBUG_ADDR_TIMEOUT MBWrBusy FipUpEn VLANExtEnablePort2 CChecksumInsertIP AttackFilterEnable TCPChecksumOffload TP_CMM_TIMER_BASE TP_PMM_DEFRAG_BASE TP_PMM_TX_PAGE_SIZE EnableMtuVfMode TP_TCP_BACKOFF_REG0 TP_TCP_BACKOFF_REG1 RxFragEnable RxCoalescePshEn TP_PARA_REG4 TahoeCfg EnableDeferACK EnableClearRxmtOos TnlErrorPing TnlErrorPktLen DropErrorPktLen TNLAllLookup ChnCount3 TP_SYNC_TIME_LO TP_CMM_MM_TX_FLST_BASE FreeRxPageChn TP_IX_SCHED3 DbgLaWhlf extra_tag_insertion_enable pbl_fifo_perr_set3 lso_hdr_sram_perr_set2 ULP_TX_ERR_TABLE_BASE ULP_TX_SE_CNT_CH0 SOP_CNT_LSO_IN stat_to_ch iespi0_Tx_framing_error PM_TX_MODE icspi2_fifo2x_Rx_framing_error oespi_par_error Prty6 CTL_P3 MPS_RX_PG_RSV2 EN MPS_RX_LPBK_BP0 PG_TH_INT4 MPS_RX_PT_ARB4 MPS_PFVF_ATRB_CTL PF MPS_PF_RPLCT_MAP RX_QFC_EN QFC_FWD_UP FIXED_PFVF_LPBK_OV Bubble MPS_PORT_TX_MAC_RELOAD_CH1 MPS_TRC_PERR_ENABLE PLErrEnb MPS_TRC_FILTER1_DONT_CARE MPS_STAT_CTL MPS_PORT_STAT_LB_PORT_BYTES_L MPS_PORT_STAT_LB_PORT_64B_L MPS_PORT_STAT_LB_PORT_512B_1023B_H MPS_PORT_STAT_RX_PORT_1024B_1518B_L MPS_PORT_STAT_RX_PORT_PPP1_L MPS_PORT_STAT_RX_PORT_PPP7_H MatchTCAM MultiListen3 CPL_SWITCH_CNTRL cim_op_map_perr cim_ovfl_error SlvFifoDbg SlvByteCntErrEn SlvUnExpBusStopInt SlvNoRepStartInt MstDoneInt AuxAddr2Val WakeUp CAUSE_MPARF_1 PL_PF_INT_CAUSE OwnerOverride LE_DB_HASH_CONFIG LE_DB_INT_CMD DropFilterFIDX LE_DB_FTID_FLTRBASE LE_HASH_MASK_GEN_IPV6 NCSI_STATUS CopyPause NCSI_MACB_WOL_CFG Port_Sel XFI_PCS_Reset Led0_Polarity_Inv XGMAC_PORT_XGMII_SE_COUNT PCSR_Hi_BER RXADATASYNC Toggle XGMAC_PORT_AN_TX_NONCE_CONTROL XGMAC_PORT_AE_RX_COEF_STAT Training_Failure XGMAC_PORT_HSS_TXA_MODE_CFG XGMAC_PORT_HSS_TXA_8023AP_AE_STATUS XGMAC_PORT_HSS_TXB_8023AP_AE_STATUS PRBSSEL DFERST XGMAC_PORT_HSS_RXA_VGA_CTRL3 H2EMAG FH4H5 XGMAC_PORT_HSS_RXB_PH_ROTATOR_POSITION1 XGMAC_PORT_HSS_TXC_TAP2_IDAC_OVR XGMAC_PORT_HSS_TXC_PWR_DAC_OVR XGMAC_PORT_HSS_RXC_DFE_D10_D11_OFFSET XGMAC_PORT_HSS_PORT_EN_0 TXCRST XGMAC_PORT_HSS_TX_POLARITY perr_dbp_hint_fl_fifo perr_egr_dbp_tx_coal Bar2Full perr_pointer_hdr_fifo1 CGEN_DBP dbp_fetch_threshold_en2 debug_uP_SOP_cnt debug_T_Rx_EOP1_cnt debug_UD_Rx_SOP3_cnt debug_U_Tx_EOP2_cnt debug_U_Tx_EOP1_cnt debug_CPLSW_SOP1_cnt MAReqTimeout MEMRspRdTagErr MEMRspWrTagErr PCIE_CFG5 NPH0 LTSSMEnable PCIE_LTSSM Disable_DeSkew PCIE_HMA_STAT3 RspRdq_Dynamic_CGEN PIOCpl_PLMRspPerr ReqUnderFLRIntEn pm_linkst_in_l2 LnA_RxStateDone PCIE_PHY_CURRXPWR T5_STATIC_C_PLL_FFENABLE T5_STATIC_C_PLL_LOCKTUNE T5_STATIC_C_PLL_RANGEA T5_STATIC_U_PLL_STOPCLKB T5_STATIC_KX_PLL_CCALLOAD DBG_EFUSE_BYTE40_43 DIS_BANK_FAIR MA_ULPTX_RDDATA_CNT CL5_WR_DATA_TO_ERROR MA_READ_TIMEOUT_ERROR_STATUS DEBUGSELL TnlErrorFPMA bundle_len_ParErr bundle_len_ovfl MPS_TX_PAUSE_RETRANS_BUF_GRP_TH14 MTU_ERR_INT0 TP2MPS_Ch3 MPS_TX_CGEN MPS_PORT_TX_PAUSE_PENDING_STATUS StopStat PtRx LE_Part_CGEn ENABLE_PF_PBL_1 MapMAC3 ActCntIPv4Tzero SGMIISEL MAC_PORT_CFG2 MAC_PORT_PKT_COUNT AEC2_TX_WIDTH AEC0_TX_WIDTH Perr0_tx HSSPLLBYPA TXCREFRESH RXCASSTCLK HSSPLLCONFIGA MAC_PORT_HSS_EEE_STATUS MAC_PORT_PTP_TIMER_INCR0 Y_TICK VER CMD_FRAME_ENA MAC_PORT_APAUSEMACCTRLFRAMESRECEIVED MAC_PORT_AFRAMETOOLONGERRORSHI MAC_PORT_AINRANGELENGTHERRORS MAC_PORT_IFINMULTICASTPKTS MAC_PORT_ETHERSTATSUNDERSIZEPKTS MAC_PORT_ETHERSTATSPKTS512TO1023OCTETSHI MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4 DPLX MAC_PORT_MTIP_SGMII_PARTNER_NP MAC_PORT_MTIP_VLAN_TPID_7 BLOCK_CNT_HI MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS4 REM_FAULT_STATUS MAC_PORT_BEAN_REM_ABILITY_1 MAC_PORT_BEAN_REM_ABILITY_2_LANE1 MAC_PORT_AE_PRBS_CTL T5_AE1_RXSTAT_RDY MAC_PORT_AE_RX_SIGDET_3 MAC_PORT_RESISTOR_CALIBRATION_CONTROL SPSEL MAC_PORT_TX_LINKA_TRANSMIT_DCC_CONTROL SDOVRDEN MAC_PORT_TX_LINKB_TRANSMIT_CONFIGURATION_MODE MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTE_4 MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_1 MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C0_INIT_EXTENDED RSTUCK IQSEP T5BER6 LOFE2S_ReadOnly LOFO1S_ReadOnly LOFO4S_ReadOnly T5_RX_VGABOD H11SN_ReadOnly H10MAG ACJPDN MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_1 MAC_PORT_RX_LINKB_RECEIVER_SIGDET_CONTROL MAC_PORT_RX_LINKC_RECEIVER_CONFIGURATION_MODE MAC_PORT_RX_LINKC_RECEIVER_INTERNAL_STATUS MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS MAC_PORT_RX_LINKC_DFE_H2 MAC_PORT_RX_LINKD_DFE_CONTROL MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_3 MAC_PORT_RX_LINKD_RECEIVER_ANALOG_CONTROL_SWITCH MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_2 MC_DDRPHY_PC_BASE_CNTR0 CC_ERROR ENA_DQS_ALIGN MC_DDRPHY_PC_MR2_PRI_RP ADR_DELAY_BITS1_7 MC_ADR_DDRPHY_ADR_DELAY2 MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN3 SLEW_CTL0 DVCC_REG_PD ADVANCE_PING_PONG ATEST_MUX_CTL3 CLK16_SINGLE_ENDED_BIT10 CLK20_SINGLE_ENDED_BIT12 SxMCVREF_0_3 MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP MC_DDRPHY_DP18_DQS_GATE_DELAY_RP WL_ERR_CLK20_ST MC_DDRPHY_DP18_WR_ERROR0 INVALID_NS_SMALL_L OFFSET_ERR VALID_NS_JUMP_BACK_MASK CHECKER_RESET CNTL_POL DQS_OFFSET MC_DDRPHY_DP18_DEBUG_SEL DYN_RX_GATE_CNTL_EN ODT_WR_VALUES_BITS8_15 TZQINIT_CYCLES MC_DDRPHY_WC_WRCLK_CNTL MC_DDRPHY_APB_ERROR_MASK0 ADR12_1_Populated hw_idle cke_or_en MC_UPCTL_TXPDLL MC_UPCTL_TDPD MC_UPCTL_DTULFSRWD odt_lat_r dfi_tlp_resp USER_DATA2 EDC_H_BIST_CMD_LEN db_prog_thresh fatal_tag_mismatch SGE_DBG_QUEUE_STAT1_CTRL debug_idma1_IDMA2IMSG_EOP Cur_LnA_RxPwrState PCIE_MULTI_PHY_INDIR_DATA PCIE_RESET_STAT PIO_WARM_RST_MODE1_STATE_flag LastResetState STATIC_M_PLL_MULTFRAC DBG_STATIC_M_PLL_CONF4 STATIC_M_PLL_VCVTUNE STATIC_U_PLL_FRAMESTOP STATIC_U_PLL_VCVTUNE STATIC_U_PLL_LFTUNE_32_40 DBG_CUST_EFUSE_OUT pcie_obq_if_disable HashAll IWARP_SEQ_UPDATE_EN map_fifo_perr_set0 DROP_INVLD_MC_CH0 bypass_last MPS_RX_MAC_BG_PG_CNT0 MPS_RX_IPV4 EN_UDP_LEN_CHK ClsTrcPortMap PERR_ENABLE_CTX_1 PERR_ENABLE_CTX_0 iscsi_all_cmp_mode IGNR_TUP_ZERO TCAM_ACTV_SUCC TcamAccFail mac1g10g_gate_ff_rx_clk pcs100g_clk_enable pcs40g_clk_enable Perr_rx19_pcs100g SET_LEN MAC_PORT_MTIP_1G10G_TX_FIFO_ALMOST_F_E CL2_PAUSE_QUANTA CL2_QUANTA_THRESH MAC_PORT_MTIP_1G10G_RX_IFINERRORSHI MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTSHI MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1024TO1518OCTETSHI MAC_PORT_MTIP_1G10G_TX_IFUCASTPKTS MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_6 MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_7 MAC_PORT_MTIP_SGMII_NP_TX Low_power_Ability MAC_PORT_MTIP_KR_PCS_CONTROL_2 10GBASE_R_Capable MAC_PORT_MTIP_KR_10GBASE_R_PCS_STATUS_1 Test_Pattern_Select PMD_PMA_present RX_link_status Lane_3_blck_lck MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_3 MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_7 RS_FEC_Bypass_Error_Indication RS_FEC_high_SER MAC_PORT_MTIP_RS_FEC_NCCW_LO MAC_PORT_MTIP_FEC1_NCERR_CNT_0 TX_FIXED MAC_PORT_IMPEDENCE_CALIBRATION_STATUS_1 RCALBENAB ISLT OS2X2 OS1X4 MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_1X_OVERRIDE MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_4X_OVERRIDE T5_RX_MODE8023AZ FGAINCHK OVRDCDPST RX_OVRSUMPD H5SN H13SN MAC_PORT_RX_LINKA_DFE_H14_15 MAC_PORT_RX_LINKB_AC_CAPACITOR_BIST MAC_PORT_RX_LINKD_AC_COUPLING_CURRENT_SOURCE_ADJUST MAC_PORT_RX_LINK_BCST_DFE_H12_13 ADDR_MIRROR_A11_A13 FAIL_PASS_V QUAD1_CAVEAT MC_DDRPHY_APB_MTCTL_REG1 INIT_COMPLETE MC_LMC_CMD10 MC_LMC_SDTR1 T_PHY_WRDATA WR_LEVEL MPD_MODE MCmdNRE EDC_H_DBG_EDRAM1_RDATA_INTF EDC_H_DBG_BIST_WR_REQ_CNT inp_wrdq_notempty ADDR0_MIN HMA_REG0_MASK RTF_INT_CAUSE HMA_IDTF_ERR MPS_VF_STAT_TX_VF_DROP_FRAMES_H CIM_VF_EXT_MAILBOX_DATA_3c sched-queue sge %s pmu mode invalid dmac address "%s" IP StatusPgNS: SplitEn: SP_RO: QSFP-DD TF_TX_QUIESCE TF_RX_QUIESCE TF_TX_QUEUE TF_CORE_PUSH active_open ip_version RSS field TOS field for IP header Offset of NewReno fast recovery end sequence from tx_max rx_frag2_start_idx_offset_raw irs_ulp aux3_slush OPT_0_INJECT_TIMER OPT_0_MAXRT_OVERRIDE TIMERS:
mod_schd: tx: %u, rx: %u, reason 0x%1x
core_more %u, core_urg, %u core_push %u, ULP: ulp_type %u (%s), ulp_raw %u
irs_ulp %u, iss_ulp %u
Buf0: %u 0x%6.6x 0x%6.6x 0x%8.8x Data being indicated to host
TF_RSS_FW SGE_INT_CAUSE1 perr_isw_idma1_fifo err_bad_db_pidx0 err_ing_pcie_chan EDRAMPtrCnt Drop_Timeout TimerValue3 MaxTag3 Error_QID_Valid MinTag2 SGE_CTXT_DATA1 SGE_LA_RDDATA_7 SGE_LA_RESERVED_11 IDE PCIE_NONFAT_ERR IN_RD_CPLSIZE CH0 SRD5 RPCP CRSE ALEA PMC3 GPIO6_OEn GPIO12_Out_Val GPIO4_Out_Val GPIO6 DBG_PVT_REG_TERMP PVT_REG_TERMP_EN REG_IN_TERMN_B DBG_PVT_REG_IN_DRVP REG_IN_DRVP_B REG_OUT_TERMN_B bank_addr row_addr_width MC_PCTL_TRAS MC_PCTL_TZQCSI clr_ecc_intr dtu_wr_byte10 MC_PCTL_DTUWD3 dtu_wr_byte12 dtu_rd_byte12 FDEPTH CAL OCPOND MC_DDR3PHYAC_PMBDR1 PHYRST PONR MC_PVT_REG_CALIBRATE_CTL MC_PVT_REG_IN_TERMN STATIC_MODE BIST_OPCODE THRESHOLD1 MA_CLIENT2_WR_LATENCY_THRESHOLD MA_ULPTX_DEBUG_CNT EDRAM0_SIZE MA_EDRAM1_BAR HMA_BASE EDRAM1_ENABLE CL1_PAR_WRQUEUE_ERROR_EN ARB0_PAR_WRQUEUE_ERROR CL8_PAR_WRQUEUE_ERROR CL8_PAR_RDQUEUE_ERROR EDC_BIST_CMD_LEN CIM_EEPROM_ADDR_SIZE CIM_SDRAM_BASE_ADDR TieQInParErrIntEn CIM_HOST_INT_CAUSE RspOvrLookupIntEn SglWrPlIntEn SglRdPlInt ObqDbgWr PBT_enable CIM_MEM_ZONE7_LEN Timer0En NICMode EChecksumCheckIP UDPChecksumOffload TxDataAckRateEnable EnableRDMAError DisableTblMmgr TimerBackoffIndex1 TnlErrorFrag SYN4tupEnIpv6 TP_TX_MOD_QUEUE_WEIGHT2 imm_data_perr_set_ch3 ULP_TX_LA_RDDATA_4 pcmd_len_ovfl2 CH_MAP3 CH_MAP2 MPS_PORT_RX_PAUSE_STATUS Prty1 MPS_RX_LPBK_BP1 MPS_RX_LPBK_BP2 PPM2 MPS_PFVF_ATRB_FLTR0 ST_NCSI NOV_DROP PortErr Ncsi Lpbkpt0 pt2 ErrCh2 ValidPt0 FullPt2 MPS_TRC_FILTER0_DONT_CARE MPS_PORT_STAT_TX_PORT_BYTES_H MPS_PORT_STAT_RX_PORT_UCAST_L MPS_PORT_STAT_RX_PORT_65B_127B_H MPS_PORT_STAT_RX_PORT_128B_255B_L MPS_PORT_CLS_BMC_VLAN MPS_CLS_BMC_MAC_ADDR_H MPS_CLS_BMC_VLAN MPS_CLS_PL_TEST_CTL MPS_CLS_SRAM_L cim_truncate_enable SlvCrcOutBitInv SlvUnExpNackMstEn SlvUnExpAckMstInt SlvRxPecErrInt SMB_SLV_ARP_CTL SubsystemVendorID SMB_SLV_AUX_ADDR0 ENABLE_DDPDF_0 IscsiUlimit ULP_RX_PBL_LLIMIT PERR_ENABLE_APF_0 EN_DBG_L MAP2 ModOffset DELACTSYNOEN SYNCookieBad DBGIRspMHit LE_DEBUG_LA_SELECTOR BufferExhausted RxBufQPtr NCSI_MACB_RX_FRAMES_OK Pmux_Rx_Loop XGMAC_PORT_FAULT_TEST PatDetWake SigDetChg TxFifo_prty_err HSSAVDHI HSSEXTC16SEL TXAPRBSRST XGMAC_PORT_HSS_CFG2 RXCPHSLOCK SendZeroPause En1536BFrames ModuleRev XGMAC_PORT_XGM_STAT_RX_1024_1518B_FRAMES partner_an_ability 10GBASE_KR_Capable NP_Info PCS_AN_Complete Module_Revision PRBS_CHK_ERRCNT XGMAC_PORT_HSS_TXA_TAP1_IDAC_OVR PCHKEN SDPDN GATEEN DSAMP D00SN E1SN XGMAC_PORT_HSS_RXA_DACA_OFFSET AOFFE MINWIDTH H5ESN WERRFLG XGMAC_PORT_HSS_TXD_SEG_DIS_APP XGMAC_PORT_HSS_RXD_DFE_D10_D11_OFFSET XGMAC_PORT_HSS_RXD_DFE_H3 PFVAL XGMAC_PORT_HSS_TX_TAP0_COEFF XGMAC_PORT_HSS_TX_TAP1_IDAC_OVR XGMAC_PORT_HSS_RX_DFE_H1 OpenBar2GateOnce err_cpl_exceed_max_iqe_size0 err_large_minfetch_with_txcoal0 perr_payload_fifo0 debug_PD_RdRsp_SOP0_cnt debug_PD_WrReq_Int1_cnt SGE_DEBUG_DATA_LOW_INDEX_2 SGE_DEBUG_DATA_LOW_INDEX_12 TRGT1BARTypeErr CfgdExtTagEn CMDReqPriority CPLD0 PD0 CPLH1 DLL_Link_Enable TxCPLH_FC NFTS_Gen2_3 PCIE_CMD_STAT2 PCIE_MA_RSP GPIO17 DBG_FEF T5_STATIC_M_PLL_DCO_BYPASS T5_STATIC_KR_PLL_M T5_STATIC_KX_PLL_CCALMETHOD T5_STATIC_KX_PLL_N1 STATIC_C_DFS_RANGEB GPIO18_PS_En GPIO5_PS_En GPIO0_PS_En MA_HMA_WRDATA_CNT CL2_WR_DATA_TO_EN CL1_RD_CMD_TO_ERROR CL4_RD_DATA_TO_ERROR MA_WRT_ARB WR_WIN CL6_IF_PAR_ERROR DEBUGSELH TP2CIMIntfParErr ByteCountHighSpeed IdleCwndNewReno VfVlanEn ULP_TX_CGEN_RDMA ULP_TX_INT_CAUSE_2 ULP_TX_ASIC_DEBUG_1 PM_RX_DBG_CTRL LpbkCrdtCtrl MPS_TX_PAUSE_RETRANS_BUF_GRP_TH13 PTCP1EN TxSchMAC0_CGEN TxInCh0_CGEN MPS_TRC_VF_OFF_FILTER_0 MPS_STAT_STOP_UPD_TX_VF_96_127 MstBusBusy DDP_HINT_0 AEC0_RX_WIDTH MAC_PORT_INT_EN TXAREFRESH_STATUS TXCREFRESH_STATUS MAC_PORT_EEE_TX_10G_SLEEP_TIMER MAC_PORT_PTP_TIMER_RD0_HI REV MAC_PORT_AFRAMESRECEIVEDOK MAC_PORT_IFOUTBROADCASTPKTS MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7HI SGMII_SPEED MAC_PORT_MTIP_PCS_DEVICE_PKG1 10GBASE_R HiBERCount Lane10 MAC_PORT_MTIP_PCS_BIP_ERR_CNT_7 EXT_NXP_CTRL PAUSE_ABILITY 1GKX MAC_PORT_FEC_KR_CONTROL rx_ready C0_STAT EN_MAX_ST TOG_LIM BOOT_DEC_C0 MAC_PORT_AET_SIGNAL_LOSS_DETECTION_3 DIVSEL8 T5REGAEN T5REGAMP CALSSTP CINIT DCCOFFSET MAC_PORT_TX_LINKA_TRANSMIT_DCC_APPLIED MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C2_INIT_EXTENDED MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_ADDR MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_OVERRIDE MAC_PORT_RX_LINKA_RECEIVER_INTERNAL_STATUS LOFE1S_ReadWrite LOFO2S_ReadOnly H7SN_ReadWrite DFEDACLSSD MAC_PORT_RX_LINKB_DFE_OFFSET_EVN1_EVN2 MAC_PORT_RX_LINKB_DFE_E0_AND_E1_OFFSET MAC_PORT_RX_LINKB_INTEGRATOR_DAC_OFFSET MAC_PORT_RX_LINKB_DIGITAL_EYE_CONTROL MAC_PORT_RX_LINKB_DFE_H2 MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_2 MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_2 MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_1 MC_DDRPHY_PC_PER_CAL_CONFIG PER_ZCAL_NEXT_RANK MC_DDRPHY_PC_MR3_SEC_RP ADR_TEST_LANE_PAIR_FAIL SLEW_CTL3 MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0 INTERP_SIG_SLEW_0_3 MASTER_PD_CNTL QUAD1_CLK18_BIT5 MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR MIN_RD_EYE_SIZE LEADING_EDGE_FOUND_MASK FW_RIGHT_SIDE MEMINTD11_POS MC_DDRPHY_DP18_RD_DIA_CONFIG0 MC_DDRPHY_SEQ_RESERVED_ADDR4 MC_DDRPHY_SEQ_ERROR_STATUS0 INVALID_REQTYPE TMRSC_CYCLES MC_DDRPHY_WC_CONFIG2 MC_DDRPHY_RC_CONFIG2 ALLOW_RD_FIFO_AUTO_R_ESET MC_UPCTL_TZQCL MC_UPCTL_ECCCFG MC_UPCTL_DFITPHYWRDATA parity_en MC_P_BIST_NUM_ERR RW HMA_PAR_ENABLE HMA_INT_ENABLE fl_prog_thresh err_pc_rsp_len0 SGE_QBASE_MAP3 st_cong last_xoff SGE_DEBUG0_DBP_THREAD Req_LnG_RxStateDone Req_LnF_RxPwrState Req_LnE_RxStateReq Req_LnJ_RxPwrState Cur_LnM_RxPwrState LnN_STAT PCIE_FLR_VF5_STATUS PCIe_WARM_RST_MODE0_STATE_flag PF0_DState DBG_STATIC_M_PLL_CONF3 STATIC_C_PLL_MULTFRAC DBG_STATIC_C_DFS_CONF EFUSE_PROG_PERIOD TnlErrorIp6Opt DropErrorOpaque dma_fifo_perr_set3 dma_fifo_perr_set0 push_last save_middle MPS_RX_GENEVE_TYPE GENEVE VXLAN_FLAG MPS_RX_CNT_TNL_ERR_PKT_MAC0 Outer_IPv4_n_Double_VLAN_GRE Outer_IPv6_n_Double_VLAN_GRE MPS_PORT_CLS_NCSI_ETH_TYPE_EN MPS_CLS_MATCH_CNT_HPROM ClsTrcReqPort MPS_CLS_DIPIPV6ID_0_TABLE CtlXYBitSel ulp_insert_pi TlsKeyLlimit LE_DB_ACTIVE_TABLE_START_INDEX TCAM_SRVR_HIT_ACTF LE_DB_DBG_MATCH_DATA TID_CMP_MASK TID_CMP pcs40g_reset_sd1_rx_clk mac1g10g_gate_ff_tx_clk mac1g10g_xoff_gen mac1g_loop_bck Perr_rx1_fec100g_dk Perr_rx_pcs10g RX_EMPTY TX_EMPTY CL0_QUANTA_THRESH MAC_PORT_MTIP_1G10G_RX_ETHERSTATSFRAGMENTS MAC_PORT_MTIP_1G10G_TX_OCTETSOK MAC_PORT_MTIP_1G10G_TX_OCTETSOKHI MAC_PORT_MTIP_1G10G_TX_CRCERRORSHI Collision_Test MAC_PORT_MTIP_KR_PCS_STATUS_2 MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_3 LANE_3_BLK_LCK MAC_PORT_MTIP_RS_FEC_SYMBLERR2_LO MAC_PORT_MTIP_RS_FEC_SYMBLERR2_HI MAC_PORT_MTIP_FEC0_CERR_CNT_1 T5_AE1_RXSTAT_C3 DPC_METH MAC_PORT_PLLB_PLL_MICELLANEOUS_CONTROL MAC_PORT_TX_LINKA_TRANSMIT_1X_SEGMENT_APPLIED OS4X0 MAC_PORT_TX_LINKB_TRANSMIT_AE_C1_INIT_EXTENDED MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_5_4 MAC_PORT_TX_LINKC_TRANSMIT_AE_C0_LIMIT_EXTENDED MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE MAC_PORT_TX_LINKD_TRANSMIT_AE_C2_LIMIT_EXTENDED MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C3_INIT_EXTENDED PPOL FROTCAL LRDY RX_DISSPY2D EMSF FDFE QCCCMP DCDAMP QCCSIGN MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_3 MAC_PORT_RX_LINK_BCST_RECEIVER_INTERNAL_STATUS_2 ANALOG_PD_DLY FP_PF_EDGE_NF NON_SYMETRIC DQS_REC_LOW_POWER HALT_ROTATION X16_DEVICE TWR_MPR MC_LMC_MCSTAT INIT_START CLK_DISABLE CL0 MC_LMC_SMR1 DIC1 MPR_RD_FMT PAR_ERR_STAT RMW_MERGE_EN MC_CE_ERR_ECC_DATA1 MCmdAddr Edram1RdEnLo EdramWData ECmdNRB ECmdAddr HMA_TLB_DESC_2_H HMA_REG2_MAX SGE_VF_GTS MPS_VF_STAT_RX_VF_MCAST_FRAMES_L MPS_VF_STAT_RX_VF_MCAST_FRAMES_H CIM_VF_EXT_MAILBOX_DATA_14 policy %s mac CHELSIO_T4_GET_FILTER_MODE iport CHELSIO_T4_SET_FILTER WRLength: %#llx
DCA_ST: FetchSizeMode: mmap argument must be 3 characters (tx<n> or rx<n>) GBIC weight loadboot: incorrect number of arguments. rx_flow_control_disable tx_pace_fixed cctrl_sel1 core_urg TF_CORE_FLUSH t_state Connection TCP state (see TCP state table) t_rxtshift t_dupacks Number of duplicate ACKs received ts_last_ack_sent_raw frag0_idx %-10u length %-10u frag0_ptr 0x%-8x
frag3_idx %-10u length %-10u frag3_ptr 0x%-8x
SGE_CONTROL perr_imsg_ob_fifo perr_isw_idma0_fifo err_flm_dbp SGE_DOORBELL_CONTROL SGE_DEBUG_INDEX Error_QID Egress_Base SGE_LA_RDDATA_2 SGE_LA_WRPTR_4 SGE_LA_RDDATA_5 SGE_LA_RDDATA_13 HCntPerr PIOCplPerr MaxRdReqSize PCIE_HMA_CTRL PCIE_FW PCIE_FW_PF PCIE_DBG_INDIR_REQ PCIE_DBG_INDIR_DATA_2 VecNum PDEBUGSelL IP3H VRB3 TCAP PMC1 PMC5 GPIO10_CHG_DET GPIO5_CHG_DET C_LOCK GPIO10 GPIO9_ACT_LOW STATIC_U_PLL_TUNE STATIC_M_PLL_MULT STATIC_CCLK_FREQ_SEL DBG_TRACE_COUNTER DBG_STATIC_REFCLK_PERIOD tfaw_cfg bl8int_en dtu_err_b5 MC_PCTL_TAL MC_PCTL_DWLCFG3 MC_DDR3PHYDATX8_WDSDR MC_DDR3PHYDATX8_RDBDR5 RMW_PERF_CTRL MA_CLIENT9_WR_LATENCY_THRESHOLD CL0_PAR_WRQUEUE_ERROR_EN CL0_PAR_RDQUEUE_ERROR_EN CL0_PAR_RDQUEUE_ERROR SdramBaseAddr ExtMem2AddrSize OBQULP3ParErr uPAccNonZero EEPROMWRIntEn IbqDbgEn CIM_PF_HOST_INT_ENABLE VnTagEnable PortQfcEn RxMaxOpCntDisable PMRxNumChn TimerBackoffIndex2 FastTnlCnt RxMacCheck TunnelCngDrop2 TxPaceFixedStrict PMMaxXferLen1 TnlErrorCsum TnlErrorTcpOpt RxtShiftMaxR1 KeepaliveMaxR1 TP_PORT_MTU_1 RowValue TNLMapEn OFDMapEn VfWrAddr TX_MOD_QUEUE_REQ_MAP TP_TX_MOD_QUEUE_WEIGHT5 TP_TX_MOD_CHANNEL_WEIGHT TP_MIB_INDEX DbL2tLutPerr FreeTxPageChn BlockSelect ULP_TX_INT_CAUSE ULP_TX_FPGA_CMD_12 ULP_TX_LA_RDDATA_0 ULP_TX_LA_WRPTR_5 iespi1_Tx_framing_error MPS_INT_ENABLE MPS_VF_RX_CTL_63_32 MPS_TX_PAUSE_DURATION_BUF_GRP0 TxEn FCSStripEn MPS_PORT_TX_PAUSE_SOURCE_H MPS_RX_PG_FL VLAN_ID EOP_CNT_1 TP ValidCh1 EOPCh2 SizePt0 MPS_TRC_FILTER_MATCH_CTL_A MPS_PORT_STAT_TX_PORT_MCAST_L MPS_PORT_STAT_RX_PORT_MCAST_H MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H MPS_PORT_STAT_RX_PORT_128B_255B_H MPS_PF_STAT_RX_PF_BCAST_BYTES_H CimWeight MPS_CLS_PORT_BMC_CTL MultiListen0 MPS_CLS_TCAM_X_H SlvDoneIntEn MstTxFifoParInt SlvTimeOutInt SMB_DEBUG_DATA AuxAddr3 SMB_COMMAND_CODE3 T4_St PMU_SLEEPMODE_WAKEUP HWWakeUpEn Port3SleepMode disable_0B_STAG_ERR STAG_RQE PagePodME CAUSE_AF_0 CAUSE_PRSDF_1 CAUSE_DDPDF_0 ULP_RX_TDDP_LLIMIT SW SourcePF PM_TX MapXGMAC1 LE_DB_CONFIG HASHEN MOSTCMDOEN RTINDX DBGICMD LastCmdB LE_TCAM_DEBUG_LA_DATA CH1_SADDR_EN NCSI_CH3_SADDR_HIGH NCSI_WORK_REQHDR_1 NCSI_MPS_DEMUX_CNT Master NCSI_PAUSE_TIMEOUT PauseLWM TxSndZeroPause TxStart NoRxBuf NCSI_MACB_TX_FRAMES_OK NCSI_MACB_RX_JABBER_ERR PatEn linkup HSSRESYNC RXBPRBSEN CRCCal RmFCS XGMAC_PORT_XGM_RX_TYPE_MATCH_4 XGMAC_PORT_XGM_INT_STATUS polarity_inv_rx XGMAC_PORT_PCSR_TXTEST_SEEDA_LOWER XGMAC_PORT_AE_TX_COEF_REQ TXREQ_CINIT XGMAC_PORT_HSS_TXA_COEFF_CTRL SLEW XGMAC_PORT_HSS_TXB_MODE_CFG XGMAC_PORT_HSS_TXB_DRIVER_MODE XGMAC_PORT_HSS_TXB_TAP0_IDAC_OVR XGMAC_PORT_HSS_TXB_TAP0_IDAC_APP RSRVO VLCKF XGMAC_PORT_HSS_TXC_PWR XGMAC_PORT_HSS_RXD_DFE_DATA_EDGE_SAMPLE XGMAC_PORT_HSS_RXD_VGA_CTRL2 RECAL TXAEN RXCRST LFREQO XGMAC_PORT_HSS_RX_PH_ROTATOR_STATIC_PH_OFFSET XGMAC_PORT_HSS_RX_DFE_E0_E1_OFFSET dbp_fetch_threshold_lp dbp_fetch_threshold_iq0 debug_uP_EOP_cnt SGE_DEBUG_DATA_HIGH_INDEX_7 debug_PD_WrReq_SOP2_cnt GlobalEnable_Off debug_CPLSW_CIM_TxAFull_d debug_CPLSW_CIM_SOP0_cnt SGE_DEBUG_DATA_HIGH_INDEX_11 debug_itp_evr_state debug_st_dbp_thread2_cimfl SGE_DEBUG_DATA_LOW_INDEX_3 SGE_DEBUG_DATA_LOW_INDEX_5 SGE_DEBUG_DATA_LOW_INDEX_9 debug_imsg_qid TRGT1GrpPerr AutoTxnDisable PCIE_PF_INT_CFG PCIE_FID_VFID CPLD1 PCIE_FLR_VF1_STATUS PCIE_CORE_TRANSMIT_NONPOSTED_FC_CREDIT_STATUS VC1_PD_Credits Eql_Disable Preset_Request_Vector EQMasterPhase_MinTime PCIE_RSP_ERR_LOG1 LnE_RxPwrState PCIE_PHY_FS_LF1 GPIO17_OEn GPIO17_Out_Val GPIO18_Out_Val T5_STATIC_M_PLL_RANGEB T5_STATIC_U_PLL_SDORDER T5_STATIC_U_PLL_FFENABLE T5_STATIC_U_PLL_FFTUNE T5_STATIC_KR_PLL_VBOOSTDIV DBG_T5_STATIC_KX_PLL_CONF2 EXT_MEM0_SIZE EXT_MEM1_ENABLE MA_PARITY_ERROR_STATUS2 CL1_WR_CMD_TO_EN CL9_WR_CMD_TO_ERROR CL4_WR_CMD_TO_ERROR CL0_WR_DATA_TO_ERROR CL0_RD_CMD_TO_EN CL7_RD_CMD_TO_ERROR ULP2CIMIntfParErr sdc_err MPS_TX_PAUSE_DURATION_BUF_GRP_TH5 PUDP1EN MPS_RX_LPBK_CLS_DROP_CNT2 LpbkPadEnPt1 CountPauseMCRx PFTx Termimate_msg atomic_immediate_len ULP_RX_CTX_SKIP_MA_REQ IPv4HASHSIZEEN LE_ACT_CNT_THRSH LE_GLOBAL_COLLISION TXIF_Reset Perr_mask_ram Perr3_tx HSSPDWNPLLA RXCQUIET TXACONFIGSEL HSSCALSSTP HSSVBOOSTDIVB MAC_PORT_RUNT_FRAME MAC_PORT_TX_TS_VAL_HI EEE_CTRL X TX_FLUSH PHY_TXENA PROMIS_EN MAC_PORT_MTIP_CURRENT_CREDIT MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6HI MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2HI 10MbpsHalfDplx MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_1 data_word 10BASE_TL DTEXS PCS Lane1 Lane18 AMLOCK4 AMLOCK10 MAC_PORT_MTIP_PCS_BIP_ERR_CNT_18 MAC_PORT_MTIP_PCS_LANE_MAP_1 MAC_PORT_MTIP_PCS_LANE_MAP_11 MAC_PORT_BEAN_MS_COUNT MU 40GKR4 MAC_PORT_BEAN_MS_COUNT_LANE3 MAC_PORT_AE_RX_COEF_STAT T5_AE0_RXSTAT_C0 INIT_METH EN_SD_TH RCCOMP MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_1 AFDWEN ZCALOVRD MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_OVERRIDE_CONTROL MAC_PORT_TX_LINKA_TRANSMIT_802_3AZ_CONTROL AECMD70 MAC_PORT_TX_LINKB_TRANSMIT_DCLK_DRIFT_TOLERANCE MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_1 MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_ADDR MAC_PORT_TX_LINKD_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_DRIFT_TOLERANCE MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_4 MAC_PORT_RX_LINKA_RECEIVER_TEST_CONTROL MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 T5ROCCMP LOFO4S_ReadWrite T5_RX_PDTERM MAC_PORT_RX_LINKA_DFE_H1 H8SN_ReadWrite H11MAG RXDOBS MAC_PORT_RX_LINKC_DFE_H6_AND_H7 MAC_PORT_RX_LINKD_RECEIVER_DACAP_AND_DACAN MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 MAC_PORT_RX_LINKD_RECEIVER_INTERNAL_STATUS MAC_PORT_RX_LINKD_DFE_OFFSET_ODD3_ODD4 MAC_PORT_RX_LINKD_DIGITAL_EYE_CONTROL MAC_PORT_RX_LINK_BCST_DYNAMIC_DATA_CENTERING_DDC MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN1_EVN2 MC_DDRPHY_PC_RANK_PAIR0 RANK_PAIR0_PRI_V RANK_PAIR1_PRI_V RC_ERROR_MASK ERROR_WRITE_CTR MC_DDRPHY_PC_RANK_GROUP PLL_TUNE_0_2 MC_DDRPHY_ADR_SYSCLK_PR_VALUE_RO SLEW_CAL_START MC_DDRPHY_DP18_DATA_BIT_ENABLE1 QUAD3_CLK16_BIT3 DQSCLK_ROT_CLK_N0_N2 INITIAL_DQS_ROT_N1_N3 WL_ERR_CLK16_ST CE0DLTVCCD1 MC_DDRPHY_DP18_IO_TX_NFET_SLICE MEMINTD23_POS MC_DDRPHY_DP18_RD_DIA_CONFIG3 WRCLK_CAL_START ALIGN_ON_EVEN_CYCLES MC_DDRPHY_APB_ADR_POPULATION MC_UPCTL_TXP rank3_odt_write_nsel MC_UPCTL_DFITCTRLUPDDLY dfi_init_complete MC_UPCTL_DFITRRDLVLGATEDELAY1 dfitrcmd_opcode MC_UE_ERR_DATA_RDATA EDC_H_BIST_CMD_ADDR PERR_PAR_ENABLE perr_pc_rsp err_pc_rsp_len3 DbpTbufRsv0 db_gts_qid PfWCQsPerPage PfWCOffEn MA_RspCtlPerr Req_LnB_RxStateDone Cur_LnN_RxPwrState LnO_STAT PCIE_FLR_VF6_STATUS TxDeemph_gen2_6db DBG_STATIC_M_PLL_CONF5 STATIC_SWMC0CfgRst_ STATIC_C_PLL_STOPCLKB DBG_STATIC_C_PLL_CONF4 STATIC_U_PLL_LOCKTUNE STATIC_U_PLL_RANGEPRE DBG_STATIC_U_PLL_CONF5 FUTURE_DEXPANSION_WTE EcnSynAck ULPType6Length KeyWrAddrX MPS_FPGA_BIST_CFG_P1 VXLAN_EN MPS_RX_CTL_ORG MPS_RX_PRS_CTL GRE_VER_CHK_EN MPS_RX_MAX_TNL_HDR_LEN MPS_RX_PAUSE_DA_H Outer_IPv6_n_VLAN_VXLAN MatchAll Cls_Spare MPS_CLS_DIPIPV6ID_3_TABLE MPS_CLS_TCAM_DATA2_CTL ddp_version_0 ULP_RX_TLS_IND_CMD CLTCAMDEEPSLEEP DBGICMDMSKREAD LE_DB_PSV_FILTER_MASK_FLT_IPV4 LE_DB_SRVR_VF_SRCH_TABLE_DATA pcs40g_gate_sd_tx_clk MAC_PORT_AEC_ADD_CTL_STAT_0 MAC_PORT_AEC_DEBUG_LO_3 pad pcs100g_tx_lane_thresh Perr_rx9_pcs100g Perr_rx4_pcs100g MAC_PORT_MAC_25G_50G_AM3 rx_st_mac1g10g RXBERROFLOW RX_LINT_FAULT CL4_QUANTA_THRESH MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS64OCTETSHI MAC_PORT_MTIP_1G10G_TX_AMACCONTROLFRAMES MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_1HI MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_2HI MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_4 DTE_xS_present Latched_Block_Lock MAC_PORT_MTIP_KR4_CONTROL_1 10GBase_W_capable LANE_ALIGN_STATUS RX_Link_Status Lane4_algn_mrkr_lck Lane14_algn_mrkr_lck MAC_PORT_MTIP_CR4_LANE_9_MAPPING MAC_PORT_MTIP_CR4_LANE_19_MAPPING T5_AE3_RXSTAT_C3 MAC_PORT_AET_LIMITS3 MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_7_6 DATAPOS MAC_PORT_TX_LINKB_TRANSMIT_AE_C3_INIT_EXTENDED MAC_PORT_TX_LINKC_TRANSMIT_AE_V2_LIMIT_EXTENDED MAC_PORT_TX_LINKD_TRANSMIT_AE_C1_INIT2_EXTENDED PFLAG FDCC LOFU FROTCAL4 MAC_PORT_RX_LINKA_DFE_TAP_CONTROL MAC_PORT_RX_LINKA_DFE_TAP CSVAL QCDAMP MAC_PORT_RX_LINK_BCST_DFE_H1ODD_DELTA_AND_H1EVEN_DELTA ERS_MODE MC_LMC_INITSEQ5 EDC_H_DBG_BIST_CMD_INTF Edram0WrEnLo EDC_H_DBG_EDRAM0_RMW_CNT EDC_H_DBG_EDRAM1_RD_REQ_CNT dead_cycle1 dead_cycle1_pre_ref_rmw HMA_TLB_DESC_1_H HMA_REG0_BASE clearstats ncsi %1d:%1x:%02x/%1d:%1x:%02x RSS none UserModeIO: BaseAddress: UpdateScheduling: Generation: FetchTPHint: X2 microQSFP mss ISCSI ssws_disabled rcv_coalesce_push rcv_coalesce_last_psh t_rtseq_recent Variance in round-trip time pdu_len rx_ptr_raw Receive re-order fragment 3 length Length of Tx FPDU cq_idx_sq PDU response STAG Current FPDU has L-bit set ddp_indicate_out TF_DDP_OFF Remove_VLAN tx_pdu_out %u
Buf1: %u %u %u %u %u
Buf1: %u 0x%6.6x 0x%6.6x 0x%8.8x And buf0, which is also valid, has %u - %u = %u bytes of space left
is causing %u bytes to be held in PMRX
HostPageSizePF1 QueuesPerPageVFPF2 perr_conm_sram Size SGE_DBQ_CTXT_BADDR BaseAddr Opcode Threshold_0 HP_Count NoCoalesce SGE_LA_RESERVED_9 SGE_LA_WRPTR_14 RxWrPerr PCIE_PERR_ENABLE PCIE_NPTRANS_TOT PCIE_DBG_INDIR_DATA_1 SRD8 SBRS PCIE_CORE_PCI_EXPRESS_TAGS_ALLOCATION PSFE TXE0 TCIP TCIS TDCS PCIE_PF_CLI ClkSelect GPIO13_OEn GPIO3_CHG_DET DBG_TRACE0_CONF_COMPREG1 dse_alen MC_PCTL_ECCCFG phy_upd_done_pol CKPOND INIT TESTD MC_DDR3PHYDATX8_RDBDR6 MC_DDR3PHYDATX8_CLKENR MC_PVT_REG_OUT_DRVN ECC_CE_PAR_CAUSE ECC_CECNT MA_CLIENT10_WR_LATENCY_THRESHOLD MA_ULPRX_DEBUG_CNT CL9_PAR_WRQUEUE_ERROR_EN EDC_PAR_ENABLE EDC_ECC_STATUS FlashBaseAddr IllWrInt CIM_UP_ACC_INT_CAUSE CIM_HOST_ACC_CTRL CDebugDataH LAReset CIM_MEM_ZONE7_VA CIM_PF_MAILBOX_ACC_STATUS EPktDistChn2 RXFlowControlDisable MTUDefault LockTid EnableFilterLpbk CngRecSndNxt EnableNonOfdTidRss TpTcamKey MaxRxData EnableBUFE TableLatencyDone TP_SHIFT_CNT TNLIp6Sel SYN2tupEnIpv4 PortEnable DisableVlan EnableUp0 ETpOutIpFifoPerr ETpInCplFifoPerr TP_TM_HEAP_POP_CNT TP_TM_DACK_PUSH_CNT CommitLimit3 RxChnXoff1 ULP_TX_LA_RESERVED_0 use_bundle_len cong_thresh0 icspi0_Rx_framing_error oespi1_ofifo2x_Tx_framing_error icspi_par_error NumPorts PLIntEnb MPS_TX_PAUSE_RETRANS_BUF_GRP2 oVlanSelMac2 LpbkEn MPS_RX_CHMN_CNT FF CDM2 PG_TH_INT7 EOP_CNT_3 DBG_CDS_INV MPS_PORT_RX_RSS_HASH EOPCh1 SizeCh0 SOPCh2 Tx MPS_STAT_PERR_INT_ENABLE_RX_FIFO MPS_PORT_STAT_TX_PORT_BCAST_L MPS_PORT_STAT_TX_PORT_PPP4_L MPS_PORT_STAT_TX_PORT_PPP7_L MPS_PORT_STAT_RX_PORT_CRC_ERROR_L MPS_PF_STAT_TX_PF_UCAST_BYTES_H PlWeight SMB_MST_TIMEOUT_CFG MstRxByteCfg MstBusySts SlvCtlEn MstLostArbIntEn SMB_INT_CAUSE SlvErrInt SMB_ARP_UDID2 CAUSE_TPTCF_0 WB SEL_L ULP_RX_LA_RDPTR PF_EnableErr PLErr MAP6 Write FilterEn LEBUSEN CLIPTINDX LE_DB_DBGI_REQ_DATA NCSI_MPS_HDR_HI NCSI_LA_RDDATA TxProgress NCSI_MACB_RX_BUF_QPTR NCSI_MACB_SINGLE_COL_FRAMES NCSI_MACB_RX_UNDERSIZE_FRAME NCSI_MACB_HASH_HIGH Specific1En Tx_Byte_Swap XGM_Reset HWM XGMAC_PORT_XGM_TX_CTRL XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_1 PhyFrameComplete test_en link_status XGMAC_PORT_AN_INTERRUPT_STATUS TXSTAT_RDY XGMAC_PORT_AE_FSM_CTL TFSM_STATE RTSEL OPVAL XGMAC_PORT_HSS_TXB_TDM_BIASGEN_PWRON_TIMER XGMAC_PORT_HSS_TXB_TAP2_IDAC_OVR RRATE ROT0A XGMAC_PORT_HSS_RXA_SIGDET_CTRL XGMAC_PORT_HSS_RXA_DFE_AMP_SAMPLE XGMAC_PORT_HSS_RXA_DFE_D00_D01_OFFSET H4EMAG DPCTGT DPCCMP FH1SN XGMAC_PORT_HSS_RXB_PH_ROTATOR_OFFSET_CTRL XGMAC_PORT_HSS_RXD_PH_ROTATOR_POSITION2 XGMAC_PORT_HSS_RXD_DFE_E0_E1_OFFSET XGMAC_PORT_HSS_RXD_DFE_H2 XGMAC_PORT_HSS_TX_SEG_DIS_APP XGMAC_PORT_HSS_RX_PH_ROTATOR_OFFSET_CTRL FL_Count Coal_Strict_CIM_Pri SGE_DEBUG_DATA_HIGH_INDEX_10 debug_CIM_AFull_d SGE_DEBUG_DATA_HIGH_INDEX_15 TgtTagQPerr AUXPOWER_DETECTED PCIE_VC0_CDTS0 PCIE_VC0_CDTS1 Force_Link Link_Mode_Enable VC6_WRR PCIE_CORE_VC0_NONPOSTED_RECEIVE_QUEUE_CONTROL PCIE_CORE_VC1_COMPLETION_RECEIVE_QUEUE_CONTROL WinAperture_CPlus1 MinTag WrReqCnt DMA_Static_CGEN PCIE_PERR_GROUP ReqUnderFLRLogEn xmlh_in_rl0s GPIO19_ACT_LOW DBG_FUSE_SENSE_DONE T5_STATIC_C_PLL_PREDIV T5_STATIC_U_PLL_MULT T5_STATIC_KR_PLL_BGOFFSET DBG_T5_STATIC_KX_PLL_CONF1 MA_SGE_TH1_WRDATA_CNT MA_SGE_TH1_RDDATA_CNT MA_EXT_MEMORY1_RDDATA_CNT0 CNT_LOCK CL1_WR_DATA_TO_EN CL5_WR_CMD_TO_ERROR CL11_WR_DATA_TO_ERROR CL4_RD_CMD_TO_EN CL3_RD_CMD_TO_EN CL2_RD_CMD_TO_ERROR CL10_IF_PAR_EN MA_IF_PARITY_ERROR_STATUS CL4_IF_PAR_ERROR PHYS_ADDR_RESP_EN EOF_LS3 PM_TX_DBG_CTRL MPS_RX_PAUSE_GEN_TH_3_3 MPS_RX_MAC_CLS_DROP_CNT3 MacPadEnPt1 TrcMultiRSSFilter MPS_STAT_STOP_UPD_RX_VF_0_31 PCIE_Part_CGEn atomic_rd_opcode All_DataPath_CGEN ULP_RX_RFE_DISABLE skip_ma_req_en0 LN0_AESTAT LN0_AECMD TUPLESIZEEN SRVRSRAMEN LE_DB_SECOND_GEN_HASH_MASK_IPV4 NCSI_PERR_ENABLE EEE_RESET tx_lane MAC_PORT_CFG4 AEC3_RX_WIDTH HSSCALENAB HSSPLLCONFIGB RXAREFRESH_STATUS MAC_PORT_EEE_CTL MAC_PORT_EEE_TX_1G_QUIET_TIMER MAC_PORT_EEE_TX_1G_REFRESH_TIMER MAC_PORT_PTP_TIMER_OFFSET_0 RS_COL_CNT_EXT RX_ERR_DISC PAD_EN MAC_PORT_MTIP_HASHTABLE_LOAD PHY_LOS MAC_PORT_IFINUCASTPKTSHI MAC_PORT_IFINMULTICASTPKTSHI MAC_PORT_ETHERSTATSOCTETS SGMII_HDUPLEX 10GBASE_T MAC_PORT_MTIP_10GBASER_SEED_B2 MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS3 MAC_PORT_MTIP_PCS_BIP_ERR_CNT_11 CP1_STAT MAC_PORT_AE_PRBS_CTL_1 GAIN_TH BOOT_LUT0123 NEU_STATE RCAMP0 MAC_PORT_RESISTOR_CALIBRATION_STATUS_2 T5SASIMP MAC_PORT_TX_LINKA_TRANSMIT_DCLK_ROTATOR_OVERRIDE MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTE_4 MAC_PORT_TX_LINKA_TRANSMIT_DCC_TIME_OUT LPITERM C48DIVCTL MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_DATA MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 WRPSM ROT00 T5TRCMP MAC_PORT_RX_LINKA_DFE_OFFSET_EVN1_EVN2 MAC_PORT_RX_LINKA_DFE_OFFSET_ODD3_ODD4 LOFO4 MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS H3OSN_ReadOnly H4OSN_ReadWrite H10SN_ReadWrite ACJZNT MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_1 MAC_PORT_RX_LINKB_DFE_H5 MAC_PORT_RX_LINKD_DFE_OFFSET_EVN3_EVN4 MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_ERROR_COUNT MAC_PORT_RX_LINK_BCST_DFE_H2 MAC_PORT_RX_LINK_BCST_DFE_H8_AND_H9 MC_DDRPHY_PC_INIT_CAL_ERROR EN_SLICE_N_WR_1 POST_CUR_SEL_BITS2_3 POST_CUR_SEL_BITS12_13 PLL_TUNECP_0_2 PLL_TUNEF_0_5 DATA_BIT_ENABLE_16_23 MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR INCOMPLETE_RD_CAL_N3_MASK VALID_NS_BIG_L MC_DDRPHY_DP18_IO_TX_PFET_SLICE MEMINTD15_POS EN_RESET_WR_DELAY_WL DP18_0_Populated DP18_11_Populated ADR16_1_Populated MC_UPCTL_SCTL lp_trig MC_UPCTL_INTRSTAT mrrstat_beat3 zqcl_op MC_UPCTL_TOGCNT100N odt_rank_map1 dfi_lp_wakeup_dpd dfi_lp_wakeup_pd MC_UPCTL_DFITRWRLVLDELAY1 MC_P_BIST_STATUS_RDATA C_SEL NullPtr en_flm_fifth err_ishift_ur1 err_inv_ctxt4 err_pc_rsp_len1 FlmThreshPack KDBEOPErr Cur_LnE_RxPwrState Req_LnP_RxStateDone Req_LnK_RxStateReq LnI_STAT LnM_CMD PCIE_MULTI_PHY_INDIR_REQ PCIE_VF_MSIX_EN_7 TxDeemph_gen2_3p5db BUS_RST_STATE_flag PF3_DState STATIC_M_PLL_FFBYPASS STATIC_KX_PLL_CCALBANDSEL DBG_CUST_EFUSE_BYTE60_63 DDR_MODE ActiveFilterCounts EcnAckEct stag_fifo_perr_set0 flush_last MPS_VF_RX_CTL_191_160 LPBK_ALLOC MPS_RX_GRE_PROT_TYPE MPS_RX_PAUSE MPS_RX_DEFAULT_VNI DIP_EN Outer_IPv6_n_VLAN_NVGRE MPS_STAT_STOP_UPD_TX_VF_128_159 MPS_STAT_STOP_UPD_RX_VF_224_255 DataVIDH1 MPS_CLS_TCAM_RDATA0_REQ_ID0 LE_DB_EXEC_CTRL ACTV_OPEN_ERR TotCntErr xgmii_sel Enable_25G an_reset_sd_tx_clk pcs40g_reset_sd3_rx_clk pcs100g_reset_sd0_rx_clk xgmii_clk_reset REG_FPH_ATTR_TXSTAT_VALID MAC_PORT_AEC_DEBUG_HI_3 mac1g10g_tx_rem_fault an_pcs_rx_clk_ena pcs100g_block_lock Perr_rx0_fec100g_dk Perr_rx16_pcs100g MAC_PORT_PTP_SINGLE_ALARM MAC_PORT_MTIP_1G10G_TX_ETHERSTATSOCTETSHI MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_3 10GBASE_R_PCS_Block_Lock PRBS31_TX_Tst_Pttrn_En MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_4 MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_3 Lane_15_blck_lck Lane_9_blck_lck MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_15 MAC_PORT_MTIP_CR4_LANE_17_MAPPING RS_FEC_bypass_error_indication_ability MAC_PORT_MTIP_RS_FEC_SYMBLERR0_LO MAC_PORT_MTIP_RS_FEC_VENDOR_INFO_1 MAC_PORT_MTIP_FEC1_NCERR_CNT_1 MAC_PORT_MTIP_FEC_STATUS3 CTRL_STAT RCALERR DCCCOMPINV AS2X0 AT4X MAC_PORT_TX_LINKA_TRANSMIT_AE_C3_INIT_EXTENDED MAC_PORT_TX_LINKB_TRANSMIT_TAP_3_COEFFICIENT MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_4X_OVERRIDE MAC_PORT_TX_LINKD_TRANSMIT_AE_C2_INIT_EXTENDED MAC_PORT_TX_LINKD_TRANSMIT_AE_C0_INIT2_EXTENDED MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C0_INIT2_EXTENDED ADAC1 MAC_PORT_RX_LINKA_DFE_H1H2H3_LOCAL_OFFSET H12SN CSIND DCDALTWPDIS PRBSMODE MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2 MAC_PORT_RX_LINKD_RECEIVER_DCD_CONTROL MAC_PORT_RX_LINK_BCST_RECEIVER_IQAMP_CONTROL_2 MAC_PORT_RX_LINK_BCST_RECEIVER_DACAP_AND_DACAN_SELECTION MC_DDRPHY_AD32S_OUTPUT_DRIVER_FORCE_VALUE0 HW_VALUE PASS_FAIL_VALUE SS_QUAD EN_DQS_OFFSET FORCE_MPR PMUM QUADCS_RDIMM DEV_TYPE CE_THRESHOLD CKE_OE ROW_WIDTH MC_LMC_SDTR0 T_WTR MC_LMC_SDTR4 CL31 CS_LAT_MODE VREF_DQ_VALUE BCmdVld BRspRdy DCA IDTF MPS_VF_STAT_TX_VF_MCAST_BYTES_H PL_VF_REVISION OpCode i2c %s (type %d, rev %d) is not a known card. dbg Prot - tos fcoe sip-sp smac invalid smac address "%s" FLMPacking: Rx CHELSIO_T4_SET_TRACER must supply a port QSFP8X cl-wrr s CHELSIO_T4_LOAD_BOOT CHELSIO_T4_SET_OFLD_POLICY Error while reading from file "%s" at line %d missing "]" after "[%c" on line %zd Coding Error in: scb_slush tx_channel turbo mod_schd_reason2 tx_compact TF_RDMA_ERROR TF_TX_PDU_OUT recv_sack pd_id rdmap_opcode TF_DDP_PSHF_ENABLE_0 OPT_0_KEEPALIVE Data being DDP'ed to buf 0, TF_TLS_KEY_MODE DDP control flags QueuesPerPageVFPF0 perr_idma2imsg_fifo1 perr_eswitch_fifo3 SGE_FLM_CFG Threshold_2 ITPOpMode SGE_INGRESS_QUEUES_PER_PAGE_VF SGE_ERROR_STATS Uncaptured_Error SGE_PC0_REQ_BIST_ERROR_CNT MATagPerr BypassMSICache PCIE_CFG_SPACE_DATA VFVld PCIE_PDEBUG_DATA_LOW PCIE_BUS_MST_STAT_7 EPES RCAS PIND RLNS PME0 L23S GPIO7_OEn GPIO0_CHG_DET ARM_FAIL_int_enbl U_LOCK GPIO5 STATIC_U_PLL_RANGEA STATIC_KX_PLL_C STATIC_KR_PLL_C STATIC_LVDS_CLKOUT_EN STATIC_KR_PLL_V PSRO_sel DBG_TRACE0_CONF_MASKREG0 dbg_operate_sgl_dbl_trigger DBG_PVT_REG_DRVN REG_IN_DRVP_A DBG_PVT_REG_SAMPLE_WAIT_CLKS dual_pctl_en MC_PCTL_MCMD i_phy_upd_trig MC_DDR3PHYAC_ACCR HDRCLKEN MC_DDR3PHYDATX8_PMBDR1 EXT_MEM_PAGE_SIZE MA_ARB_CTRL DIS_ADV_ARB CL7_PAR_WRQUEUE_ERROR_EN CL9_PAR_RDQUEUE_ERROR EDC_BIST_NUM_ERR CIM_EEPROM_BASE_ADDR IBQSGEHIParErr SglRdCtlIntEn BlkWrBootIntEn IllWrIntEn QueDbg8BEn CIM_MEM_ZONE5_LEN TP_CMM_MM_FLST_SIZE TP_PMM_RX_MAX_PAGE SACKMode MSSThreshold EnableDDPFlowControl TunnelCngDrop0 DisableTmoCng TnlErrorEthHdrLen TnlErrorMac MaxRtt SYN2tupEnIpv6 SYNVrtSel CongestionEnable VirtPort2Table TP_TX_MOD_QUEUE_WEIGHT0 TP_MIB_DATA FlmTxFlstEmpty TP_TM_DACK_POP_CNT RxFutureData TxRxmTimerKeepalive RxChnXoff0 ULP_TX_TPT_ULIMIT ULP_TX_CPL_ERR_VALUE_L ULP_TX_ULP2TP_BIST_CMD ULP_TX_FPGA_CMD_13 DROP_CH3 PM_TX_INT_CAUSE Detect8023 MPS_TP_CSIDE_MUX_CTL_P0 oVlanSelMac0 RegHaltOn TH_LOW MPS_RX_PAUSE_GEN_TH_2 MPS_PFVF_ATRB_FLTR2 MPS_PFVF_ATRB_FLTR4 MPS_VF_RPLCT_MAP2 MPS_PKD_MEM_DATA2 MPS_RX_SE_CNT_IN5 SOP_CNT_2 MPS_RX_SPI_ERR BUBBLE TxDescFifo SOPCh1 SOPCh3 EOPPt2 Rxvf Rxpf MPS_STAT_RX_BG_0_LB_DROP_FRAME_H MPS_PORT_STAT_LB_PORT_1024B_1518B_L MPS_PORT_STAT_RX_PORT_SYM_ERROR_H MPS_PORT_STAT_RX_PORT_512B_1023B_L MPS_PF_STAT_TX_PF_UCAST_BYTES_L MPS_PF_STAT_TX_PF_UCAST_FRAMES_H MPS_PORT_CLS_HASH_SRAM MPS_PORT_CLS_BMC_MAC_ADDR_L MPS_CLS_SRAM_H SMB_MST_TX_FIFO_RDWR SlvRxRdyInt SlvInjDataErr AuxAddr1 MI_ADDR LEPartCGEn CAUSE_DDPDF_1 CAUSE_MPARC_1 ULP_RX_PERR_ENABLE PERR_ENABLE_DDPMF_0 EOP_CNT_IN0 ULP_RX_LA_RESERVED PL_INT_MAP4 EnablePF PL_VF_SLICE_L ASBOTHSRCHEN BUILD LE_MISC LE_DB_MASK_IPV4 LE_PERR_ENABLE LE_DEBUG_LA_CONFIG LE_MA_DEBUG_LA_DATA soft_pkg_sel NCSI_CH1_SADDR_LOW CH3_SADDR_HIGH TXFIFO_prty_err PauseHWM LoopLocal PClkDiv128 UCastHashEn RxOverrunErr RetryLimitErr NCSI_MACB_TYPE_ID NCSI_MACB_TX_PAUSE_QUANTUM NCSI_MACB_REV_STATUS XGM_Tx_Disable_Crc XGMAC_PORT_FPGA_ERRPKT_CNT stopErr PCSR_Link_Fail PCS_Link_Fail XGM_Int XGMAC_PORT_INT_CAUSE RXDPHSLOCK RXBPHSLOCK XGMAC_PORT_HSS_STATUS RXAPRBSERR EnJumbo TxUFlow XGMAC_PORT_XGM_STAT_TX_ERR_FRAMES XGMAC_PORT_XGM_STAT_RX_65_127B_FRAMES tx_tst_en an_enable 10GBASE_KX4_Capable Selector_Field 10GBASE_KR_neg 1000BASE_KX_neg RXREQ_C2 PRBS_SYNCCNT PRBS_GEN_OFF XGMAC_PORT_AE_KR_STATUS DFEREQ ESAMP XGMAC_PORT_HSS_RXA_DFE_D10_D11_OFFSET XGMAC_PORT_HSS_RXA_DFE_H5 XGMAC_PORT_HSS_RXA_DAC_DPC FSDET XGMAC_PORT_HSS_RXB_PH_ROTATOR_POSITION2 XGMAC_PORT_HSS_RXB_PH_ROTATOR_STATIC_PH_OFFSET XGMAC_PORT_HSS_TXC_TEST_CTRL XGMAC_PORT_HSS_TXD_TDM_BIASGEN_PWRON_TIMER XGMAC_PORT_HSS_TXD_TAP2_IDAC_OVR XGMAC_PORT_HSS_RXC_PH_ROTATOR_CTRL CVHOLD TXBEN TXARST XGMAC_PORT_HSS_RX_DACAP_DAC_AN_OFFSET XGMAC_PORT_HSS_RX_ADAC_CTRL err_wr_len_too_large1 perr_edma_input_fifo0 SGE_DBP_FETCH_THRESHOLD SGE_DBVFIFO_SIZE debug_PC_Req_EOP0_cnt debug_T_RxAFull_d debug_itp_expired debug_st_edma0_req SGE_DEBUG_DATA_LOW_INDEX_15 HReqWrPerr PCIE_VF_INT_CFG TxNPD_FC VC2_WRR PCIE_CORE_VC1_POSTED_RECEIVE_QUEUE_CONTROL VC1_NPH_Credits DC_Balance_Disable NPH_CreditsAvailVC0 PIOReq_MEMDataPerr LnD_CMD LnG_STAT GPIO18_CHG_DET DBG_T5_STATIC_M_PLL_CONF2 T5_STATIC_M_PLL_SDORDER T5_STATIC_M_PLL_VCVTUNE T5_STATIC_KR_PLL_CCALFMAX DBG_T5_STATIC_C_DFS_CONF GPIO15_PE_En DBG_GPIO_PS_EN GPIO13_PS_En EXT_MEM1_SIZE MA_PMTX_THROTTLE FL_LIMIT MA_EXT_MEMORY0_RDDATA_CNT1 MA_WRITE_TIMEOUT_ERROR_STATUS CL8_RD_DATA_TO_EN CL11_RD_CMD_TO_ERROR CL11_RD_DATA_TO_ERROR CIM_QUEUE_FEATURE_DISABLE ULP_TX_CGEN_GLOBAL MPS_RX_PAUSE_GEN_TH_1_0 MPS_RX_LPBK_CLS_DROP_CNT1 MPS_RX_CGEN LpbkSeCnt LpbkPadEnPt0 TrcMPS2TP_MacOnly LPBK_DMAC_TCAM_SEL atomic_wr_opcode sdc_crc_prot_en ENABLE_PF_PBL_0 clear_ctx_err_cnt0 ULP_RX_CHNL0_CTX_ERROR_COUNT_PER_TID TxFIFO_empty MAC_PORT_MAGIC_MACID_LO Perr0_rx_sd RXDQUIET TXCQUIET RXDASSTCLK sd6_CGEN MAC_PORT_EEE_TX_10G_WAKE_TIMER SW_RESET TX_PAD_EN ENABLE MAC_PORT_ETHERSTATSPKTS256TO511OCTETS MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETS Loopback CollisionTest 100BaseXFullDplx RealTimePgRcvd MAC_PORT_MTIP_MDIO_REGADDR VendDev1 AMLOCK14 MAC_PORT_MTIP_PCS_LANE_MAP_5 PDF MAC_PORT_BEAN_ABILITY_0_LANE3 MAC_PORT_BEAN_XNP_1_LANE3 T5_RXREQ_C1 CIN_ENABLE RCCTL0 RCAMP1 MACROTEST MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_1 MAC_PORT_PLLB_MACRO_TEST_CONTROL_1 MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C0_INIT_EXTENDED MAC_PORT_TX_LINKC_TRANSMIT_TEST_CONTROL MAC_PORT_TX_LINKC_TRANSMIT_DCC_APPLIED MAC_PORT_TX_LINKC_TRANSMIT_802_3AZ_CONTROL MAC_PORT_TX_LINKD_TRANSMIT_DCC_OVERRIDE MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 RSTFW FHGS LOFO3S_ReadOnly T5E0AMP EMOFLO H9SN_ReadWrite H10GS MAC_PORT_RX_LINKB_RECEIVER_DACAP_AND_DACAN MAC_PORT_RX_LINKC_DFE_E0_AND_E1_OFFSET MAC_PORT_RX_LINKD_DFE_H2 MAC_PORT_RX_LINK_BCST_RECEIVER_ADAC_CONTROL MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN3_EVN4 RANK_PAIR0_PRI MC_DDRPHY_PC_ERROR_STATUS0 ENA_CUSTOM_WR ERROR_DQS_ALIGN ERROR_COARSE_RD MC_DDRPHY_PC_MR3_PRI_RP ADDR_MIRROR_RP2_SEC RANK_GROUPING MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN3 VREG_VCCTUNE_0_1 SYSCLK_ROT ATEST1CTL0 WL_ADVANCE_DISABLE PEAK_AMP_CTL_SIDE1 RDCLK_SELECT3 MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR MAX_DQS_DRIFT NO_DQS COARSE_PATTERN_ERR_N1_MASK MC_DDRPHY_DP18_WR_LVL_STATUS0 MC_DDRPHY_DP18_WR_CNTR_STATUS0 VALID_NS_JUMP_BACK MC_DDRPHY_DP18_PATTERN_POS_2 ecc_intr dtu_rd_row0 MC_UPCTL_DTUWD0 MC_UPCTL_DFITCTRLUPDI MC_UPCTL_DFITDRAMCLKEN dfi_lp_en_dpd MC_UPCTL_DFITRWRLVLRESP2 MC_UPCTL_DFITRWRLVLDELAY2 MC_P_INT_ENABLE STATIC_SWLAT MC_P_BIST_USER_WDATA2 HMA_TABLE_ACCESS HMA_COOKIE C_FID mps_ch_cng SGE_DBG_QUEUE_STAT0 debug_idma1_ishift_tx_size debug_idma0_ishift_tx_size PCIE_PHY_REQRXPWR1 Cur_LnK_RxPwrState LnL_STAT LnK_CMD Lane11FS PF6_DState STATIC_M_PLL_LOCKTUNE STATIC_SWMC1CfgRst_ STATIC_C_PLL_DCO_BYPASS STATIC_KR_PLL_CCALFMIN EFUSE_OPER_TYP HMA_DIS_BANK_FAIR PCIE2CIMIntfParErr ma_timer_enable ULIMIT_EXCLUSIVE_FIX sge_fifo_perr_set1 sge_fifo_perr_set0 T5Mode AddrMask CONG_EN GRE MPS_RX_INNER_HDR_IVLAN MPS_RX_ENCAP_GENEVE EN_IP_CSUM_CHK MPS_RX_PAUSE_DA_L MPS_RX_CNT_GENEVE_PKT_TO_TP1 Outer_IPv4_n_Inner_IPv4 PHY_STATUS REGION_EN TPDB_IF_PAUSE_REQ HashTblMemAccErr TcamBkChkEn PRI_FILT Led0_thi sgmii_sd_sig_det AEC_SYS_LANE_TYPE_1 CU_C2_ACK_VALUE an_int pcs10g_fec_locked rx_mac1g10g MDIO_read_error CLEAR MAC_PORT_MTIP_1G10G_IF_MODE PRBS31_Pttrn_Tstng_Ability Latched_High_BER MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_CONTROL TX_Test_Pattern_En Clause_22_reg Ber_cnt RX_TP_EN MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_17 MAC_PORT_MTIP_RS_FEC_CONTROL RS_FEC_Enable 100GCR4 MAC_PORT_INEQUALITY_HIGH_LIMIT AS4X7 MAC_PORT_TX_LINKB_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER MAC_PORT_TX_LINKC_TRANSMIT_AE_C2_INIT_EXTENDED MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C2_LIMIT_EXTENDED MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_VM_LIMIT_EXTENDED MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_V2_LIMIT_EXTENDED WRTACC1 FDCCAL MAC_PORT_RX_LINKA_RECEIVER_LOFF_CONTROL_REGISTER H11SN H15MAG MAC_PORT_RX_LINKB_DFE_TAP_CONTROL MAC_PORT_RX_LINKC_DFE_H14_15 MAC_PORT_RX_LINK_BCST_RECEIVER_IQAMP_CONTROL_1 MAC_PORT_RX_LINK_BCST_AC_COUPLING_CURRENT_SOURCE_ADJUST MAC_PORT_RX_LINK_BCST_RECEIVER_DCD_CONTROL FORCE_HI_Z DESIRED_EDGE_CNTR_TARGET_LOW QUAD0_PWR_CTL MT_SYSCLK_RESET MT_PVTN WD_DLY INIT_ENABLE MC_LMC_CMD7 MC_LMC_INITSEQ9 T_RTRO T_RRD_L SMR0_RFU0 PPD RBT SMR1_DLL PAR_LAT_MODE WR_HI_TH MASK_128_0 MCmdNRB MCmdRdy BCmdRdy stg_wrdq_notempty HMA_REG0_MIN PAGE_SIZE0 ADDR3_MIN MPS_VF_STAT_RX_VF_MCAST_BYTES_L CIM_VF_EXT_MAILBOX_DATA_18 hma delete Switch: port=%d %02x macidx conflicting IPv4/IPv6 specifications. pass prefix %u is too long for an %s address Valid: CIDXFlushThresh: GTSmode: QueueEntrySize: QueueEntryOverride: invalid byte offset "%s"
tracer %u (currently %s) captures rx second argument can only be "raw" XBI HD4X invalid rate-unit parameter "%s" sched config "minmax" parameter missing not ecn %4d:%4d %31s: 0x%1llx TF_TX_PACE_AUTO TF_RCV_COALESCE_PUSH TF_MOD_SCHD_REASON0 rss_info max_rt rcv_scale Highest sequence number in transmit buffer ddp_wait_frag TF_DDP_BUF0_UNUSED ddp_pshf_enable_1 TF_DDP_PSH_NO_INVALIDATE1 DDP: DDPOFF ActBuf IndOut WaitFrag Rx2Tx BufInf
Ind PshfEn PushDis Flush NoInvalidate
ULP mode: 0 =toe, 2=iscsi, 4=rdma, 5=ddp, 6=fcoe, 7=user, remaining values reserved , ulp_ext %u TF_DDP_INDICATE_FLL RxPktCPLMode IngIntCompareIDX PktShift IngPCIeBoundary HostPageSizePF4 InjectDataErr perr_dbp_pc_rsp_fifo1 perr_pd_fifo3 SGE_FL_BUFFER_SIZE11 SGE_DBFIFO_STATUS TimerValue2 MaxTag0 SGE_LA_RDDATA_4 SGE_LA_WRPTR_7 SGE_LA_RDDATA_10 SGE_LA_RESERVED_10 SGE_LA_RDPTR_15 SGE_LA_RESERVED_15 NonFatalErr RdRspErr ForceProgressCnt LINKDOWN_RESET_EN Pointer TC PCIE_PDEBUG_DATA_HIGH PCIE_RSP_ERR_STAT_6 PCIE_MSIX_EN_5 SWD0 SRD0 RCES OTDS TDUS PC3S OPM2 GPIO2 P_OCLK_MUXSEL DBG_PVT_REG_UPDATE_CTL FAST_UPDATe termp_a_history rank1_odt_read_sel MC_PCTL_TZQCL inline_syn_en dtu_wr_byte1 pvt_upd_done_pol phy_upd_done_type WLSDVT MC_DDR3PHYDATX8_ACR MA_CLIENT6_WR_LATENCY_THRESHOLD MA_CLIENT7_RD_LATENCY_THRESHOLD HMA_ENABLE BlkWrPlIntEn SglWrCtlIntEn BlkWrFlashIntEn TimeOutInt QueSize QueBase CIM_CDEBUGDATA CIM_MEM_ZONE0_VA DAddrTimeOut TP_PMM_RX_PAGE_SIZE TP_PMM_TX_MAX_PAGE EnableOcspiFull EnableELbkAFull EnableNonOfdTcbRss TimerBackoffIndex3 TimerBackoffIndex14 CngCtrlECN TnlErrorCsumIP TP_TX_MOD_QUEUE_REQ_MAP FlmPerrSet TP_TM_HEAP_PUSH_CNT RxRcvWndZero TxRcvAdvLtMss CommitReset1 ForceCong1 ForceCong0 CommitLimit0 OfdRate2 WriteEnable TP_PROTOCOL_DATA0 ULP_TX_TPT_LLIMIT ULP_TX_FPGA_CMD_3 ULP_TX_FPGA_CMD_14 DROP_CH2 DROP_CH1 ULP_TX_LA_RESERVED_1 ULP_TX_LA_RDPTR_2 ULP_TX_LA_RESERVED_4 ULP_TX_LA_WRPTR_7 PM_RX_STAT_MSB ocspi0_Rx_framing_error PM_TX_STAT_MSB MPS_VF_RX_CTL_127_96 MPS_FPGA_DEBUG oVlanSelLpbk2 MPS_RX_PG_SHR_BG0 TRUNC_WT SPMX CDL3 MPS_RX_QFC0_ATRB MAC_WT MPS_PFVF_ATRB_FLTR6 SOP_CNT_3 ST3 MPS_RX_OUT_BUS_STATE RPLCT_SEL_L CHK_8023_LEN_L FIXED_VF_VLD MPS_PORT_TX_LPBK_RELOAD_CH3 MPS_TRC_TIMESTAMP_H MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H MPS_PORT_STAT_TX_PORT_DROP_L MPS_PORT_STAT_TX_PORT_PPP2_H MPS_PORT_STAT_LB_PORT_1024B_1518B_H VF MPS_PORT_CLS_BMC_MAC_ADDR_H BMC_VLAN_SEL MPS_CLS_CTL MacParityMaskSize MPS_CLS_TCAM_Y_H CPL_MAP_TBL_IDX SlvCrcPreset UART_CONFIG ULP_RX_TDDP_PSZ ULP_RX_CTX_ACC_CH1 SOP_CNT_AL1 ULP_RX_DBG_DATAH ULP_RX MapDefault PL_REV PL_PORTX_MAP SRINDX HASHTIDSIZE DBGICMDPERR LE_RSP_DEBUG_LA_DATA NCSI_CH2_SADDR_HIGH NCSI_CH3_SADDR_LOW NCSI_CIM_DEMUX_CNT NCSI_MACB_NETWORK_CFG NCSI_MACB_LATE_COL NCSI_MACB_SPECIFIC_3_LOW UserProgOutput XGMAC_PORT_CFG LoopNoFwd XGM_Tx_pause_size Rx_Lane_Swap XGMAC_PORT_RESET_CTRL locflt pause XGMAC_PORT_INT_EN PCSR_FEC_Error RxFifo_prty_err TXCOBS HSSRXTS RXBPHSDNIN DecAvgTxIPG ReadSnpShot PortAddr XGMAC_PORT_XGM_STAT_RX_BYTES_HIGH Decode_Error tx_prbs9_en NP FSM_GDMRK CC0FSM_STATE XGMAC_PORT_HSS_TXA_TDM_BIASGEN_STANDBY_TIMER CXINIT XGMAC_PORT_HSS_TXB_TEST_CTRL XGMAC_PORT_HSS_TXB_PWR_DAC XGMAC_PORT_HSS_TXB_EXT_ADDR_DATA EMEN H1EMAG H5OMAG BLKODEC FVOFF XGMAC_PORT_HSS_RXB_DDC XGMAC_PORT_HSS_TXC_DRIVER_OVR_CTRL XGMAC_PORT_HSS_RXD_PH_ROTATOR_POSITION1 XGMAC_PORT_HSS_RXD_DAC_DPC XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_4 XGMAC_PORT_HSS_PORT_RESET_0 XGMAC_PORT_HSS_TX_COEFF_CTRL XGMAC_PORT_HSS_RX_DFE_AMP_SAMPLE err_large_minfetch_with_txcoal1 perr_idma_switch_output_fifo1 FL_Int_Thresh FetchBurstMax3 CGEN_Ingress_Context SGE_DBVFIFO_BADDR LP_Int_Thresh_Low CIM_WM debug_UD_Rx_EOP2_cnt debug_PD_WrReq_Int0_cnt debug_CPLSW_TP_Rx_SOP0_cnt debug_CPLSW_TP_Rx_EOP0_cnt debug_st_idma0_ialn debug_st_dbp_thread0_main SGE_DEBUG_DATA_LOW_INDEX_7 SGE_DEBUG_DATA_LOW_INDEX_11 PIOTagQPerr ExitL1 PCIE_VF_MSI_EN_2 RcvdBAR2Cookie PCIE_CRS Low_Power_Entrance_Count Mask_RADM_Filter DLLP_Delay_Disable PCIE_CORE_GEN3_EQ_FS_LF AtmEOPMatchSOP PIOReq_PLMDataPerr NegotiatedWidth Lane1FS PCIE_PHY_PRESET_COEFF GPIO16_OEn T5_STATIC_M_PLL_MULTPRE DBG_T5_STATIC_C_PLL_CONF1 T5_STATIC_KR_PLL_CPISEL T5_STATIC_KX_PLL_CPISEL MA_TP_TH0_RDDATA_CNT MA_EDRAM0_RDDATA_CNT1 CL3_WR_CMD_TO_EN CL10_WR_CMD_TO_ERROR CL4_WR_DATA_TO_ERROR WR_TIM DEBUGPAGE ospi_or_bundle_len_par_err NCSI_Ch4_CLR CountPauseStatRx MA_Part_CGEn ENABLE_ALN_SDC_ERR_0 ASBOTHSRCHENPR TCAMARBOFF AEC1_TX_WIDTH HSSRECCALA RXAREFRESH TXAREFRESH eee_tx_1g_state sd7_CGEN LPI_ACTIVE MAC_PORT_EEE_WF_COUNT NO_LGTH_CHECK AlmstFull MAC_PORT_MTIP_SGMII_CONTROL read_incr LP_MODE 10G 10GPRBS31 MAC_PORT_MTIP_10GBASER_SEED_A MAC_PORT_MTIP_BASER_TEST_CTRL TxTestPatEn Lane6 AMLOCK1 MAC_PORT_MTIP_PCS_BIP_ERR_CNT_1 frame_lock CP1_UPD T5_TXREQ_C1 MAC_PORT_AE_RX_SIGDET_1 EMIS RESYNC MAC_PORT_PLLB_EYE_METRICS_INTERVAL_CONTROL CALSSTN MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_ADDR LPIPRCD MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_APPLIED MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_DATA MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS H1E3 FINTTRIM LOFE2 LOFE3S_ReadWrite T5E1SN_ReadWrite T5E0SN_ReadWrite T5_RX_VTBYP T5EMMD MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PDF_EYE_COUNT MAC_PORT_RX_LINKA_DFE_H3 MAC_PORT_RX_LINKB_DFE_H4 MAC_PORT_RX_LINKB_DFE_H10_AND_H11 RANK_PAIR3_SEC WRITE_LATENCY_OFFSET MC_DDRPHY_PC_MR0_SEC_RP MC_ADR_DDRPHY_ADR_DELAY0 MC_ADR_DDRPHY_ADR_DELAY1 MC_ADR_DDRPHY_ADR_DELAY7 WR_DELAY MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP OFFSET_BITS1_7 RD_EYE_SIZE_BITS2_7 TRAILING_EDGE_FOUND MIN_EYE COARSE_PATTERN_ERR_N2_MASK DDONE INVALID_NS_SMALL_L_MASK MEMINTD16_POS MEMINTD19_POS MPR_PATTERN_BIT DISABLE_PARITY_CHECKER MC_DDRPHY_APB_ERROR_STATUS0 DP18_10_Populated ADR16_3_Populated MC_UPCTL_SCFG mrrstat_beat0 hw_exit_idle_en dtu_wr_row0 MC_UPCTL_DTURD1 EDC_H_ECC_STATUS InvOnDBSync SGE_GK_CONTROL2 SGE_QBASE_MAP2 debug_idma0_idma2imsg_cmp_out_nocpl RcvdVDMRxCookie RcvdVDMTxCookie PIOCpl_VDMTxCtlPerr Req_LnG_RxStateReq Req_LnD_RxStateDone Req_LnP_RxStateReq Cur_LnP_RxPwrState PCIE_VF_MSIX_EN_6 PCIE_PHY_CTRL1 DL_DOWN_PCIeCRST_MODE0_STATE_flag STATIC_M_PLL_STOPCLKA DBG_STATIC_U_PLL_CONF3 STATIC_KR_PLL_CPISEL STATIC_KR_PLL_CCALCVHOLD DBG_CUST_EFUSE_BYTE56_59 HMA_DIS_BG_ARB FUTURE_CEXPANSION_WTE CCplAckMode map_fifo_perr_set2 urgent_last more_middle ULP_TX_TLS_IND_DATA MPS_VF_TX_CTL_159_128 MPS_RX_FIFO_0_CTL MAC_ALLOC MPS_RX_PRS_CTL_2 MPS_RX_CNT_VXLAN_PKT_MAC0 MPS_RX_CNT_NVGRE_PKT_TO_TP1 Outer_IPv6_n_Inner_IPv6 EN1 CtlCmdType LE_DB_RSP_CODE_1 CmdPrsrIntErr DBGIRspLearn an_gate_sd_tx_clk sgmii_gate_ref_clk AEC_SYS_LANE_SELECT_O AEC_RX_UNKNOWN_LANE_2 AEC_RX_LANE_ID_2 FC_LSNA_ CUF_C1_FSM_DEBUG MAC_PORT_PCS_DEBUG0_RO pcs40g_ber_timer_done sgmii_sg_rx_sync sgmii_loop MAC_PORT_MAC_25G_50G_AM1 Perr_rx3_pcs40g Perr_rx1_fec40g Perr_tx_pcs1g MAC_PORT_MTIP_1G10G_MDIO_REGADDR MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1024TO1518OCTETS MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_2 MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_7HI SGMII_DUPLEx RX_LPI PCS_RX_Link_STAT 10GBASE_R_PCS_High_BER MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_0 MAC_PORT_MTIP_KR4_LANE_0_MAPPING MAC_PORT_MTIP_CR4_SPEED_ABILITY ERR_BLKS_CNTR MAC_PORT_MTIP_CR4_LANE_11_MAPPING MAC_PORT_MTIP_RS_FEC_LANEMAPRS_FEC_NCCW_HI MAC_PORT_MTIP_FEC0_NCERR_CNT_0 MAC_PORT_MTIP_FEC3_CERR_CNT_0 MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE ATUNEN MAC_PORT_TX_LINKA_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER AS4X0 AS1X7 OS4X3 ERRORP MAC_PORT_TX_LINKA_TRANSMIT_AE_C1_INIT_EXTENDED MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_2X_OVERRIDE MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_5 SELAPAN MAC_PORT_RX_LINKA_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL MAC_PORT_RX_LINKA_DFE_OFFSET_VALUE FDCD2 FPRBSPOLTOG H10SN H1ODELTA STNDBYSTAT DCDOVRDEN MAC_PORT_RX_LINKB_PEAKED_INTEGRATOR MAC_PORT_RX_LINKB_DFE_H14_15 MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_3 MAC_PORT_RX_LINKD_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL MAC_PORT_RX_LINKD_RECEIVER_LOFF_CONTROL_REGISTER MAC_PORT_RX_LINKD_RECEIVER_DCC_CONTROL MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2 MAC_PORT_RX_LINK_BCST_RECEIVER_DCC_CONTROL SPAM_EN ADDR_MIRROR_BG0_BG1 CMD SMR1_RFU0 RD_CRC BWDataRdy EDC_H_DBG_BIST_RDATA_INTF EdramDwsn EdramCra EDC_H_DBG_EDRAM0_RD_REQ_CNT rdtag_notfull dead_cycle1_bbi dead_cycle1_rmw dead_cycle0_bbi_rmw PCIEMST_INT_ENABLE > filter /dev/%s mc le Pass: Q= Prio ipv4 ipv4 param %s: mask not allowed for hashfilter or nat params FetchBurstMin: uPTokenEn: PackOffset: SplitLenMode: invalid i2c device address "%s" Unknown sched "type" parameter missing sched params "class" missing * %d stray negation(s) at end of offload settings High Priority TCAM Region: non_offload TF_RX_FLOW_CONTROL_DISABLE core_fin rcv_coalesce_heartbeat mod_schd_tx Timer accounting field Receive re-order fragment 2 length tx_oos_rxmt ddp_buf_inf OPT_1_FLT_INFO cctrl: sel %s, ecn %u, ece %u, cwr %u, rfr %u
frag1_ptr 0x%-8x
aux1_slush0: 0x%x aux1_slush1 0x%x
ulp_ext ULP mode: 0 =toe, 2=iscsi, 4=rdma, 5=ddp, 6=fcoe, 7=user, 8=tls, 9=dtls, remaining values reserved rx_tls_flags aux3_slush: 0x%x, unused: buf0 0x%x, buf1: 0x%x
TimerReg SGE_HOST_PAGE_SIZE HostPageSizePF7 QueuesPerPageVFPF5 perr_itp_evr err_invalid_cidx_inc egress_size_err Throttle_Enable MaxTag1 SGE_LA_WRPTR_2 SGE_LA_WRPTR_9 SGE_LA_RDDATA_12 PCIE_CMD_CTRL PCIE_CFG_SPACE_REQ PCIE_BUS_MST_STAT_1 PCIE_BUS_MST_STAT_6 PCIE_MSI_EN_4 MaxBufWrReq OP2D VRB1 RDPE PC6I L1RS GPIO14_CHG_DET GPIO13_IN GPIO12_ACT_LOW STATIC_C_PLL_PREDIV STATIC_M_PLL_RANGEA STATIC_M_PLL_BYPASS rank2_odt_write_nsel MC_PCTL_TRTW MC_PCTL_TRSTL dtu_wr_byte15 byte_oe_ctl OCPONR CKEPONR PLLRST MC_DDR3PHYDATX8_WDBDR1 MA_CLIENT5_WR_LATENCY_THRESHOLD CL9_PAR_RDQUEUE_ERROR_EN CL2_PAR_WRQUEUE_ERROR ENABLE_PERF EEPROMAddrSize MBHostParErr LAFillOnce CIM_MEM_ZONE6_LEN EnableOptMtu EnableOespiFull EnableCHdrAFull TimerBackoffIndex10 InitRwnd TxPaceAuto EnableReadAhead SchdEnable TnlErrorIpHdrLen RxtShiftMaxR2 MTUValue LkpTblQueue0 RRCPLQueWidth HashDelay VirtPort0Table TP_RESET RxRcvRxmData EnableFifoFull0 TP_TX_SCHED CommitReset3 TcamEnable stagf_fix_disable CQE_fifo_perr_set2 ULP_TX_FPGA_CMD_5 ocspi_par_error oespi3_Tx_framing_error MPS_VF_RX_CTL_95_64 MPS_TX_PAUSE_DURATION_BUF_GRP3 MPS_RX_PG_RSV5 PGLL PPM0 NV_DROP MPS_RX_SE_CNT_IN2 MPS_PORT_RX_CTL MPS_PORT_RX_SPARE MPS_TX_LPBK_DROP_BP_CTL_CH1 FullCh1 SizePt1 MPS_TX_DEBUG_REG_TX2MAC_32 FullPt3 MaxPktCnt TfCaptureMax MPS_TRC_PERR_INJECT MPS_TRC_INT_CAUSE MPS_STAT_PERR_ENABLE_SRAM MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H MPS_PORT_STAT_TX_PORT_512B_1023B_H MPS_PORT_STAT_TX_PORT_PPP5_L HashSRAM CPL_INTR_ENABLE sge_framing_error SlvFifoParEn AuxAddr0Val RDMA_0b_wr_opcode ENABLE_DDPCF_0 CAUSE_DDPMF_1 ULP_RX_CTX_ACC_CH0 SOP_CNT_MR1 VFID LE LE_HASH_MASK_CMP_IPV4 max_pkt_size MPS2CIM_CNT CIM2BMC_CNT BUS_STATE_CIM_OUT PHYMgmtStatus NCSI_MACB_LENGTH_ERR ARPIPAddr PartRef Preamble HSSPRT_READY BEAN_Int RXCPHSUPIN RXBPRBSSYNC XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_2 TXREQ_C0 PRBS_CHK_RST FSM_TR_FAIL Training SPCEN DFEPWR D11SN DACAN XGMAC_PORT_HSS_RXA_DACA_MIN H4OSN XGMAC_PORT_HSS_RXB_DFE_H4 XGMAC_PORT_HSS_RXB_INTERNAL_STATUS XGMAC_PORT_HSS_RXC_CFG_MODE XGMAC_PORT_HSS_RXC_PH_ROTATOR_STATIC_PH_OFFSET XGMAC_PORT_HSS_RXD_VGA_CTRL3 XGMAC_PORT_HSS_LOFREQ_OVR LFSEL XGMAC_PORT_HSS_RX_DAC_DPC perr_idma_switch_output_fifo0 SGE_INT_ENABLE5 SGE_DBFIFO_STATUS2 IngPackBoundary Throttle_Threshold_hp debug_CIM_EOP0_cnt debug_M_rd_req_outstanding_CMARB SGE_DEBUG_DATA_HIGH_INDEX_9 debug_st_dbp_thread1_main PIORspRdTagErr BAR2RdErr PCIE_VC1_CDTS0 PCIE_CORE_SYMBOL_TIMER_FILTER_MASK1 SKP_Interval VC0_PTLP_Queue_Mode Convergence_WinDepth RspSOPCnt NPD_CreditsAvailVC1 LnE_RxStateDone GPIO19_Out_Val GPIO17_ACT_LOW DBG_T5_STATIC_M_PLL_CONF1 T5_STATIC_M_PLL_MULT T5_STATIC_U_PLL_LOCKSEL T5_STATIC_KX_PLL_BYPASS T5_STATIC_KX_PLL_BGOFFSET STATIC_C_DFS_FFTUNE5 GPIO12_PS_En GPIO6_PS_En DBG_EFUSE_BYTE56_59 MA_EXT_MEMORY0_BAR FUTURE_EXPANSION MA_HOST_MEMORY_RDDATA_CNT0 CLIENT CL6_WR_CMD_TO_EN CL12_WR_DATA_TO_EN CL8_WR_CMD_TO_ERROR MA_READ_TIMEOUT_ERROR_ENABLE CL2_RD_DATA_TO_ERROR MA_BKP_CNT RD_WIN CL8_IF_PAR_ERROR ibq_rra_dsbl emsg_more_info fso_hdr_sram_perr_set0 MPS_TX_PAUSE_DURATION_BUF_GRP_TH7 TxOutMAC2_CGEN TxSchLpbk2_CGEN Terminate_with_err ULP_RX_T10_CRC_ENDIAN_SWITCHING Status ACCNTFULLEN LE_DB_ACT_CNT_IPV4_TCAM SmuxTxSel AET1Reset MAC_PORT_LED_CFG Perr_crc_ram RXBQUIET T5RXBPRBSRST RXBQUIET_STATUS RXBREFRESH_STATUS TX_ADDR_INS WAN_MODE MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTEDHI MAC_PORT_IFOUTUCASTPKTS MAC_PORT_ETHERSTATSPKTS65TO127OCTETS MAC_PORT_AMACCONTROLFRAMESRECEIVED MAC_PORT_MTIP_ACT_CTL_SEG PMD_PMA Lane13 AMLOCK6 AMLOCK19 AMLOCK17 MAC_PORT_MTIP_PCS_BIP_ERR_CNT_5 MAC_PORT_MTIP_PCS_LANE_MAP_0 MAC_PORT_BEAN_ABILITY_1 ACK2 MAC_PORT_BEAN_CTL_LANE1 MAC_PORT_LP_BEAN_XNP_1_LANE3 MAC_PORT_FEC_KR_LD_COEFF fec_ind_ability MAC_PORT_FEC_STATUS T5_RXREQ_C0 MAC_PORT_AE_REG_MODE T5_AE1_RXSTAT_C2 MAC_PORT_AE_FSM_STATE_1 MAC_PORT_AE_RX_COEF_STAT_3 T5_AE3_RXSTAT_C1 MAC_PORT_AE_TX_COEF_STAT_3 MAC_PORT_AE_RX_SIGDET MAC_PORT_AET_STATUS_0 MAVDHI MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_0 AEPOL RSTEP LPIDCLK MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_2 MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C2_INIT_EXTENDED FERRST H1E2 T5BER3VAL ACJPDP MAC_PORT_RX_LINKB_DFE_CONTROL MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS MAC_PORT_RX_LINKC_RECEIVER_TEST_CONTROL MAC_PORT_RX_LINKC_RECEIVER_ANALOG_CONTROL_SWITCH MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_1 MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_2 MAC_PORT_RX_LINK_BCST_DFE_H4 MC_DDRPHY_PC_INIT_CAL_MASK ERROR_INITIAL_COARSE_WR_MASK MC_DDRPHY_PC_INIT_CAL_STATUS ADDR_MIRROR_RP3_PRI DI_ADR8_ADR9 DI_ADR12_ADR13 MC_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET MRS_CMD_DATA_N2 DATA_BIT_DISABLE_16_23 ATEST_MUX_CTL0 QUAD2_CLK20_BIT6 MC_DDRPHY_DP18_RX_PEAK_AMP SxPODVREF DQSCLK_ROT_CLK_N1_N3 DQSCLK_SELECT1 RDCLK_SELECT2 MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR LEADING_EDGE_FOUND COARSE_PATTERN_ERR_N3_MASK WL_ERR_CLK18_MASK WR_ERR_CLK22_MASK MC_DDRPHY_DP18_IO_TX_PFET_TERM MEMINTD06_POS MEMINTD13_POS HS_PROBE_B_SEL MC_DDRPHY_SEQ_ODT_RD_CONFIG3 TWLO_TWLOE FW_WR_RD WRCLK_CAL_DONE ADR12_2_Populated ADR12_3_Populated MC_UPCTL_CMDTSTATEN self_refresh MC_UPCTL_ECCCLR MC_UPCTL_DTUWD2 MC_UPCTL_DFITPHYUPDTYPE2 MC_UPCTL_DFIUPDCFG MC_UPCTL_DFITREFMSKI MC_UPCTL_DFITRSTAT0 MC_UPCTL_DFITRWRLVLDELAY0 dfitrcmd_en CTL_RST_N MC_CE_ERR_DATA_RDATA fatal_off_wdenq fl_enq_cnt debug_idma1_idma2imsg_cmp_out_srdy Req_LnB_RxPwrState KDB_PF_Len LnP_STAT LnN_CMD PCIE_VF_MSIX_EN_4 STATIC_M_PLL_LFTUNE_32_40 STATIC_PHY1RecRst_ STATIC_SWMC1Rst_ STATIC_C_PLL_FRAMESTOP STATIC_U_PLL_LOCKSEL STATIC_KX_PLL_BGOFFSET DBG_STATIC_KX_PLL_CONF2 CXoffOverride push_middle MPS_VF_RX_CTL_223_192 PROT_TYPE TTL_CHK_EN_IPV4 MPS_RX_CNT_NVGRE_PKT_MAC1 MPS_RX_CNT_VXLAN_PKT_MAC1 MPS_RX_CNT_TNL_ERR_PKT_TO_TP0 MPS_PORT_RX_VF_MAP6 MPS_CLS_MATCH_CNT_BCAST MPS_CLS_REQUEST_TRACE_MAC_DA_H ClsTrcDIPHit ClsTrcMultiListen MPS_CLS_DIPIPV6MASK_0_TABLE MPS_CLS_DIPIPV6MASK_1_TABLE MPS_CLS_TCAM_DATA1 zbyte_fix_disable ULP_RX_TLS_KEY_ULIMIT CHK_FUL_TUP_ZERO CLCAM_INIT HASH_ACTV_SUCC CTcamInvldEnt PipelineErr MAC_PORT_AEC_ADD_CTL_STAT_1 Perr_rx17_pcs100g Perr_rx5_pcs100g Perr_tx3_fec40g Perr_rx2_pcs40g MAC_PORT_MTIP_1G10G_HASHTABLE_LOAD MAC_PORT_MTIP_1G10G_STATUS CL6_QUANTA_THRESH MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS MAC_PORT_MTIP_1G10G_TX_ETHERSTATSDROPEVENTS MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS512TO1023OCTETSHI Speed_Sel MAC_PORT_MTIP_KR_PCS_DEVICES_IN_PACKAGELO 10GBASE_x_Capable PRBS9_TX_Tst_Pttrn_En Vendor_specific_device Latched_bl_lk Block_Lock Latched_block_lock Latched_high_BER MAC_PORT_MTIP_CR4_LANE_10_MAPPING MAC_PORT_MTIP_RS_FEC_SYMBLERR1_HI MAC_PORT_AET_LIMITS1 FRCCAL_COMP MAC_PORT_IMPEDENCE_CALIBRATION_STATUS_3 AS1X1 MAC_PORT_TX_LINKA_TRANSMIT_AE_C0_LIMIT_EXTENDED MAC_PORT_TX_LINKB_TRANSMIT_AE_C1_INIT2_EXTENDED MAC_PORT_TX_LINKC_TRANSMIT_AE_C3_INIT_EXTENDED MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_1X_OVERRIDE CDROVREN H1OX DPCFRZ LFRC FPHSLOCK DCDLOCK MAC_PORT_RX_LINKA_RECEIVER_DCC_CONTROL QCCLOCK MAC_PORT_RX_LINKB_RECEIVER_DACA_MIN MAC_PORT_RX_LINKC_DFE_H1H2H3_LOCAL_OFFSET_VALUE MAC_PORT_RX_LINK_BCST_CDR_ANALOG_SWITCH MAC_PORT_RX_LINK_BCST_DFE_OFFSET_VALUE MAC_PORT_RX_LINK_BCST_H_COEFFICIENBT_BIST MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2 DQS_ALIGN_SM PREFILL_COMPLETE MC_LMC_MCOPT2 WR_MID_TH MC_P_BIST_USER_WMASK0 MRspData EDC_H_DBG_EDRAM1_WR_REQ_CNT OP_MODE HMA_REG2_MASK HMA_REG3_MASK loadboot prio dip frag unknown context type "%s"; known types are egress, ingress, fl, and cong. PIDX: ISCSICoalescing: DCAFLEn: SP_NS: Cache_Lock : tracer: no arguments. "%s" is neither an index nor a tracer subcommand. @%u
missing scheduling sub-command pkts channel rxq UNKNOWN ESC_2_STATE l2t_ix Peer advertised window Receive re-order fragment 0 length rq_MSN Log size RQ (the size in hardware is rounded up to a power of 2) TF_DDP_MAIN_UNUSED Insert_VLAN max_rt %-2u, rxtshift %u, keepalive %u
core_fin %u, tx_hdr_offset %u
nagle %u, ssws_disable %u, turbo %u, rcv_wnd %u >> snd_scale %u == %u, recv_scaleflag = %u
L_valid %u, rdmap opcode %u
NAT_flag_check Hit_frame_cnt rx_tls_seq TLS/SSL sequence number IgrAllCPLtoFL HostPageSizePF3 QueuesPerPagePF7 perr_imsg_hint_fifo perr_mc_egr_ctxt perr_pc_chpi_rsp1 perr_isw_gts_fifo perr_egr_ctxt_cache SGE_FL_BUFFER_SIZE0 SGE_FL_BUFFER_SIZE3 SGE_FL_BUFFER_SIZE10 Threshold_3 SGE_PD_RSP_CREDIT01 SGE_DEBUG_DATA_HIGH SGE_LA_RDDATA_0 SGE_LA_RESERVED_0 MSIDataPerr PCIE_CMD_STAT PCIE_DBG_INDIR_DATA_3 PCIE_CMD_RSP_FREE PCIE_RSP_ERR_STAT_2 OC1T OTDD TPCI RLCS PCIE_CORE_ENDPOINT_ERROR_SEVERITY PTOI INTXType PCIE_PF_EXPROM_OFST DBG_DBG1_EN GPIO1_Out_Val PCIE_OCLK_En GPIO11_ACT_LOW GPIO10_ACT_LOW GPIO6_ACT_LOW DBG_EFUSE_BYTE4_7 PVT_REG_TERMN_A REG_IN_DRVN_A REG_OUT_TERMP_A rank1_odt_read_nsel dtu_error_b7 dtu_err_b1 MC_PCTL_DTUNE dtu_allbits_4 MC_PCTL_TOGCNT100N dtu_wr_byte3 dtu_rd_byte4 MC_PCTL_PHYTUPDWAIT MC_PVT_REG_OUT_TERMN FIFOR_PAR_CAUSE MA_ULPTXRX_DEBUG_CNT EDRAM0_BASE EDRAM1_BASE EXT_MEM_SIZE BRC_MODE MEM_WRAP_INT_CAUSE MA_SGE_PCIE_COHERANCY_CTRL BlkWrFlashInt CIM_DEBUG_ADDR_ILLEGAL CrcPassPrt1 EChecksumInsertIP PingDrop DontFragment RxPoolSize EnableOnFlyPDU HearbeatDACK DisableFINOldData EnableUrgDdpOff EnableRxPktTmstpRss TimerBackoffIndex0 EnableTnlCngFifo TunnelCngDrop3 TxPDUSizeAdj EnableESnd TP_RXT_MIN TP_RXT_MAX PerShiftMax Port0MTUValue TP_CCTRL_TABLE SYN4tupEnIpv4 KeyWrEn RstChn3 CTpInTcpOpFifoPerr PduFbkFifoPerr TimerSeparator TP_RX_SCHED RxModXoff1 TP_TX_ORATE ULP_TX_FPGA_CMD_9 SOP_CNT_CIM2ULP ULP_TX_LA_RESERVED_10 prefetch_enable ch3_output oespi1_Rx_framing_error ClsIntEnb MPS_DEBUG_DATA_REG_H MPS_BUILD_REVISION RegHalted CTL_P2 MPS_RX_PG_RSV1 PSMX MPS_PKD_MEM_DATA0 IN_DBG_CHNL MPS_TX_INT_ENABLE SECNTERR ErrPt1 MPS_STAT_PERR_INJECT MPS_PORT_STAT_LB_PORT_1519B_MAX_L PortMap MPS_CLS_PERR_INJECT MPS_CLS_PL_TEST_DATA_H Cls_Index SlvRxPecErrIntEn MstRxInjDataErr SMB_COMMAND_CODE5 Op EDC1PartCGEn ULP_RX_ISCSI_TAGMASK PERR_ENABLE_AF_1 PERR_ENABLE_TPTCF_0 EOP_CNT_AL0 PIORst SYNMode FilterHit DBGICMDERASE TCAM DBGIRspMsg LE_REQ_DEBUG_LA_DATA NCSI_SE_CNT_MPS ExtClass MCastHashEn NCSI_MACB_INT_DIS NCSI_MACB_RX_OVERRUN_ERR MagicPktEn rxrst MagicDetected TXCTS TXBTS HSSTXACMODE TXDPRBSRST EnTestModeWr XGMAC_PORT_XGM_STAT_TX_BYTE_HIGH XGMAC_PORT_XGM_STAT_TX_256_511B_FRAMES XGMAC_PORT_XGM_STAT_TX_1519_MAXB_FRAMES restart_an RXREQ_C0 OCOEF COEFRST XGMAC_PORT_HSS_TXA_PWR_DAC SSCENABLE FSTLCK SMODE D00AMP XGMAC_PORT_HSS_RXA_DACAP_DAC_AN_OFFSET EMPAT H2OMAG H3OMAG XGMAC_PORT_HSS_RXB_CFG_MODE XGMAC_PORT_HSS_RXB_DFE_DATA_EDGE_SAMPLE XGMAC_PORT_HSS_RXB_VGA_CTRL3 XGMAC_PORT_HSS_TXC_8023AP_AE_STATUS XGMAC_PORT_HSS_TXD_TAP0_IDAC_APP XGMAC_PORT_HSS_RXC_ADAC_CTRL XGMAC_PORT_HSS_TX_DRIVER_MODE XGMAC_PORT_HSS_TX_TDM_BIASGEN_STANDBY_TIMER XGMAC_PORT_HSS_TX_TAP1_IDAC_APP XGMAC_PORT_HSS_TX_EXT_ADDR perr_uP_Data VFIFO_Enable IDMA0_Sleep_Status EDMA2_Sleep_Req dbp_fetch_threshold_hp debug_CIM_SOP0_cnt debug_T_Rx_SOP1_cnt debug_UD_Rx_EOP0_cnt debug_PD_RdRsp_EOP0_cnt debug_PC_ReqAFull_d debug_st_idma0_flm_req debug_st_edma3_align EnableL2EntryInL1 PCIE_PF_INT_CFG2 PCIE_VF_INT_CFG2 PCIE_CORE_VENDOR_SPECIFIC_DLLP Insert_TxSkew VC1_WRR RdSeqNumUpdCnt RdSOPCnt PCIE_DMA_STAT3 VPD_Dynamic_CGEN CMD_Dynamic_CGEN MA_ReqTagQPerr TimeoutLogEn ByteLen Reason Lane0LF Clk_en_on_dbg1 T5_STATIC_M_PLL_STOPCLKA T5_STATIC_C_PLL_SLEEP T5_STATIC_C_PLL_BYPASS T5_STATIC_U_PLL_PREDIV GPIO19_PE_En GPIO0_PE_En MA_PMRX_RDDATA_CNT MA_EDRAM1_WRDATA_CNT1 CL7_WR_DATA_TO_EN CL6_WR_DATA_TO_EN CL12_WR_CMD_TO_ERROR CL10_RD_CMD_TO_EN CL4_IF_PAR_EN CL5_IF_PAR_ERROR VLANExtEnPort1 DisablePDUAck SOF_3 ULP_TX_FC_EOF ULP_TX_ASIC_DEBUG_CTRL ULP_TX_ASIC_DEBUG_4 MPS_TX_PAUSE_RETRANS_BUF_GRP_TH2 PETYPE2 PUDPORT2 MPS_RX_PAUSE_GEN_TH_1_3 TxInCh1_CGEN MPS_TRC_FILTER2_RSS_HASH EDC1_Part_CGEn T10Diff_DataPath_CGEN Rd_or_Term_msn_check_enable tx_dff_seg0 HSSREFCLKVALIDB pma_tx_refresh PCSSEG2_CGEN MAC_PORT_TX_TS_ID HSS_TIMER MAC_PORT_MTIP_MAC_CREDIT_TRIGGER MAC_PORT_ETHERSTATSPKTSHI MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7 SGMII_REM_FAULT HD rx_link_status TestPatSel AMLOCK11 MAC_PORT_MTIP_PCS_LANE_MAP_14 MAC_PORT_MTIP_PCS_LANE_MAP_16 MP 40GCR4 MAC_PORT_BEAN_REM_ABILITY_0_LANE1 MAC_PORT_BEAN_REM_ABILITY_1_LANE1 MAC_PORT_BEAN_XNP_1_LANE2 MAC_PORT_BEAN_REM_ABILITY_0_LANE3 MAC_PORT_AE_RX_COEF_STAT_1 MAC_PORT_AE_TX_COEF_REQ_2 T5_AE3_RXSTAT_RDY EN_AI_C1 BOOT_LUT6 MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_2 MAC_PORT_RESISTOR_CALIBRATION_STATUS_1 SOFTRESET MAC_PORT_PLLB_MACRO_TEST_CONTROL_4 TPGMD T5DRVHIZ MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_APPLIED MAINSC OBS MAC_PORT_TX_LINKB_TRANSMIT_DCC_APPLIED MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED MAC_PORT_TX_LINK_BCST_TRANSMIT_CONFIGURATION_MODE T5_RX_LINKEN SSCEN H1E4 T5TOOFAST H5OGS H7GS MAC_PORT_RX_LINKA_DFE_H12 MAC_PORT_RX_LINKD_DFE_E0_AND_E1_OFFSET MAC_PORT_RX_LINK_BCST_RECEIVER_CONFIGURATION_MODE MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_3 MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_3 MAC_PORT_RX_LINK_BCST_RECEIVER_DACAP_AND_DACAN PER_ENA_SYSCLK_ALIGN ADDR_MIRROR_RP0_SEC ADDR_MIRROR_RP1_SEC DI_ADR2_ADR3 MC_ADR_DDRPHY_ADR_DELAY6 SLICE_SEL_REG_BITS14_15 POST_CURSOR3 SLEW_CTL_SEL_BITS2_3 SLEW_CTL_SEL_BITS10_11 MC_DDRPHY_ADR_POWERDOWN_1 SYSCLK_CLK_GATE MRS_CMD_DATA_N0 QUAD0_CLK18_BIT4 MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR EN_TERM_N_WR_FFE MC_DDRPHY_DP18_RD_DIA_CONFIG2 EARLY_REQ_ERROR MC_DDRPHY_SEQ_ERROR_MASK0 ODT_RD_VALUES_x2 MRS_CMD_DQ_ON MC_UPCTL_DTUWD3 dfi_rdlvl_mode EDC_H_INT_CAUSE FlmThresh debug_idma1_idma2imsg_fifo_in_drdy thread_cmdop Req_LnH_RxPwrState Cur_LnG_RxPwrState Cur_LnF_RxPwrState KDB_VF_Len PCIE_KDOORBELL_GTS_VF_OFFSET LnP_CMD Lane11LF PON_RST_STATE_flag STATIC_KR_PLL_CCALBANDSEL DBG_CUST_EFUSE_BYTE36_39 EGreDropEn SrqTablePerr TlsDisableCFuse shove_last TX_PORT_STATS_MODE FULL_FRAME_MODE MPS_RX_LPBK_BG_PG_CNT0 MPS_RX_CNT_GENEVE_PKT_TO_TP0 MPS_CLS_TCAM_RDATA2_REQ_ID1 TlsPpUlimit MTCAM_INIT TCAMDEEPSLEEP_STAT TCAM_ACTV_HIT LE_DB_PSV_FILTER_MASK_FLT_IPV6 an_reset_sd_rx_clk mac40g100g_reset_rxclk an_gate_sd_rx_clk pcs40g_gate_sd_rx_clk mac40g100g_ts_clk MAC_PORT_AEC_XGMII_TIMER_LO_40G LCK_FSM_CUR_STATE mac1g10g_tx_loc_fault fpga_lock an_select sgmii_gmii_col Perr_rx11_pcs100g Perr_tx0_fec40g Perr_rx_pcs10g_lpbk HSSREFDIVB RXAERROFLOW MAC_PORT_MTIP_1G10G_SCRATCH MAC_PORT_MTIP_1G10G_TX_APAUSEMACCTRLFRAMESHI MAC_PORT_MTIP_1G10G_ETHERSTATSPKTS1519TOTX_MTUHI MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_0HI MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_7 Speed_SEL1 10GBASE_R_RX_Link_Status PRBS31_RX_Tst_Pttrn_En Receive_fault Latched_hg_br LANE_0_BLK_LCK MAC_PORT_MTIP_KR4_TX_LANE_THRESH BASE_R_FEC_Ability SET_WAIT_TIMER SASMODE MAC_PORT_TX_LINKA_TRANSMIT_2X_SEGMENT_APPLIED MAC_PORT_TX_LINKA_TRANSMIT_TAP_SIGN_OVERRIDE OS1X5 ERRORN C0INIT1 MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE MAC_PORT_TX_LINKB_TRANSMIT_AE_C2_INIT_EXTENDED MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_7_6 MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_2X_OVERRIDE MAC_PORT_TX_LINKC_TRANSMIT_AE_C2_INIT2_EXTENDED MAC_PORT_TX_LINKD_TRANSMIT_1X_SEGMENT_APPLIED MAC_PORT_TX_LINKD_TRANSMIT_AE_V2_LIMIT_EXTENDED MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED SAVEADAC ACCPLREF FRPTCALF FINTCALGS ACCRD LGIDLE SMQ H9SN TSTCMP MAC_PORT_RX_LINKC_DFE_TAP_CONTROL MAC_PORT_RX_LINKD_DFE_H1H2H3_LOCAL_OFFSET_VALUE MC_DDRPHY_AD32S_MCCLK_WRCLK_PR_STATIC_OFFSET MC_DDRPHY_AD32S_SLEW_CAL_CNTL MRS_CMD_SPACE MT_GLOBAL_PHY_OFFSET BG1 MC_LMC_INITSEQ12 RTT_WR TCCD_L EDC_H_DBG_MA_RDATA_INTF EDC_H_DBG_BIST_WR_EXP_DAT_CYC_CNT dead_cycle0_pre_ref_rmw HMA_TLB_ACCESS HMA_EXIT_TF exit invalid command "%s" mc1 VFvld:PF:VF EthType "vnic_id" and "ovlan" are mutually exclusive. nat_sip all unknown nat type "%s"; known types are dip, dip-dp, dip-dp-sip, dip-dp-sp, sip-sp, dip-sip-sp, and all WRLengthKnown: Inflight: incorrect number of arguments. CHELSIO_T4_GET_I2C snap length: %u, min length: %u
packets captured %smatch filter
argument '%s' isn't tx<n> or rx<n> /sbin/ifconfig packet Failed to open pcap device SYN_RCVD HighSpeed IWARP TF_CCTRL_RFR Scaling for send window (0-14). Note: this is reverse of common definition. snd_rec_raw Receive credits (advertised to peer in receive window) Offset of receive fragment 1 start sequence from rcv_nxt DW aligned starting addres of RQ RDMAP_opcode tx_flush OPT_0_MAX_SEG Loopback_TX_Channel snd_cwnd %-5u snd_ssthresh %u snd_rec %u
t_dupacks %u, dupack_count_odd %u, fast_recovery %u
Tag for TLS crypto state perr_eswitch_fifo2 perr_pc_dbp1 perr_dbp_hint_fifo err_flm_idma1 ForceVFPF0DBtoLP SGE_DROPPED_DOORBELL Critical_Time SGE_STAT_MATCH SGE_LA_WRPTR_11 RxCplPerr DRspPerr CCntPerr MSIXAddrLPerr PopH Bus PCIE_HMA_RSP_FREE PCIE_MSI_EN_0 SRD7 USBP PCIE_CORE_SYSTEM_BUS_BURST_SIZE_CONFIGURATION IP1D IC3T TPCP TCAS PLUS PINC RCTS CRSS PC2S DBG_PLL_OCLK_PAD_EN DBG_TRACE1_CONF_COMPREG1 DBG_TRACE1_CONF_MASKREG0 RD_ADDR0 MC_PCTL_MCFG MC_PCTL_DQSECFG dv_alat dtu_rd_missing MC_PCTL_TRP MC_PCTL_TRC run_dtu dtu_wr_byte8 dtu_rd_byte0 ACOEN WLDEC MC_DDR3PHYAC_OCSR MC_DDR3PHYDATX8_RDBDR0 MC_CORE_PCTL_STAT MA_CLIENT5_RD_LATENCY_THRESHOLD CL6_PAR_WRQUEUE_ERROR_EN CL3_PAR_RDQUEUE_ERROR_EN EDC_BIST_USER_WDATA0 CIM_HOST_UPACC_INT_ENABLE TimeOutIntEn BlkWrEEPROMIntEn SglWrCtlInt SglRdFlashInt CIM_MEM_ZONE4_LEN EEthernet TP_OUT_CONFIG EPktDistChn3 DisableSYNData TsmpMode DropErrorAny KeyMode VfWrEn RstChn0 UpdChn1 TimerMode TP_TX_MOD_QUEUE_WEIGHT1 TX_MOD_RATE_LIMIT_TICK CmRcfOpPerr CmRcfDataPerr DbExtPerr CTpOutIpFifoPerr ULP_TX_CPL_ERR_MASK_L Ch3Size1 ULP_TX_ERR_CNT_CH2 ULP_TX_LA_RDDATA_1 ULP_TX_LA_RDDATA_7 ch1_output PM_RX_STAT_CONFIG oespi1_Tx_framing_error TxInt RxInt LPBK_EN MPS_TOP_SPARE TopSpare SgeSendEn MPS_PORT_TX_PAUSE_DEST_H CMPRS MPS_RX_PG_RSV6 MPS_RX_PG_SHR1 INT_ERR_INT LPBK_WT MPS_PGD_MEM_DATA ERR OVLAN_ETYPE SOPCh0 FullCh3 TfEn MPS_TRC_INT_ENABLE MPS_PORT_STAT_TX_PORT_PPP0_H MPS_PORT_STAT_LB_PORT_512B_1023B_L MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L MPS_CLS_INT_CAUSE Cls_VF_Vld SMB_SLV_CTL_STS SlvDoneInt ArpAddrVal CAUSE_DDPMF_0 ULP_RX_ISCSI_LLIMIT TddpUlimit MPS PL_PF_INT_ENABLE PL_RST MAP0 LimitAddr PL_FLR_PF_STATUS FTINDX LIP0 Miss DBGIRspMsgVld LE_REQ_DEBUG_LA_WRPTR NCSI_INT_CAUSE NonStdPreOK RxBCastDis NCSI_MACB_SPECIFIC_4_HIGH XGMAC_PORT_LED_CFG tx_sop_count XGMAC_PORT_MAGIC_MACID_LO RxSop XGMAC_PORT_CHECKIN XAUI_Link_Fail XGMAC_PORT_XGM_INT_EN XGMAC_PORT_XGM_STAT_TX_64B_FRAMES XGMAC_PORT_XGM_STAT_RX_64B_FRAMES XGMAC_PORT_XGM_STAT_RX_LENGTH_ERR_FRAMES XGMAC_PORT_AN_CONTROL XGMAC_PORT_AN_LP_NP_LOWER RXSTAT_C0 XGMAC_PORT_AE_KR_CTRL XGMAC_PORT_HSS_TXA_EXT_ADDR_DATA XGMAC_PORT_HSS_RXA_VGA_CTRL2 MINAMP H5EMAG XGMAC_PORT_HSS_RXB_PH_ROTATOR_CTRL XGMAC_PORT_HSS_TXD_PWR XGMAC_PORT_HSS_RXD_TEST_CTRL XGMAC_PORT_HSS_RXD_DFE_AMP_SAMPLE XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_2 CMETH RXARST XGMAC_PORT_HSS_TX_TAP0_IDAC_OVR Type dbfifo_fl_int_low perr_pointer_hdr_fifo0 SGE_CHANGESET SGE_DEBUG_DATA_HIGH_INDEX_0 debug_U_Tx_SOP3_cnt debug_PD_RdReq_SOP2_cnt debug_st_flm_idma1_cache debug_flm_idma0_cache_data_active debug_flm_idma0_ctxt_data_active debug_CPLSW_EOP1_cnt debug_st_idma1_flm_req PCIE_VF_MSIX_EN_1 Ack_Latency_Timer_Limit RxQueue_Not_Empty SeqChkDis GPIO17_IN T5_STATIC_MPLL_REFCLK_SEL T5_STATIC_KR_PLL_N2 GPIO9_PE_En GPIO11_PS_En EXT_MEM0_ENABLE EXT_MEM1_BASE MA_CIM_RDDATA_CNT CL11_WR_CMD_TO_EN CL9_WR_CMD_TO_EN CL0_WR_CMD_TO_EN CL0_WR_CMD_TO_ERROR CL7_RD_DATA_TO_ERROR WRT_EN ByteCountReno cim2ulp_data_perr_set MPS_RX_PAUSE_GEN_TH_1_2 MPS_RX_MAC_CLS_DROP_CNT1 MPS_PORT_RX_PTP_RSS_HASH TxSchMAC1_CGEN MPS_STAT_STOP_UPD_RX_VF_32_63 SMB_CTL_STATUS TDDP_CGEN MAC3 MapMAC1 TCAMDEEPSLEEP1_STAT ActCntIPv6zero LE_DB_SECOND_CMP_HASH_MASK_IPV4 PTP_TIMER HSSVCOSELB HSSCALSSTN MAC_PORT_EEE_STATUS eee_tx_10g_state eee_rx_1g_state HSS_CTL MAC_PORT_EEE_RX_CTL MAC_PORT_EEE_TX_10G_QUIET_TIMER CYCLE1 MAC_PORT_MTIP_TX_FIFO_ALMOST_F_E MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETS MAC_PORT_ETHERSTATSJABBERSHI MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1HI MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5HI SGMII_PCS_ENABLE MAC_PORT_MTIP_MDIO_COMMAND 100G 10GBASE_W MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS2 MAC_PORT_MTIP_PCS_BIP_ERR_CNT_6 MAC_PORT_BEAN_XNP_0_LANE1 MAC_PORT_LP_BEAN_XNP_1_LANE1 MAC_PORT_BEAN_XNP_0_LANE2 startup_status MAC_PORT_FEC_NCERR_CNT_1 T5_TXSTAT_C2 MAC_PORT_AE_TX_DIS_1 PCKSEL MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_2 T5_TX_PLLSEL DCCASIGN MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_OVERRIDE_CONTROL MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C1_INIT_EXTENDED MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C1_INIT_EXTENDED MAC_PORT_TX_LINK_BCST_TRANSMIT_AMPLITUDE MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_APPLIED MAC_PORT_RX_LINKA_PHASE_ROTATOR_CONTROL OFFSN_ReadOnly MINWDTH H3OSN_ReadWrite H8MAG H12SN_ReadOnly MAC_PORT_RX_LINKB_RECEIVER_DACA_MIN_AND_DACAZ MAC_PORT_RX_LINKB_DFE_OFFSET_EVN3_EVN4 MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_2 MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_1 MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS RANK_PAIR2_PRI_V PER_ZCAL_ENA_RANK RC_ERROR ENABLE_ZCAL ENA_WRITE_CTR DI_ADR0_ADR1 DADR_TEST_MODE ADR_TEST_RESET MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN2 MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN0 SLEW_CTL_SEL_BITS6_7 SLEW_CAL_ENABLE RD_DELAY_BITS0_6 MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR MC_DDRPHY_DP18_DRIFT_LIMITS LEADING_EDGE_NOT_FOUND_1 TRAILING_EDGE_NOT_FOUND_16_23 INCOMPLETE_RD_CAL_N0 DRIFT_ERROR_MASK WL_ERR_CLK18_ST BIT_CENTERED S0INSDLYTAP MC_DDRPHY_SEQ_RESERVED_ADDR1 TWLDQSEN_CYCLES MC_DDRPHY_WC_ERROR_MASK0 DP18_8_Populated ADR16_2_Populated MC_DDRPHY_APB_ATEST_MUX_SEL nfifo_nif1_dis MC_UPCTL_MRRCFG0 MC_UPCTL_PPCFG MC_UPCTL_MSTAT MC_UPCTL_DTUPRD3 MC_UPCTL_TINIT MC_UPCTL_TRAS MC_UPCTL_DFITCTRLUPDMIN MC_UPCTL_DFITRCFG0 MC_UPCTL_DFITDRAMCLKDIS MC_P_DEBUG_CNT EDC_H_BIST_USER_WDATA1 EDC_H_PAR_ENABLE dbp_tbuf_full fatal_enq_ctl_rdy tp_ch_cng thread_qid Req_LnI_RxStateReq PCIE_PHY_CURRXPWR1 Cur_LnO_RxPwrState PCIE_PHY_FS_LF6 STATIC_M_PLL_DCO_BYPASS STATIC_M_PLL_LOCKSEL DBG_STATIC_C_PLL_CONF3 STATIC_U_PLL_STARTUP EFUSE_OPER_DONE CRxPktEnc EcnThresh sge_fifo_perr_set2 DROP_INVLD_MC_CH1 MPS_FPGA_BIST_CFG_P0 MPS_RX_LPBK_BG_PG_CNT1 NVGRE_EN TTL_IPV6 ORG_CHK_EN MPS_RX_CNT_VXLAN_PKT_TO_TP1 MPS_PORT_RX_PRS_DEBUG_FLAG_MAC OUT_TH MPS_CLS_MATCH_CNT_HASH ULP_RX_TLS_PP_ULIMIT LE_DB_MIN_NUM_ACTV_TCAM_ENTRIES MaifwrIntPerr SrvSramAccFail LE_DB_DBGI_REQ_CMD LE_DB_PSV_FILTER_MASK_TUP_IPV6 macclk_sel PCS1G_RESET AEC_SYS_LANE_SELECT_1 MAC_PORT_MAC_CTRL_RW Perr_tx1_pcs40g HSSPLLDIV2B HSSPLLDIV2A MAC_PORT_MTIP_1G10G_RX_IFINUCASTPKTS MAC_PORT_MTIP_1G10G_AMACCONTROLFRAMESRECEIVED MAC_PORT_MTIP_1G10G_TX_FRAMESOK MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS128TO255OCTETSHI MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_5HI 10G_capable MAC_PORT_MTIP_KR4_STATUS_2 LANE_1_BLK_LCK LANE_3_ALIGN_MRKR_LCK MAC_PORT_MTIP_CR4_BASE_R_STATUS_2 MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_12 MAC_PORT_MTIP_RS_FEC_CCW_LO fec_align_status_ll MAC_PORT_MTIP_FEC1_CERR_CNT_0 T5_AE0_RXSTAT_C3 EN_AI_N0 MAC_PORT_AET_STATUS_23 MAC_PORT_IMPEDENCE_CALIBRATION_STATUS_2 MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_4X_OVERRIDE MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_5 BSOUTP MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_7_6 MAC_PORT_TX_LINKD_TRANSMIT_TAP_SIGN_OVERRIDE MAC_PORT_TX_LINKD_TRANSMIT_AE_C1_LIMIT_EXTENDED MAC_PORT_TX_LINKD_TRANSMIT_AE_VM_LIMIT_EXTENDED MAC_PORT_TX_LINK_BCST_TRANSMIT_2X_SEGMENT_APPLIED PMOFFTIME OVRCAP VIEWSCAN T5IQCMP FDCD MAC_PORT_RX_LINKA_H_COEFFICIENBT_BIST ACCIND FCLKALDYN H14MAG ACISRCCMP SNAPEN MAC_PORT_RX_LINKB_RECEIVER_AC_COUPLING_CONTROL MAC_PORT_RX_LINKC_RECEIVER_INTERNAL_STATUS_2 MAC_PORT_RX_LINK_BCST_DFE_TAP_CONTROL MC_DDRPHY_DP18_WRCLK_STATUS QUAD3_CAVEAT CALIBRATE_BIT MC_DDRPHY_APB_MTCTL_REG0 ECC_EN MC_LMC_CMD5 T_WTWO WR_PRE EdramRefEnLo EDC_H_DBG_MA_WR_EXP_DAT_CYC_CNT EDC_H_DBG_BIST_RD_EXP_DAT_CYC_CNT EDC_H_DBG_EDRAM_REF_BURST_CNT inp_wrdq_wrrdy HMA_TLB_DESC_3_L HMA_REG3_MAX HMA_LOCAL_DEBUG_RPT MPS_VF_STAT_TX_VF_BCAST_FRAMES_H CIM_VF_EXT_MAILBOX_DATA_1c Usage: %s <nexus> [operation]
CHELSIO_T4_REGDUMP mi %4s %8s %1d/%1d nat_dip nat_dport swapmac natflag IPv6 uPToken: TPHint: DISABLED loopback MPS Tx too many arguments RX Power %fmW
ESTABLISHED parse_tcb TF_NON_OFFLOAD TF_SSWS_DISABLED tx_quiesce TF_RCV_COALESCE_ENABLE TF_MOD_SCHD_REASON2 dupack_count_odd fast_recovery TF_CCTRL_CWR cctrl_rfr snd_nxt_raw snd_nxt Offset of snd_nxt from tx_max Receive re-order fragment 1 length Receive recovered PDU length rq_max_offset rq_write_ptr Hits_high peer_fin %u, rx_pdu_out %u, pdu_len %u
rx_tls_buf_tag perr_pc_mc_rsp err_flm_hint SGE_FL_BUFFER_SIZE8 HdrStartFLQ CreditCnt TP_Enable err_bad_upfl_inc_credit3 err_unexpected_timer SGE_LA_RDDATA_15 MSIXDataPerr HotRstPCIeCRstMode TABOfst CH3 PCIE_DMAI_CNT PCIE_RSP_ERR_STAT_0 PCIE_MSIX_EN_6 RNPS PCIE_CORE_UTL_SYSTEM_BUS_AGENT_INTERRUPT_ENABLE OTWS IP0H IN1H RCAI PABI AENI OPM4 ModuleSelect KX_LOCK STATIC_C_PLL_RANGEA STATIC_KR_PLL_N3 STATIC_U_PLL_SLEEP STATIC_C_PLL_SLEEP dbg_operate0_or_1 dtu_random_error MC_PCTL_DTUPRDO MC_PCTL_TREFI MC_PCTL_TCWL dtu_rd_byte10 dtu_rd_byte14 MC_PCTL_PVTTUPON MC_DDR3PHYAC_MDPPR0 TSEL MC_DDR3PHYAC_PRCR MC_DDR3PHYAC_PLLCR0 DTOSEL RDATA_FIFOR_PAR_CAUSE MA_CLIENT2_RD_LATENCY_THRESHOLD MA_CLIENT7_WR_LATENCY_THRESHOLD MA_EXT_MEM_PAGE_SIZE IBQTP1ParErr IllRdBEIntEn BlkWrEEPROMInt MstPlInt QueFullThrsh CDebugDataL IbqDbgBusy PILADbgWrPtr CIM_MEM_ZONE1_VA CIM_MEM_ZONE5_BA VepaMode CTunnel VLANExtEnablePort3 ProtectedMode TP_PC_CONFIG RxCongestionMode HearbeatOnceDACK FastTblCnt TimerResolution VfRdEn UpdChn0 TP_CMM_MM_PS_FLST_BASE CTpOutTcpFifoPerr CQE_fifo_perr_set3 lso_hdr_sram_perr_set0 ULP_TX_SE_CNT_CH2 ULP_TX_LA_WRPTR_0 ULP_TX_LA_RESERVED_9 iespi1_fifo2x_Rx_framing_error iespi2_fifo2x_Rx_framing_error iespi_par_error MPS_PF_CTL MPS_RX_PG_HYST_BG3 MPS_RX_FUNC_INT_ENABLE MPS_PFVF_ATRB_FLTR1 MPS_PFVF_ATRB_FLTR5 MPS_RX_SE_CNT_IN3 OUT_DBG_CHNL ErrCh0 ValidCh3 FullPt1 SizePt3 MPS_PORT_TX_MAC_RELOAD_CH4 TrcFifoEmpty MPS_TRC_FILTER3_MATCH Txvf MPS_PORT_STAT_TX_PORT_MCAST_H MPS_PORT_STAT_LB_PORT_BYTES_H MPS_PORT_STAT_RX_PORT_256B_511B_L MPS_PORT_STAT_RX_PORT_PPP3_L MPS_PF_STAT_RX_PF_MCAST_BYTES_H MemWriteFault MPS_CLS_TCAM_Y_L MacroCntCfg SMB_INT_ENABLE SlvByteCntErrInt I2CM_CFG PCMD1Threshold ENABLE_MEMRF_0 ULP_RX_DBG_CTL IsVF LE_DB_ACTIVE_MASK_IPV6 ClearStat NCSI_MACB_RX_SYMBOL_ERR Signal_Det XGMAC_PORT_PKT_COUNT XGMAC_PORT_EXT_LOS_CTRL PatDetected ClearMagic PCS_CTC_Error PCS_Link_Good HSSEyeQual HSSRECCAL RXDPRBSFRCERR RXCLATEIN UnidirTxEn DisNonVlan IncrStats err_blk_cnt_rst Parallel_Det_Fault RXREQ_CPRE FSM_TR_COMP FSM_TR_EN Training_Enable ALOAD XGMAC_PORT_HSS_TXA_TAP2_IDAC_OVR AUXCLK REQCMP HBND1 D10AMP XGMAC_PORT_HSS_RXA_DIGITAL_EYE_METRICS BLKH1T ROCADJ ROCCMP XGMAC_PORT_HSS_RXB_DACAP_DAC_AN_OFFSET XGMAC_PORT_HSS_TXD_TAP1_IDAC_APP XGMAC_PORT_HSS_RXD_DIGITAL_EYE_CTRL RXCEN TXCEN LFREQ1 XGMAC_PORT_HSS_TX_TAP2_IDAC_APP ClrCoalesceDisable err_large_minfetch_with_txcoal3 debug_CIM_SOP1_cnt SGE_DEBUG_DATA_HIGH_INDEX_4 debug_PC_Rsp_EOP1_cnt debug_PD_RdReq_EOP1_cnt debug_PD_WrReq_SOP3_cnt debug_PD_WrReq_SOP1_cnt debug_M_rd_req_outstanding_PC debug_flm_idma1_ctxt_data_active SGE_DEBUG_DATA_LOW_INDEX_6 DReqRdPerr MARspTimeout PCIE_PF_MSI_EN PCIE_FLR_VF0_STATUS Fast_Link_Mode Flow_Control_Disable Ack_Nak_Timer_Modifier Disable_FC_Watchdog VC0_NPH_Credits VC1_NPTLP_Queue_Mode VC1_CPLTLP_Queue_Mode RspIPif_Dynamic_CGEN LnD_RxStateDone LnB_STAT Lane3FS T5_P_OCLK_MUXSEL DBG_CUST_EFUSE_SEL1_EN DBG_FEENABLE T5_STATIC_M_PLL_LFTUNE_32_40 T5_STATIC_C_PLL_LOCKSEL GPIO10_PE_En GPIO5_PE_En GPIO2_PE_En GPIO1_PE_En HMA_MUX MA_EXT_MEMORY1_BAR MA_HOST_MEMORY_RDDATA_CNT1 CL9_WR_DATA_TO_EN CL7_WR_DATA_TO_ERROR MA_BKP_CNT_SEL CL11_IF_PAR_EN CL0_IF_PAR_EN EOF_LS2 MPS_TX_PAUSE_DURATION_BUF_GRP_TH8 MPS_TX_PAUSE_RETRANS_BUF_GRP_TH7 PETYPE2EN TxSchMAC3_CGEN MPS_TX_CGEN_DYNAMIC MPS_TRC_VF_OFF_FILTER_1 MPS_TRC_CGEN TxCh MPS_STAT_STOP_UPD_TX_VF_32_63 LPBK_TCAM1_HIT_PRIORITY PF_VLAN_SEL MC1_Part_CGEn ULP_RX_CH1_CGEN ALN_SDC_ERR_1 SRVRAMCLKOFF MAC_PORT_RESET_CTRL MtipSd1TxRst T5_AEC_PMA_TX_READY rx_sff_seg0 tx_sff_mac10 HSSPLLBYPB PCSSEG4_CGEN MAC_PORT_TX_TS_VAL_LO MAC_PORT_PTP_CFG CUSTREV PAUSE_FWD MAC_PORT_MTIP_MAC_ADDR_1 RX_REM_FAULT MAC_PORT_AALIGNMENTERRORSHI MAC_PORT_IFINUCASTPKTS MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0 MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4HI MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1 MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5HI disable_preamble MAC_PORT_MTIP_PCS_STATUS1 10GPRBS9 MAC_PORT_MTIP_10GBASER_SEED_B1 MAC_PORT_MTIP_10GBASER_SEED_B3 Lane0 MAC_PORT_MTIP_PCS_BIP_ERR_CNT_10 MAC_PORT_LP_BEAN_XNP_2_LANE1 MAC_PORT_LP_BEAN_XNP_1_LANE2 MAC_PORT_AE_RX_COEF_STAT_2 MAC_PORT_AET_STAGE_CONFIGURATION_3 RCERR MAC_PORT_PLLA_CHARGE_PUMP_CONTROL MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_3 DCCOUT DCCHOLD RATEDIVCTL MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C0_INIT_EXTENDED C0MIN C1MIN MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 MAC_PORT_TX_LINKD_TRANSMIT_AMPLITUDE MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 T5_RX_DMSEL RBOOFF DUTYI LOFE1 LOFE3 T5E0SN_ReadOnly H7MAG MAC_PORT_RX_LINKD_RECEIVER_TEST_CONTROL MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_2 MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_OFFSET_CONTROL MAC_PORT_RX_LINK_BCST_DFE_H5 MAC_PORT_RX_LINK_BCST_DFE_H6_AND_H7 SEQ_ERROR_MASK PVTN ADDR_MIRROR_RP0_PRI SLEW_DONE_STATUS SLEW_CNTL DQSCLK_SELECT2 MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP MC_DDRPHY_DP18_RD_LVL_STATUS2 INCOMPLETE_RD_CAL_N1 WL_ERR_CLK22 VALID_NS_BIG_R S1INSDLYTAP MC_DDRPHY_DP18_PATTERN_POS_0 DYN_MCTERM_CNTL_EN CALGATE_ON MC_DDRPHY_SEQ_MEM_TIMING_PARAM2 WR_CNTL_ERROR_MASK DP18_3_Populated MC_UPCTL_TCWL MC_UPCTL_TRC MC_UPCTL_DTUWDM MC_UPCTL_DTURD2 ea_row0 dfi_lp_en_sr MC_UPCTL_DFITRRDLVLRESP1 fl_merge_cnt_thresh SGE_DBG_DB_PKT_CNT debug_PC_Req_SOP_cnt debug_st_idma0_idma2imsg PfIQsPerPage Stall_Disable PIOCpl_VDMTxDataPerr Req_LnG_RxPwrState Req_LnO_RxPwrState LnM_STAT Lane8FS Lane13FS PCIE_BUS_MST_STAT_8 PCIE_FUNC_DSTATE STATIC_M_PLL_FFENABLE DBG_STATIC_M_PLL_CONF6 STATIC_PHY0RecRst_ STATIC_C_PLL_STARTUP STATIC_C_PLL_STOPCLKA STATIC_KX_PLL_ANALOGTUNE Que1KEn EcnMode DropErrorIp6Opt TNLFcoeSid dma_fifo_perr_set1 MPS_RX_TCP IPV6_UDP_CSUM_COMPAT Outer_IPv6_n_VLAN_GRE IN_TH ClsTrcPortNum ClsTrcPF MPS_CLS_DIPIPV4_ID_TABLE CtlReqID MPS_CLS_TCAM_RDATA1_REQ_ID0 MPS_CLS_TCAM_RDATA0_REQ_ID1 MTCAM_INIT_BUSY NORM_FILT_HIT TUPLZERO VfSramPerr LE_DB_CLCAM_TID_BASE port_map debug_port_sel Led0_tlo pcs100g_reset_cgmii_txclk pcs10g_clk_enable AEC_RX_UNKNOWN_LANE_0 CU_C0_ACK_VALUE CX_PRESET MAC_PORT_AEC_DEBUG_HI_0 mac40g100g_tx_loc_fault tx_li_fault Perr_rx2_pcs100g ALARM_START AlmostFull MAC_PORT_MTIP_1G10G_MDIO_CFG_STATUS MAC_PORT_MTIP_1G10G_RX_VLANOK MAC_PORT_MTIP_1G10G_RX_AFRAMETOOLONGHI MAC_PORT_MTIP_1G10G_TX_IFOUTERRORSHI MAC_PORT_MTIP_1G10G_TX_IFBROADCASTPKTSHI MII_ENA_10 100G_capable MAC_PORT_MTIP_CR4_STATUS_1 Clause22reg_present Clause22_ExT_Present BER_counter MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_4 MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_10 MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_16 MAC_PORT_MTIP_CR4_LANE_3_MAPPING MAC_PORT_MTIP_FEC_ABILITY MAC_PORT_MTIP_FEC2_NCERR_CNT_0 EN_P2 RCALCOMP ISGT C3STAT C3INIT1 MAC_PORT_TX_LINKC_TRANSMIT_4X_SEGMENT_APPLIED MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE REQWOV FINTRCALDYN H6SN CALSDONE DCCQCCDYN CALMODEEDGE MAC_PORT_RX_LINKB_RECEIVER_DACAP_AND_DACAN_SELECTION MAC_PORT_RX_LINKB_DFE_TAP MAC_PORT_RX_LINK_BCST_RECEIVER_AC_COUPLING_VALUE MEMCTL_CIS_IGNORE PASS_FAIL_V DQS_ALIGN_CNTR QUAD2_PWR_CTL PORT_ID_CHK_EN RESET_RANK WAIT MC_LMC_CMD0 RTT_NOM0 SMR5_RFU MC_P_BIST_USER_WMASK1 MaxOpsPerTRC BWData RefCnt HMA_TLB_DESC_6_H OTF SGE_KDOORBELL MPS_VF_STAT_RX_VF_BCAST_BYTES_H hashfilter CHELSIO_T4_SETREG pci CHELSIO_T4_GET_FILTER proto matchtype ivlan dip-dp-sip dmac FetchBurstMax: SEInterruptArmed: InterruptArmed: CngChMap: Temp: XFP-E sched params "max-rate" missing for rate-limit level sched params mode flow needs rate-mode absolute CHELSIO_T4_SCHED_CLASS parameter "%s" has bad value "%s" unknown settings keyword: "%s"
0x%4.4x: mod_schd_rx recv_tstmp tx_max rq_msn OPT_0_WSF Direct_Steer_Hash Rewrite_DMAC rcv_adv %-5u (rcv_scale %-2u recv_scaleflag %u active_open %u)
tx_quiesce %u
Swap_MAC_addresses Hit_byte_cnt_low TF_CORE_BYPASS SGE_INT_CAUSE2 perr_imsg_pd_fifo perr_headersplit_fifo0 err_flm_idma0 err_cpl_opcode_0 err_ing_ctxt_prio SGE_FL_BUFFER_SIZE15 NoEDRAM SGE_TIMESTAMP_LO Value HP_Int_Thresh ForceVFPF4DBtoLP err_flm_invalid_pkt_drop1 Egress_Log2Size SGE_LA_RESERVED_4 SGE_LA_RDPTR_13 PCIE_INT_ENABLE MSIXDIPerr MaxRspCnt IPConfigDown IN_RD_BUFMODE PndTxns CDEBUGSelL PCIE_DMAW_EOP_CNT CH0_SOP CH0_WSOP PCIE_RSP_ERR_STAT_5 SWD3 SWD5 RCCP TNPS TCII PCIE_CORE_ROOT_COMPLEX_STATUS PCIE_CORE_ROOT_COMPLEX_ERROR_SEVERITY PCIE_CORE_ROOT_COMPLEX_INTERRUPT_ENABLE RCTI PCIE_CORE_ENDPOINT_STATUS PTOS PME4 PCIE_CORE_GENERAL_PURPOSE_CONTROL_2 AIVec GPIO13_CHG_DET GPIO9_CHG_DET GPIO2_IN IBM_FDL_FAIL_int_cause GPIO14_ACT_LOW GPIO3_ACT_LOW DBG_TRACE1_DATA_OUT DBG_PVT_REG_OUT_DRVN MC_PCTL_SCFG slave_mode MC_PCTL_POWSTAT clr_ecc_log MC_PCTL_DTUCFG ea_column ICPSEL MC_DDR3PHYDATX8_WDBDR0 MC_DDR3PHYDATX8_PMBDR0 MC_DDR3PHYDATX8_PMBDR3 RDQSCAL DDRIO_ENABLE MA_CLIENT4_RD_LATENCY_THRESHOLD MA_INT_WRAP_STATUS MA_SGE_THREAD1_MAPPER ARB2_PAR_WRQUEUE_ERROR_EN ARB0_PAR_WRQUEUE_ERROR_EN ARB0_PAR_RDQUEUE_ERROR CL1_PAR_RDQUEUE_ERROR ECC_BYPASS PERR_PAR_CAUSE Timer0IntEn TimeOutMAIntEn SglRdBootIntEn IllTransIntEn SglRdCtlInt QueNumSelect CIM_PO_LA_DEBUGDATA CIM_MEM_ZONE6_VA ECPL CxMaxOpCntDisable AutoState1 EnableLbkChn SwsMode TP_PARA_REG2 DisablePDUTimeout DisablePDUxmt EngineLatencyMmgr TP_ERR_CONFIG TnlErrorTcpHdrLen DropErrorCsum TP_TIMER_RESOLUTION ULPType3Field MaskFilter ChnOvrFlow1 TP_LA_TABLE_0 TP_TM_PIO_ADDR TP_TX_MOD_QUEUE_WEIGHT7 TP_PER_ENABLE FreeRxPageCount TP_TX_TRATE TP_DBG_LA_DATAL ULP_TX_ERR_CNT_CH1 ULP_TX_SE_CNT_ERR ERR_CH1 ULP_TX_LA_RESERVED_8 PM_TX_STAT_LSB oespi0_Rx_framing_error oespi2_Tx_framing_error oVlanSelMac1 QUOTA TH_HIGH MPS_PF_OUT_EN OFF MPS_PFVF_ATRB_FLTR11 MPS_RX_SE_CNT_IN6 OVLAN_EN2 OVLAN_EN0 TxDataFifo MPS_TX_SECNT_SPI_BUBBLE_ERR pt3 SizeCh2 EOPPt1 ErrPt0 MPS_PORT_TX_MAC_RELOAD_CH2 TrcKeepDuplicates MPS_TRC_FILTER_RUNT_CTL MPS_TRC_FILTER2_DONT_CARE MPS_STAT_PERR_ENABLE_TX_FIFO MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H MPS_PORT_STAT_TX_PORT_UCAST_L MPS_PORT_STAT_TX_PORT_PPP5_H MPS_PORT_STAT_LB_PORT_128B_255B_L MPS_PORT_STAT_RX_PORT_BCAST_H MPS_PORT_STAT_RX_PORT_UCAST_H MPS_PORT_STAT_RX_PORT_CRC_ERROR_H MPS_PORT_STAT_RX_PORT_1519B_MAX_L HypervisorOnly MPS_CLS_PERR_ENABLE MatchSRAM switch_table_enable SlvFifoTxCnt SMB_ARP_UDID1 AuxAddr2 TddpTagTcb CAUSE_CTX_0 REQ EOP_CNT_OUT0 EOP_CNT_AL1 SGE LE_DB_FILTER_TABLE_INDEX LE_DB_INT_TID DropFilterClear rx_halt CHO_SADDR_EN CH2_SADDR_HIGH NCSI_MACB_TX_BUF_QPTR NCSI_MACB_SPECIFIC_1_LOW DesRev XAUI20_XGMII_Sel TxEop CheckIn incmptbl_link RXCEARLYIN RXBPHSUPIN RXALATEIN XGMAC_PORT_XGM_RX_CTRL XGMAC_PORT_XGM_STAT_RX_FRAMES_HIGH rx_clk_speed hi_ber AN_Ability XGMAC_PORT_AE_RX_SIGDET RX_Trained TPGRST FFE XADDR LBSYNC APADJ E0SN DACAZ H1ESN BER6VAL XGMAC_PORT_HSS_RXB_DAC_DPC XGMAC_PORT_HSS_TXD_TAP0_IDAC_OVR XGMAC_PORT_HSS_RXD_DFE_H5 VISEL XGMAC_PORT_HSS_TX_TAP0_IDAC_APP err_cpl_exceed_max_iqe_size1 err_large_minfetch_with_txcoal2 dbfifo_fl_int RxCplSizeAutocorrect SGE_DOORBELL_THROTTLE_THRESHOLD debug_CIM_EOP1_cnt debug_U_Tx_SOP2_cnt debug_PD_WrReq_SOP0_cnt debug_M_ReqVld debug_PD_RdRspAFull_d debug_U_TxAFull_d debug_PC_Req_SOP2_cnt debug_itp_add_done debug_st_dbp_ctxt debug_flm_dbptr_cidx_stall IPRxDataGrpPerr MAGrpPerr PIOCplGrpPerr PCIE_VF_MSIX_EN_3 PH1 PM_Status VC7_WRR Feedback_Mode RspDataProc_Dynamic_CGEN IPRxData_VC1Perr CplStatusLogEn STATIC_JTAG_VersionNr TVSENSE_OUTPUTVALID T5_STATIC_M_PLL_FFENABLE DBG_T5_STATIC_KR_PLL_CONF1 T5_STATIC_KR_PLL_CCALFMIN STATIC_C_DFS_RANGEA STATIC_U_DFS_RANGEB GPIO3_PE_En MEM_TO_INT_ENABLE MA_SGE_TH0_WRDATA_CNT MA_ULPTXRX_RDDATA_CNT MA_EDRAM0_WRDATA_CNT0 CL8_WR_DATA_TO_EN CL3_WR_DATA_TO_EN CL12_RD_DATA_TO_EN CL6_RD_DATA_TO_EN CL10_RD_CMD_TO_ERROR CL2_IF_PAR_ERROR CIM_PF_MAILBOX_CTRL_SHADOW_COPY LOSDR ULP_TX_FC_SOF ULP_TX_CSU_REVISION MPS_TX_PAUSE_RETRANS_BUF_GRP_TH3 MPS_TX_PAUSE_RETRANS_BUF_GRP_TH6 LEN_ERR_INT MPS_RX_LPBK_CLS_DROP_CNT3 TxSchLpbk1_CGEN on_pending MPS_PORT_STAT_LB_PORT_DROP_FRAMES_H perr_cpl_128to128_1 MARspParErr sd_rx_clk_ena HSSC16C20SEL AEC2_RX_WIDTH Perr3_rx_mix Perr2_tx Perr1_tx RXDREFRESH MAC_PORT_HSS_STATUS HSSPRTREADYB TOV LPI_IND FRZ MAC_PORT_MTIP_MAC_ADDR_0 MAC_PORT_MTIP_RX_FIFO_SECTIONS MAC_PORT_AOCTETSTRANSMITTEDOK MAC_PORT_IFOUTERRORS 10MbpsFullDplx 100BaseT2FullDplx LINK_STATUS VL_INTVL MAC_PORT_MTIP_PCS_PKG_ID0 AMLOCK5 AMLOCK8 RESTART_BEAN EXT_NXP_STATUS MAC_PORT_BEAN_ABILITY_2_LANE3 MAC_PORT_FEC_KR_LD_STAT T5_AE1_RXSTAT_C0 MAC_PORT_AE_KR_CTRL_3 MAC_PORT_AET_STAGE_CONFIGURATION_0 ACC_LIM MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_0 BOOT_LUT7 CTRL_STATE RXACMODE HSSACJAC T5_TX_LINKRST MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_1 MAC_PORT_TX_LINKC_TRANSMIT_DCLK_ROTATOR_OVERRIDE MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C0_INIT_EXTENDED MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_ADDR MAC_PORT_TX_LINK_BCST_TRANSMIT_COEFFICIENT_CONTROL MAC_PORT_RX_LINKA_DFE_CONTROL MAC_PORT_RX_LINKA_RECEIVER_DACAP_AND_DACAN ADSN_ReadWrite MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_2 SDACDC INTDAC EMF8 H4EGS H7SN_ReadOnly H9MAG WHICHNRZ MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 MAC_PORT_RX_LINKB_DFE_H12 MAC_PORT_RX_LINKC_RECEIVER_DACA_MIN_AND_DACAZ MAC_PORT_RX_LINKC_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC MAC_PORT_RX_LINKC_RECEIVER_SIGDET_CONTROL MAC_PORT_RX_LINKD_RECEIVER_ADAC_CONTROL MAC_PORT_RX_LINKD_RECEIVER_SIGDET_CONTROL MAC_PORT_RX_LINK_BCST_INTEGRATOR_DAC_OFFSET DP18_PLL_LOCK ENA_PER_DQS_ALIGN START_PER_ZCAL DDR4_CMD_SIG_REDUCTION SEQ_ERROR ERROR_READ_CTR_MASK BIT_ENABLE_12_15 EN_SLICE_P_WR_FFE POST_CUR_SEL_BITS6_7 MC_ADR_DDRPHY_ADR_POWERDOWN_2 PLL_TUNETDIV_0_2 SLEW_LATE_SAMPLE HS_PROBE_A_SEL_ DQSCLK_SELECT3 MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR NO_LOCK EN_TERM_P_WR_FFE MEMINTD10_POS TODTLON_OFF_CYCLES WL_ONE_DQS_PULSE MC_DDRPHY_WC_CONFIG1 FW_RD_WR MC_DDRPHY_RC_ERROR_STATUS0 MC_UPCTL_TREFI MC_UPCTL_TRTW MC_UPCTL_TCKSRX MC_UPCTL_ECCTST MC_UPCTL_DTURD0 MC_UPCTL_DFITRRDLVLGATEEN dfi_dram_clk_disable_en parity_intr_en EDC_H_BIST_CMD EDC_H_BIST_USER_WDATA0 EDC_H_BIST_STATUS_RDATA HMA_TABLE_LINE1 RO HMA_INT_CAUSE gts_dbg_en en_db_fifth err_th0_max_fetch err_bad_upfl_inc_credit4 VfWCOffset PCIE_PHY_GEN3_AE2 PCIE_PHY_STAT1 STATIC_M_PLL_STARTUP NUM_PG_128B_FDBK FUTURE_DEXPANSION_IPS TxTcamKey ULPType7Length MR_SIZE_FIX_EN edma_in_fifo_perr_set0 MPS_RX_MAC_BG_PG_CNT3 LENGTH_ETYPE VXLAN_FLAG_MASK MPS_RX_CNT_NVGRE_PKT_LPBK0 HASH_PRIO_SEL_LPBK Outer_IPv4_n_VLAN_NVGRE Outer_IPv6_n_VLAN_GENEVE MPS_PORT_RX_PRS_DEBUG_FLAG_LPBK MPS_CLS_TCAM_RDATA2_REQ_ID0 iscsi_dcrc_error_cmp_en pdu_dpi SrvSramPerr HashTblAccFail DBGITID LE_DB_SRVR_VF_SRCH_TABLE_CTRL VFLUTSTART debug_tx_rx_sel PCS100G_RESET mac1g10g_reset_ff_tx_clk AEC_RX_LANE_ID_3 mac40g100g_ff_tx_pfc_xoff sgmii_sd_loopback pcs100g_ber_timer_short pcs100g_align_lock Perr_rx1_pcs100g MAC_PORT_PERR_ENABLE_100G PPS_EN SFD_ANY RX_ENAMAC TX_ENAMAC MAC_PORT_MTIP_1G10G_MDIO_COMMAND MAC_PORT_MTIP_1G10G_TX_ETHERSTATSUNDERSIZEPKTS MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_1 Fault Low_power DEVICE_ID1 TX_TP_EN LANE_0_ALIGN_MRKR_LCK MAC_PORT_MTIP_CR4_DEVICE_ID0 MAC_PORT_MTIP_CR4_BER_HIGH_ORDER_CNT Lane5_algn_mrkr_lck MAC_PORT_MTIP_CR4_LANE_12_MAPPING MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_SYMBOLS MAC_PORT_AET_STATUS_22 MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE TAPSEL C1INIT1 MAC_PORT_TX_LINKB_TRANSMIT_4X_SEGMENT_APPLIED MAC_PORT_TX_LINKC_TRANSMIT_APPLIED_TUNE_REGISTER MAC_PORT_TX_LINKC_TRANSMIT_AE_C2_LIMIT_EXTENDED APLYDCD PMCFG LOAD1 ACCPLBIAS LIDLE H15GS VCC_REG_PD MT_PLL_RESET WIDTH1 MC_LMC_INITSEQ1 ODT_DELAY T_RP0 SRT_ASR1 ASR0 MC_LMC_SMR6 EDC_H_DBG_MA_RD_REQ_CNT CmdSplitFsm dead_cycle0_max_op VALID_E HMA_TLB_DESC_6_L MPS_VF_STAT_TX_VF_UCAST_FRAMES_H CIM_VF_EXT_MAILBOX_DATA_00 stdio DPORT %4d , smac=%02x:%02x:%02x:%02x:%02x:%02x , smtidx=%d rpttid, queue and tcbhash don't make sense with action "drop" or "switch" RelaxedOrdering: invalid address "%s" CHELSIO_T4_GET_MEM tracing is %s
unknown CDFP3 SFP-DD sched params "max-rate" takes percentage value(1-100) for rate-mode relative
timestamp tstamp invalid queue specification "%s". "%s" needs an integer value, or "random". TIME_WAIT smac_sel core_flush TF_RCV_COALESCE_LAST_PSH TF_RECV_SCALE MTU table index t_rttvar snd_max ts_last_ack_sent aux1_slush0 rx_frag3_len TF_DDP_BUF0_INDICATE TF_DDP_BUF1_FLUSH OPT_0_NAGLE timestamp_offset 0x%x, timestamp 0x%x
tx_pdu_len %u
And buf1, which is also valid, has %u - %u = %u bytes of space left
SGE_PF_GTS SGE_USER_MODE_LIMITS perr_edma_fifo3 SGE_FL_BUFFER_SIZE1 SGE_FL_BUFFER_SIZE12 ForceUserDBtoLP Dropped_DB MaxRspCnt0 SGE_PC1_REQ_BIST_CMD SGE_LA_RESERVED_2 SGE_LA_RDPTR_5 SGE_LA_WRPTR_10 MaxPyldSize GBIF_NPTRANS_TOT PCIE_RSP_ERR_STAT_4 SWD4 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS PCIE_CORE_INBOUND_NON_POSTED_REQUESTS_BUFFER_ALLOCATION PCIE_CORE_GBIF_READ_TAGS_ALLOCATION IC2T OTDI PINB PME6 PCIE_PF_GEN_MSG GPIO9_OEn GPIO14_Out_Val GPIO15_CHG_DET GPIO8_CHG_DET GPIO2_CHG_DET GPIO1_CHG_DET GPIO8_IN GPIO5_IN DBG_INT_ENABLE GPIO13 GPIO15_ACT_LOW DBG_EFUSE_BYTE8_11 STATIC_KX_PLL_M DBG_STATIC_KR_PLL_CONF STATIC_UCLK_FREQ_SEL C_OCLK_MUXSEL Wr_pointer_addr0 RESET_CALIBRATE PVT_REG_DRVP_B DBG_PVT_REG_THRESHOLD MC_PCTL_STAT rank2_odt_default rank0_odt_write_nsel dtu_allbits_2 dtu_allbits_5 dtu_rd_bank MC_PCTL_DTUWDM MC_PCTL_DTURD1 i_phy_upd_done WLRANK CKCLKEN MC_DDR3PHYDATX8_RDBDPR ECC_DISABLE ECC_UE_INT_ENABLE STATIC_WIDTH MC_DEBUG_CNT MA_CLIENT1_WR_LATENCY_THRESHOLD MA_PMTX_DEBUG_CNT MA_INT_ENABLE CL10_PAR_WRQUEUE_ERROR BONUS_REG EDC_BIST_CMD_ADDR IBQTP0ParErr CIM_PO_LA_MADEBUGDATA CIM_MEM_ZONE7_BA CIM_CIM_DEBUG_SPARE CrcPassPrt2 CChecksumCheckTCP CEthernet TP_PMM_RX_BASE DisableHitCheck EnableRddpRcvAdvClr TimerBackoffIndex9 RxtPace TP_PARA_REG1 RenoCfg EnablePDUE EngineLatencyDelta TimestampResolution TP_DACK_TIMER CTpOutEthFifoPerr DelInvFifoPerr TxModXoff2 TP_IX_SCHED1 DbgLaMode LineAddress sge2ulp_fifo_perr_set3 cim2ulp_fifo_perr_set0 pbl_fifo_perr_set2 Ch1Size2 ULP_TX_FPGA_CMD_CTRL ULP_TX_FPGA_CMD_1 ERR_CH2 ULP_TX_LA_RDPTR_1 ULP_TX_LA_RESERVED_3 ULP_TX_LA_RESERVED_6 oespi2_Rx_framing_error c_pcmd_par_error RxEn RegSending PKTQ PG_TH_INT6 MPS_RX_PPP_ATRB MPS_BMC_BYTE_CNT PKD ST2 MPS_RX_CLS_DROP_CNT0 PRIO_VLAN_SEL PASS_NO_MATCH OVLAN_EN1 NCSI_Source MPS_TX_SE_CNT_MAC23 FullCh0 QueueNumber Rxbg Pause PV MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L MPS_PORT_STAT_TX_PORT_PPP3_H MPS_PORT_STAT_LB_PORT_FRAMES_L MPS_PORT_STAT_RX_PORT_BYTES_L MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L MPS_PORT_STAT_RX_PORT_256B_511B_H MPS_PORT_STAT_RX_PORT_PPP3_H MPS_PORT_STAT_RX_PORT_PPP7_L MPS_PORT_STAT_RX_PORT_LESS_64B_L MPS_PORT_STAT_RX_PORT_LESS_64B_H MPS_PF_STAT_TX_PF_MCAST_BYTES_L MPS_PF_STAT_RX_PF_FRAMES_L MPS_CLS_INT_ENABLE Cls_Replicate cpl_pkt_tid cim_to_up_full_size tp_framing_error SlvTimeOutIntEn SMB_PERR_EN SMB_PERR_INJ ArpAddrRes MDIO_1P2V_Sel EDC0PartCGEn Hpz2 Hpz0 XGMAC_KR1 NCSI DBG PerrVFID LE_DB_ACT_CNT_IPV4 LE_DB_INT_ENABLE LE_DB_DBGI_RSP_DATA DropFilterEn LE_HASH_MASK_CMP_IPV6 tx_byte_swap NCSI_RX_IE_CNT NCSI_PAUSE_WM PClkDiv SerEn UsedBitRead NCSI_MACB_PAUSE_FRAMES_RCVD NCSI_MACB_ALIGN_ERR NCSI_MACB_TX_PAUSE_FRAMES NCSI_MACB_SPECIFIC_4_LOW XGM_Rx_Sel HSS_Reset Led1_Cfg Rx_Polarity_Inv StopOnPerr linkdn xgmii RxFifoOverFlow RXCPHSDNIN RXAPHSDNIN RXCPRBSERR XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_8 EnTypeMatch XGMIIExtInt TakeSnpShot XGMAC_PORT_XGM_STAT_TX_65_127B_FRAMES XGMAC_PORT_XAUI_CTRL XGMAC_PORT_AN_LP_NP_UPPER XGMAC_PORT_HSS_TXA_PWR_DAC_OVR XGMAC_PORT_HSS_TXB_TAP1_IDAC_OVR E0AMP H5OSN OCCMP XGMAC_PORT_HSS_RXB_SIGDET_CTRL XGMAC_PORT_HSS_RXB_DACA_OFFSET XGMAC_PORT_HSS_RXB_DFE_H1 XGMAC_PORT_HSS_RXB_DFE_H5 XGMAC_PORT_HSS_TXC_TDM_BIASGEN_PWRON_TIMER XGMAC_PORT_HSS_TXD_TAP2_IDAC_APP XGMAC_PORT_HSS_RXC_PH_ROTATOR_POSITION1 XGMAC_PORT_HSS_RXC_VGA_CTRL1 XGMAC_PORT_HSS_RXC_VGA_CTRL3 XGMAC_PORT_HSS_RXC_DFE_D00_D01_OFFSET XGMAC_PORT_HSS_RXD_VGA_CTRL1 XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_3 XGMAC_PORT_HSS_ANALOG_TEST_MUX XGMAC_PORT_HSS_CHARGE_PUMP_CTRL XGMAC_PORT_HSS_VOLTAGE_BOOST_CTRL bar2_egress_coal0_err Throttle_Threshold_lp debug_st_idma1_idma_sm Egress_Size VFIDPerr FLRPndCplMode PCIE_FLR_VF2_STATUS Vendor_Specific_DLLP_Request PCIE_CORE_SYMBOL_NUMBER CookieCnt EnableVC1 PCIE_CUR_LINK CfgInitCoeffDoneSeen pm_linkst_in_l0s LnD_RxPwrState LnC_RxPwrState LnH_STAT T5_STATIC_SWMC1Rst_ T5_STATIC_C_PLL_FFSLEWRATE T5_STATIC_C_PLL_SDORDER T5_STATIC_C_PLL_STOPCLKB T5_STATIC_KX_PLL_P GPIO17_PE_En GPIO4_PE_En MA_ULPRX_WRDATA_CNT MA_TP_TH1_WRDATA_CNT CL4_WR_DATA_TO_EN CL3_WR_CMD_TO_ERROR CL11_RD_DATA_TO_EN CL12_RD_CMD_TO_ERROR CL0_RD_DATA_TO_ERROR VnTagDefaultVal TxDfrFast num_flits MPS_TX_PAUSE_RETRANS_BUF_GRP_TH1 MPS_TX_PAUSE_RETRANS_BUF_GRP_TH10 SE_CNT_ERR_INT MPS_RX_PAUSE_GEN_TH_1_1 PFRx perr_cpl_128to128_0 SlvFifo skip_ma_req_en1 MapMAC0 Control MASKCMDOLAPDIS PROTOCOLMASKEN CRCHASH TWGDSK_HSSC16B AET0Reset HSSPLLSEL MAC_PORT_PERR_INT_EN T5RXCPRBSRST IPW runtclear pma_tx_quiet MACSEG1_CGEN EEE_RX_RESET MAC_PORT_PTP_SUM_LO MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTED MAC_PORT_ETHERSTATSPKTS64OCTETS MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0HI MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4 MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3HI MAC_PORT_AMACCONTROLFRAMESTRANSMITTED MAC_PORT_AMACCONTROLFRAMESRECEIVEDHI AN_RESTART MAC_PORT_MTIP_TX_PRMBL_CTL_SEG MAC_PORT_MTIP_PCS_DEVICE_ID0 MAC_PORT_MTIP_PCS_STATUS2 HiBER MAC_PORT_MTIP_BER_HIGH_ORDER_CNT HiCountPrsnt Lane7 Lane19 Lane12 AMLOCK18 MAC_PORT_MTIP_PCS_BIP_ERR_CNT_8 MAC_PORT_LP_BEAN_XNP_0_LANE2 train_fail C0_UPD AET_RSVD MAC_PORT_AE_KR_STATUS_3 BOOT_LUT45 FRCBAND MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_4 MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_APPLIED TS MAC_PORT_TX_LINKB_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_2 MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED MAC_PORT_TX_LINKC_TRANSMIT_COEFFICIENT_CONTROL MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_1 MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE MAC_PORT_TX_LINKD_TRANSMIT_DCC_APPLIED MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_DATA MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED T5_RX_BWSEL MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_2 LOFE2S_ReadWrite MAC_PORT_RX_LINKA_DFE_E0_AND_E1_OFFSET EMCRST EMCEN SM2RST MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PATTERN_LENGTH H6MAG DFEOBSBIAS CALMODE MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PDF_EYE_COUNT MAC_PORT_RX_LINKC_INTEGRATOR_DAC_OFFSET MAC_PORT_RX_LINKC_DFE_H1 MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_2 PER_ENA_ZCAL LOW_LATENCY ENA_RANK_PAIR SLICE_SEL_REG_BITS10_11 SLEW_TARGET_PR_OFFSET MRS_CMD_DATA_N3 MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP QUAD3_CLK18_BIT15 MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR OFFSET_BITS9_15 RD_EYE_SIZE_BITS10_15 NO_DQS_MASK MC_DDRPHY_DP18_PATTERN_POS_1 MEMINTD08_POS TMOD_CYCLES TWRMRD_CYCLES SINGLE_BIT_MPR_RP1 FINE_CAL_STEP_SIZE WR_PAR_ERR_MASK DP18_9_Populated ctl_stat sr_idle dfi_wrlvl_rank_sel dfi_wrlvl_mode MC_UPCTL_DFITRRDLVLDELAY1 PHY_CALIB_DONE EDC_H_BIST_DATA_PATTERN EDC_H_ECC_ERR_ADDR Egress0_Size debug_idma1_s_cpl_flit_remaining Req_LnI_RxPwrState Phy_Reg_Select PCIE_VF_MSI_EN_7 PHY1_RTune_Req PCIE_DEBUG_ADDR_RANGE2 STATIC_C_PLL_SDORDER EFUSE_DIN MC_SPLIT MEM_WIDTH FUTURE_DEXPANSION_RTE DAddrTimeOutType EVlanPrio ULPType0Length ULPType0Offset IWARP_SEQ_FLIT_DIS MPS_VF_RX_CTL_159_128 EN_UDP_CSUM_CHK HASH_PRIO_SEL_MAC EthType1 VlanClsEn_in MPS_CLS_DIPIPV6ID_2_TABLE iscsi_enable_cmp_mode INVLDRD CMD_CMP_MASK pll_sel MAC_PORT_MTIP_GATE_CTRL mac1g10g_ff_rx_empty an_pcs_tx_clk_ena an_dis_timer MAC_PORT_MAC_25G_50G_AM0 SHORT_DISCARD REG_LOWP_RXEMPTY PREAMBLE_DISABLE MAC_PORT_MTIP_1G10G_CL01_QUANTA_THRESH MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_2HI PHY_xS_present MAC_PORT_MTIP_KR4_PKG_ID0 MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_3 MAC_PORT_MTIP_CR4_DEVICE_ID1 MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_2 Lane9_algn_mrkr_lck MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_11 MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_13 MAC_PORT_MTIP_CR4_LANE_1_MAPPING MAC_PORT_MTIP_CR4_LANE_16_MAPPING RS_FEC_PCS_align_status T5_AE1_RXSTAT_LSNA MAC_PORT_REFISRC_CONTROL MAC_PORT_INEQUALITY_CONTROL_AND_RESULT INEQ PLLDIVA DRTOL MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_5_4 OS4X5 C1PRESET MAC_PORT_TX_LINKC_TRANSMIT_TAP_SIGN_APPLIED_REGISTER MAC_PORT_TX_LINKC_TRANSMIT_TAP_SIGN_OVERRIDE MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_5 GAIN_STAT MAC_PORT_RX_LINKA_PEAKED_INTEGRATOR HSEL RX_OVRKBPD FTIMEOUT H13GS MAC_PORT_RX_LINKB_DFE_OFFSET_CHANNEL MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_3 MAC_PORT_RX_LINKD_DFE_H1H2H3_LOCAL_OFFSET MAC_PORT_RX_LINK_BCST_RECEIVER_QCC_CONTROL FAIL_PASS_VALUE FORCE_RESERVED IPW_SIDEAB_SEL WOOO ECC_MUX MC_LMC_INITSEQ15 T_RCD0 T_RAS T_CCD PASR MPR_SEL RD_MID_TH QDR_ClkPhase NumPipeStages EDC_H_DBG_BIST_RD_DAT_CYC_CNT inp_cmdq_notempty ECmdWr HMA_TLB_DESC_4_L ADDR1_MIN HMA_SW_SYNC MAMST_INT_CAUSE HMA_MA_MST_ERR SGE_GTS MPS_VF_STAT_RX_VF_BCAST_FRAMES_H CIM_VF_EXT_MAILBOX_DATA_24 invalid value "%s" mps clear frag ethtype tos CHELSIO_T4_DEL_FILTER invalid priority "%s"; must be "0" or "1" no value for "%s" FLMcongMode: RxIntCounter: 0x%x [%u]
'%c' in %s is invalid TX Bias %fuA
SFF params rate-mode max-rate invalid queue "%s" loadcfg: incorrect number of arguments. failed to allocate memory for %d rules SYN_SENT CLOSING SYN_PEND TF_MIGRATING TF_LOCK_TID TF_TURBO cctrl_sel0 mod_schd_reason1 TF_RECV_SACK t_maxseg Scaling for receive window (0-14). Note: this is reverse of common definition. Timestamp offset from running clock PD index TF_DDP_BUF_INF ddp_rx2tx ddp_push_disable_1 ddp_psh_no_invalidate1 Hits_low tx_flush: %u, tx_oos_rxmt %u, tx_oos_txmt %u
DDP is off (which also disables indicate)
DDP is enabled, but no buffers are active && valid.
Indicate is off, which %-12s (%-2u), %s, lock_tid %u, rss_fw %u
IngHintEnable0 QueuesPerPageVFPF6 perr_align_ctl_fifo1 perr_eswitch_fifo1 err_bad_db_pidx3 err_bad_db_pidx1 ForceVFPF1DBtoLP SGE_ITP_CONTROL SGE_CTXT_DATA3 SGE_CTXT_MASK6 SGE_LA_RDPTR_3 SGE_LA_RDDATA_8 MSIXAddrHPerr RspCnt PCIE_STATIC_CFG1 PCIE_CORE_UTL_SYSTEM_BUS_CONTROL SMTD SWD1 SWD2 PCIE_CORE_UTL_STATUS OP3H OC0T VRB0 TXE3 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS PLDN TFTS PAAS RCPI PMC0 PC1S PC7S CPM3 GPIO4_OEn GPIO13_Out_Val GPIO10_IN KR_LOCK GPIO12 GPIO0 ARM_FAIL_int_cause DBG_EFUSE_BYTE0_3 STATIC_C_PLL_RANGEB RD_ADDR1 PVT_REG_DRVN_EN rank2_odt_write_sel dtu_err_b3 number_ranks MC_PCTL_TRCD dtu_wr_byte7 dtu_rd_byte7 dyn_soc_odt ISEL WLCAL MC_PVT_REG_TERMP MC_PVT_REG_HISTORY_TERMN MC_BIST_CMD MC_BIST_CMD_ADDR THRESHOLD0_EN MA_PMRX_DEBUG_CNT CL1_PAR_WRQUEUE_ERROR CL5_PAR_RDQUEUE_ERROR EDC_BIST_DATA_PATTERN EDC_BIST_USER_WDATA1 CIM_UP_ACC_INT_ENABLE CIM_IBQ_DBG_CFG POLADbgWrPtr CIM_MEM_ZONE2_BA CIM_MEM_ZONE5_VA TcpOptParserDisCh3 TcpOptParserDisCh1 EnableCLbkAFull TimerBackoffIndex11 ByteCountLimit TxUrgMode EnablePDUC DisablePDUCng PMMaxXferLen0 DropErrorIpHdrLen MTUIndex TP_TM_PIO_DATA TP_TX_MOD_QUEUE_WEIGHT4 ETpInTcpFifoPerr ETpInIpFifoPerr TP_INT_CAUSE TxRxmSyn ForceCong3 TP_FX_SCHED DbgLaFatalFreeze ULP_TX_CPL_PACK_SIZE1 strobe1 iespi3_fifo2x_Rx_framing_error DbgSel_L MPS_PORT_TX_PAUSE_STATUS FILT_VLAN_SEL CLR_INTR SET_INTR MPS_RX_PERR_INT_ENABLE MPS_PFVF_ATRB_FLTR12 MPS_RPLC_MAP_CTL MPS_RX_SE_CNT_CLR MPS_RX_DBG_CTL Ch1_Prty DataCh2 PortH MPS_PORT_STAT_TX_PORT_FRAMES_H MPS_PORT_STAT_RX_PORT_FRAMES_L MPS_PORT_STAT_RX_PORT_PPP6_L MPS_PF_STAT_RX_PF_BYTES_H MPS_CLS_BMC_MAC_ADDR_L Priority2 MPS_CLS_TCAM_X_L SlvNoBusStopEn SlvUnExpBusStartInt SlvUnExpNackMstInt FifoInjDataErrEn AuxAddr0 SMB_SLV_AUX_ADDR1 MacroCntClkCfg PhyAddr StopBits RDMA_permissive_mode CAUSE_MEMRF_1 CAUSE_DDPCF_1 ULP_RX_ISCSI_PSZ PERR_ENABLE_PRSDF_0 EOP_CNT_MR0 SourceBus MapDBG DBGICMDRANGE HASHBASE_ADDR mac_tx_rst NCSI_CH0_SADDR_LOW NCSI_CH1_SADDR_HIGH CH1_SADDR_HIGH MPS2NC_SOP_CNT BUS_STATE_MPS_OUT NCSI_MACB_NETWORK_STATUS NCSI_MACB_RX_RESOURCE_ERR Pmux_Tx_Loop Led1_Polarity_Inv XGMAC_PORT_EXT_LOS_STATUS XGMAC_PORT_EPIO_DATA0 XGMAC_PORT_EPIO_DATA3 AE_Train_Local TXDPRBSEN RXCPRBSRST RXCSIGDET LenErrFrameDis XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_4 XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_7 Resrv test_sel ber_count ACK TX_Pause_Okay BP_AN_Ability LFSR_Init NP_From_LP XGMAC_PORT_AE_RX_COEF_REQ TXSTAT_C2 MWT_DISABLE MDIO_OVR STICKY_MODE XGMAC_PORT_AE_PRBS_CTL FSM_TR_LCL FSM_CU_DIS XGMAC_PORT_AE_FSM_STATE XGMAC_PORT_HSS_TXA_TEST_CTRL EQMODE CXPRESET XGMAC_PORT_HSS_TXA_TAP0_IDAC_APP FDPC FNRND XGMAC_PORT_HSS_RXB_DIGITAL_EYE_CTRL XGMAC_PORT_HSS_TXC_TDM_BIASGEN_STANDBY_TIMER XGMAC_PORT_HSS_TXC_POLARITY XGMAC_PORT_HSS_TXC_TAP1_IDAC_OVR XGMAC_PORT_HSS_TXC_PWR_DAC XGMAC_PORT_HSS_TXD_MODE_CFG XGMAC_PORT_HSS_RXC_VGA_CTRL2 XGMAC_PORT_HSS_RXC_DIGITAL_EYE_CTRL XGMAC_PORT_HSS_RXD_DFE_H4 XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_1 TXDRST XGMAC_PORT_HSS_RX_DFE_D10_D11_OFFSET XGMAC_PORT_HSS_RX_DFE_H5 perr_dbp_fl_fifo err_rx_cpl_packet_size1 EDMA1_Sleep_Req debug_U_Tx_SOP1_cnt debug_PD_RdReq_SOP0_cnt debug_PD_RdRsp_SOP2_cnt debug_PD_WrReq_EOP1_cnt debug_PD_WrReq_Int2_cnt debug_flm_idma1_cache_hdr_active debug_CPLSW_SOP0_cnt debug_PC_Req_EOP2_cnt debug_st_edma3_align_sub debug_st_edma1_align_sub MSIXStiPerr DCAEn AutoPIOCookieMatch HMADCASTFirstOnly ReadyEnterL23 Scramble_Disable Full_Swing WrEOPMatchSOP RspErrCnt ReqBurstFrequency TimeoutIntEn Source LnG_RxPwrState LnB_RxStateReq LnH_CMD LnF_STAT Lane4LF Lane6FS DBG_CUST_EFUSE_OUT_EN T5_STATIC_M_PLL_RANGEA DBG_T5_STATIC_U_PLL_CONF1 DBG_T5_STATIC_U_PLL_CONF4 T5_STATIC_KR_PLL_P T5_STATIC_KX_PLL_ANALOGTUNE GPIO14_PE_En GPIO7_PE_En GPIO14_PS_En MEM_TO_INT_CAUSE ARB4_PAR_RDQUEUE_ERROR MA_EDRAM1_RDDATA_CNT0 CL9_WR_DATA_TO_ERROR CL6_RD_CMD_TO_EN CL5_RD_CMD_TO_ERROR CL9_RD_DATA_TO_ERROR CL1_RD_DATA_TO_ERROR MA_IF_PARITY_ERROR_ENABLE ma_cim_IntfPerr RssSynSteerEnable IdleCwndReno EOF_2 ULP_TX_ASIC_DEBUG_3 PM_RX_DBG_DATA MPS_TX_PAUSE_DURATION_BUF_GRP_TH2 MPS_TX_PAUSE_DURATION_BUF_GRP_TH15 FRM_ERR_INT PETYPE1 TxOutLpbk1_CGEN MPS_TRC_FILTER0_RSS_HASH cim_split_enable MstRxFifo ALN_SDC_ERR_0 ChipID POCLIPTID0 SRAMDEEPSLEEP_STAT ActCntIPv6Tzero LE_HASH_COLLISION TxFIFO_full MtipRefReset AEC2Reset MAC_PORT_LED_COUNTLO an_ena RXCCONFIGSEL HSSDIVSELA runt LPI_REQ MAC_PORT_EEE_TX_1G_SLEEP_TIMER OFFSER_ADJUST_SIGN LOOPBACK_EN MAC_PORT_VLANRECEIVEDOK MAC_PORT_IFOUTERRORSHI MAC_PORT_ETHERSTATSPKTS65TO127OCTETSHI MAC_PORT_MTIP_SGMII_AN_EXPANSION MAC_PORT_MTIP_MODE_CTL_SEG MAC_PORT_MTIP_VLAN_TPID_5 FaultDet PHYXS PAGE_RCVD MAC_PORT_BEAN_XNP_1 MAC_PORT_BEAN_ABILITY_1_LANE1 MAC_PORT_BEAN_XNP_1_LANE1 MAC_PORT_BEAN_REM_ABILITY_0_LANE2 Preset MAC_PORT_FEC_KR_LP_STAT CN1_STAT T5_TXSTAT_C1 MAC_PORT_AE_PRBS_CTL_2 T5_AE3_RXSTAT_C0 SPEDIV NXTPOL AECMD1312 MAC_PORT_TX_LINKB_TRANSMIT_DCC_OVERRIDE MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_APPLIED MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_APPLIED MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED T5WERRFLG FTOOFAST T5LFRC H5OSN_ReadWrite H6SN_ReadOnly LSSDT MAC_PORT_RX_LINKB_RECEIVER_TEST_CONTROL MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_1 MAC_PORT_RX_LINKB_DFE_H3 MAC_PORT_RX_LINKB_DFE_H8_AND_H9 MAC_PORT_RX_LINKC_DFE_OFFSET_EVN1_EVN2 MAC_PORT_RX_LINKC_DFE_H12 MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD1_ODD2 START_INIT_CAL READ_LATENCY_OFFSET MC_DDRPHY_PC_RESETS PC_ERROR CC_ERROR_MASK ABORT_ON_CAL_ERROR ERROR_DQS_ALIGN_MASK ERROR_DIGITAL_EYE_MASK DI_ADR4_ADR5 MC_ADR_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL POST_CUR_SEL_BITS10_11 GIANT_MUX_TEST_VAL ANALOG_INPUT_STAB2 TX_TRISTATE_CNTL DELAY_PING_PONG_HALF QUAD1_CLK16_BIT1 RDCLK_SELECT1 MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR MATCH_STEP_RIGHT OFFSET_ERR_MASK MC_DDRPHY_DP18_PLL_CONFIG0 MEMINTD14_POS PER_RDCLK_UPDATE_DIS MC_DDRPHY_SEQ_RD_WR_DATA0 MC_DDRPHY_SEQ_CONFIG0 MULTIPLE_REQ_SOURCE CUSTOM_INIT_WRITE SINGLE_BIT_MPR_RP0 MC_DDRPHY_RC_CONFIG1 INVALID_ADDRESS WR_PAR_ERR INVALID_ADDRESS_MASK MC_DDRPHY_APB_DP18_POPULATION MC_UPCTL_TMRD MC_UPCTL_TCL MC_UPCTL_TRRD MC_UPCTL_TZQCS odt_len_bl8_w dfi_data_byte_disable dfi_freq_ratio dfi_init_start0 dfi_init_start MC_P_BIST_CMD_ADDR InvOnGTSSync err_th3_max_fetch fatal_deq_drdy SGE_DEBUG_CONM debug_idma1_idma2imsg_cmp_out_nocpl SGE_WC_EGRS_BAR2_OFF_PF VfIQsPerPage Req_LnM_RxStateDone Cur_LnJ_RxPwrState Lane15LF PF1_DState DBG_CUST_EFUSE_BYTE28_31 HMA_DIS_PAGE_HINT IBQPCIEParErr EcnModeCwr ULPType2Offset align_ctl_fifo_perr_set0 stag_fifo_perr_set3 shove_first GRE_EN ORG_VALUE MPS_RX_CNT_NVGRE_PKT_TO_TP0 MPS_STAT_STOP_UPD_RX_VF_128_159 VlanLkpEn iscsi_eff_offset_en CLCAM_INIT_BUSY HASHTBLSIZE CmdTidErr LE_DB_HASH_MASK_GEN_IPV4 pcs10g_reset_sd_tx_clk AEC_RX_LANE_ID_1 MAC_PORT_AEC_DEBUG_LO_0 CU_C1_ACK_VALUE CUF_C1_UPDATE mac1g10g_rx_sfd_o sgmii_sg_hd Perr_rx14_pcs100g MAC_PORT_PTP_PPS MAC_PORT_MTIP_1G10G_FRM_LENGTH_TX_MTU MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS64OCTETS MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS512TO1023OCTETS MAC_PORT_MTIP_1G10G_RX_ETHERSTATSJABBERS MAC_PORT_MTIP_1G10G_IF_STATUS MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_4HI MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_5HI RX_LPI_ACTIVE MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_1 Speed_selection MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_1 Lane_7_blck_lck Lane_4_blck_lck Lane_18_blck_lck Lane18_algn_mrkr_lck RS_FEC_Bypass_Correction tx_datapath_restart T5_AE1_RXSTAT_TF GTORLT AS4X2 MAC_PORT_TX_LINKA_TRANSMIT_AE_C2_INIT_EXTENDED MAC_PORT_TX_LINKA_TRANSMIT_AE_V2_LIMIT_EXTENDED MAC_PORT_TX_LINKB_TRANSMIT_2X_SEGMENT_APPLIED MAC_PORT_TX_LINKB_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE MAC_PORT_TX_LINKC_TRANSMIT_AE_VM_LIMIT_EXTENDED MAC_PORT_TX_LINK_BCST_TRANSMIT_1X_SEGMENT_APPLIED MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED OVRPK QCCIND INDEX H8SN SS_QUAD_CAL QUAD3_PWR_CTL MT_DQ_SEL_QUAD MC_LMC_CMD4 MC_LMC_INITSEQ8 WR_RTP SMR1_RFU1 MPR RK0W MWData BWDataVld EdramAddr stall_rmw dead_cycle1_max_op MPS_VF_STAT_TX_VF_BCAST_BYTES_L sched-class Port vlan invalid vlan "%s" CachePriority: FLMcontextID: invalid number of bytes "%s" CLOSED NewReno RDMA DTLS dack TF_DACK_NOT_ACKED TF_INIT peer_fin TF_PEND_CTL1 TF_UNUSED snd_una_raw Offset of receive fragment 0 start sequence from rcv_nxt rx_frag1_start_idx_offset rx_frag1_ptr_raw iss_ulp tx_oos_txmt ddp_pshf_enable_0 TF_DDP_PSH_NO_INVALIDATE0 TF_DDP_PUSH_DISABLE_1 OPT_0_ULP_MODE STATE:
rcv_adv %-5u << %-2u == %u (recv_scaleflag %u rcv_scale %u active open %u)
tx_channel %u, tx_channel1 %u, tx_channel0 %u
tx_hdr_ptr 0x%-6x tx_last_ptr 0x%-6x tx_compact %u
RECEIVE BUFFER:
cq_idx_sq %u, cq_idx_rq %u
!!! Invalid DDP buf 0 valid, but buf 1 active.
tls_key_mode GlobalEnable QueuesPerPagePF6 QueuesPerPageVFPF7 perr_flm_cntxmem HP_Disable TimerValue0 err_bad_upfl_inc_credit0 StatMode SGE_LA_RESERVED_8 PCIESINT PCIE_INT_CAUSE TagCpl CfgdMaxPyldSzRx MaxTag Register PCIE_FID CDEBUGSelH CH1_EOP CH0_EOP BufWrCnt UPES RVID OP3D RLCI GPIO2_Out_Val GPIO1 U_OCLK_En GPIO13_ACT_LOW GPIO2_ACT_LOW GPIO1_ACT_LOW STATIC_C_PLL_TUNE PVT_REG_TERMN_EN PVT_REG_TERMP_B rpmem_dis MC_PCTL_TMOD dtu_wr_rank dtu_generate_random MC_PCTL_DTUWD1 dtu_wr_byte9 dtu_rd_byte1 MC_PCTL_PVTTUPDDLY WL CK5PONR CK5POND CK4PONR MC_DDR3PHYAC_CLKENR RDSDVT MC_DDR3PHYDATX8_WDBDR7 DSINV MC_PVT_REG_HISTORY_DRVN MC_INT_CAUSE STATIC_RKS MC_BIST_STATUS_RDATA MA_SGE_TH1_DEBUG_CNT MA_PCIE_DEBUG_CNT MEM_WRAP_INT_ENABLE MEM_WRAP_ADDRESS ARB1_PAR_RDQUEUE_ERROR_EN CL5_PAR_WRQUEUE_ERROR_EN CL7_PAR_RDQUEUE_ERROR_EN TDebugInt TieQInParErrInt BlkWrPlInt CIM_UP_INT_ENABLE CIM_IBQ_DBG_DATA CIM_OBQ_DBG_DATA CIM_DEBUGCFG SYNCookieNoOptions IPIdentSplit PMRxMaxPage EnableVlanCheck EnableArpMiss EnableTnlCngLpbk EnableTnlCngHdr IndicateSize RearmDdpOffset EnableDeferPDU SynShiftMax KeepaliveMaxR2 ChnCount1 ChnUndFlow3 TX_MOD_RATE_LIMIT_INC FlstInitEnable RxUrgDataDrop TxDupAckInc CommitLimit2 TxModXoff0 TP_PROTOCOL_DATA3 ULP_TX_SE_CNT_CLR PM_RX_STAT_COUNT ocspi1_Rx_framing_error icspi3_Rx_framing_error oespi0_ofifo2x_Tx_framing_error DbgModeCtl_H PPPAndPause MPS_PORT_TX_PAUSE_CTL2 Prty4 MPS_RX_PG_HYST_BG1 CDM1 MPS_RX_PERR_ENABLE ETYPE MPS_RX_PT_ARB2 PGD MPS_RX_SE_CNT_IN7 LPBK_CNT1 DropEn DataPt0 SubPrtL MPS_PORT_TX_MAC_RELOAD_CH0 MiscPerr MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L MPS_PORT_STAT_TX_PORT_1519B_MAX_H MPS_PORT_STAT_LB_PORT_1519B_MAX_H MPS_PORT_STAT_RX_PORT_MTU_ERROR_H MPS_PF_STAT_RX_PF_BYTES_L MPS_PF_STAT_RX_PF_BCAST_FRAMES_H Valid VF_Valid UnicastEnable MstRxByteCnt SlvAlrtSts SlvErrIntEn SlvRxAddrInt VersionID Crc1_En ULP_RX_INT_ENABLE ENABLE_APF_0 ENABLE_AF_0 ULP_RX_INT_CAUSE CAUSE_DDPCF_0 IscsiTagMask ULP_RX_STAG_ULIMIT PERR_ENABLE_DDPCF_1 TID ULP_RX_SE_CNT_CLR ULP_RX_SE_CNT_CH1 MapXGMAC0 MapMI PIORstMode LE_DB_SIZE ServerHit DBGICMDMSKTYPE DBGITINDEX LE_DB_DBGI_REQ_MASK NCSI_TX_FIFO_CNT CopyAllFrames NCSI_MACB_SQE_TEST_ERR xg2g_speed_mode XGM_Tx_pause_frame XGMAC_PORT_LA_TX_0 HSSREFCLKSEL HSSDIVSEL RXCPRBSSYNC XGMAC_PORT_XGM_RX_CFG XGMAC_PORT_XGM_RX_TYPE_MATCH_1 XGMAC_PORT_XGM_STAT_RX_MCAST_FRAMES XGMAC_PORT_XGM_STAT_RX_CRC_ERR_FRAMES XGMAC_PORT_PCSR_STATUS soft_reset Noncer_Match Bypass_LFSR XGMAC_PORT_AN_BREAK_LINK_TIMEOUT AESOURCE XGMAC_PORT_HSS_TXA_TAP0_COEFF XGMAC_PORT_HSS_RXA_PH_ROTATOR_POSITION1 PEAK XGMAC_PORT_HSS_RXB_DFE_FUNC_CTRL XGMAC_PORT_HSS_TXC_SEG_DIS_APP XGMAC_PORT_HSS_RXC_DAC_DPC XGMAC_PORT_HSS_RXD_INTERNAL_STATUS RXAEN XGMAC_PORT_HSS_RX_PH_ROTATOR_CTRL XGMAC_PORT_HSS_RX_VGA_CTRL3 err_wr_len_too_large2 perr_PD_RdRspData perr_mgt_bar2_fifo debug_PD_RdReq_EOP3_cnt debug_PD_RdRsp_SOP1_cnt debug_uP_Full debug_flm_idma1_ctxt_hdr_active debug_st_flm_idma0_cache SGE_DEBUG_DATA_HIGH_INDEX_12 SGE_DEBUG_DATA_LOW_INDEX_1 debug_idma0_qid VPDTimeout BAR2Req MstReqRdRRASimple CMDDCASTFirstOnly RVF MSTPauseDone PCIE_VF_MSIX_EN_2 RcvdMAReqCookie PM_CurrentState PCIE_CORE_LANE_SKEW PCIE_CORE_TRANSMIT_COMPLETION_FC_CREDIT_STATUS Eql_Redo_Disable Include_Initial_FOM After24ms ReqCtl_Dynamic_CGEN xmlh_ltssm_state_rcvry_eq LnG_RxStateReq LnA_CMD Lane7LF GPIO16_Out_Val MCIMPED2_out DBG_FEREADCLK T5_STATIC_M_PLL_RANGEPRE DBG_T5_STATIC_M_PLL_CONF6 T5_STATIC_C_PLL_STOPCLKA T5_STATIC_U_PLL_DCO_BYPASS T5_STATIC_U_PLL_SLEEP GPIO8_PS_En MA_ULPTXRX_WRDATA_CNT CIM_ULP_TX_PKT_ERR_CODE VnTagEthEnable IdleCwndTahoe RxmtCwndTahoe OverdriveTahoe ENDIANESS_CHANGE SOF_2 channel_sel intf_sel MPS_RX_PAUSE_GEN_TH_2_1 TxSchLpbk0_CGEN PtTx atomic_req_qno ISCSI_CGEN ULP_RX_CHNL1_CTX_ERROR_COUNT_PER_TID LTSSM ValidPerr SRVRINITBUSY LE_SRVR_VF_SRCH_TABLE AET3Reset MAC_PORT_EPIO_DATA2 MAC_PORT_WOL_STATUS Perr2_rx_sd RXAQUIET RXBCONFIGSEL RXDQUIET_STATUS PCSSEG5_CGEN WAKE_TIMER MAC_PORT_EEE_RX_10G_WF_TIMER RX_LOC_FAULT MAC_PORT_MTIP_TS_TIMESTAMP CuLinkStatus MAC_PORT_MTIP_SGMII_DEVICE_NP MAC_PORT_MTIP_SGMII_LINK_TIMER_LO SGMII_ENA CL22 blocklockLL Lane5 Lane11 MAC_PORT_MTIP_PCS_BIP_ERR_CNT_17 MAC_PORT_BEAN_REM_ABILITY_2_LANE3 MAC_PORT_LP_BEAN_XNP_0_LANE3 T5_RXREQ_C2 T5_TXREQ_C0 MAC_PORT_AET_SIGNAL_LOSS_DETECTION_1 MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_4 T5_TX_RSYNCC MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 DCCTIMEEN DCCAAMP MAC_PORT_TX_LINKD_TRANSMIT_COEFFICIENT_CONTROL MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_CONTROL MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_1 FLOFF LOFO2 MAC_PORT_RX_LINKA_DFE_OFFSET_EVN3_EVN4 T5LFSEL MAC_PORT_RX_LINKA_DFE_H5 H12GS TESTMODE MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_1 MAC_PORT_RX_LINKC_DFE_OFFSET_ODD3_ODD4 MAC_PORT_RX_LINKD_DFE_H12 MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_2 MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_CONTROL MAC_PORT_RX_LINK_BCST_DFE_H3 ENA_PER_RDCLK_ALIGN MC_DDRPHY_PC_CONFIG0 RANK_OVERRIDE PC_ERROR_MASK ENA_DIGITAL_EYE ADDR_MIRROR_RP3_SEC ADR_DELAY_BITS9_15 ADR_TEST_DATA_EN MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP0 QUAD2_CLK18_BIT14 DQ_WR_OFFSET_N0 MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR DQS_GATE_DELAY_N2 NO_EYE_DETECTED_MASK WL_ERR_CLK16 MC_DDRPHY_DP18_RD_DIA_CONFIG4 MC_DDRPHY_SEQ_RESERVED_ADDR0 BURST_WINDOW ATEST_CNTL mrrstat_beat1 MC_UPCTL_MCFG MC_UPCTL_TEXSR MC_UPCTL_TZQCSI dfi_rdlvl_edge MC_UPCTL_DFITRRDLVLEN MC_UPCTL_DFITRRDLVLGATEDELAY0 MC_P_DEBUG_RPT MC_P_BIST_ERR_FIRST_ADDR err_bad_db_pidx4 fatal_deq SGE_DBG_GTS_PKT_CNT debug_PC_Rsp_EOP_cnt debug_idma0_idma2imsg_cmp_in_drdy Req_LnE_RxStateDone Lane15FS STATIC_SWMC0Rst_ DBG_STATIC_C_PLL_CONF5 DBG_STATIC_U_PLL_CONF6 DBG_CUST_EFUSE_BYTE40_43 ULP_TX_TLS_CTL TlsPerrEn edma_in_fifo_perr_set2 shove_middle MPS_VF_TX_CTL_255_224 MPS_RX_CONGESTION_THRESHOLD_BG2 MPS_RX_CNT_NVGRE_PKT_LPBK1 MPS_RX_CNT_GENEVE_PKT_LPBK1 MPS_PORT_CLS_NCSI_ETH_TYPE MPS_CLS_NCSI_ETH_TYPE MPS_CLS_DIPIPV6MASK_3_TABLE MPS_CLS_TCAM_DATA0 TcamInvldEnt LE_DB_ERR_CMD_TID LE_DB_DBG_MATCH_DATA_MASK PRI_HFILT PRI_SRVR Enable_50G Led1_thi mac40g100g_reset_ff_rx_clk AEC_SYS_LANE_TYPE_3 mac1g10g_tx_empty mac1g10g_tx_sfd_o periodic_alarm tx_mac40g rx_status_mac1g10g RXDERROFLOW MAC_PORT_PTP_STATUS FRM_LEN_SET MAC_PORT_MTIP_1G10G_RX_IFINUCASTPKTSHI MAC_PORT_MTIP_1G10G_RX_IFINBROADCASTPKTSHI MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS1024TO1518OCTETS MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_3 DUPLEx_MODE MAC_PORT_MTIP_KR_PCS_DEVICE_IDENTIFIER_1 Speed_selection1 LANE_2_ALIGN_MRKR_LCK MAC_PORT_MTIP_KR4_LANE_3_MAPPING Lane_2_blck_lck Lane_17_blck_lck Lane_10_blck_lck Lane13_algn_mrkr_lck MAC_PORT_MTIP_CR4_CORE_REVISION T5_AE1_RXSTAT_FEC MAC_PORT_REFISINK_CONTROL T5_TX_ENFFE4 SASCMD OS2X0 DATASIGN MAC_PORT_TX_LINKC_TRANSMIT_TAP_3_COEFFICIENT MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE MAC_PORT_TX_LINKC_TRANSMIT_AE_C1_INIT2_EXTENDED RAOFF DASEL FACCPL DCVSCTMODE DPCLKNQ ROTFCMP DCCQCCHOLD MAC_PORT_RX_LINKB_RECEIVER_QCC_CONTROL MAC_PORT_RX_LINKC_RECEIVER_AC_COUPLING_VALUE MAC_PORT_RX_LINKD_RECEIVER_IQAMP_CONTROL_2 MAC_PORT_RX_LINK_BCST_RECEIVER_POWER_MANAGEMENT_CONTROL ENA_PER_RD_CTR DDR4_IPW_LOOP_DIS FULL_RANGE MC_DDRPHY_DP18_WRCLK_AUX_CNTL DQS_ALIGN_JITTER MT_DP18_PLL_LOCK_SUM MC_LMC_MCOPT1 MC_LMC_INITSEQ3 MC_LMC_CMD13 MC_LMC_SMR2 MC_LMC_SMR4 MC_LMC_ODTR0 PHYUPD_ERR RMW_DWRITE_EN STATIC_PPEN EDC_H_DBG_BIST_WDATA_INTF EdramWByteEn EDC_H_DBG_MA_RD_EXP_DAT_CYC_CNT EDC_H_DBG_FSM_STATE ECmdLen HMA_CFG ADDR2_MAX ENTER_SYNC dumpstate pl mbdata edc0 pmrx xgmac Drop ethtype ovlan pf %d
%08x%08x tx %dC
level unknown scheduler parameter "%s" Unknown ID tvp->hi-tvp->lo+1<=64 FIN_WAIT_2 ESTABLISHED_RX TF_NAGLE TF_TIMER TF_DACK_TIMER rdma_flm_error tx_pdu_out rcv_adv snd_rec main_slush Offset of receive fragment 3 start sequence from rcv_nxt CQ index of CQ for SQ qp_id ddp_buf1_indicate dack_mss %u dack %u, dack_not_acked: %u
aux3_slush: 0x%x, unused: buf0 0x%x, buf1: 0x%x, main: 0x%x
%u %u %u %u %u %u
QID PIDX HostPageSizePF0 perr_flm_DbpFifo SGE_PERR_ENABLE1 perr_isw_dbp_fifo err_pcie_error2 CachePtrCnt EgrThreshold SGE_TIMER_VALUE_0_AND_1 SGE_TIMER_VALUE_2_AND_3 MaxRspCnt2 EgrCtxtOpMode DLDnPCIeCRstMode PCIE_DMA_CTRL PCIE_MA_CTRL PCIE_FUNC_INT_CFG PCIE_DMAW_SOP_CNT PCIE_DMAR_REQ_CNT PCIE_CMDR_RSP_ERR_CNT BufRdCnt RFTS ON3H IN3H RCAP PLUI CRSI PMC7 PC0S PC2I INTXStat PortEn GPIO12_CHG_DET GPIO11_CHG_DET GPIO6_CHG_DET pll_lock_lost_int_enbl P_LOCK DBG_EFUSE_BYTE12_15 DBG_STATIC_U_PLL_CONF STATIC_M_PLL_RESET DBG_PVT_REG_TERMN PVT_REG_TERMN_B hw_low_power_en phy_calibdone rank1_odt_default MC_PCTL_TCKE dtu_enable dtu_wr_byte6 dtu_wr_byte4 MC_PCTL_DTUEAF MC_DDR3PHYAC_PMBDR0 MC_DDR3PHYAC_PLLCR1 WDSDVT MC_BIST_USER_WDATA2 ARB3_PAR_WRQUEUE_ERROR_EN TP_DMARBT_PAR_ERROR EDC_BIST_CMD BootLen OBQSGEParErr SglWrBootIntEn RsvdSpaceIntEn CIM_MEM_ZONE0_BA MEM_ZONE_BA TP_PC_CONFIG2 EnableRssErrCheck EnableRstPaws EnableIPv6RSS EnableNonOfdHybRss TP_PARA_REG0 InitialSSThresh RxCoalesceSize HighSpeedCfg OnFlyDDPEnable EnableBytePersist TP_KEEP_IDLE ULPType6Field ULPType4Field SYNIp6Sel ChnOvrFlow3 RxTimerDackFirst TxChnXoff3 TxModXoff3 TP_DBG_LA_CONFIG TP_DBG_LA_DATAH lso_hdr_sram_perr_set1 ULP_TX_ERR_MSG2CIM ULP_TX_ULP2TP_BIST_ERROR_CNT ULP_TX_LA_RESERVED_7 ULP_TX_LA_WRPTR_10 DbgSel_H RST MPS_RX_PG_RSV0 MPS_RX_PG_RSV7 MPS_RX_PG_SHR_BG2 MPS_RX_OCH_CTL MPS_BMC_MTU ST1 MPS_RX_CLS_DROP_CNT3 MPS_PORT_RX_VF_MAP0 FIXED_PFVF_MAC FullCh2 MPS_TX_DEBUG_REG_TX2MAC_10 SOPPt3 DataPt2 TfPort PktFifo MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L MPS_PORT_STAT_TX_PORT_65B_127B_L Cls_Priority CPL_SWITCH_ZERO_ERROR zero_cmd_ch0 SMB_MST_CTL_CFG SlvNoBusStopInt AuxAddr1Val SMB_COMMAND_CODE0 I2CM_OP ENABLE_MEMRF_1 ENABLE_TPTCF_0 ENABLE_MPARF_0 CAUSE_MEMRF_0 ULP_RX_TDDP_ULIMIT PERR_ENABLE_MEMRF_0 PERR_ENABLE_MPARC_1 EN_DBG_H PL PL_INT_MAP3 PL_PL_PERR_INJECT FatalPerr PL_TIMEOUT_STATUS0 flush_rx_fifo rx_byte_swap NC2MPS_EOP_CNT EnMgmtPort RxEnHalfDup ColEvent RxComplete NCSI_MACB_SPECIFIC_1_HIGH XAUI20_Rem_Pre TXFIFO_Reset rx_sop_count XGMAC_PORT_LINK_STATUS txrst RXCPRBSFRCERR RXDEARLYIN RXBSIGDET XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_5 XGMAC_PORT_XGM_STAT_TX_BCAST XGMAC_PORT_XAUI_STATUS FECEn Page_Received NP_Indication 10GBASE_KR_FEC_neg TXREQ_CPRE MANUAL_RDY DRVOFFT VHSEL XGMAC_PORT_HSS_TXA_EXT_ADDR XGMAC_PORT_HSS_TXB_DRIVER_OVR_CTRL DMSEL LBERROR D10SN OES BER6 FH1 XGMAC_PORT_HSS_RXB_DFE_D00_D01_OFFSET XGMAC_PORT_HSS_TXC_DRIVER_MODE FMAX XGMAC_PORT_HSS_RX_DFE_H3 XGMAC_PORT_HSS_RX_DFE_FUNC_CTRL FetchBurstMax2 HP_Int_Thresh_Low debug_PD_RdRsp_EOP3_cnt debug_CPLSW_TP_Rx_SOP1_cnt SGE_DEBUG_DATA_LOW_INDEX_0 debug_st_dbp_thread3_main debug_flm_cache_agent debug_imsg_cpl MstTimeoutPerr CFGInitDoneErr RcvdPIOReqCookie PCIE_CORE_PORT_FORCE_LINK Link_Number PCIE_CORE_VC0_POSTED_RECEIVE_QUEUE_CONTROL VC1_PH_Credits VC1_NPD_Credits PCIE_CORE_GEN3_EQ_PRESET_COEFF CMD_Static_CGEN MST_RspRdQPerr CplStatus PCIE_DBI_TIMEOUT_CTL PCIE_DBI_TIMEOUT_STATUS1 pm_linkst_l2_exit LnH_RxStateReq LnF_RxPwrState Lane5LF DBG_TVSENSE_EN DBG_T5_STATIC_C_PLL_CONF2 DBG_T5_STATIC_C_PLL_CONF3 T5_STATIC_U_PLL_RANGEB MA_EXT_MEMORY1_WRDATA_CNT1 MA_EDRAM1_RDDATA_CNT1 MA_TIMEOUT_CFG CL12_WR_DATA_TO_ERROR CL4_RD_DATA_TO_EN CL0_RD_CMD_TO_ERROR CL8_IF_PAR_EN CL6_IF_PAR_EN CL2_IF_PAR_EN OBQSGERx0ParErr EthUpEn TNLFcoeEn TSO_ETHLEN_EN sge2ulp_data_perr_set PTCPORT1 MPS_RX_PAUSE_GEN_TH_3_1 MPS_TX_PAD_CTL TP2MPS_Ch0 MPS_TX_PFVF_PORT_DROP_CTL off_pending VfFiltEn VfFiltData TP_Part_CGEn MC0_Part_CGEn PERR_RSVD0 MAC1 Rev LE_DEBUG_LA_SEL_DATA SigDetCtrl MAC_PORT_EPIO_OP Perr1_rx_sd HSSPLLLOCKB TXAQUIET_STATUS MAC_PORT_CGEN MAC_PORT_EEE_RX_1G_QUIET_TIMER MAC_PORT_MTIP_TX_FIFO_SECTIONS MAC_PORT_AFRAMESTRANSMITTEDOKHI MAC_PORT_AOCTETSTRANSMITTEDOKHI MAC_PORT_IFINERRORS MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3 MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5 ExtdCapability MAC_PORT_MTIP_WAN_RS_COL_CNT MAC_PORT_MTIP_MDIO_CFG_STATUS MAC_PORT_MTIP_PCS_CTL MAC_PORT_MTIP_PCS_CTL2 10GBASE_X AMLOCK15 AMLOCK12 MAC_PORT_MTIP_PCS_LANE_MAP_12 BEAN_ABILITY ACKNOWLEDGE TOGGLE MAC_PORT_BEAN_ABILITY_0_LANE1 MAC_PORT_BEAN_ETH_STATUS_LANE3 enable_tr MAC_PORT_FEC_NCERR_CNT_0 T5_AE0_RXSTAT_C2 MAC_PORT_AE_KR_STATUS_1 CE_DECS MAC_PORT_AET_ZFE_LIMITS_0 MAC_PORT_AET_STAGE_CONFIGURATION_2 RCCTL1 MAC_PORT_MACRO_TEST_CONTROL_5 MAC_PORT_PLLA_MACRO_TEST_CONTROL_1 T5SLEW MAC_PORT_TX_LINKA_TRANSMIT_DCLK_DRIFT_TOLERANCE DCCTIMEDOUT DCCLOCK DCCAEN DCCCLK SLEWCODE MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_4 MAC_PORT_TX_LINKC_TRANSMIT_AMPLITUDE MAC_PORT_TX_LINKD_TRANSMIT_TEST_CONTROL MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_OVERRIDE_CONTROL MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C0_INIT_EXTENDED T5_RX_CFGACT SYNCST MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_3 LOFO3S_ReadWrite LOFO3 H4OSN_ReadOnly H4ESN_ReadOnly H5EGS MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_1 MAC_PORT_RX_LINKB_DYNAMIC_DATA_CENTERING_DDC MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_3 MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_ERROR_COUNT MAC_PORT_RX_LINKD_RECEIVER_DACA_MIN_AND_DACAZ MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_ERROR_COUNT MAC_PORT_RX_LINKD_DFE_H6_AND_H7 MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_CONTROL MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 MC_DDRPHY_PC_BASE_CNTR1 APB_ERROR_MASK MC_DDRPHY_PC_IO_PVT_FET_CONTROL PVT_OVERRIDE SLEW_CTL_SEL_BITS4_5 SYSCLK_ROT_OVERRIDE MC_DDRPHY_ADR_GIANT_MUX_RESULTS_A1 MC_DDRPHY_DP18_WRCLK_EN_RP MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP DQS_GATE_DELAY_N0 NO_EYE_DETECTED MC_DDRPHY_DP18_WR_CNTR_STATUS2 INVALID_NS_SMALL_R SLEW_CTL MC_DDRPHY_DP18_DFT_WRAP_STATUS ERROR MEMINTD17_POS MEMINTD22_POS SYSCLK_DQSCLK_OFFSET MC_DDRPHY_DP18_DQSCLK_OFFSET RD_DEBUG_SEL MC_DDRPHY_SEQ_RESERVED_ADDR3 MC_DDRPHY_SEQ_ODT_RD_CONFIG0 ODT_RD_VALUES_x2plus1 TRC_CYCLES ADVANCE_RD_VALID PERFORM_RDCLK_ALIGN DQ_SEL_QUAD MC_DDRPHY_APB_CONFIG0 DP18_1_Populated dtu_err_b7 MC_UPCTL_TCKESR MC_UPCTL_DFITRRDLVLRESP2 MC_P_INT_CAUSE STATIC_AWEN STATIC_WLAT STATIC_ALIGN EDC_H_ECC_ERR_DATA_RDATA SGE_INT_CAUSE6 debug_PC_Rsp_SOP_cnt VfMaxWCSize Req_LnN_RxStateDone Cur_LnL_RxPwrState PCIE_PHY_FS_LF7 Lane14LF PHY1_RTune_Ack PF7_DState STATIC_M_PLL_STOPCLKB STATIC_C_PLL_FASTSTOP STATIC_C_PLL_LFTUNE_32_40 DBG_STATIC_KX_PLL_CONF1 STATIC_KX_PLL_CCALLOAD DBG_STATIC_C_PLL_CONF6 DIS_BG_ARB CRxPktXt stag_fifo_perr_set1 dma_fifo_perr_set2 push_first MPS_RX_FIFO_1_CTL GENEVE_VER_CHK_EN MPS_RX_CNT_TNL_ERR_PKT_MAC1 Err_UDP_Payload_Len ClsTrcVNI ClsTrcVF MPS_CLS_DIPIPV6ID_1_TABLE DataPortNum LE_DB_SRVR_START_INDEX SRAM_SRVR_HIT LE_DB_HASH_TBL_BASE_ADDR LE_DB_SSRAM_TID_BASE pcs10g_reset_xfi_rxclk AEC_SYS_LANE_SELECT_3 MAC_PORT_AEC_XGMII_TIMER_HI_100G CRI_FSM_CUR_STATE CUF_C0_FSM_DEBUG MAC_PORT_AEC_DEBUG_HI_1 mac40g100g_tx_underflow mac1g10g_pause_on sgmii_sg_page_rx Perr_tx2_pcs100g Perr_rx_pcs1g MAC_PORT_MTIP_1G10G_TX_IPG_LENGTH MAC_PORT_MTIP_1G10G_CREDIT_TRIGGER MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOCTETS MAC_PORT_MTIP_1G10G_RX_IFINBROADCASTPKTS MAC_PORT_MTIP_1G10G_RX_ETHERSTATSUNDERSIZEPKTS MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS128TO255OCTETS MAC_PORT_MTIP_1G10G_RX_ETHERSTATSFRAGMENTSHI MAC_PORT_MTIP_1G10G_RX_AINRANGELENGTHERRORS MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS1024TO1518OCTETSHI MAC_PORT_MTIP_1G10G_TX_AMACCONTROLFRAMESHI MAC_PORT_MTIP_KR4_PKG_ID1 Block_lock MAC_PORT_MTIP_CR4_BASE_R_STATUS_1 Lane7_algn_mrkr_lck MAC_PORT_MTIP_CR4_LANE_6_MAPPING MAC_PORT_MTIP_CR4_LANE_15_MAPPING fec_align_status MAC_PORT_MTIP_RS_FEC_SYMBLERR0_HI RS_FEC_enabled_status TXREQ_FEC MAC_PORT_VBGENDOC_CONTROL MAC_PORT_INEQUALITY_HIGH_LIMIT_MASK C3UPDT AS4X6 AS1X6 OS4X1 TESTENA C2INIT1 MAC_PORT_TX_LINKB_TRANSMIT_TAP_SIGN_APPLIED_REGISTER MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_7_6 MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C3_INIT2_EXTENDED OVRAC HBISTRST INTDACEGS INTDACE MAC_PORT_RX_LINKA_DFE_H1ODD_DELTA_AND_H1EVEN_DELTA MAC_PORT_RX_LINKA_RECEIVER_QCC_CONTROL MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2 MAC_PORT_RX_LINKB_RECEIVER_DCD_CONTROL MAC_PORT_RX_LINKC_CDR_ANALOG_SWITCH MAC_PORT_RX_LINKD_PEAKED_INTEGRATOR MAC_PORT_RX_LINKD_DFE_TAP MAC_PORT_RX_LINK_BCST_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL QUAD3_EDGES DP18_DFT_ERROR ITERATION_CNTR DQS_ALIGN_ITER_CNTR DP18_HS_PROBE_A_SEL MT_PVTP RDIMM MC_LMC_CMD3 MC_LMC_INITSEQ11 MC_LMC_DBG0 AL ALERT_STAT Edram1WrEnLo stall_edc_cmd dead_cycle1_pre_ref LOCK_ENTRY HMA_TLB_DESC_4_H HMA_REG0_MAX HMA_REG3_MIN loadboot-cfg ulptx stray arguments after "%s". SIP %1x/%1x vf Hashfilters doesn't support "prio"
missing address prefix for %s QueueSize: MaxuPFLCredits: CngTPMode: CHELSIO_T4_CLEAR_STATS %02x: %02x %02x %02x %02x %02x %02x %02x %02x Xenpak bits sched params "mode" parameter missing CHELSIO_T4_SCHED_QUEUE offset => no settings provided txq TF_DACK unused timestamp_offset snd_una snd_ssthresh tx_hdr_ptr 1 = flush CPL_TX_DATA ddp_buf1_valid Length of DDP buffer 1 Rewrite_SMAC (Inactive)
!!! Invalid DDP buf 1 valid, but buf 0 active.
TLS: offset: 0x%6.6x, len:0x%6.6x, flags: 0x%4.4x
IngHintEnable1 HostPageSizePF6 QueuesPerPageVFPF3 SGE_PERR_INJECT perr_pc_mctag perr_dbp_pc_rsp_fifo3 perr_align_ctl_fifo2 perr_ing_ctxt_mifrsp perr_headersplit_fifo1 err_timer_above_max_qid SGE_FL_BUFFER_SIZE9 SGE_DOORBELL_THROTTLE_CONTROL SGE_TIMER_VALUE_4_AND_5 TimerValue4 MaxRspCnt1 SGE_STAT_CFG SGE_PD_WRR_CONFIG SGE_CTXT_CMD SGE_CTXT_DATA2 SGE_QUEUE_BASE_MAP_HIGH SGE_LA_WRPTR_1 SGE_LA_RDPTR_11 MaxReqCnt PauseTime PCIE_DBG_INDIR_DATA_0 PBAOfst PCIE_DMAR_RSP_ERR_CNT CH0_READ SRD1 RCCS IN2H TPCS PME2 PC7I OPM1 DDREn GPIO14_IN M_LOCK STATIC_M_PLL_RANGEB DBG_EXTRA_STATIC_BITS_CONF DBG_STATIC_OCLK_MUXSEL_CONF DBG_TRACE1_CONF_COMPREG0 dbg_operate_indv_combined DBG_TRACE_WRADDR LAST_MEASUREMENT_SELECT TERMN_B_HISTORY MC_PCTL_DTUNA MC_PCTL_TXPDLL CK5OEN CK4POND MC_DDR3PHYDATX8_RSR MC_PVT_REG_DRVN MC_PAR_CAUSE ECC_UE_INT_CAUSE MA_CLIENT1_RD_LATENCY_THRESHOLD MA_CLIENT8_WR_LATENCY_THRESHOLD DBG_WRITE_REQ_CNT LOGIC_FIFO_PAR_ERROR_EN ARB3_PAR_RDQUEUE_ERROR_EN CL3_PAR_WRQUEUE_ERROR EDC_INT_ENABLE Timer0Int IllRdBEInt IllRdInt RsvdSpaceInt CIM_QUEUE_CONFIG_CTRL CIM_PI_LA_MADEBUGDATA CIM_GLB_TIMER CIM_PERR_ENABLE CIM_EEPROM_BUSY_BIT EChecksumCheckTCP EChecksumInsertTCP AutoEnable HearbeatOnceHeap EnableFLMError FilterPeerFIN EnableFeedbackSend EnableLroEcn TimerBackoffIndex13 TimerBackoffIndex12 InitCwndIdle InitCwnd TxPaceAutoStrict DropErrorIpVer Port1MTUValue VirtPort1Table TP_MOD_CONFIG TX_MOD_WEIGHT TP_FLM_FREE_RX_CNT TP_TIMER_SEPARATOR RxPawsDrop OfdRate0 EOP_CNT_LSO_IN EOP_CNT_CIM2ULP ULP_TX_LA_RDPTR_3 ch3_input stat_from_ch iespi3_Rx_framing_error pcmd_len_ovfl0 oVlanSelLpbk1 MPS_PORT_CTL MPS_RX_PG_SHR_BG3 TH PG_TH_INT0 RD_WRN PFVF MPS_PFVF_ATRB_FLTR3 IN_DBG_PORT FLTR_VLAN_SEL NIV_DROP FIXED_PFVF_LPBK Ch4_Prty MPS_TX_SE_CNT_TP01 DataCh1 FifoTh MPS_TRC_RSS_CONTROL TfInvertMatch TfDrop TfLength TfDropBufferCount Nq MPS_STAT_DEBUG_SUB_SEL MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L MPS_STAT_RX_BG_2_LB_DROP_FRAME_L MPS_PORT_STAT_TX_PORT_BCAST_H MPS_PORT_STAT_TX_PORT_ERROR_H MPS_PORT_STAT_TX_PORT_65B_127B_H MPS_PORT_STAT_TX_PORT_256B_511B_L MPS_PORT_STAT_TX_PORT_PPP6_H MPS_PORT_STAT_LB_PORT_ERROR_H MPS_PORT_STAT_RX_PORT_PPP5_L MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H MPS_PF_STAT_RX_PF_BCAST_FRAMES_L MPS_PF_STAT_RX_PF_MCAST_BYTES_L MPS_PF_STAT_RX_PF_UCAST_FRAMES_L MPS_PF_STAT_RX_PF_ERR_FRAMES_L MstLostArbInt AuxAddr3Val SMB_COMMAND_CODE4 Inc PCIE_Atrb_En ENABLE_APF_1 CAUSE_APF_1 ULP_RX_RQ_LLIMIT ULP_RX_LA_RDDATA CIM PL_INT_MAP1 MapXGMAC_KR1 PL_FLR_VF_STATUS LE_DB_REQ_RSP_CNT NCSI_CH0_SADDR_HIGH CIM2NC_EOP_CNT NCSI_LA_WRPTR NCSI_DEBUG RetryLimit TxBufErr NCSI_MACB_HASH_LOW NCSI_MACB_USER_IO Led0_Cfg XGMAC_PORT_LED_COUNTHI InstanceNum MACTxEn TxSop FltType ext_los RXAPHSLOCK DisDefIdleCnt XGMAC_PORT_XGM_RX_TYPE_MATCH_3 ClrStats XGMAC_PORT_XGM_STAT_RX_FRAMES_LOW XGMAC_PORT_XGM_STAT_RX_BCAST_FRAMES XGMAC_PORT_XGM_STAT_RX_1519_MAXB_FRAMES tx_fault Module_ID Frame_Lock TPSEL DCCEN XGMAC_PORT_HSS_TXA_TAP1_COEFF XGMAC_PORT_HSS_TXA_POLARITY C1STAT XGMAC_PORT_HSS_TXB_SEG_DIS_APP PRST XGMAC_PORT_HSS_RXA_PH_ROTATOR_CTRL RSNP XGMAC_PORT_HSS_RXA_ADAC_CTRL WIDTH FDDC XGMAC_PORT_HSS_RXB_DIGITAL_EYE_METRICS XGMAC_PORT_HSS_TXC_TAP2_IDAC_APP XGMAC_PORT_HSS_RXC_DACA_OFFSET XGMAC_PORT_HSS_RXC_DFE_FUNC_CTRL RXDEN XGMAC_PORT_HSS_TXTEST_CTRL Bar2Valid perr_U_RxData uPFLCutoffDis TX_Coalesce_Pri dbp_fetch_threshold_en3 SGE_DEBUG_DATA_HIGH_INDEX_2 debug_PC_Rsp_EOP0_cnt debug_PD_RdReq_SOP1_cnt debug_PD_RdRsp_EOP1_cnt debug_PD_WrReq_EOP2_cnt debug_M_ReqRdy debug_st_edma0_align_sub debug_idma0_flm_req_qid SGE_DEBUG_DATA_LOW_INDEX_14 MAExtraRspErr INTPLIRspErr PIORspWrTagErr PIOUnAlindWr AI_INTX_ReAssertEn PCIE_CFG4 Replay_Time_Limit Ack_Nak_Disable VC1_CPLH_Credits MA_Dynamic_CGEN Tagq_Dynamic_CGEN VC1_SleepStatus TRGT1_FIDLkUpHdrPerr DisabledIntEn PCIE_DBI_TIMEOUT_STATUS0 DBG_GPIO_EN_NEW GPIO19_CHG_DET GPIO18_IN GPIO19 TVSENSE_SNSOUT TVSENSE_SLEEP DBG_T5_STATIC_M_PLL_CONF3 T5_STATIC_M_PLL_LOCKSEL T5_STATIC_M_PLL_PREDIV T5_STATIC_C_PLL_DCO_BYPASS DBG_T5_STATIC_C_PLL_CONF4 T5_STATIC_KX_PLL_CCALBANDSEL DBG_EFUSE_BYTE52_55 MA_PMRX_WRDATA_CNT MA_EXT_MEMORY0_RDDATA_CNT0 CL4_WR_CMD_TO_EN CL10_RD_DATA_TO_EN CL6_RD_DATA_TO_ERROR CL12_IF_PAR_EN CL1_IF_PAR_ERROR CIM_DPSLP_EN OverdriveHighSpeed TP_STAMP_TIME fso_hdr_sram_perr_set3 fso_hdr_sram_perr_set2 MPS_TX_PAUSE_DURATION_BUF_GRP_TH4 MPS_TX_PAUSE_DURATION_BUF_GRP_TH10 MPS_TX_PAUSE_DURATION_BUF_GRP_TH13 MPS_RX_PAUSE_GEN_TH_0_0 MPS_RX_PAUSE_GEN_TH_0_1 PFNOVFDROP TxOutMAC3_CGEN TrcAllVf MPS_STAT_PERR_ENABLE_SRAM1 TCAM_PRIORITY ENABLE_PF_UNTAGGED_TPT_1 FilterRWnoCLIP TCAMDEEPSLEEP0 PKG_ID TXBCONFIGSEL MAC_PORT_HSS_CFG4 MAC_PORT_EEE_RX_10G_QUIET_TIMER wake_cnt_clr A RX_ENA MAC_PORT_APAUSEMACCTRLFRAMESRECEIVEDHI MAC_PORT_VLANTRANSMITTEDOKHI MAC_PORT_IFOUTMULTICASTPKTS MAC_PORT_ETHERSTATSPKTS64OCTETSHI MAC_PORT_IFINERRORSHI MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5 RF1 port_addr SPEED_SEL0 MAC_PORT_MTIP_PCS_BASER_STATUS1 RxLinkStatus ErrBlkCnt Lane16 AMLOCK7 MAC_PORT_MTIP_PCS_BIP_ERR_CNT_9 MAC_PORT_MTIP_PCS_LANE_MAP_3 MAC_PORT_MTIP_PCS_LANE_MAP_9 MAC_PORT_MTIP_PCS_LANE_MAP_10 BEAN_COMPLETE FEC MAC_PORT_BEAN_ABILITY_2_LANE2 MAC_PORT_AE_RX_COEF_REQ_2 MAC_PORT_AE_KR_CTRL_1 MAC_PORT_AE_TX_DIS_3 MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_2 EMID MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE T5XADDR C2MAX MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_3 MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED MAC_PORT_TX_LINKD_TRANSMIT_CONFIGURATION_MODE MAC_PORT_TX_LINKD_TRANSMIT_DCLK_ROTATOR_OVERRIDE MAC_PORT_TX_LINKD_TRANSMIT_802_3AZ_CONTROL MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_3 T5_RX_AUXCLK T5_RX_ADCORR T5AERRFLG H25SPC MAC_PORT_RX_LINKA_DFE_OFFSET_ODD1_ODD2 T5E1SN_ReadOnly ISTRIM EMCNT H8SN_ReadOnly MAC_PORT_RX_LINKB_PHASE_ROTATOR_CONTROL MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_1 MAC_PORT_RX_LINKB_RECEIVER_ANALOG_CONTROL_SWITCH MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_ERROR_COUNT MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_2 MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PDF_EYE_COUNT MAC_PORT_RX_LINKD_RECEIVER_LOFF_CONTROL MAC_PORT_RX_LINKD_DFE_TAP_ENABLE RANK_PAIR2_SEC MC_DDRPHY_PC_CAL_TIMER SYSCLK_RESET VREFDQ0DSGN DI_ADR10_ADR11 SLICE_SEL_REG_BITS12_13 POST_CUR_SEL_BITS8_9 SLEW_CTL_SEL_BITS14_15 PLL_TUNEMDIV_0_1 DFT_FORCE_OUTPUTS QUAD2_CLK16_BIT2 QUAD3_CLK22_BIT9 READ_CENTERING_MODE INVALID_NS_SMALL_R_MASK MC_DDRPHY_SEQ_ODT_WR_CONFIG1 WR_PRE_DLY MRS_CMD_DQ_OFF RD_CNTL_ERROR MC_UPCTL_MRRSTAT0 mrrstat_beat2 mrrstat_beat6 mrrstat_beat5 power_down zqcs_ma MC_UPCTL_DTUWACTL SleepReq EDC_H_BIST_ERR_FIRST_ADDR C_REQ Sync vfifo_cnt merge_cnt_thresh err_th1_max_fetch err_db_sync fatal_enq2ll_vld Ingress0_Size debug_PL_BAR2_ReqFull Auto_Lane_Flip_Ctrl_En Req_LnH_RxStateDone Req_LnJ_RxStateDone PCIE_VF_MSI_EN_4 STATIC_M_PLL_FASTSTOP STATIC_C_PLL_DIVCHANGE STATIC_C_PLL_VCVTUNE STATIC_KX_PLL_CCALCVHOLD MA_EXIT_ADDR_FAULT EnableCByp ULPType5Length ULPType1Offset ERR_ITT_EN flush_middle CONG_TH GENEVE_VER MPS_CLS_NCSI_ETH_TYPE_EN MPS_CLS_MATCH_CNT_TCAM MPS_CLS_REQUEST_TRACE_MAC_SA_L MPS_CLS_RESULT_TRACE ClsTrcPriority CtlTcamSel DataVIDH2 TPDB_IF_PAUSE_ACK HASH_ACTV_HIT MISS LE_DB_RSP_CODE_2 HASHTBLADDR HashTblMemCrcErr TcamIntPerr DBGICMDWRITE MAC10G1G_RESET sgmii_reset_rx_clk mac40g100g_reset_txclk mac1g10g_reset_txclk pcs10g_gate_xfi_txclk pcs100g_gate_tx_clk AEC_SYS_LANE_TYPE_2 mac1g10g_magic_ind mac40g_loop_bck MAC_PORT_PCS_CTRL_RW Perr_rx13_pcs100g single_alarm MAC_PORT_MTIP_1G10G_RX_FIFO_SECTIONS MAC_PORT_MTIP_1G10G_TX_FIFO_SECTIONS Device_Reg_Addr MAC_PORT_MTIP_1G10G_MDIO_DATA MAC_PORT_MTIP_1G10G_RX_APAUSEMACCTRLFRAMES MAC_PORT_MTIP_1G10G_RX_IFINMULTICASTPKTS MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOVERSIZEPKTSHI MAC_PORT_MTIP_1G10G_TX_AALIGNMENTERRORSHI MAC_PORT_MTIP_1G10G_TX_ETHERSTATSUNDERSIZEPKTSHI MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS512TO1023OCTETS MAC_PORT_MTIP_KR_PCS_CONTROL_1 MAC_PORT_MTIP_KR_10GBASE_R_PCS_PACKAGE_IDENTIFIER_LO 10GBase_R_capable Hi_ORDER_CNT_Present MAC_PORT_MTIP_RS_FEC_STATUS RS_FEC_bypass_correction_ability MAC_PORT_MTIP_FEC2_CERR_CNT_0 MAC_PORT_MTIP_FEC2_CERR_CNT_1 T5_AE0_RXSTAT_TF MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE AS4X3 MAC_PORT_TX_LINKA_TRANSMIT_AE_C3_LIMIT_EXTENDED MAC_PORT_TX_LINKB_TRANSMIT_AE_C2_INIT2_EXTENDED MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE MAC_PORT_TX_LINKC_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER MAC_PORT_TX_LINKC_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE MAC_PORT_TX_LINKD_TRANSMIT_AE_C3_INIT2_EXTENDED ACTL MAC_PORT_RX_LINKA_RECEIVER_IQAMP_CONTROL_1 MAC_PORT_RX_LINKA_RECEIVER_AC_COUPLING_VALUE MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_3 FDDC3456 MAC_PORT_RX_LINKA_RECEIVER_INTERNAL_STATUS_2 DCDTOEN MAC_PORT_RX_LINKC_RECEIVER_QCC_CONTROL MAC_PORT_RX_LINK_BCST_RECEIVER_AC_COUPLING_CONTROL OPERATE_MODE DELAY_LINE_CTL_OVERRIDE T_RC TCR_MODE DDR3_BRBC_MODE MASK_128_1 EDC_H_DBG_BIST_RD_REQ_CNT EDC_H_DBG_EDRAM1_RMW_CNT EXIT_SYNC IDTF_INT_ENABLE RTF MPS_VF_STAT_TX_VF_DROP_FRAMES_L MPS_VF_STAT_TX_VF_OFFLOAD_BYTES_L CIM_VF_EXT_MAILBOX_DATA_20 clearstats <port> clear port statistics
context <type> <id> show an SGE context
dumpstate <dump.bin> dump chip state
filter <idx> [<param> <val>] ... set a filter
filter <idx> delete|clear [prio 1] delete a filter
filter list list all filters
filter mode [<match>] ... get/set global filter mode
hashfilter [<param> <val>] ... set a hashfilter
hashfilter <idx> delete|clear delete a hashfilter
hashfilter list list all hashfilters
hashfilter mode get global hashfilter mode
i2c <port> <devaddr> <addr> [<len>] read from i2c device
loadboot <bi.bin> [pf|offset <val>] install boot image
loadboot clear [pf|offset <val>] remove boot image
loadboot-cfg <bc.bin> install boot config
loadboot-cfg clear remove boot config
loadcfg <fw-config.txt> install configuration file
loadcfg clear remove configuration file
loadfw <fw-image.bin> install firmware
memdump <addr> <len> dump a memory range
modinfo <port> [raw] optics/cable information
policy <policy.txt> install offload policy
policy clear remove offload policy
reg <address>[=<val>] read/write register
reg64 <address>[=<val>] read/write 64 bit register
regdump [<module>] ... dump registers
sched-class params <param> <val> .. configure TX scheduler class
sched-queue <port> <queue> <class> bind NIC queues to TX Scheduling class
stdio interactive mode
tcb <tid> read TCB
tracer <idx> tx<n>|rx<n> set and enable a tracer
tracer <idx> disable|enable disable or enable a tracer
tracer list list all tracers
invalid register "%s" CHELSIO_T4_GETREG edc1 MACIdx MPS vnic_id dport tcbhash CHELSIO_T4_GET_SGE_CONTEXT HostFCMode: PCIeChannel: %llu
FetchTPHintEn: TPHintEn: CngMPSEnable: x8MiniLink missing argument for "%s" cl-rl r failed to compile "%s" on line %zd: %s unknown congestion algorithm "%s". Diagnostics not supported. FCoE ulp_type TF_RX_CHANNEL TF_RX_COMPACT TF_PEND_CTL0 pend_ctl1 t_srtt TCP receive next QP index Host RQ write pointer ddp_psh_no_invalidate0 TF_DDP_BUF1_INDICATE Tag for DDP buffer 0 rx_channel %u rx_quiesce %u rx_flow_ctrl_dis %u, rss_fw Extension of ulp_raw for PI configuration Drop_Encapsulation_Headers seq: 0x%llx
HostPageSizePF2 Length_Min err_data_cpl_on_high_qid0 err_egr_ctxt_prio err_inv_ctxt3 SGE_FL_BUFFER_SIZE5 SGE_TIMESTAMP_HI SGE_CTXT_MASK3 SGE_LA_RESERVED_3 SGE_LA_WRPTR_8 SGE_LA_RDPTR_9 MASyncEn DCAEnDMA VPDReqProtect PCIE_DMA_CFG PCIE_CDEBUG_DATA_HIGH PCIE_BUS_MST_STAT_0 PCIE_BUS_MST_STAT_4 PCIE_MSIX_EN_2 SSTD PCIE_CORE_REVISION_ID PME1 PC3I GPIO12_IN GPIO11_IN GPIO3 KR_OCLK_En GPIO7_ACT_LOW STATIC_U_PLL_PREDIV KR_OCLK_MUXSEL Rd_en1 Rd_en0 PVT_CALIBRATION_DONE THRESHOLD_TERMN_MAX_SYNC THRESHOLD_DRVP_MIN_SYNC REG_IN_TERMN_A pd_exit_mode dtu_wr_byte5 dtu_rd_byte5 MC_PCTL_PHYPVTCFG MC_DDR3PHYAC_RCR0 BYPASS DDRCLKEN MC_DDR3PHYDATX8_WDBDR6 MA_CLIENT3_RD_LATENCY_THRESHOLD MA_CLIENT4_WR_LATENCY_THRESHOLD MA_CLIENT8_RD_LATENCY_THRESHOLD MA_CLIENT10_RD_LATENCY_THRESHOLD MA_EXT_MEMORY_BAR CL6_PAR_RDQUEUE_ERROR_EN CIM_FLASH_ADDR_SIZE CIM_EXTMEM2_BASE_ADDR BlkWrCtlIntEn CIM_QUEUE_CONFIG_REF CIM_MEM_ZONE1_BA CIM_MEM_ZONE4_VA CIM_MA_TIMER_EN MBIntReq TXPacingEnable FragmentDrop DBMaxOpCnt EnableFLMErrorDDP ResetDdpOffset DackTimerSpin EnableBUFI TP_MSL TP_PERS_MIN PerShiftBackoffMax ChannelEnable UseWireCh VfPerrEn ChnOvrFlow2 RstChn2 RstChn1 Queue VirtPort3Table RXChannelWeight0 TxChannelXoffEn TP_CMM_MM_RX_FLST_BASE TP_FLM_FREE_TX_CNT EnablePcmdFull0 RxChnXoff3 TP_IX_SCHED0 DbgLaRptr TP_PROTOCOL_CNTRL imm_data_perr_set_ch1 ULP_TX_PBL_LLIMIT Ch0Size2 CLR_CH2 SOP_CNT_ULP2TP ULP_TX_LA_RDDATA_2 PM_RX_INT_ENABLE zero_e_cmd_error PM_TX_CFG pcmd_len_ovfl1 MPS_TX_PAUSE_RETRANS_BUF_GRP3 MPS_DEBUG_DATA_REG_L ALLOC MPS_RX_PORT_GAP PKFL ST0 ST_TP MPS_PORT_RX_VF_MAP3 MPS_PORT_RX_IVLAN Lpbkpt1 ValidCh2 SOPPt0 MPS_TRC_FILTER3_DONT_CARE MPS_STAT_INT_CAUSE MPS_STAT_RX_BG_1_LB_DROP_FRAME_L MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H MPS_PORT_STAT_TX_PORT_BYTES_L MPS_PORT_STAT_LB_PORT_UCAST_L MPS_PORT_STAT_RX_PORT_PAUSE_L MPS_PORT_STAT_RX_PORT_PPP1_H MPS_PORT_STAT_RX_PORT_PPP6_H MultiListen MPS_CLS_VLAN_TABLE MacParity0 DeviceCap I2CM_DATA Ack MDIInv ULP_RX_CTL SOP_CNT_OUT1 EOP_CNT_MR1 CPL_SWITCH MA MC SW_CIM PL_INT_MAP0 MapI2CM Timeout PL_SEMAPHORE_CTL PL_VFID_MAP DBGICMDSTRT LE_SPARE LE_PERR_INJECT mac_ref_rst bmc_rx_fwd_all LenChkEn MDIStatus PCSR_fec_corr HSSRSTCONFIG RXBLATEIN XGMAC_PORT_XGM_TX_CFG XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_4 XGMAC_PORT_XGM_STAT_TX_FRAME_LOW Align_Status ScrBypass tx_tst_dat_sel XGMAC_PORT_PCSR_TXTEST_SEEDA_UPPER XGMAC_PORT_AN_LINK_PARTNER_ABILITY RXSTAT_C2 FSM_BADMRK XGMAC_PORT_HSS_TXA_TAP1_IDAC_APP XGMAC_PORT_HSS_TXB_TAP2_IDAC_APP FREEZEFW XGMAC_PORT_HSS_RXA_PH_ROTATOR_OFFSET_CTRL OFFEN SHORTV DACAP DACAM H1OMAG H4OMAG BLKOAE H1TGT XGMAC_PORT_HSS_RXB_VGA_CTRL2 XGMAC_PORT_HSS_TXD_TAP2_COEFF XGMAC_PORT_HSS_RXC_DACAP_DAC_AN_OFFSET XGMAC_PORT_HSS_RXC_DFE_H1 XGMAC_PORT_HSS_RXD_PH_ROTATOR_OFFSET_CTRL XGMAC_PORT_HSS_RXD_SIGDET_CTRL XGMAC_PORT_HSS_RXD_DFE_D00_D01_OFFSET XGMAC_PORT_HSS_RXTEST_CTRL XGMAC_PORT_HSS_RX_DIGITAL_EYE_CTRL EDMA3_Sleep_Req SGE_DEBUG_DATA_HIGH_INDEX_6 debug_PD_WrReq_EOP3_cnt debug_PD_WrReq_Int3_cnt debug_itp_pause debug_itp_del_done DReqWrPerr MARdEOPErr PCIE_CFG2 DMADCASTFirstOnly PCIE_FID_VFID_SEL CPLH0 Common_Clock_N_FTS PCIE_CORE_DEBUG_1 VC0_TLP_Ordering VC0_NPTLP_Queue_Mode VC1_TLP_Ordering PreCursor PCIE_CORE_GEN3_EQ_PRESET_INDEX Phase23_2ms_Timeout_Disable RdReqCnt TimerValue PIOReq_MEMCtlPerr PIOReq_BAR2DataPerr Addr10b LnE_RxStateReq LnC_RxStateDone LnA_RxStateReq Lane3LF Lane2LF GPIO17_CHG_DET GPIO16 T5_STATIC_SWMC1CfgRst_ T5_STATIC_U_PLL_RANGEPRE GPIO8_PE_En DBG_EFUSE_BYTE24_27 DBG_EFUSE_BYTE32_35 MA_EDRAM0_WRDATA_CNT1 WRN CL10_WR_CMD_TO_EN CL7_IF_PAR_EN CL1_IF_PAR_EN MA_LOCAL_DEBUG_CFG ULP_TX_PERR_INJECT_2 smarbt2ulp_data_perr_set fso_hdr_sram_perr_set1 t10_pi_sram_perr_set2 ULP_TX_PERR_ENABLE_2 MPS_TX_PAUSE_RETRANS_BUF_GRP_TH4 MPS_RX_PTP_UDP MPS_RX_PAUSE_GEN_TH_2_2 TP2MPS_Ch0_CLR TxOutMAC0_CGEN TxSchMAC2_CGEN TrcAllTP2MPS MPS_STAT_STOP_UPD_TX_VF_64_95 TCAM0_HIT_PRIORITY PERR_SE_CNT_MISMATCH_0 immediate_opcode PF_UNTAGGED_TPT_1 PF_PBL_1 MAC_PORT_LED_COUNTHI rx_lane MAC_PORT_PERR_INT_CAUSE sd0_CGEN MACSEG4_CGEN SEND_IDLE EMPTY MAC_PORT_IFINBROADCASTPKTS MAC_PORT_IFOUTMULTICASTPKTSHI MAC_PORT_ETHERSTATSUNDERSIZEPKTSHI MAC_PORT_ETHERSTATSOVERSIZEPKTSHI MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6 sppedsel1 100BaseT4 LPBK RESEREVED Lane3 AMLOCK16 MAC_PORT_MTIP_PCS_LANE_MAP_17 MAC_PORT_BEAN_CTL MAC_PORT_BEAN_XNP_2_LANE2 restart_tr ability T5_AE0_RXSTAT_RDY MAC_PORT_AE_FSM_STATE T5_AE2_RXSTAT_C2 MAC_PORT_AE_TX_COEF_REQ_3 MAC_PORT_AET_SIGNAL_LOSS_DETECTION_0 MAC_PORT_AET_STATUS_1 REFSELRESET MAC_PORT_TX_LINKA_TRANSMIT_CONFIGURATION_MODE T5_TX_EXTC16 MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_APPLIED MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 MAC_PORT_TX_LINKC_TRANSMIT_DCC_TIME_OUT MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED T5BYTE0 T5_RX_ASAMP T5BER6VAL FDQCC H6GS H12SN_ReadWrite MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_2 MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_3 MAC_PORT_RX_LINKB_DFE_H6_AND_H7 MAC_PORT_RX_LINKC_DFE_H5 MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_1 MAC_PORT_RX_LINKD_DFE_H4 MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_1 MAC_PORT_RX_LINK_BCST_RECEIVER_DACA_MIN_AND_DACAZ MAC_PORT_RX_LINK_BCST_RECEIVER_INTERNAL_STATUS MC_DDRPHY_PC_ZCAL_TIMER DATA_MUX4_1MODE WC_ERROR ERROR_CUSTOM_WR MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN0 MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN2 POST_CUR_SEL_BITS4_5 SLEW_CTL_SEL_BITS0_1 SLEW_CTL_SEL_BITS12_13 ADR_LANE_12_15_PD ANALOG_WRAPON SYSCLK_PHASE_CNTL_EN TSYS_WRCLK ATEST1CTL1 MC_DDRPHY_DP18_DATA_BIT_DIR0 QUAD2_CLK22_BIT8 MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP MC_DDRPHY_DP18_RD_STATUS0 NO_LOCK_MASK POST_CURSOR MEMINTD21_POS MULTIPLE_REQ_ERROR MULT_REQ_ERR_MASK TRP_CYCLES TZQCS_CYCLES DDR4_MRS_CMD_DQ_EN MC_DDRPHY_WC_ERROR_STATUS0 STAGGERED_PATTERN DP18_13_Populated MC_UPCTL_STAT mrrstat_beat7 mddr_lpddr2_bl MC_UPCTL_DTUPRD2 MC_UPCTL_TDQS MC_UPCTL_IPVR MC_P_PAR_CAUSE BURST_LEN ECC_UE_INT0_CAUSE EDC_H_ECC_ERR_SEL EDC_H_BIST_CRC_SEED HMA_TABLE_LINE3 SGE_IDMA1_DROP_CNT debug_PC_Req_EOP_cnt debug_idma1_IDMA2IMSG_Full Req_LnF_RxStateReq Req_LnK_RxPwrState Cur_LnI_RxPwrState PCIE_DEBUG_ADDR_RANGE_CNT DBG_STATIC_U_PLL_CONF2 DAddrIllegalType TlsPathCtl stag_fifo_perr_set2 VXLAN GENEVE_EN MPS_RX_TTL TTL_CHK_EN_IPV6 MPS_RX_CNT_TNL_ERR_PKT_LPBK0 MPS_RX_CNT_VXLAN_PKT_LPBK1 Outer_IPv6_n_Double_VLAN_NVGRE Outer_IPv6_n_Double_VLAN_GENEVE DMACH ASLIPCOMPEN_IPV4 CLIP_FAIL CMD_CMP Led0_Cfg1 pcs100g_reset_cgmii_rxclk sgmii_gate_rx_clk pcs10g_gate_sd_rx_clk mac40g100g_gate_ff_rx_clk AEC_SYS_LANE_SELECT_2 MAC_PORT_AEC_XGMII_TIMER_LO_100G mac1g10g_magic_ena an_prog MAC_PORT_PCS_DEBUG1_RO MAC_PORT_MTIP_1G10G_MAC_ADDR_0 MAC_PORT_MTIP_1G10G_TX_IFMULTICASTPKTS MAC_PORT_MTIP_KR_PCS_DEVICE_IDENTIFIER_2 MAC_PORT_MTIP_KR_PCS_DEVICES_IN_PACKAGEHI Data_Pattern_Select 10GBase_x_capable MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_19 T5_TXSTAT_C3 T5_AE2_RXSTAT_TF MAC_PORT_AET_LIMITS2 MAC_PORT_INEQUALITY_LOW_LIMIT AS2X1 AT2X MAC_PORT_TX_LINKA_TRANSMIT_TAP_SIGN_APPLIED_REGISTER OS1X0 MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE MAC_PORT_TX_LINKB_TRANSMIT_TAP_SIGN_OVERRIDE MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_2X_OVERRIDE MAC_PORT_TX_LINK_BCST_TRANSMIT_4X_SEGMENT_APPLIED ROTE H5GS MAC_PORT_RX_LINKA_DFE_H12_13 DCDCMP QCCSTEP TESTCAP MAC_PORT_RX_LINKB_RECEIVER_DCC_CONTROL MAC_PORT_RX_LINKC_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL MAC_PORT_RX_LINKD_DFE_OFFSET_CHANNEL MC_DDRPHY_AD32S_PLL_VREG_CONFIG_1 WRCLK_CALIB_DONE VALUE_UPDATED QUAD1_EDGES PRBS_WAIT PRBS_SYNC_EARLY DQ_REC_LOW_POWER DQS_ALIGN_QUAD DQS_ALIGN_BY_QUAD DIS_LOW_PWR_PER_CAL DFI_PHYUD_CNTL T_WTRO MC_P_BIST_USER_WMASK2 EDC_H_DBG_STALL_CYCLES dead_cycle0_bbi dead_cycle0_post_ref RefCntExpr ADDR0_MAX SGE_VF_KDOORBELL PL_VF_WHOAMI -h
ulp_rx smb %04x/%04x %04x/%04x (QID) proto sport nat InterruptDestination: ENABLED port %u %s, PN %s
XFP HD8X QSFP28 sched params "max-rate" takes value(1-100000000) for rate-mode absolute CHELSIO_T4_CUDBG_DUMP tvp->hi>=tvp->lo ESC_1_STATE Reno lock_tid TF_PEND_CTL2 Receive in-order buffered data Page pointer for in-order receive buffer rx_frag2_len ord_L_bit_vld TF_DDP_BUF0_VALID Report_TID Buf0: %u %u %u %u %u
pend_ctl: 0x%1x, core_bypass: 0x%x, main_slush: 0x%x
QueuesPerPagePF5 SGE_EGRESS_QUEUES_PER_PAGE_VF perr_align_ctl_fifo3 err_inv_ctxt0 SGE_FL_BUFFER_SIZE4 FetchThresh LP_Int_Thresh Throttle_Count SGE_SHARED_TAG_CHAN_CFG Ingress1_Base FIDPerr CfgSnpPerr PopC PCIE_HMA_STAT ExtRegister PCIE_MEM_ACCESS_OFFSET PCIE_CDEBUG_INDEX PCIE_DMAR_RSP_SOP_CNT SRD4 PCIE_CORE_OUTBOUND_NON_POSTED_BUFFER_ALLOCATION RCPS RLNI PACI PC5S PME3 GPIO8_OEn GPIO1_IN PCIe_LOCK DBG_PLL_LOCK DBG_STATIC_C_PLL_CONF DBG_STATIC_KX_PLL_CONF Counter0 DBG_PVT_REG_LAST_MEASUREMENT PVT_REG_DRVN_B REG_OUT_TERMP_B REG_OUT_TERMN_A REG_OUT_DRVP_B REG_OUT_DRVN_B DBG_PVT_REG_HISTORY_TERMP DRVP_A_HISTORY DRVN_A_HISTORY cmd_opcode qse_alat dtu_err_b2 MC_PCTL_TWTR MC_DTULFSRWD ea_bank CKINV RDBDVT MC_PVT_REG_IN_DRVN ECC_CE_INT_ENABLE WDATA_OCNT MC_BIST_CMD_LEN CL10_PAR_WRQUEUE_ERROR_EN CL8_PAR_WRQUEUE_ERROR_EN EDC_REF RefFreq EDC_BIST_ERR_FIRST_ADDR BootAddr BootVecSel OBQNCSIParErr SglRdFlashIntEn ObqDbgBusy DebugSelH CIM_MEM_ZONE6_BA CCPL FiveTupleLookup TP_DB_CONFIG TP_PMM_TX_BASE PMTxMaxPage SACKTx DisableTimeWait DisableNewPshFlag TimerBackoffIndex5 TimerBackoffIndex8 EngineLatencyWire TP_PERS_MAX TP_ULP_TABLE OFDHashSave TP_RSS_CONFIG_SYN VfRdRg RX_MOD_WEIGHT RxTimerHeartbeat TxRcvAdvShrunk TxModXoff4 Ch1Size1 ULP_TX_CPL_PACK_SIZE2 ULP_TX_FPGA_CMD_7 ULP_TX_LA_WRPTR_1 ULP_TX_LA_WRPTR_2 ULP_TX_LA_RDPTR_6 ULP_TX_LA_RDDATA_9 icspi2_Rx_framing_error MPS_VF_TX_CTL_63_32 MPS_TP_CSIDE_MUX_CTL_P1 DbgModeCtl_L RegSendOff DROP MPS_RX_FUNC_INT_CAUSE MPS_RX_PAUSE_GEN_TH_0 MPS_RX_QFC1_ATRB MTU MPS_PFVF_ATRB_FLTR8 MPS_RX_SE_CNT_ERR LPBK_CNT3 CHK_8023_LEN_M MPS_PORT_RX_CTL1 Lpbkpt3 pt0 ErrCh1 DataCh0 EOPPt0 SubPrtH MPS_PORT_FPGA_PAUSE_CTL MPS_STAT_PERR_INT_CAUSE_SRAM MPS_STAT_RX_BG_3_LB_DROP_FRAME_L MPS_PORT_STAT_TX_PORT_1024B_1518B_L MPS_PORT_STAT_TX_PORT_PPP1_L MPS_PORT_STAT_TX_PORT_PPP7_H MPS_PORT_STAT_LB_PORT_MCAST_L MPS_PORT_STAT_LB_PORT_MCAST_H MPS_PORT_STAT_RX_PORT_LEN_ERROR_H MPS_PORT_STAT_RX_PORT_64B_L MPS_PORT_STAT_RX_PORT_PPP5_H MPS_PF_STAT_RX_PF_FRAMES_H MPS_PF_STAT_RX_PF_BCAST_BYTES_L MstCtlEn MstRxFifoParInt SlvPrepToArpInt SMB_ARP_UDID3 Parity ENABLE_CTX_0 ENABLE_AF_1 ENABLE_PCMDF_1 PERR_ENABLE_AF_0 PERR_ENABLE_TPTCF_1 ULP_RX_RQUDP_ULIMIT SMB PL_PERR_ENABLE PL_SEMAPHORE_LOCK LE_DB_ACT_CNT_IPV6 LE_DB_HASH_TID_BASE MsgSel UnknownCmd SYNCookieOff LIPMiss LE_DB_DBGI_REQ_TCAM_CMD MPS2BMC_CNT NCSI_INT_ENABLE NCSI_PERR_INJECT PauseTimeZero TxUsedBitRead NCSI_MACB_CARRIER_SENSE_ERR XAUI_Reset XGMAC_PORT_DEBUG_CFG LWM RXDPRBSEN TXCPRBSRST RXBDATASYNC RXDPHSDNIN RXAEARLYIN XGMAC_PORT_XGM_INT_MASK Data XGMAC_PORT_XGM_MODULE_ID Lane1_Sync_Status tx_tst_sel XGMAC_PORT_PCSR_RXTEST_CTRL test_cnt_pre XGMAC_PORT_PCSR_TEST_STATUS XGMAC_PORT_HSS_TXA_8023AP_AE_CMD C0UPDT XGMAC_PORT_HSS_TXA_SEG_DIS_APP XGMAC_PORT_HSS_TXB_COEFF_CTRL XGMAC_PORT_HSS_TXB_EXT_ADDR XGMAC_PORT_HSS_RXA_CFG_MODE DACSD VOFFA AMAXT D01AMP DPCCVG XGMAC_PORT_HSS_RXB_DFE_AMP_SAMPLE XGMAC_PORT_HSS_RXB_DFE_H2 XGMAC_PORT_HSS_TXD_DRIVER_MODE XGMAC_PORT_HSS_TXD_DRIVER_OVR_CTRL XGMAC_PORT_HSS_RXC_DDC PFEN XGMAC_PORT_HSS_TX_TAP2_COEFF XGMAC_PORT_HSS_TX_PWR_DAC_OVR XGMAC_PORT_HSS_RX_DFE_H2 perr_cim_fifo1 IdmaArbRoundRobin dbp_fetch_threshold_en0 debug_CPLSW_CIM_EOP0_cnt debug_UD_RxAFull_d IPSOTPerr IPRxHdrGrpPerr INTVFRangeErr DiagCtrlBus PERstTimer VC0_PD_Credits VC0_CPLH_Credits DirSpdChange PCIE_CORE_GEN3_EQ_DIRCHANGE_FEEDBACK WrSOPCnt STI_SleepStatus PIOCpl_CtlPerr ActiveLanes LnC_RxStateReq LnA_RxPwrState LnC_STAT PCIE_STATIC_SPARE1 GPIO19_OEn DBG_CUST_EFUSE_SEL2_EN DBG_EFUSE_BYTE36_39 MA_SGE_TH0_RDDATA_CNT MA_HOST_MEMORY_WRDATA_CNT0 CNT_VAL CL8_WR_CMD_TO_EN CL7_WR_CMD_TO_ERROR CL1_RD_DATA_TO_EN CL4_RD_CMD_TO_ERROR VLANExtEnPort2 RxmtCwndReno ERR_RTAG_EN ULP_TX_CGEN MPS_TX_PAUSE_DURATION_BUF_GRP_TH1 MPS_TX_PAUSE_RETRANS_BUF_GRP_TH8 MPS_RX_PAUSE_GEN_TH_3_0 TxOutLpbk3_CGEN VfFiltMask VfFiltValid MPS_TRC_VF_OFF_FILTER_3 StatStopCtrl CountLbVF MPS_STAT_PERR_INT_ENABLE_SRAM1 MPS_STAT_STOP_UPD_BG BusBusy GlobalDeepSleepEn ULP_RX_ATOMIC_OPCODES atomic_rpl_len MAC TCAMDEEPSLEEP0_STAT SRAMDEEPSLEEP TCAMDEEPSLEEP1 LE_DB_ACT_CNT_IPV6_TCAM SmuxRxSel RXIF_Reset MAC_PORT_EPIO_DATA0 Perr_pkt_ram rx_sff_mac10 tx_dff_mac10 HSSPDWNPLLB TXDQUIET MAC_PORT_PTP_TIMER_RD1_LO PAUSE_IGNORE CRC_FWD MAC_PORT_AFRAMECHECKSEQUENCEERRORSHI MAC_PORT_AFRAMETOOLONGERRORS MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2HI AN_EN FD mdio_hold_time dev_addr readbusy MAC_PORT_MTIP_VLAN_TPID_3 100BASE_R MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS1 MAC_PORT_MTIP_PCS_BIP_ERR_CNT_16 MAC_PORT_FEC_CONTROL T5_AE1_RXSTAT_C1 MAC_PORT_AE_TX_COEF_REQ_1 MAC_PORT_AE_REG_MODE_1 MAC_PORT_AE_FSM_CTL_3 MAC_PORT_AE_FSM_STATE_3 MAC_PORT_AE_KR_STATUS REFVALIDB MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_3 MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_4 T5_TX_CFGWRT T5_TX_CFGACT T5_TX_RTSEL RLOCK MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_APPLIED MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 MAC_PORT_TX_LINKC_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE MAC_PORT_TX_LINKD_TRANSMIT_POLARITY MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AZ_CONTROL MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_3 T5VLCKF MAC_PORT_RX_LINKA_INTEGRATOR_DAC_OFFSET T5SMQ T5EMBRDY H_EN H4OGS MAC_PORT_RX_LINKA_DFE_H10_AND_H11 H10SN_ReadOnly MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_3 MAC_PORT_RX_LINKD_RECEIVER_CONFIGURATION_MODE MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 MAC_PORT_RX_LINK_BCST_RECEIVER_ANALOG_CONTROL_SWITCH MC_DDRPHY_PC_DP18_PLL_LOCK_STATUS ENA_PER_READ_CTR SLICE_SEL_REG_BITS6_7 POST_CURSOR1 POST_CURSOR2 VREG_RANGE_0_1 MC_DDRPHY_DP18_DATA_BIT_ENABLE0 MC_DDRPHY_DP18_READ_TIMING_REFERENCE0 INCOMPLETE_RD_CAL_N0_MASK WL_ERR_CLK22_ST INVALID_NS_BIG_R WL_ERR_CLK16_MASK MC_DDRPHY_DP18_PLL_CONFIG1 CE0DLTVCCA MC_DDRPHY_DP18_POWERDOWN_1 MR_MASK_EN TRCD_CYCLES SINGLE_BIT_MPR_RP2 ADR16_0_Populated MC_UPCTL_TAL odt_rank_map2 MC_UPCTL_DFITPHYRDLAT MC_UPCTL_DFISTPARLOG MC_UPCTL_IPTR MC_P_DDRPHY_RST_CTRL MC_P_BIST_DATA_PATTERN EDC_H_REF HMA_TABLE_LINE5 SGE_GK_CONTROL SGE_INT_ENABLE6 Egress1_Size SGE_QBASE_INDEX SGE_DBG_QUEUE_STAT1 debug_PL_BAR2_ReqVld debug_idma0_s_cpl_flit_remaining PCIE_CFG7 Req_LnH_RxStateReq Req_LnN_RxPwrState LnK_STAT Phy_Reg_RegAddr PCIE_VF_256_INT_CFG2 PCIE_TGT_SKID_FIFO PCIE_PCIE_SPARE0 STATIC_C_PLL_LOCKTUNE STATIC_C_PLL_MULTPRE STATIC_C_PLL_LOCKSEL STATIC_U_PLL_STOPCLKA EFUSE_ADDR DBG_CUST_EFUSE_BYTE0_3 TP_PARA_REG8 ULPType3Length ISO_A_FLAG_EN TlsDisableIFuse urgent_middle MPS_RX_FIFO_2_CTL VXLAN_FLAG_CHK_EN Outer_IPv4_n_VLAN_GRE ClsTrcVlanVld ClsTrcVlanId IscsiTagPI LE_DB_PS_CTRL ACTV_FULL_ERR LE_DB_DBG_MATCH_CMD_IDX_DATA LE_DBG_SEL MAC_PORT_MTIP_RESET_CTRL pcs100g_reset_sd3_rx_clk REG_FPH_ATTR_TXUPDAT_VALID mac1g10g_tx_underflow Perr_tx0_pcs100g Perr_rx6_pcs100g pps tx_mac1g10g MAC_PORT_MTIP_1G10G_COMMAND_CONFIG MAC_PORT_MTIP_1G10G_INIT_CREDIT MAC_PORT_MTIP_1G10G_RX_OCTETSOKHI MAC_PORT_MTIP_1G10G_RX_FRAMESOK MAC_PORT_MTIP_1G10G_RX_VLANOKHI MAC_PORT_MTIP_1G10G_TX_VLANOKHI MAC_PORT_MTIP_1G10G_TX_IFBROADCASTPKTS MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS64OCTETSHI MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS65TO127OCTETS MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS128TO255OCTETS MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_6HI MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_0HI MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_1 PCS_present MAC_PORT_MTIP_KR_10GBASE_R_PCS_PACKAGE_IDENTIFIER_HI Transmit_fault MAC_PORT_MTIP_KR4_BASE_R_TEST_ERR_CNT MAC_PORT_MTIP_KR4_SCRATCH MAC_PORT_MTIP_CR4_CONTROL_1 Lane_11_blck_lck fec_align_status_lh T5_AE0_RXSTAT_FEC FFE4_EN MAC_PORT_AET_LIMITS0 RCALBUSY ISEQ REFDIV MAC_PORT_TX_LINKA_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE MAC_PORT_TX_LINKA_TRANSMIT_AE_STEP_SIZE_EXTENDED MAC_PORT_TX_LINKA_TRANSMIT_AE_C2_LIMIT_EXTENDED MAC_PORT_TX_LINKA_TRANSMIT_AE_C0_INIT2_EXTENDED MAC_PORT_TX_LINKB_TRANSMIT_AE_STEP_SIZE_EXTENDED MAC_PORT_TX_LINKB_TRANSMIT_AE_C2_LIMIT_EXTENDED MAC_PORT_TX_LINKB_TRANSMIT_AE_C0_INIT2_EXTENDED MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_1X_OVERRIDE MAC_PORT_TX_LINKD_TRANSMIT_AE_C1_INIT_EXTENDED MAC_PORT_TX_LINK_BCST_TRANSMIT_APPLIED_TUNE_REGISTER MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C2_INIT_EXTENDED MAC_PORT_RX_LINKA_RECEIVER_AC_COUPLING_CONTROL OVRDCDPRE DCDIND HBISTRES EMDATA59 H15SN H14GS MAC_PORT_RX_LINKC_RECEIVER_DACAP_AND_DACAN_SELECTION MAC_PORT_RX_LINKC_AC_COUPLING_CURRENT_SOURCE_ADJUST MC_DDRPHY_AD32S_SYSCLK_PR_VALUE_RO RD_DELAY_EARLY CHECKER_ENABLE MT_ALIGN_ON_EVEN_CYCLES MC_DDRPHY_APB_MTSTAT_REG0 MC_LMC_INITSEQ2 MC_LMC_CMD11 FGR_MODE SRM6_RFU RMW_DEFER_EN MWDataVld EDC_H_DBG_MA_RD_DAT_CYC_CNT CmdFsm ADDR1_MAX PAGE_SIZE1 RTF_INT_ENABLE MPS_VF_STAT_RX_VF_UCAST_FRAMES_L CIM_VF_EXT_MAILBOX_DATA_30 ulp_tx Frag %8ju macidx Cannot parse %s %s address %s ingress No module/cable in port %ld QSFP+ CXP2 %d error%s in sched-class command ULP mode: 0 =toe, 2=iscsi, 4=rdma, 5=ddp, remaining values are reserved t_flags rx_flow_control_ddp TF_CCTRL_SEL0 TF_CCTRL_SEL1 init TF_ACTIVE_OPEN Offset of snd_una from tx_max tx_last_ptr_raw rx_frag3_ptr pdu_hdr_len TF_DDP_BUF0_FLUSH OPT_0_CONN_MAXRT pdu_hdr_len %u
Valid Offset Length Tag
MemSel perr_dbp_hp_fifo perr_ing_ctxt_cache SGE_IMSG_CTXT_BADDR ForceVFPF7DBtoLP MinTag0 SGE_LA_RESERVED_1 SGE_LA_WRPTR_6 INTXClrPerr LittleEndian PCIE_DMA_STAT PCIE_MAILBOX_BASE_WIN PCIE_MA_SYNC PCIE_BUS_MST_STAT_5 SWD8 CRRE PCIE_CORE_OUTBOUND_POSTED_DATA_BUFFER_ALLOCATION OP0D IP2D IC1T PMC6 PCIE_CORE_ENDPOINT_INTERRUPT_ENABLE AL1S CPM4 CPM5 GPIO11 M_LOCK_ACT_LOW STATIC_C_PLL_MULT dbg_operate_order_of_trigger LAST_MEASUREMENT_RESULT_BANK_B DBG_PVT_REG_DRVP REG_OUT_DRVP_A termp_b_history cmd_addr MC_PCTL_PPCFG MC_PCTL_MSTAT qse_alen dtu_err_b0 dtu_allbits_1 MC_PCTL_TRSTH MC_PCTL_TCKSRX dtu_rd_row dtu_data_mask_en pvt_upd_done_type CK4OEN MC_INT_ENABLE MC_BIST_DATA_PATTERN MA_SGE_TH0_DEBUG_CNT DBG_READ_DATA_CNT MA_CIM_DEBUG_CNT ARB2_PAR_RDQUEUE_ERROR_EN CL3_PAR_WRQUEUE_ERROR_EN ARB1_PAR_RDQUEUE_ERROR IBQSGELOParErr IllWrBEIntEn IbqDbgAddr TimerEn CIM_DEBUG_PIF_UPACC_CAUSE_MASK MBGeneric CIM_PF_HOST_INT_CAUSE TtlMode OfdMpsStats TxDeferEnable TunnelCngDrop1 RxUrgMode LimitedTransmit EnableCSnd EnableDefer TP_FINWAIT2_TIMER TP_PORT_MTU_0 TP_TX_MOD_QUEUE_WEIGHT3 TP_PIO_ADDR TPReset FreeTxPageCount TP_TM_MOD_PUSH_CNT DisableTimeFreeze TxRxmNewReno CommitReset0 OfdRate1 TnlRate2 TnlRate1 stag_mix_enable ULP_TX_INT_ENABLE ULP_TX_FPGA_CMD_10 ERR_CH0 ULP_TX_LA_WRPTR_4 ULP_TX_LA_RDPTR_7 ch2_input strobe0 iespi1_Rx_framing_error PM_TX_STAT_CONFIG icspi0_Tx_framing_error oespi0_Tx_framing_error oespi3_ofifo2x_Tx_framing_error PrioPPPEnMap Prty7 SNF PGMO PG_TH_INT1 SOP_CNT_1 MAC_CNT0 LPBK_BP MPS_PORT_RX_OVLAN0 OVLAN_MASK Ch2_Prty DataCh3 DataPt3 MPS_PORT_TX_LPBK_RELOAD_CH0 MPS_TRC_RSS_HASH MPS_STAT_PERR_INT_ENABLE_TX_FIFO MPS_STAT_PERR_ENABLE_RX_FIFO MPS_PORT_STAT_TX_PORT_64B_L MPS_PORT_STAT_RX_PORT_PPP4_L MPS_PF_STAT_TX_PF_BCAST_FRAMES_H Cls_VF Cls_PF Priority0 cim_enable SlvFifoDbgClr SlvAlrtSet SMB_SLV_FIFO_RDWR CAUSE_PCMDF_1 PERR_ENABLE_APF_1 PERR_ENABLE_MPARC_0 LockStatus ModIndx TCAMCMDOVLAPEN LE_DB_INT_INDEX LE_DB_ACTIVE_MASK_IPV4 strp_crc CH2_SADDR_EN NC2MPS_SOP_CNT PauseRcvd RxOverrun WOL_Reset Tx_Polarity_Inv DisBCast XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_6 PauseCntrTimeOut XGMAC_PORT_XGM_STAT_TX_MCAST XGMAC_PORT_XGM_STAT_TX_1024_1518B_FRAMES XGMAC_PORT_XGM_STAT_RX_128_255B_FRAMES XGMAC_PORT_PCSR_TXTEST_CTRL tx_prbs31_en Echoed_Nonce TXPOL C1UPDT XGMAC_PORT_HSS_TXB_TAP2_COEFF XGMAC_PORT_HSS_TXB_PWR RCLKEN AOFFO ADMAG ODEC XGMAC_PORT_HSS_RXC_PH_ROTATOR_OFFSET_CTRL XGMAC_PORT_HSS_RXC_DFE_H4 XGMAC_PORT_HSS_RXD_CFG_MODE SGE_PF_KTIMESTAMP_LO SGE_INT_CAUSE5 perr_payload_fifo1 SGE_FETCH_BURST_MAX_0_AND_1 CGEN_Egress_Context CGEN_EDMA dbp_fetch_threshold_fl debug_T_Rx_EOP0_cnt debug_U_Tx_EOP3_cnt SGE_DEBUG_DATA_HIGH_INDEX_5 SGE_DEBUG_DATA_HIGH_INDEX_14 debug_st_idma0_idma_sm debug_flm_dbptr_qid Ingress2_Size PIOReqGrpPerr IPPerrEn TotMaxTag PERstTimerCount PCIE_MA_STAT IDO PCIE_FLR_PIO Enter_ASPM_L1_wo_L0s TxPD_FC TxNPH_FC PCIE_CORE_VC0_COMPLETION_RECEIVE_QUEUE_CONTROL PCIE_HPRD CID PB_Func CfgInitCoeffDone LnE_STAT TVSENSE_RST T5_STATIC_M_PLL_BYPASS DBG_T5_STATIC_M_PLL_CONF4 T5_STATIC_SWMC0Rst_ T5_STATIC_C_PLL_FFTUNE DBG_T5_STATIC_C_PLL_CONF5 T5_STATIC_U_PLL_MULTFRAC T5_STATIC_KR_PLL_CCALLOAD T5_STATIC_KR_PLL_N1 GPIO18_PE_En MA_PMTX_RDDATA_CNT MA_HOST_MEMORY_WRDATA_CNT1 CL7_WR_CMD_TO_EN CL7_RD_DATA_TO_EN DEBUG_OR FcoeFPMA IdleCwndHighSpeed ByteCountNewReno OverdriveReno MPS_TX_PAUSE_RETRANS_BUF_GRP_TH0 MPS_TX_PAUSE_RETRANS_BUF_GRP_TH11 MPS_RX_PAUSE_GEN_TH_0_3 MPS_RX_CGEN_LPBK_IN LpbkPadEnPt2 TP2MPS_Ch2 MPS_TRC_FILTER1_RSS_CONTROL MPS_TRC_FILTER2_RSS_CONTROL MPS_STAT_PERR_INT_CAUSE_SRAM1 MPS_STAT_STOP_UPD_RX_VF_96_127 PDP_Part_CGEn terminate_status_en DDP_HINT_1 MC1 MapMAC2 PL_PCIE_LINK CMPUNVAIL MtipSd0TxRst RXAQUIET_STATUS sd5_CGEN MAC_PORT_CGEN_MTIP TICK_START MAC_PORT_ETHERSTATSPKTS128TO255OCTETSHI MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETSHI CuSpeed CLK_DIV HiBERLH MAC_PORT_MTIP_10GBASER_SEED_A2 AMLOCK3 AMLOCK9 MAC_PORT_MTIP_PCS_LANE_MAP_7 MAC_PORT_BEAN_REM_ABILITY_0 MAC_PORT_BEAN_ETH_STATUS MAC_PORT_BEAN_MS_COUNT_LANE1 MAC_PORT_BEAN_CTL_LANE2 MAC_PORT_BEAN_REM_ABILITY_1_LANE2 MAC_PORT_BEAN_MS_COUNT_LANE2 MAC_PORT_BEAN_ETH_STATUS_LANE2 MAC_PORT_FEC_KR_STATUS Initialize FEC_LOCKED MAC_PORT_AE_TX_DIS MAC_PORT_AET_STATUS_2 MAC_PORT_ANALOG_TEST_MUX MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_2 AESRC T5REGBYP MAC_PORT_TX_LINKA_TRANSMIT_AMPLITUDE ANLGFLSH MAC_PORT_TX_LINKC_TRANSMIT_DCC_CONTROL MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_APPLIED MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT PATSEL DUTYQ T5DACCMP T5_RX_SETHDIS MAC_PORT_RX_LINKA_DFE_H8_AND_H9 AMPSEL MTHOLD MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_3 MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_2 MAC_PORT_RX_LINK_BCST_DFE_H12 AD32S_PLL_LOCK RANK_PAIR2_SEC_V RANK_PAIR3_SEC_V ENA_INITIAL_PAT_WR ENA_COARSE_RD ERROR_READ_CTR DI_ADR14_ADR15 MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1 MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP1 PLL_PLLXTR_0_1 SYSCLK_PHASE_DEFAULT_EN ATEST1CTL2 MC_DDRPHY_DP18_WRCLK_PR DQSCLK_SELECT0 MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR INCOMPLETE_RD_CAL_N2 CLK_LEVEL SMALL_STEP_RIGHT FW_LEFT_SIDE WL_ERR_CLK20 MEMINTD18_POS DP18_RX_PD EARLY_REQ_SOURCE MC_DDRPHY_SEQ_ODT_WR_CONFIG3 MC_DDRPHY_SEQ_MEM_TIMING_PARAM0 MC_DDRPHY_WC_CONFIG3 cmd_opcode0 MC_UPCTL_DTUPDES MC_UPCTL_TOGCNT1U MC_UPCTL_DTUCFG MC_UPCTL_DFITPHYUPDTYPE1 MC_UPCTL_DFISTCFG2 MC_UPCTL_DFITRRDLVLDELAY0 PERR_INT0_CAUSE HMA_TABLE_LINE4 FID debug_bar2_sop_cnt debug_st_idma1_idma2imsg thread_st_main Req_LnC_RxPwrState Req_LnB_RxStateReq Req_LnA_RxPwrState Req_LnL_RxStateReq LnL_CMD PCIE_VF_MSI_EN_6 HdrFreeCnt DataFreeCnt DBG_STATIC_M_PLL_CONF2 DBG_STATIC_U_PLL_CONF4 STATIC_KR_PLL_VBOOSTDIV DBG_STATIC_KR_PLL_CONF2 STATIC_KX_PLL_CCALFMIN DBG_CUST_EFUSE_BYTE44_47 FUTURE_CEXPANSION_RTE slow_timer_enable EnableFinCheck ForceShove ULPType3Offset TlsDisable sge_fifo_perr_set3 MPS_RX_CONGESTION_THRESHOLD_BG0 MPS_RX_VXLAN_TYPE MPS_RX_LENGTH GRE_VER MPS_PORT_RX_VF_MAP5 MPS_CLS_MATCH_CNT_BMC ULP_RX_TLS_IND_DATA PRI_HASH BkChkPeriod Ena_err_rsp sgmii_sgpcs_ena sgmii_reset_tx_clk pcs40g_reset_sd2_rx_clk mac40g100g_reset_ff_tx_clk mac40g100g_reset_ts_clk mac1g10g_reset_rxclk MAC_PORT_AEC_XGMII_TIMER_HI_40G mac40g100g_tx_rem_fault Perr_rx15_pcs100g TX_LOWP_ENA LOOP_ENA READ_MODE CL0_PAUSE_QUANTA CL5_PAUSE_QUANTA MAC_PORT_MTIP_1G10G_RX_CRCERRORSHI MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS65TO127OCTETS MAC_PORT_MTIP_1G10G_ETHERSTATSPKTS1519TOTX_MTU MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_4HI MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_7HI Auto_Negotiation_Present PMD_PMA_Present Device_Present Receive_FIFO_Fault MAC_PORT_MTIP_KR4_STATUS_1 LANE_1_ALIGN_MRKR_LCK Scrambled_ID_TP_EN Lane3_algn_mrkr_lck Lane0_algn_mrkr_lck Lane15_algn_mrkr_lck MAC_PORT_MTIP_RS_FEC_CCW_HI MAC_PORT_MTIP_RS_FEC_SYMBLERR3_HI MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_TRIGGER T5_AE2_RXSTAT_LSNA CAL_BISTENAB ISVAL MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE AS1X5 MAC_PORT_TX_LINKA_TRANSMIT_AE_C1_INIT2_EXTENDED MAC_PORT_TX_LINKB_TRANSMIT_AE_C3_INIT2_EXTENDED MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_3_COEFFICIENT MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_7_6 MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C0_LIMIT_EXTENDED RASEL MAC_PORT_RX_LINKA_RECEIVER_DACA_MIN MAC_PORT_RX_LINKA_CDR_ANALOG_SWITCH CDRANLGSW DCCCMP H4MAG PRBSOFFCMP DCDTMDOUT MAC_PORT_RX_LINKC_DFE_OFFSET_VALUE MAC_PORT_RX_LINKC_H_COEFFICIENBT_BIST MAC_PORT_RX_LINKD_AC_CAPACITOR_BIST ADDR_MIRROR_A7_A8 WR_LVL_DONE WR_CNTR_DONE MC_PROTOCOL QDEPTH DEF_REF RD_DEFREF_CNT CMD_ACTN MC_LMC_CMD15 T_RTWO MC_LMC_SDTR3 FAW_ADJ IVM_MODE RTT_PARK VREF_DQ_RANGE EDC_H_DBG_MA_CMD_INTF BCmdAddr EDC_H_DBG_EDRAM_CMD_INTF EDC_H_DBG_EDRAM0_RDATA_INTF EDC_H_DBG_FIFO_STATUS inp_beq_wrrdy_open RefDone HMA_REG1_MAX ADDR3_MAX HMA_RTF_ERR MPS_VF_STAT_TX_VF_OFFLOAD_BYTES_H MPS_VF_STAT_RX_VF_BCAST_FRAMES_L CIM_VF_EXT_MAILBOX_DATA_08 CIM_VF_EXT_MAILBOX_DATA_28 CIM_VF_EXT_MAILBOX_DATA_34 loadfw vlan ovlan and vnic_id (pf/vf) are mutually exclusive OnChipQueue: CongestionMgtEnable: InterruptSent: %-*s StatusPgTPHint: CongDrop: invalid scheduling sub-command "%s" invalid socket-type "%c" on line %zd. any TLS TF_CORE_URG Send next rx_frag1_len aux1_slush1 TF_DDP_INDICATE_OUT TF_DDP_ACTIVE_BUF rx_ddp_buf1_tag maxseg %u, recv_scaleflag %u, recv_tstmp %u, recv_sack %u
rcv_nxt %-10u hdr_off %-10u
pend_ctl: 0x%1x, unused_flags: 0x%x, main_slush: 0x%x
Loopback_TX_Loopback ind_full: %u, tls_key_mode: %u
FLSplitMode EgrStatusPageSize SGE_WR_ERROR perr_pc_chpi_rsp0 perr_eswitch_fifo0 SGE_FL_BUFFER_SIZE2 MPS_Enable RspCreditEn1 err_bad_upfl_inc_credit2 SGE_PC0_RSP_BIST_CMD SGE_CTXT_DATA0 SGE_CTXT_MASK2 SGE_LA_RESERVED_6 SGE_LA_RESERVED_12 HRspPerr ForceTxError AI PFNum PCIE_MSI_EN_2 RPCS OP2H RLFI GPIO11_Out_Val GPIO3_IN GPIO5_ACT_LOW REG_OUT_DRVN_A rank2_odt_read_nsel MC_PCTL_TRTP MC_PCTL_DTUWACTL dtu_incr_banks dtu_rd_byte3 dtu_rd_byte2 dtu_rd_byte8 pvt_upd_trig_type CKEPOND SDRCLKEN MC_DDR3PHYDATX8_RDBDMR MC_PVT_REG_IN_TERMP MA_CLIENT3_WR_LATENCY_THRESHOLD MA_PARITY_ERROR_STATUS CL9_PAR_WRQUEUE_ERROR COHERANCY_CMD_TYPE EDC_BIST_USER_WDATA2 FlashAddrSize ReqOvrLookupInt POLADbgRdPtr DAddrIllegal VLANExtEnablePort0 ByteThreshold EnableEMacAFull EngineLatencyBase DropErrorTcpOpt DropErrorEthHdrLen DropErrorAttack ULPType2Field ULPType1Field TNL4tupEnIpv6 ChnUndFlow1 TP_TX_MOD_QUEUE_WEIGHT6 RxModXoff0 TP_IX_SCHED2 TnlRate3 RequestDone sge2ulp_fifo_perr_set1 CQE_fifo_perr_set1 ULP_TX_CPL_ERR_VALUE_H ULP_TX_FPGA_CMD_4 CLR_DROP ULP_TX_LA_WRPTR_3 ULP_TX_LA_RDDATA_8 ULP_TX_LA_WRPTR_9 iespi2_Rx_framing_error icspi1_Tx_framing_error StatInt PPPEn SgeSending MPS_PORT_PRTY_BUFFER_GROUP_MAP DRAIN MPS_RX_LPBK_BP3 MPS_PFVF_ATRB_FLTR7 SOP_CNT_IN LPBK_CNT0 MPS_RX_CLS_DROP_CNT1 LPBK_CNT2 MPS_PORT_RX_VF_MAP1 MPS_PORT_RX_VF_MAP2 pt1 MPS_TX_DEBUG_SUBPART_SEL MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H MPS_PORT_STAT_TX_PORT_ERROR_L MPS_PORT_STAT_TX_PORT_128B_255B_H MPS_PORT_STAT_TX_PORT_PPP2_L MPS_PORT_STAT_TX_PORT_PPP4_H MPS_PORT_STAT_LB_PORT_BCAST_L MPS_PORT_STAT_LB_PORT_64B_H MPS_PORT_STAT_LB_PORT_256B_511B_L MPS_PORT_STAT_RX_PORT_PPP2_H MPS_PF_STAT_RX_PF_MCAST_FRAMES_H MPS_PF_STAT_RX_PF_UCAST_BYTES_L MPS_PF_STAT_RX_PF_ERR_FRAMES_H MPS_CLS_ARB_WEIGHT LpbkWeight SMB_SLV_TIMEOUT_CFG MstNAckInt SMB_SLV_AUX_ADDR3 SMB_COMMAND_CODE7 PMU_PART_CG_PWRMODE CAUSE_FF PERR_ENABLE_MPARF_0 SOP_CNT_IN0 SF_DATA ByteCnt PL_PERR_CAUSE HMA LE_BUF_CONFIG SYNCookie ActRgnFull LE_DB_INT_CAUSE DBGICMDSEARCH ReqQueue LE_DB_DROP_FILTER_ENTRY NCSI_RX_OF_CNT TxSndPause TxBufQPtr NCSI_MACB_INT_EN NCSI_MACB_INT_MASK SinkTxOnLinkDown tx_eop_count XGMAC_PORT_MAGIC_MACID_HI remflt XGMAC_PORT_EPIO_DATA2 Address XAUI_Dec_Error RXAPRBSSYNC EnHashMcast XGMAC_PORT_XGM_STAT_RX_PAUSE_FRAMES polarity_inv_tx Remote_Fault RXREQ_C1 TPGEN NTXPOL XGMAC_PORT_HSS_TXB_POLARITY XGMAC_PORT_HSS_RXA_TEST_CTRL RCALER RDOFF ASAMP DACCVG BER3VAL DDCCMP FVGAIN FNRDF XGMAC_PORT_HSS_TXC_TAP1_IDAC_APP XGMAC_PORT_HSS_TXD_TAP0_COEFF XGMAC_PORT_HSS_TXD_TAP1_IDAC_OVR XGMAC_PORT_HSS_TXD_PWR_DAC_OVR XGMAC_PORT_HSS_TXD_EXT_ADDR XGMAC_PORT_HSS_RX_PH_ROTATOR_POSITION2 Cause_Register Cause_Bit err_T_RxCRC perr_CIM2SGE_RxData FetchBurstMax0 SGE_CONTROL2 IDMA1_Sleep_Status IDMA1_Sleep_Req debug_T_Rx_SOP0_cnt debug_PC_Req_EOP1_cnt debug_PD_RdReq_EOP0_cnt debug_PD_WrReq_EOP0_cnt debug_flm_idma0_cache_hdr_active debug_st_dbp_thread0_cimfl debug_st_dbp_thread3_cimfl debug_flm_cache_locked_count SGE_DEBUG_DATA_LOW_INDEX_13 IPRetryPerr MEMReqRdTagErr PCIE_COOKIE_STAT StateCfgInitF N_FTS Replay_Timer_Modifier PCIE_CORE_VC1_NONPOSTED_RECEIVE_QUEUE_CONTROL PCIE_CORE_PHY_CONTROL NPH_CreditsRequired DisabledLogEn LnB_RxStateDone PCIE_PHY_GEN3_AE0 PCIE_PHY_GEN3_AE1 Lane2FS PCIE_STATIC_SPARE2 GPIO16_CHG_DET GPIO18 DBG_FEGATEC T5_STATIC_M_PLL_LOCKTUNE T5_STATIC_PHY1RecRst_ T5_STATIC_C_PLL_MULTFRAC DBG_T5_STATIC_U_PLL_CONF5 GPIO15_PS_En GPIO4_PS_En CL10_WR_DATA_TO_EN CL2_WR_CMD_TO_ERROR ibq_skid_fifo_eop_flsh_dsbl VLANExtEnPort3 ULP_TX_MEM_CFG PTCPORT2 PTCP2EN MacPadEnPt3 TxInCh2_CGEN CountLbPF MPS_STAT_STOP_UPD_TX_VF_0_31 MPS_PORT_STAT_RX_PORT_MAC_ERROR_L PERR_SE_CNT_MISMATCH_1 immediate_with_se_opcode RDMA_CGEN ULP_RX_INT_ENABLE_2 ENABLE_PF_UNTAGGED_TPT_0 MC0 PerrCapture HASHCLKOFF MtipSd3RxRst Perr3_rx_sd TXBREFRESH MAC_PORT_HSS_CFG3 TXBREFRESH_STATUS pma_rx_refresh sd4_CGEN MACSEG5_CGEN MAC_PORT_EEE_RX_1G_WAKE_TIMER Y ADD_OFFSET MAC_PORT_MTIP_REVISION MAC_PORT_MTIP_INIT_CREDIT MAC_PORT_AALIGNMENTERRORS MAC_PORT_ETHERSTATSDROPEVENTS MAC_PORT_ETHERSTATSPKTS128TO255OCTETS MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2 Isolate SpeedSel0 ExtdStatus MAC_PORT_MTIP_TXCLK_CTL_SEG SPEED_SEL1 40GBASE_R MAC_PORT_MTIP_BLK_HIGH_ORDER_CNT Lane4 MAC_PORT_MTIP_PCS_BIP_ERR_CNT_14 MAC_PORT_MTIP_PCS_LANE_MAP_19 T5_FEC_ABILITY MAC_PORT_BEAN_REM_ABILITY_2_LANE2 MAC_PORT_PLLA_PCLK_CONTROL MAC_PORT_PLLA_MACRO_TEST_CONTROL_3 PLLBYP MAC_PORT_PLLB_MACRO_TEST_CONTROL_3 T5_TX_RXLOOP CPREST MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_2 MAC_PORT_TX_LINKB_TRANSMIT_COEFFICIENT_CONTROL MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE MAC_PORT_TX_LINKB_TRANSMIT_DCC_TIME_OUT MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C2_INIT_EXTENDED MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_2 MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_APPLIED MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_1 MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C1_INIT_EXTENDED MAC_PORT_RX_LINKA_PHASE_ROTATOR_OFFSET_CONTROL ADSN_ReadOnly MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 T5DDCCMP LOFE4S_ReadOnly MAC_PORT_RX_LINKA_RECEIVER_LOFF_CONTROL HALF2 H2ESN_ReadOnly H3ESN_ReadOnly H9SN_ReadOnly MAC_PORT_RX_LINKB_RECEIVER_CONFIGURATION_MODE MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_1 MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_1 PLL_RESET MC_DDRPHY_PC_MR2_SEC_RP MC_ADR_DDRPHY_ADR_DELAY4 POST_CUR_SEL_BITS0_1 MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE SLEW_CTL2 ANALOG_INPUT_STAB1 DQ_WR_OFFSET_N1 MC_DDRPHY_DP18_SYSCLK_PR_VALUE MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR COARSE_PATTERN_ERR_N1 DIGITAL_EYE_EN CNTL_SRC MEMINTD02_POS HS_PROBE_A_SEL MC_DDRPHY_WC_CONFIG0 DEBUG_BUS_SEL_HI DP18_4_Populated mddr_lpddr2_en MC_UPCTL_DTUPRD0 MC_UPCTL_DTUPRD1 MC_UPCTL_TRFC MC_UPCTL_TCKSRE MC_UPCTL_DTURD3 odt_rank_map0 dfi_ctrlupd_en dfi_freq_ratio_en MC_P_ECC_STATUS fatal_wre_len coal_ctl_fifo_cnt merge_fifo_cnt fatal_large_coal wr_deq_cnt wr_enq_cnt PfMaxWCSize Cur_LnH_RxPwrState Cur_LnD_RxPwrState Req_LnL_RxStateDone Req_LnJ_RxStateReq PCIE_VF_MSI_EN_5 STATIC_M_PLL_FRAMESTOP STATIC_U_PLL_MULTPRE STATIC_U_PLL_FASTSTOP STATIC_KX_PLL_CCALMETHOD FUTURE_CEXPANSION_RTS FUTURE_DEXPANSION_RTS DisableSepPshFlag TnlErrorOpaque map_fifo_perr_set1 save_last MPS_RX_CONGESTION_THRESHOLD_BG1 Outer_IPv4_n_Double_VLAN_VXLAN MPS_CLS_REQUEST_TRACE_PORT_VLAN MPS_CLS_TCAM_RDATA1_REQ_ID1 rdma_version_1 LE_DB_HASH_MASK_GEN_IPV6 Led1_tlo aec_tx sgmii_gmii_crs MAC_PORT_PERR_INT_CAUSE_100G MAC_PORT_MAC_25G_50G_AM2 Perr_tx0_pcs40g MAC_PORT_MTIP_1G10G_REVISION COL_CNT_ExT CNTL_FRM_ENA MAC_PORT_MTIP_1G10G_RX_CRCERRORS MAC_PORT_MTIP_1G10G_RX_IFINMULTICASTPKTSHI MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS512TO1023OCTETSHI MAC_PORT_MTIP_1G10G_RX_AFRAMETOOLONG MAC_PORT_MTIP_1G10G_TX_AALIGNMENTERRORS MAC_PORT_MTIP_1G10G_TX_FRAMESOKHI MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_0 MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_5 MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_2 Speed_SEL2 MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_3 Receive_link_STAT 10PASS_TS_2Base_TL_capable MAC_PORT_MTIP_KR4_DEVICES_IN_PKG1 Vendor_specific_device1 40GBase_R_capable MAC_PORT_MTIP_KR4_BASE_R_STATUS_1 Lane2_algn_mrkr_lck Lane19_algn_mrkr_lck MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_0 MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_8 MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_9 MAC_PORT_MTIP_CR4_LANE_7_MAPPING MAC_PORT_MTIP_CR4_LANE_8_MAPPING MAC_PORT_MTIP_FEC2_NCERR_CNT_1 T5_AE0_RXSTAT_LSNA FEC_SUPPORTED MAC_PORT_PLLA_POWER_CONTROL MAC_PORT_TX_LINKA_TRANSMIT_TAP_3_COEFFICIENT OS1X2 C3MIN MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_5_4 MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_STEP_SIZE_EXTENDED MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C1_INIT_EXTENDED MAC_PORT_RX_LINKA_DFE_H1H2H3_LOCAL_OFFSET_VALUE ACCEN LFTGT FCLKALGN FCSADJ DCCQCCMODE MAC_PORT_RX_LINKC_DFE_OFFSET_CHANNEL MAC_PORT_RX_LINKC_DFE_H12_13 MAC_PORT_RX_LINKD_CDR_ANALOG_SWITCH MEMORY_TYPE DESIRED_EDGE_CNTR_TARGET_HIGH MT_WRCLK_CAL_START T_RFC_XPR SMR2_RFU0 MC_IDLE_TH BRspVld dead_cycle1_post_ref dead_cycle0_post_ref_rmw REGION HMA_TLB_DESC_2_L HMA_TLB_DESC_7_L IDTF_INT_CAUSE CIM_VF_EXT_MAILBOX_DATA_2c tcb uart "%s" is neither an index nor a filter subcommand. "prio" is the only valid keyword after "%s", found "%s" instead. %20s %20s %9s %9s %s
ipv6 sport matchtype ipv6 hitcnts address %s is not of expected family %s PadEn: TimerIx: read_mem: malloc filter pattern: XPAK flow invalid rate-mode parameter "%s" Unable to open file "%s" offload "%s" is not a valid keyword, or it does not support negation. "%s" is not a valid keyword, or it requires a parameter that has not been provided. CLOSE_WAIT LAST_ACK DDP Source MAC address index keepalive timer rx_pdu_out TF_FAST_RECOVERY cctrl_ece cctrl_cwr Slow Start threshold OPT_0_NO_CONGESTION_CONTROL OPT_0_NON_OFFLOAD Length_Max perr_pc_dbp0 SGE_FLM_CACHE_BADDR Threshold_1 Enable_Drop RspCreditEn0 RspCreditEn3 IngCtxtOpMode HintsAllowedNoHdr MinTag3 SGE_PC1_REQ_BIST_ERROR_CNT SGE_LA_RDPTR_0 SGE_LA_RDDATA_6 SGE_LA_RDPTR_10 SGE_LA_RDDATA_11 CfgdMaxPyldSzTx CfgdMaxRdReqSz FIDTableInvalid StateReq Enable PIOPause Select PCIE_REVISION CH0_WEOP PCIE_MSIX_EN_1 PCIE_MSIX_EN_4 RFTP IP0D IC0T PCIE_CORE_UTL_PCI_EXPRESS_PORT_CONTROL PLDI RLCE RCPE RCTO RLFS PABS PADS PAAI AENS PCIE_PF_CFG GPIO3_OEn DBG_GPIO_IN P_LOCK_ACT_LOW GPIO0_ACT_LOW STATIC_MPLL_CLK_SEL DBG_PVT_REG_OUT_DRVP DBG_PVT_REG_HISTORY_TERMN power_up_done ddr3_en dtu_allbits_0 MC_PCTL_DTUPRD1 MC_PCTL_DTUPRD3 MC_PCTL_TMRD MC_PCTL_DTUWD0 dtu_wr_byte14 dtu_rd_byte13 phy_upd_trig_pol CKOEN WDBDVT MC_PVT_REG_HISTORY_TERMP START_BIST THRESHOLD1_EN MA_CLIENT9_RD_LATENCY_THRESHOLD MA_CLIENT12_WR_LATENCY_THRESHOLD EXT_MEM_ENABLE BlkRdFlashIntEn SglWrFlashIntEn CIM_HOST_UPACC_INT_CAUSE BlkRdFlashInt IBQSelect HostAddr LAMaskTrig DebugSelL CIM_GLB_TIMER_CTL CIM_UP_OPERATION_FREQ MBMsgRdyInt IPv6Enable RxCoalesceEnable EnableCSav TableLatencyStart DropErrorPing TP_TM_CONFIG HashToeplitz UpdChn3 DbOpPerr TxModXoff7 DbgLaOpcEnable Pbl_bound_err_ch1 Pbl_bound_err_ch0 Ch3Size2 ULP_TX_FPGA_CMD_0 ULP_TX_FPGA_CMD_11 ocspi0_Tx_framing_error MPS_VF_TX_CTL_31_0 MPS_TX_PAUSE_DURATION_BUF_GRP1 RxSendEn Prty0 MPS_RX_PORT_MUX_CTL MPS_RX_PKT_FL MPS_RX_PG_RSV3 PPM1 PG_TH_INT2 MPS_RX_PT_ARB0 MPS_RX_SE_CNT_OUT01 EOP_CNT_0 MAC_CNT1 PPP_FWD_UP MPS_PORT_RX_PF_MAP QUE_NUM SeCnt PortL ProtocolID MPS_PORT_TX_FIFO_CTL FifoEn TfOffset MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L MPS_PORT_STAT_TX_PORT_PPP3_L MPS_PORT_STAT_RX_PORT_BYTES_H MPS_PORT_STAT_RX_PORT_65B_127B_L MPS_PORT_STAT_RX_PORT_512B_1023B_H MPS_PORT_CLS_CTL MPS_CLS_PL_TEST_DATA_L SlvUnExpBusStopEn SlvRxRdyIntEn MstTimeOutIntEn DebugDataH SMB_SLV_AUX_ADDR2 SMB_COMMAND_CODE6 PCMD0Threshold ENABLE_TPTCF_1 ENABLE_MPARC_0 SEL_H ULP_RX_LA_WRPTR XGMAC1 SF MapXGMAC_KR0 PL_PF_ENABLE MAP4 PL_TIMEOUT_STATUS1 ASLIPCOMPEN HASHSIZE LE_DB_INT_PTID DBGIRspIndex SVRBASE_ADDR LE_HASH_MASK_GEN_IPV4 LE_RSP_DEBUG_LA_HASH_WRPTR CH0_SADDR_HIGH NCSI_WORK_REQHDR_0 STRIP_OVLAN arb_status RxBufOffset TxComplete RxUsedBitRead NCSI_MACB_MUL_COL_FRAMES BEAN_Reset TXBOBS HSSRXACMODE HSSPDWNPLL RXDPHSUPIN XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_3 XGMAC_PORT_XGM_STAT_TX_512_1023B_FRAMES XGMAC_PORT_XGM_STAT_RX_256_511B_FRAMES FECErrIndEn rx_fault XGMAC_PORT_AN_MODULE_ID XGMAC_PORT_AE_TX_COEF_STAT CC2FSM_STATE C0STAT RSEL FBER6 XGMAC_PORT_HSS_RXB_VGA_CTRL1 XGMAC_PORT_HSS_TXD_8023AP_AE_STATUS XGMAC_PORT_HSS_TXD_PWR_DAC XGMAC_PORT_HSS_RXC_DFE_AMP_SAMPLE XGMAC_PORT_HSS_RXD_PH_ROTATOR_STATIC_PH_OFFSET XGMAC_PORT_HSS_RXD_DFE_CTRL XGMAC_PORT_HSS_RXD_DACA_OFFSET XGMAC_PORT_HSS_TX_PWR_DAC XGMAC_PORT_HSS_RX_DIGITAL_EYE_METRICS EgrThresholdPacking err_wr_len_too_large3 SGE_FETCH_BURST_MAX_2_AND_3 EDMA0_Sleep_Req debug_U_Rx_EOP1_cnt debug_UD_Rx_EOP3_cnt debug_PC_Rsp_SOP0_cnt debug_st_flm_idma0_ctxt debug_st_imsg PCIE_CFG6 STATIC_SPARE3 PCIE_FLR_PF_STATUS PCIE_CORE_VC_TRANSMIT_ARBITRATION_1 VC5_WRR Eql_PH2_PH3_Disable Cursor PCIE_CORE_GEN3_EQ_STATUS ReqBurstCount IPRxData_VC0Perr ChNum PCIE_CHANGESET LnG_RxStateDone LnB_CMD Lane4FS T5_STATIC_M_PLL_RESET T5_STATIC_SWMC0CfgRst_ DBG_T5_STATIC_U_PLL_CONF2 T5_STATIC_U_PLL_LFTUNE_32_40 GPIO12_PE_En DBG_EFUSE_BYTE20_23 MA_PARITY_ERROR_ENABLE2 CL6_WR_DATA_TO_ERROR CL7_RD_CMD_TO_EN CL8_RD_CMD_TO_ERROR CL12_RD_DATA_TO_ERROR CL5_RD_DATA_TO_ERROR CL7_IF_PAR_ERROR SetTimeEnable RxmtCwndHighSpeed ULP_TX_ASIC_DEBUG_0 FPGA_PTP_PORT MPS_TX_PAUSE_DURATION_BUF_GRP_TH3 MPS_TX_PAUSE_RETRANS_BUF_GRP_TH5 MPS_RX_PAUSE_GEN_TH_3_2 MPS_RX_MAC_CLS_DROP_CNT0 MPS_PORT_RX_PTP_RSS_CONTROL TP2MPS_Ch3_CLR MPS_TRC_VF_OFF_FILTER_2 MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L LPBK_SMAC_TCAM_SEL TCAM1_HIT_PRIORITY DMAC_TCAM_SEL SGE_Part_CGEn umudp_pbl_pref_enable ENABLE_ALN_SDC_ERR_1 LE_SRVR_SRAM_INIT LE_FULL_CNT_COLLISION MtipSd2RxRst AEC1_RX_WIDTH tx_stats HSSRESYNCA HSSVCOSELA RXAASSTCLK T5RXDPRBSRST sd3_CGEN MAC_PORT_PTP_TIMER_OFFSET_1 Q MAC_PORT_MTIP_COMMAND_CONFIG MAC_PORT_RX_PAUSE_STATUS MAC_PORT_ETHERSTATSFRAGMENTSHI Reset 100BaseXHalfDplx CL45_EN MAC_PORT_MTIP_VLAN_TPID_2 RESET Lane14 MAC_PORT_MTIP_PCS_LANE_MAP_8 MAC_PORT_MTIP_PCS_LANE_MAP_13 MAC_PORT_MTIP_PCS_LANE_MAP_15 MAC_PORT_MTIP_PCS_LANE_MAP_18 AN_RESET TX_NONCE MAC_PORT_BEAN_XNP_0 MAC_PORT_LP_BEAN_XNP_2 MAC_PORT_BEAN_CTL_LANE3 fec_en MAC_PORT_AE_TX_COEF_REQ MAC_PORT_AE_FSM_STATE_2 MAC_PORT_AE_KR_STATUS_2 REFVALIDA MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_4 EMIL MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_2 MAC_PORT_TX_LINKA_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE DCCSIGN MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_APPLIED MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED ROT90 MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_1 MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_2 LOFE MAC_PORT_RX_LINKA_DIGITAL_EYE_CONTROL MAC_PORT_RX_LINKA_DFE_TAP_ENABLE H2ESN_ReadWrite MAC_PORT_RX_LINKB_RECEIVER_ADAC_CONTROL MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_1 MAC_PORT_RX_LINKC_RECEIVER_DACAP_AND_DACAN MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_1 MAC_PORT_RX_LINKD_DYNAMIC_DATA_CENTERING_DDC MAC_PORT_RX_LINK_BCST_RECEIVER_TEST_CONTROL MAC_PORT_RX_LINK_BCST_DFE_CONTROL MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD3_ODD4 MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PATTERN_LENGTH RANK_PAIR1_SEC_V MC_DDRPHY_PC_PER_ZCAL_CONFIG MC_DDRPHY_PC_ERROR_MASK0 PVTP MC_DDRPHY_PC_INIT_CAL_CONFIG1 ERROR_RANK_PAIR POST_CUR_SEL_BITS14_15 BB_LOCK MC_DDRPHY_ADR_SLEW_CAL_CNTL CLK22_SINGLE_ENDED_BIT13 MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR MC_DDRPHY_DP18_WR_CNTR_STATUS1 MC_UPCTL_TRSTH prea_extra MC_UPCTL_TWTR MC_UPCTL_TRSTL MC_UPCTL_DFIODTRANKMAP odt_rank_map3 parity_log_clr MC_UPCTL_DFITRWRLVLRESP1 MC_UPCTL_DFITRRDLVLGATEDELAY2 STATIC_SLAT USER_DATA_MASK EDC_H_INT_ENABLE coal_all_thread SGE_DEBUG1_DBP_THREAD debug_idma1_idma2imsg_cmp_in_drdy debug_idma0_IDMA2IMSG_Full PfWCOffset KDB_PF_BaseAddr PCIE_PHY_FS_LF4 STATIC_U_PLL_SDORDER DBG_CUST_EFUSE_BYTE4_7 DBG_CUST_EFUSE_BYTE8_11 DIS_128B_PG_CNT_FDBK RMWHintEnable EV6FlwEn ULPType4Offset ULPType2Length atomic_fix_dis MPS_VF_TX_CTL_223_192 MPS_VF_RPLCT_MAP5 MPS_VF_RPLCT_MAP7 MPS_RX_CONGESTION_THRESHOLD_BG3 MPS_RX_UDP HASH_EN_LPBK Inner_VLAN_VLD MPS_CLS_DIPIPV6MASK_2_TABLE DataLkpType iscsi_enable_hdr_cmd ULP_RX_TLS_KEY_LLIMIT debug_clr mac40g100g_gate_rxclk AEC_RX_UNKNOWN_LANE_3 CU_C3_ACK_VALUE mac1g10g_ff_tx_ovr_err pcs40g_block_lock Perr_rx3_fec100g_dk Perr_tx3_pcs100g RXCERROFLOW MAC_PORT_MTIP_1G10G_MAC_ADDR_1 CL3_PAUSE_QUANTA CL3_QUANTA_THRESH CL5_QUANTA_THRESH MAC_PORT_MTIP_1G10G_CL67_QUANTA_THRESH SATURATE MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_6HI MAC_PORT_MTIP_SGMII_LP_NP_RX MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_2 Speed_selection2 Device_present Lane11_algn_mrkr_lck Lane8_algn_mrkr_lck MAC_PORT_MTIP_RS_FEC_VENDOR_REVISION T5_AE2_RXSTAT_FEC FEC_CNV MAC_PORT_VREFTUNE_CONTROL RCAL_RESET BSOUTN MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED MAC_PORT_TX_LINKC_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE MAC_PORT_TX_LINKD_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SIGN_APPLIED_REGISTER ROTD MAC_PORT_RX_LINKA_RECEIVER_DACAP_AND_DACAN_SELECTION ADAC2 ACCPLGAIN H13MAG MAC_PORT_RX_LINKB_RECEIVER_POWER_MANAGEMENT_CONTROL MAC_PORT_RX_LINKC_RECEIVER_IQAMP_CONTROL_2 MAC_PORT_RX_LINKD_DFE_H12_13 MAC_PORT_RX_LINKD_DFE_H14_15 MAC_PORT_RX_LINK_BCST_RECEIVER_DACA_MIN MAC_PORT_RX_LINK_BCST_RECEIVER_LOFF_CONTROL_REGISTER QUAD0_CAVEAT DFI_INIT_COMPLETE UIOS CA_PTY_DLY MC_LMC_INITSEQ6 T_CWL BL TCR_RANGE MC_P_RMW_PRIO EDC_H_DBG_EDRAM_WDATA_INTF inp_cmdq_notfull_arb inp_beq_notempty rdsideq_notempty HMA_TLB_DESC_1_L HMA_OTF_ERR reg tracer modinfo 0x%llx [%llu]
invalid register block "%s" %04x/%04x invalid parameter "%s" uPFLCredits: HostFCOwner: EQid: Vcc %fV
min-rate dumpstate: incorrect number of arguments. coalesce rx_frag0_start_idx_raw USER got_tx_max && got_rcv_nxt && got_rx_frag0_start_idx_raw core_push TF_PEER_FIN recv_scale Round-trip time; timestamps: ts_recent_age Highest sequence number sent rcv_nxt rx_frag0_len Page pointer for out-of-order receive buffer Current offset into DDP buffer 0 rx_ddp_buf0_len Tag for DDP buffer 1 OPT_0_DELAYED_ACK TRANSMIT BUFFER:
Migrating %u, ask_mode %u, non_offload %u, rss_info %u
RDMA: error %u, flm_err %u
(Active)
Current offset into DDP buffer CIDXInc perr_mc_flm SGE_INT_ENABLE2 SGE_INT_CAUSE3 err_pcie_error3 SGE_INGRESS_RX_THRESHOLD LP_Count SGE_PD_RSP_CREDIT23 MaxRspCnt3 SGE_REVISION SGE_LA_RDPTR_14 DCAEnCMD ImmFLRRsp Pad RCIS IP2H PCIE_CORE_UTL_PCI_EXPRESS_PORT_INTERRUPT_ENABLE ALES PC6S OPM6 RegSelect STATIC_KX_PLL_P DBG_TRACE0_CONF_COMPREG0 dbg_trace_operate_en DBG_TRACE_RDEN HALT_CALIBRATE THRESHOLD_TERMP_MIN_SYNC THRESHOLD_TERMN_MIN_SYNC REG_IN_TERMP_A DRVN_B_HISTORY pd_idle rank3_odt_write_nse rank3_odt_read_nsel dtu_rd_byte15 CKPONR TESTA MC_DDR3PHYDATX8_WDBDR3 STATIC_SLOW MC_BIST_ERR_FIRST_ADDR MA_HMA_DEBUG_CNT MA_EDRAM0_BAR CL10_PAR_RDQUEUE_ERROR_EN ARB3_PAR_RDQUEUE_ERROR CL6_PAR_WRQUEUE_ERROR CIM_BOOT_LEN CIM_EXTMEM2_ADDR_SIZE CIM_UP_SPARE_INT EEPROMWRInt BlkRdCtlInt SglWrEEPROMInt SglWrBootInt HostWrite MEM_ZONE_VA MEM_ZONE_LEN CIM_DEBUG_UP_CAUSE_MASK CIM_UP_PO_SINGLE_OUTSTANDING CIM_PF_MAILBOX_CTRL EPktDistChn1 VLANExtEnablePort1 TP_CMM_TCB_BASE TP_TCP_OPTIONS EnableMinRcvWnd TxDataAckPageEnable TimerBackoffIndex7 TP_TCP_BACKOFF_REG3 CplErrEnable SwsShove PushTimerEnable AllowExeption TP_TIME_LO TP_TIME_HI LkpTblRowVld LkpTblRowIdx TNLTcpSel Xoff TmCachePerr EnableFifoFull1 TxModXoff1 Pbl_bound_err_ch3 sge2ulp_fifo_perr_set0 imm_data_perr_set_ch0 ULP_TX_CPL_ERR_OFFSET CLR_CH1 ULP_TX_SE_CNT_CH1 stat_channel PM_TX_INT_ENABLE icspi3_fifo2x_Rx_framing_error MPS_TX_PAUSE_RETRANS_BUF_GRP1 oVlanSelLpbk0 CNT BORW STOP PPM3 CDL0 CDM0 MPS_RX_PERR_INJECT PG_TH_INT3 MPS_RX_PAUSE_GEN_TH_1 MODE MPS_PFVF_ATRB_FLTR10 MPS_PKD_MEM_DATA1 EOP_CNT_2 MPS_PORT_RX_OVLAN1 TP_Source MPS_TX_SE_CNT_MAC01 BpEn MPS_TX_DEBUG_REG_TP2TX_10 EOPCh0 MPS_TX_DEBUG_REG_TP2TX_32 EOPPt3 MPS_PF_TX_QINQ_VLAN MPS_PORT_TX_MAC_RELOAD_CH3 Txport MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H MPS_PORT_STAT_LB_PORT_65B_127B_H MPS_PORT_STAT_RX_PORT_MTU_ERROR_L MPS_PORT_STAT_RX_PORT_PAUSE_H CPL_SWITCH_TBL_IDX zero_cmd_ch1 SlvReset MstRxFifoPerrEn MstTxInjDataErr SMB_ARP_UDID0 SMB_COMMAND_CODE1 SMB_MICRO_CNT_CLK_CFG MicroCntClkCfg ENABLE_CTX_1 ENABLE_MPARC_1 TddpLlimit TddpTagMask ULP_RX_CTX_BASE PERR_ENABLE_DDPMF_1 SF_OP EDC0 MapNCSI LE_DB_ROUTING_TABLE_INDEX LE_DB_DBGI_CONFIG DBGICMDACKERR DBGIRspHit DropFilterSet NCSI_MPS_HDR_LO NCSI_LA_RDPTR TxStop BackPress NCSI_MACB_INT_STATUS Smux_Rx_Loop rx_eop_count XGMAC_PORT_PERR_INJECT XGMAC_PORT_WOL_STATUS MagicWake TXATS HSSLOFREQ2PLL RXDSIGDET Con802_3Preamble DisPauseFrames XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_1 XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_8 PauseFrameTxmt FrameTxmt XGMAC_PORT_XGM_STAT_TX_128_255B_FRAMES Lane3_Sync_Status ASM_DIR Message_Page XGMAC_PORT_AN_BACKPLANE_ETHERNET_STATUS TXREQ_C1 FSM_FRM_LCK Restart_Training TDMEN XGMAC_PORT_HSS_TXA_TAP0_IDAC_OVR XGMAC_PORT_HSS_RXA_VGA_CTRL1 VLCKDF H2ESN H3ESN XGMAC_PORT_HSS_RXA_DDC FDAC XGMAC_PORT_HSS_TXD_TDM_BIASGEN_STANDBY_TIMER XGMAC_PORT_HSS_RXC_DFE_H3 XGMAC_PORT_HSS_RXC_DFE_H5 TXDEN CPISEL XGMAC_PORT_HSS_RX_VGA_CTRL1 XGMAC_PORT_HSS_TXRXTEST_CTRL CreditCntPacking Bar2ThrottleCount coal_with_hp_disable_err perr_cim_fifo0 debug_UD_Rx_SOP0_cnt debug_CIM2SGE_RxAFull_d debug_U_RxAFull_d debug_st_flm_idma1_ctxt PCIE_CFG3 RcvdMARspCookie Link_State Crosslink_Enable VC0_CPLD_Credits VC1_PTLP_Queue_Mode Low_Frequency SIReqCnt PCIE_HMA_STAT2 MST_DataPathPerr TRGT1_AlindDataPerr TRGT1_ReqHdrPerr PIOCpl_DataPerr PCIE_RSP_ERR_INT_LOG_EN Lane7FS T5_STATIC_U_PLL_VCVTUNE T5_STATIC_KX_PLL_VBOOSTDIV T5_STATIC_KX_PLL_CCALFMAX GPIO2_PS_En ARB4_PAR_WRQUEUE_ERROR_EN MA_LE_RDDATA_CNT MA_TIMEOUT_CNT CL2_WR_CMD_TO_EN CL1_WR_CMD_TO_ERROR CL1_WR_DATA_TO_ERROR CL3_RD_CMD_TO_ERROR CL10_IF_PAR_ERROR CL3_IF_PAR_ERROR CL0_IF_PAR_ERROR DEBUG_HI SGE2CIMIntfParErr OBQSGERx1ParErr CIM_CGEN_GLOBAL TxRxmMisc MIN_PTP_SPACE MPS_RX_PAUSE_GEN_TH_2_3 MPS_TX_PFVF_PORT_DROP_NCSI TP2MPS_Ch2_CLR TxOutLpbk0_CGEN TxSchLpbk3_CGEN MPS_TRC_FILTER0_RSS_CONTROL send_msn_check_enable MAC2 an_done block_lock MAC_PORT_INT_CAUSE HSSRECCALB TXBQUIET TXDREFRESH TSU PCSSEG1_CGEN MAC_PORT_EEE_RX_10G_WAKE_TIMER MAC_PORT_PTP_DRIFT_ADJUST_COUNT MAC_PORT_PTP_OFFSET_ADJUST_TOTAL MAC_PORT_ETHERSTATSOCTETSHI MAC_PORT_ETHERSTATSOVERSIZEPKTS MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7 MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6HI mdio_read_err MAC_PORT_MTIP_PCS_DEVICE_PKG2 MAC_PORT_MTIP_10GBASER_SEED_A3 TXPRBS31 AMLOCK13 BEAN_EN REM_FAULT MAC_PORT_BEAN_ABILITY_1_LANE2 MAC_PORT_LP_BEAN_XNP_2_LANE3 MAC_PORT_AE_TX_COEF_STAT_1 T5_AE3_RXSTAT_C2 EN_ZFE CNV_LIM MAC_PORT_AET_STAGE_CONFIGURATION_1 MAC_PORT_AET_ZFE_LIMITS_3 MAC_PORT_PLLA_MACRO_TEST_CONTROL_4 T5_TX_DCKSEL MAC_PORT_TX_LINKA_TRANSMIT_TEST_CONTROL POSTSC SDOVRD MAC_PORT_TX_LINKB_TRANSMIT_POLARITY MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_3 MAC_PORT_TX_LINKC_TRANSMIT_POLARITY MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_2 MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_ROTATOR_OVERRIDE WRPMD MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 T5SHORTV FH1CAL LOFO1S_ReadWrite H3ESN_ReadWrite H5ESN_ReadOnly MAC_PORT_RX_LINKC_DYNAMIC_DATA_CENTERING_DDC MAC_PORT_RX_LINKC_DFE_OFFSET_ODD1_ODD2 MAC_PORT_RX_LINKC_DFE_OFFSET_EVN3_EVN4 MAC_PORT_RX_LINKC_RECEIVER_LOFF_CONTROL MAC_PORT_RX_LINKC_DFE_H3 MAC_PORT_RX_LINKD_PHASE_ROTATOR_CONTROL MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_1 MAC_PORT_RX_LINK_BCST_RECEIVER_SIGDET_CONTROL RANK_PAIR0_SEC PERIODIC_CAL_REQ_EN PER_ENA_RANK_PAIR VREFDQ1D ENA_READ_CTR MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE CONTINUOUS_UPDATE ATEST_MUX_CTL1 DQ_WR_OFFSET_N2 MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP WL_ERR_CLK20_MASK MC_DDRPHY_DP18_IO_TX_NFET_TERM INTERP_SIG_SLEW DIGITAL_EYE_VALUE MEMINTD12_POS WR_DEBUG_SEL INVALID_REQTYPE_ERR_MASK SINGLE_BIT_MPR_RP3 GENERATE_EVEN_PARITY MC_UPCTL_MRRSTAT1 MC_UPCTL_TWR MC_UPCTL_DFISTCFG0 MC_UPCTL_DFITRRDLVLDELAY2 MC_P_DEBUG_CFG SGE_QBASE_MAP0 mgt_sel Req_LnD_RxPwrState Cur_LnB_RxPwrState Req_LnP_RxPwrState Req_LnM_RxStateReq Req_LnM_RxPwrState Lane9LF TxDeemph_gen1 STATIC_C_PLL_RANGEPRE DBG_STATIC_U_DFS_CONF DBG_CUST_EFUSE_BYTE16_19 KeyExtend T10_ISO_FIX_EN align_ctl_fifo_perr_set3 LPBK_USED CTL_CHK_EN Outer_IPv4_n_VLAN_GENEVE MPS_PORT_RX_REPL_VECT_SEL DIS_REPL_VECT_SEL EthType2 MPS_CLS_MISS_CNT DataDipHit t10_offset_update_en pio_rdma_send_rqe ULP_RX_TLS_PP_LLIMIT TlsKeyUlimit EXTN_HASH_IPV4 TCAM_SRVR_HIT ClipSubErr Led1_Cfg1 pcs40g_gate_rxclk AEC_SYS_LANE_TYPE_0 mac1g10g_if_mode_set sgmii_sg_speed Perr_rx_fec100g Perr_tx3_pcs40g MAC_PORT_MTIP_1G10G_CL45_PAUSE_QUANTA MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS256TO511OCTETS IF_MODE MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_0 MAC_PORT_MTIP_SGMII_SCRATCH MAC_PORT_MTIP_SGMII_REV Low_Power TX_LPI RX_Test_Pattern_En VSD_1_PRESENT MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_1 Lane_19_blck_lck Lane16_algn_mrkr_lck Lane12_algn_mrkr_lck MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_5 MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_6 MAC_PORT_MTIP_RS_FEC_SYMBLERR3_LO deskew_empty rx_datapath_restart MAC_PORT_MTIP_FEC3_NCERR_CNT_0 T5_AE2_RXSTAT_C3 T5_AE3_RXSTAT_LSNA T5_AE3_RXSTAT_TF ATUNEP MAC_PORT_TX_LINKA_TRANSMIT_4X_SEGMENT_APPLIED OS4X6 MAC_PORT_TX_LINKA_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE MAC_PORT_TX_LINKB_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE MAC_PORT_TX_LINKB_TRANSMIT_AE_VM_LIMIT_EXTENDED MAC_PORT_TX_LINKC_TRANSMIT_1X_SEGMENT_APPLIED MAC_PORT_TX_LINKD_TRANSMIT_APPLIED_TUNE_REGISTER MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_2X_OVERRIDE ACCPLMEANS RX_OFFVGADIS H4SN MAC_PORT_RX_LINKA_RECEIVER_DCD_CONTROL MAC_PORT_RX_LINKB_RECEIVER_IQAMP_CONTROL_2 MAC_PORT_RX_LINK_BCST_DFE_OFFSET_CHANNEL MAC_PORT_RX_LINK_BCST_DFE_TAP AD32S_HS_PROBE_A_SEL DP18_HS_PROBE_B_SEL MC_DDRPHY_DP18_DELAY_LINE_PWR_CTL SELF_REF_MODE DFI_PHYUD_ACK T_XSDLL MC_LMC_SMR0 SMR0_DLL FESR_MODE RK0R PHYUPD_BUSY MC_LMC_T_PHYUPD0 MC_CE_ERR_ECC_DATA0 EDC_H_DBG_EDRAM0_WR_REQ_CNT HMA_REG1_BASE HMA_REG2_BASE MBVFReady Length16 Request CIM_VF_EXT_MAILBOX_DATA_0c cplsw ovlan CHELSIO_T4_SET_FILTER_MODE dip-dp FetchNS: enable %c%c%c%c %c%c%c%c
SFP/SFP+/SFP28 minmax invalid class "%s" CHELSIO_T4_LOAD_BOOTCFG invalid scheduling class "%s". "class" needs an integer value where 0 <= value <= 15 get_tcb_field IANDP_DDP ulp_raw TF_CORE_FIN core_more TF_RX_PDU_OUT pend_ctl0 TF_CCTRL_ECE Maximum re-transmissions tx_hdr_ptr_raw rx_frag2_start_idx_offset ord_l_bit_vld ddp_buf0_valid Length of DDP buffer rx_tls_key_tag perr_mc_igr_ctxt perr_dbp_pc_rsp_fifo2 perr_pd_fifo2 perr_base_size err_inv_ctxt2 IngThreshold ForceVFPF5DBtoLP LL_Empty MinTag1 SGE_PC1_RSP_BIST_CMD SGE_CTXT_DATA7 SGE_LA_WRPTR_0 SGE_LA_RDDATA_1 SGE_LA_WRPTR_5 SGE_LA_RDPTR_8 SGE_LA_RDPTR_12 RPLPerr VFMSIPndEn IPLTSSM PCIE_MAILBOX_OFFSET PDEBUGSelH PCIE_DMAR_RSP_EOP_CNT PCIE_BUS_MST_STAT_2 PCIE_MSI_EN_3 USBS RPAM PC1I PC5I PCIE_CORE_PCI_POWER_MANAGEMENT_CONTROL_1 GPIO1_OEn GPIO10_Out_Val KX_LOCK_ACT_LOW STATIC_U_PLL_RANGEB STATIC_KR_PLL_M KX_OCLK_MUXSEL REG_IN_TERMP_B ppmem_en column_addr_width MC_PCTL_ECCCLR dtu_incr_cols dtu_wr_byte2 dtu_wr_byte0 dtu_rd_byte11 LPFDEPTH MC_DDR3PHYAC_MDPPR1 SDRSELINV MC_DDR3PHYDATX8_WLDR MC_DDR3PHYDATX8_WDBDR5 WLDONE MC_BONUS TP_DMARBT_PAR_ERROR_EN ARB0_PAR_RDQUEUE_ERROR_EN CL5_PAR_RDQUEUE_ERROR_EN CL7_PAR_WRQUEUE_ERROR SglRdPlIntEn SglWrPlInt IllTransInt CIM_HOST_ACC_DATA CIM_OBQ_DBG_CFG CIM_MEM_ZONE3_BA CIM_DEBUG_PIF_CAUSE_MASK FcoeEnable IPTTL TxMaxOpCnt TP_DACK_CONFIG AutoState2 Mode EnableFilterCount EnablePcmdCheck EnableEHdrAFull TblTimer RxChnTunnel MaxProxySize DropErrorCsumIP DelayedACKResolution TP_MTU_TABLE UpdChn2 RX_MOD_RATE_LIMIT_INC CTpInCplFifoPerr TxRxmTimerPersist RxChnXoff2 cim2ulp_fifo_perr_set2 ULP_TX_PERR_ENABLE ULP_TX_PBL_ULIMIT zero_c_cmd_erro MPS_VF_RX_CTL_31_0 MPS_DEBUG_CTL Prty5 Prty2 BLK_SNDR MPS_RX_PG_HYST_BG2 ATRB CDL2 OPCODE MPS_VF_RPLCT_MAP1 MPS_MEM_DBG_CTL MPS_RX_SE_CNT_IN0 MPS_RX_SE_CNT_IN4 SOP_CNT_0 MPS_RX_CLS_DROP_CNT2 MPS_PORT_RX_MTU MPS_PORT_RX_OVLAN2 MPS_TX_PORT_ERR Lpbkpt2 SizeCh1 SOPPt2 Tag TrcIgnoreDropInput MPS_TRC_FILTER_DROP Lpbk Mac MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L MPS_PORT_STAT_TX_PORT_1024B_1518B_H MPS_PORT_STAT_RX_PORT_PPP2_L MPS_PF_STAT_TX_PF_MCAST_FRAMES_L MstTxByteCfg SlvPrepToArpIntEn VendorID InitPowerMode Hpz1 PERR_ENABLE_MPARF_1 PERR_ENABLE_PCMDF_0 PL_PF_CTL PM_RX MapSMB FatalPerrEn MAP3 PL_VF_SLICE_H LE_DB_CLIP_TABLE_INDEX DBGICMDREAD DBGICMDBUSY LE_DB_DBGI_RSP_STATUS FLTRBASE_ADDR NCSI_PORT_CFGREG NCSI_CTL NCSI_NCSI_ETYPE NC2CIM_EOP_CNT MPS_DM_prty_err StatWrEn IncrStat LinkStatus NCSI_MACB_RX_STATUS NCSI_MACB_SPECIFIC_2_LOW XGMAC_PORT_CFG2 AEC_PMA_TX_READY HSSLOFREQPLL HSSPRBSEN RXBPRBSFRCERR RXDDATASYNC RXDPRBSSYNC LinkFaultChange StatOFlow XGMAC_PORT_XGM_STAT_TX_BYTE_LOW XGMAC_PORT_XGM_STAT_RX_SHORT_FRAMES Lane0_CTC_Status XGMIILoopEn XGMAC_PORT_PCSR_TXTEST_SEEDB_LOWER 1000BASE_KX_Capable PRBS_CHK_OFF BWSEL XGMAC_PORT_HSS_TXA_TAP2_COEFF XGMAC_PORT_HSS_TXB_TAP1_COEFF RSTONSTUCK TRAINEN ASAMPQ VOFFSN E1AMP H2OSN OLS XGMAC_PORT_HSS_TXD_COEFF_CTRL XGMAC_PORT_HSS_RXC_SIGDET_CTRL XGMAC_PORT_HSS_RXC_DFE_DATA_EDGE_SAMPLE XGMAC_PORT_HSS_RXC_INTERNAL_STATUS XGMAC_PORT_HSS_RXD_PH_ROTATOR_CTRL XGMAC_PORT_HSS_RXD_DFE_FUNC_CTRL XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_0 TXBRST XGMAC_PORT_HSS_TX_8023AP_AE_STATUS ForceOpenBar2Gate flm_pc_rsp_err dbfifo_lp_int_low perr_MC_RspData perr_UD_RxData TX_Coalesce_Size IDMA0_Sleep_Req EDMA2_Sleep_Status dbp_fetch_threshold_mode SGE_DEBUG_DATA_HIGH_INDEX_8 debug_CPLSW_CIM_SOP1_cnt debug_CPLSW_CIM_EOP1_cnt debug_itp_empty debug_st_dbp_thread2_main debug_st_edma3_req debug_st_edma2_req debug_idma1_flm_req_qid CReqRdPerr BAR2Timeout VPDTimer L0s_Entrance_Latency TxPH_FC VC0_WRR TxCmplRcv Eql_EIEOS_CntRst_Disable HMA_Static_CGEN TRGT1_UnAlinDataPerr TRGT1_ReqDataPerr MA_RspDataPerr RspDropFLRIntEn xmlh_link_up PCIE_PHY_FS_LF0 Lane0FS Lane5FS CoeffDone GPIO18_ACT_LOW TVSENSE_SENSV DBG_FEPROGP DBG_FETIME T5_STATIC_U_PLL_LOCKTUNE DBG_T5_STATIC_U_PLL_CONF3 DBG_T5_STATIC_U_DFS_CONF DBG_EFUSE_BYTE60_63 MA_HMA_RDDATA_CNT CL10_WR_DATA_TO_ERROR CL12_RD_CMD_TO_EN CL9_IF_PAR_EN ECheckUDPLen EnableFilterNat EOF_3 ma2ulp_data_perr_set t10_pi_sram_perr_set3 MPS_CGEN_GLOBAL MPS_TX_PAUSE_RETRANS_BUF_GRP_TH9 MPS_TX_PFVF_PORT_DROP_TP TxInCh3_CGEN cim_split_opcode_program ULP_RX_CGEN_GLOBAL PL_PCIE_CTL_STAT ActCntIPv4zero AEC1Reset TXDCONFIGSEL HSSVBOOSTDIVA RXDREFRESH_STATUS pma_rx_quiet MACSEG3_CGEN PAUSE_PFC_COMP MAC_PORT_MTIP_MAC_STATUS MAC_PORT_ETHERSTATSPKTS MAC_PORT_MTIP_SGMII_DEV_ABILITY MAC_PORT_MTIP_VLAN_TPID_6 MAC_PORT_MTIP_PCS_SPEED_ABILITY MAC_PORT_MTIP_10GBASER_SEED_A1 MAC_PORT_MTIP_10GBASER_SEED_B Lane15 MAC_PORT_MTIP_PCS_BIP_ERR_CNT_19 ECHO_NONCE SELECTOR MAC_PORT_BEAN_STATUS_LANE1 MAC_PORT_BEAN_XNP_2_LANE1 MAC_PORT_BEAN_STATUS_LANE2 MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_1 LOGICTEST REFVALIDC MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_1 VBST MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_0 MAC_PORT_TX_LINKA_TRANSMIT_COEFFICIENT_CONTROL DCCSTEP DCCOEN MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_APPLIED MAC_PORT_TX_LINKB_TRANSMIT_DCC_CONTROL T5_RX_PLLSEL WPLPEN T5_RX_SMODE H1O3 H1O4 T5DQCCCMP T5_RX_BYPASS T5_RX_VTERM H8GS BANKA BANKB MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_2 MAC_PORT_RX_LINKC_DFE_H4 MAC_PORT_RX_LINKD_PHASE_ROTATOR_OFFSET_CONTROL MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_1 MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_2 MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 MAC_PORT_RX_LINK_BCST_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_2 RANK_PAIR0_SEC_V MC_DDRPHY_PC_CONFIG1 ENA_WR_LEVEL ERROR_RDCLK_ALIGN ADDR_MIRROR_RP2_PRI MC_ADR_DDRPHY_ADR_BIT_ENABLE MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1 SYSCLK_ROT_OVERRIDE_EN GIANT_MUX_TEST_EN DISABLE_PING_PONG MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR RDCLK_SELECT0 MC_DDRPHY_DP18_RD_LVL_STATUS1 COARSE_PATTERN_ERR_N2 INCOMPLETE_RD_CAL_N1_MASK TRIG_PERIOD INVALID_REQTYPE_ERRO WR_CNTL_ERROR COARSE_CAL_STEP_SIZE DP18_12_Populated MC_UPCTL_POWSTAT MC_UPCTL_MCFG1 MC_UPCTL_DTURACTL MC_UPCTL_DTUWD1 MC_UPCTL_DFITCTRLDELAY MC_UPCTL_DFITPHYUPDTYPE3 CTL_CAL_REQ MC_P_STATIC_CFG_STATUS EDC_H_BIST_USER_WDATA2 NullPtrEn en_pshb SGE_TBUF_CONTROL last_qid dbg_tbuf_used1 debug_idma0_idma2imsg_fifo_in_drdy Req_LnE_RxPwrState Req_LnA_RxStateReq PCIE_KDOORBELL_GTS_PF_BASE_LEN Lane12LF PCIE_VF_MSIX_EN_5 PCIE_RSP_ERR_STAT_8 STATIC_U_PLL_DCO_BYPASS DBG_STATIC_KR_PLL_CONF1 DBG_CUST_EFUSE_BYTE20_23 bypass_middle urgent_first MPS_RX_REPL_CTL MPS_VF_RPLCT_MAP4 MPS_RX_MAC_BG_PG_CNT1 MPS_RX_CNT_GENEVE_PKT_LPBK0 MPS_CLS_REQUEST_TRACE_MAC_DA_L CtlTcamIndex ERRSTOP_EN CMD_TID_ERR LE_DB_DBG_MATCH_CMD_IDX_MASK LE_DB_TCAM_TID_BASE PCS40G_RESET pcs100g_gate_cgmii_txclk MAC_PORT_AEC_DEBUG_LO_1 mac1g10g_pfc_mode pcs10g_block_lock sgmii_sg_an_done sgmii_tx_lane_ckmult Perr_rx18_pcs100g Perr_rx10_pcs100g Perr_rx3_pcs100g rx_st_mac40g Perr_rx1_pcs40g HSSREFDIVA CL1_PAUSE_QUANTA MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS65TO127OCTETSHI MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS256TO511OCTETS MAC_PORT_MTIP_1G10G_TX_ETHERSTATSOCTETS MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS64OCTETS MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_3HI MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_5 MAC_PORT_MTIP_KR_PCS_STATUS_1 WIS_present MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_2 MAC_PORT_MTIP_KR4_DEVICES_IN_PKG2 MAC_PORT_MTIP_KR4_BASE_R_STATUS_2 MAC_PORT_MTIP_CR4_SCRATCH rx_dp_overflow marker_check_restart BASE_R_FEC_Error_Indication_Ability MAC_PORT_MTIP_FEC_STATUS1 MAC_PORT_MTIP_FEC3_CERR_CNT_1 T5_RXREQ_C3 T5_AE3_RXSTAT_FEC BOOT_LUT5 MAC_PORT_PLLREFSEL_CONTROL NPWRENA C0PRESET MAC_PORT_TX_LINKA_TRANSMIT_AE_C3_INIT2_EXTENDED MAC_PORT_TX_LINKB_TRANSMIT_1X_SEGMENT_APPLIED MAC_PORT_TX_LINKC_TRANSMIT_AE_C0_INIT2_EXTENDED MAC_PORT_TX_LINKD_TRANSMIT_AE_STEP_SIZE_EXTENDED MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C3_LIMIT_EXTENDED DPCWDFE FIQAMP FQCC MAC_PORT_RX_LINKA_DFE_OFFSET_CHANNEL RX_VTERM RX_OBSOVEN SMQM H7SN DCCOVRDEN MAC_PORT_RX_LINKB_H_COEFFICIENBT_BIST MAC_PORT_RX_LINKC_RECEIVER_DACA_MIN MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2 ADR_TEST_MODE FORCE_EN RWOO RESET_OE DFI_INIT_START MC_LMC_CMD1 T_CPDED TM RPT_MODE SMR4_RFU MC_LMC_SMR5 RD_DBI PHY_CAL_REQ BUF_USE_TH USER_MASK_ECC MCmdVld EDC_H_DBG_MA_WR_DAT_CYC_CNT dead_cycle1_post_ref_rmw EDC_H_DBG_CMD_QUEUE TPH_V E_SEL PAGE_SIZE2 MAMST_INT_ENABLE MPS_VF_STAT_TX_VF_UCAST_FRAMES_L MPS_VF_STAT_RX_VF_UCAST_BYTES_L CIM_VF_EXT_MAILBOX_DATA_04 [%#7x] %-47s %#-10x %u
ma mc0 FCoE %1d:%04x/%1d:%04x sip set_filter sip rpttid dip-sip-sp natseq NoSnoop: UpdateDelivery: DBpriority: CngDBPData: fstat CHELSIO_T4_GET_TRACER must specify tx<n> or rx<n>. Vendor %s
CDFP DSFP x4MiniLink/OcuLink invalid mode parameter "%s" rate-unit Error parsing line %d of "%s" newreno bind lu_tcbvar: bad name %s
FIN_WAIT_1 -> %1u (0x%x) ULP subtype Destination MAC address index TF_RDMA_FLM_ERROR snd_max_raw snd_cwnd Congestion-control window Highest sequence number acked rx_frag1_ptr rx_frag3_ptr_raw rq_start Transmit is out of FPDU sync, or disable aligned transmission TF_DDP_RX2TX ddp_main_unused ddp_buf0_unused rx_ddp_buf1_offset OPT_0_TOS OPT_0_TCAM_BYPASS Direct_Steer rx_tls_buf_offset tag: 0x%8.8x, key:0x%8.8x
SEIntArm QueuesPerPageVFPF4 perr_egr_ctxt_mifrsp perr_hint_delay_fifo0 err_dropped_db reg_address_err OpMode HP_Weight ForceVFPF2DBtoLP TimerValue1 err_physaddr_len0_idma0 Ingress2_Base SGE_LA_RDDATA_3 SGE_LA_WRPTR_3 SGE_LA_RDPTR_6 MSIAddrLPerr PCIE_PERR_INJECT AI_TCVal ReqCnt PCIE_MEM_ACCESS_BASE_WIN IN_WR_DISCONTIG OUT_PDAT_TOT PCIE_BUS_MST_STAT_3 PCIE_MSI_EN_5 PCIE_DMA_BUF_CTL SWD6 RNPP RPCI IP1H IP3D PLUP GTRP TCAI OPM0 PCIE_CORE_GENERAL_PURPOSE_CONTROL_1 GPIO11_OEn GPIO2_OEn GPIO4_CHG_DET GPIO4_IN M_OCLK_En GPIO4_ACT_LOW STATIC_U_PLL_MULT STATIC_U_PLL_BYPASS PVT_REG_DRVN_A THRESHOLD_DRVP_MAX_SYNC THRESHOLD_DRVN_MIN_SYNC TERMN_A_HISTORY MC_PCTL_SCTL MC_PCTL_ODTCFG rank2_odt_read_sel rank1_odt_write_sel MC_PCTL_DTUPDES dtu_allbits_6 MC_PCTL_DTUAWDT MC_PCTL_TRFC MC_PCTL_TXP MC_PCTL_TCKSRE MC_PCTL_DTURD0 MC_PCTL_DTURD3 MC_DDR3PHYDATX8_RDSDR MC_DDR3PHYDATX8_PMBDR2 PHY_RST_N ECC_CE_PAR_ENABLE PERR_BLK_INT_ENABLE CL2_PAR_WRQUEUE_ERROR_EN ARB3_PAR_WRQUEUE_ERROR ARB2_PAR_RDQUEUE_ERROR CL10_PAR_RDQUEUE_ERROR CL2_PAR_RDQUEUE_ERROR SdramAddrSize SglRdEEPROMInt SglRdBootInt CIM_UP_INT_CAUSE LAMaskStop CIM_TIMER1 MBMsgValid ELpbkIncMpsStat TxPoolSize PMTxNumChn DisableLbkCheck TxPaceFixed EnableReadPdu DropErrorMac Port3MTUValue SYNLkpEn KeyPerrEn UpdVld RssLkpPerr TxRxmUrg EnableLpbkFull0 DbgLaWptr cim2ulp_fifo_perr_set3 cmd_fifo_perr_set2 ULP_TX_CPL_ERR_MASK_H Ch2Size2 ULP_TX_LA_RDPTR_4 ULP_TX_LA_RDDATA_5 ULP_TX_LA_RDPTR_8 db_options_par_error icspi1_fifo2x_Rx_framing_error TxIntEnb MPS_WOL_CTL_MODE MPS_PFVF_ATRB_FLTR15 DBG_PKD_QSEL NO_RPLCT_M FIXED_PF FIXED_VF MPS_TX_LPBK_DROP_BP_CTL_CH0 ValidPt1 MPS_PORT_TX_LPBK_RELOAD_CH2 FiltMem CountVFinPF MPS_STAT_PERR_INT_ENABLE_SRAM MPS_STAT_RX_BG_1_LB_DROP_FRAME_H MPS_PORT_STAT_TX_PORT_DROP_H MPS_PORT_STAT_RX_PORT_PPP0_H MPS_PF_STAT_TX_PF_UCAST_FRAMES_L MPS_PF_STAT_RX_PF_UCAST_BYTES_H VlanClsEn cim_framing_error CPL_INTR_CAUSE MstTxByteCnt MstTimeOutInt Cont ClkDiv PDPPartCGEn Port0SleepMode IscsiTagTcb ENABLE_PRSDF_1 ENABLE_DDPCF_1 CAUSE_MPARF_0 IscsiLlimit ULP_RX_SE_CNT_ERR ULP_RX_LA_CHNL ULP_RX_LA_CTL XGMAC_KR0 PL_PL_PERR_ENABLE MAP5 Addr RoutingHit DBGICMDIPv6 LE_DB_TID_HASHBASE NCSI_WORK_REQHDR_3 NCSI_SE_CNT_CTL En1536Frame TX_IPG HSSREFDIV StretchMode XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_6 Non0PauseRcvd XGMAC_PORT_XGM_STAT_RX_SYM_CODE_ERR_FRAMES Lane0_Sync_Status FEC_Ability TMSCAL XGMAC_PORT_HSS_RXA_PH_ROTATOR_STATIC_PH_OFFSET XGMAC_PORT_HSS_RXA_DFE_DATA_EDGE_SAMPLE VGAIN D01SN EMMD XGMAC_PORT_HSS_RXA_DFE_H2 TRCMP XGMAC_PORT_HSS_RXC_DACA_MIN XGMAC_PORT_HSS_RXD_DACAP_DAC_AN_OFFSET VBADJ XGMAC_PORT_HSS_RX_DFE_CTRL XGMAC_PORT_HSS_RX_DFE_D00_D01_OFFSET XGMAC_PORT_HSS_RX_DACA_OFFSET perr_pc_dbp2 err_wr_len_too_large0 bar2_egress_size_err err_rx_cpl_packet_size0 perr_pointer_data_fifo0 FetchBurstMax1 dbp_fetch_threshold_iq1 LP_Ptrs_Equal debug_UD_Rx_SOP2_cnt debug_PC_Rsp_SOP1_cnt debug_PD_RdReqAFull_d debug_PC_Rsp_SOP2_cnt debug_st_flm_cache DroppedRdRspData BAR2Timer PCIE_VF_MSI_EN_0 PCIE_PF_MSIX_EN CookieB PCIE_STAT Ack_Frequency PCIE_CORE_PORT_LINK_CONTROL TxRetryBuf_Not_Empty VC3_WRR VC1_CPLD_Credits UseCmdPool PCIE_CMD_STAT3 STI_SleepReq IPRxHdr_VC0Perr PIOReq_PLMCtlPerr LnH_RxStateDone LnF_RxStateDone PCIE_PHY_FS_LF3 Lane6LF PCIE_PHY_INDIR_REQ PCIE_PHY_INDIR_DATA TVSENSE_RATIO T5_STATIC_C_PLL_RANGEPRE T5_STATIC_C_PLL_VCVTUNE GPIO6_PE_En GPIO16_PS_En GPIO3_PS_En DBG_EFUSE_BYTE28_31 MA_PMTX_WRDATA_CNT MA_ULPRX_RDDATA_CNT MA_TP_TH1_RDDATA_CNT MA_EDRAM1_WRDATA_CNT0 TYPE obq_throuttle_on_eop obq_read_ctl_perf_mode_disable CChecksumCheckUDP EnableFinDdpOff CTpOutPldFifoPerr ULP_TX_ASIC_DEBUG_2 OspiWrBusy PM_TX_DBG_DATA MPS_TX_PAUSE_DURATION_BUF_GRP_TH6 MPS_PORT_PRTY_BUFFER_GROUP_TH_MAP PETYPE1EN PTP_FWD_UP NcsiSeCnt MPS_STAT_STOP_UPD_PORT PERR_RSVD1 ULP_RX_PERR_ENABLE_2 ENABLE_ULPRX2MA_IntfPerr ENABLE_DDP_HINT_1 ULP_RX_ATOMIC_LEN COMPTID SRCHLADDR an_page_rcvd tx_sff_seg0 HSSCALCOMP RXCREFRESH MAC_PORT_HSS_CFG2 T5RXAPRBSRST RXBASSTCLK RXCQUIET_STATUS MAC_PORT_PTP_TIMER_RD1_HI MAC_PORT_PTP_SUM_HI TS_AVAIL MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1HI RF2 MAC_PORT_MTIP_VLAN_TPID_4 TxFault MAC_PORT_MTIP_PCS_BIP_ERR_CNT_15 MAC_PORT_MTIP_PCS_LANE_MAP_2 10GKR MAC_PORT_BEAN_ABILITY_1_LANE3 MAC_PORT_FEC_CERR_CNT_1 MAC_PORT_AE_TX_DIS_2 H1TEQ_GOAL AMIN_TH LBIST AUXEN PDWNP MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_DATA AECMDVAL MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C2_INIT_EXTENDED MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_TIME_OUT RBEOFF MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_1 T5BYTE1 MAC_PORT_RX_LINKA_RECEIVER_ADAC_CONTROL LOFE4S_ReadWrite MAC_PORT_RX_LINKB_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_2 MAC_PORT_RX_LINKD_INTEGRATOR_DAC_OFFSET MAC_PORT_RX_LINK_BCST_DFE_H1 MAC_PORT_RX_LINK_BCST_DFE_H10_AND_H11 MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_1 ABORT_ON_ERR_EN DDR4_BANK_REFRESH DISABLE_MEMCTL_CAL APB_ERROR WC_ERROR_MASK MC_DDRPHY_PC_VREF_DRV_CONTROL VREFDQ1DSGN ENA_RDCLK_ALIGN REFRESH_COUNT ERROR_RDCLK_ALIGN_MASK EN_SLICE_N_WR_2 SYSCLK_PHASE_ALIGN_RESE SYSCLK_POS_EDGE_ALIGN MC_DDRPHY_ADR_GMTEST_ATEST_CNTL SLEW_CAL_OVERRIDE_EN MC_DDRPHY_DP18_DQ_WR_OFFSET_RP MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP RD_DELAY_BITS8_14 SMALL_STEP_LEFT SYNC BUMP SMALL_STEP MC_DDRPHY_RC_PERIODIC DP18_6_Populated parity_intr MC_UPCTL_TMOD MC_UPCTL_DFITCTRLUPDMAX MC_P_PAR_ENABLE PING_PONG perr_pc_req enq_perr buf_perr dbq_timer_tick SGE_DBG_QUEUE_STAT0_CTRL VfWCQsPerPage Cur_LnC_RxPwrState PCIE_VF_INT_INDIR_REQ PIO_WARM_RST_MODE0_STATE_flag STATIC_MPLL_REFCLK_SEL STATIC_KX_PLL_VBOOSTDIV EcnFinEct DROP_INVLD_MC_CH3 MPS_VF_RPLCT_MAP6 ETYPE_EN CTL_VALUE TTL_IPV4 MPS_RX_CNT_VXLAN_PKT_TO_TP0 Outer_IPv4_n_Inner_IPv6 MPS_STAT_STOP_UPD_TX_VF_224_255 MPS_CLS_REQUEST_TRACE_MAC_SA_H MPS_CLS_REQUEST_TRACE_ENCAP LE_DB_ID IGNR_LIP_ZERO CLTCAMDEEPSLEEP_STAT TCAMDEEPSLEEP LE_DB_HPRI_FILT_TABLE_START_INDEX ClCamFifoerr pcs10g_gate_sd_tx_clk AEC_RX_UNKNOWN_LANE_1 CIN_FSM_CUR_STATE CX_INIT REG_MAN_DEC_REQ CUF_C2_FSM_DEBUG pcs100g_vl_intvl MAC_PORT_PERR_INT_EN_100G Perr_rx_fec100g_dly Perr_tx1_pcs100g rx_mac40g CL4_PAUSE_QUANTA MAC_PORT_MTIP_1G10G_CL67_PAUSE_QUANTA CL1_QUANTA_THRESH MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOVERSIZEPKTS MAC_PORT_MTIP_1G10G_RX_ETHERSTATSJABBERSHI MAC_PORT_MTIP_1G10G_AMACCONTROLFRAMESRECEIVEDHI MAC_PORT_MTIP_1G10G_TX_CRCERRORS MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_3HI Speed_Sel1 Next_Page_Able PAGE_RECEIVE Speed_SEL 10GBASE_W_Capable MAC_PORT_MTIP_KR4_DEVICE_ID1 10GBase_T_capable HI_ORDER_CNT_EN MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_2 Errored_blocks_cntr Lane_8_blck_lck MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_14 MAC_PORT_MTIP_CR4_LANE_18_MAPPING FEC_LOCKED0 100GKP4 P7CHK MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_2X_OVERRIDE OS2X3 OS1X7 OS1X3 OS1X1 MAC_PORT_TX_LINKA_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE TUNEBIT C2PRESET MAC_PORT_TX_LINKC_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE MAC_PORT_TX_LINKD_TRANSMIT_4X_SEGMENT_APPLIED MAC_PORT_TX_LINKD_TRANSMIT_2X_SEGMENT_APPLIED MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_5 MAC_PORT_TX_LINKD_TRANSMIT_AE_C3_LIMIT_EXTENDED FH1ACAL FH1AFLTR MAC_PORT_RX_LINKA_RECEIVER_POWER_MANAGEMENT_CONTROL SELI LOFL HBISTEN ACCRST RX_OFFACDIS FPRBSOFF2 FDDCFLTR FDAC6 MAC_PORT_RX_LINKD_RECEIVER_IQAMP_CONTROL_1 MAC_PORT_RX_LINK_BCST_DFE_H14_15 DDR4_PDA_MODE ADDR_MIRROR_A3_A4 ADDR_MIRROR_A5_A6 SS_RD_DELAY PARITY_DLY MT_DATA_MUX4_1MODE RANK_ENABLE BANK T_RCD1 T_RDDATA_EN DIC0 CRC_CLEAR MC_LMC_CALSTAT SYNC_PAB_EN MCmdLen rddq_notfull_open ECmdNRE EDC_H_DBG_REFRESH HMA_TLB_DESC_0_H HMA_TLB_DESC_7_H HMA_REG1_MIN loadcfg open(%s) Idx (region %d) (hash) RptTID drop invalid action "%s"; must be one of "pass", "drop" or "switch" tcbrss nat params only make sense with valid nat mode %s is not a valid address prefix FCThreshOverride: FetchSizeMode CIDX: invalid port id "%s" %s %u, sched params "rate-unit" parameter missing sched params "rate-mode" parameter missing loadbootcfg: incorrect number of arguments. missing "[" on line %zd highspeed TOE mod_schd_reason0 TF_MOD_SCHD_TX pend_ctl2 Sequence number being timed t_rtseq; timestamps t_recent rx_hdr_offset rx_frag0_start_idx Offset of receive fragment 2 start sequence from rcv_nxt rx_frag2_ptr ddp_buf1_flush snd_una %u, snd_nxt %u, snd_max %u, tx_max %u
rcv_coal %u rcv_co_psh %u rcv_co_last_psh %u heart %u
will cause new data to be held in PMRX.
IngressQID DCASysType SGE_EGRESS_QUEUES_PER_PAGE_PF perr_dbp_pc_rsp_fifo0 perr_dbp_lp_fifo err_pcie_error1 err_bad_db_pidx2 err_inv_ctxt1 SGE_FL_BUFFER_SIZE13 ForceVFPF3DBtoLP StatSource Busy SGE_LA_RDPTR_2 SGE_LA_RESERVED_5 PIOTagPerr PopD SimSpeed TagFree PCIE_CMD_CFG IN_PDAT_TOT PCIE_CMDR_RSP_CNT PCIE_MSIX_EN_0 PCIE_MSIX_EN_3 RCIP PCIE_CORE_UTL_SYSTEM_BUS_AGENT_ERROR_SEVERITY RFTI ON0H TXE1 TNPP TFTP RLFE PACS PCIE_CORE_PCI_POWER_MANAGEMENT_CONTROL_2 CPM2 GPIO7_Out_Val DBG_INT_CAUSE C_OCLK_En STATIC_KR_PLL_N1 ExPHYClk_sel M_OCLK_MUXSEL FORCE_REG_IN_VALUE PVT_REG_DRVP_EN dse_alat MC_PCTL_DWLCFG2 ecc_en dtu_rd_col dtu_target_lane dyn_soc_odt_alat soc_odt_en MC_DDR3PHYAC_GSR MC_DDR3PHYAC_ACR CALBYP MC_PVT_REG_LAST_MEASUREMENT MC_PVT_REG_DRVP MC_PVT_REG_HISTORY_DRVP DDR3_BRC_MODE MC_ECC_CTRL ECC_BYPASS_BIST PERR_INT_ENABLE EDRAM1_SIZE EXT_MEM_BASE MA_HOST_MEMORY_BAR HMA_SIZE MA_TARGET_MEM_ENABLE MA_INT_CAUSE MEM_PERR_INT_CAUSE CL5_PAR_WRQUEUE_ERROR CL0_PAR_WRQUEUE_ERROR EDC_BIST_STATUS_RDATA uPSpareInt Timer1IntEn BlkRdEEPROMInt HostBusy ObqDbgAddr ObqDbgEn FcoeUpEn EReportUdpHdrLen EPktDistChn0 TxMaxOpCntDisable EnableTxDataArpMiss EnableCPCMDAFull TP_TCP_BACKOFF_REG2 TxDataAckIdx TP_PARA_REG5 TP_PARA_REG6 EngineLatencyWireIp6 DropErrorTcpHdrLen ULPType7Field OFDVrtSel VirtEnable RRCPLMapEn TP_RSS_CONFIG_VRT CommitLimit1 cmd_fifo_perr_set1 imm_data_perr_set_ch2 CLR_CH0 PM_RX_CFG PM_RX_MODE iespi0_fifo2x_Rx_framing_error icspi0_fifo2x_Rx_framing_error MPS_CMN_CTL TrcIntEnb MPS_PORT_RX_PAUSE_CTL RxHaltEn SEL MAX CDL1 CDM3 MPS_VF_RPLCT_MAP3 EOP_CNT_PM IVLAN_EN MPS_TX_PRTY_SEL Ch0_Prty Spi MPS_TX_LPBK_DROP_BP_CTL_CH2 TfSopEopErr MPS_TRC_FILTER1_MATCH MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H MPS_PORT_STAT_TX_PORT_FRAMES_L MPS_PORT_STAT_TX_PORT_1519B_MAX_L MPS_PORT_STAT_TX_PORT_PAUSE_H MPS_PORT_STAT_LB_PORT_UCAST_H MPS_PORT_STAT_RX_PORT_1024B_1518B_H MPS_PORT_STAT_RX_PORT_PPP0_L MPS_PORT_STAT_RX_PORT_PPP4_H MemWriteWaiting MultiListen1 CPL_MAP_TBL_DATA SlvBusySts SlvUnExpBusStartEn PreEn PCIePartCGEn ENABLE_MPARF_1 CAUSE_PRSDF_0 ULP_RX_ISCSI_ULIMIT ULP_RX_PBL_ULIMIT PERR_ENABLE_MEMRF_1 PERR_ENABLE_DDPDF_0 PERR_ENABLE_PCMDF_1 PL_WHOAMI ULP_TX PL_PL_INT_ENABLE LE_RSP_DEBUG_LA_WRPTR NCSI_RST_CTRL NCSI_WORK_REQHDR_2 NCSI_RX_ERR_CNT CIM2MPS_CNT SOP_CNT_ERR BUS_STATE_CIM_IN NCSI_PAUSE_CTRL NCSI_MACB_DEF_TX_FRAMES NCSI_MACB_SPECIFIC_3_HIGH XGMII_Clk_Sel Tx_Lane_Swap AE_Reset HSSPLLBYP XGMAC_PORT_HSS_CFG1 TXCPRBSEN RXASIGDET TxPauseEn XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_5 type XGMAC_PORT_XGM_STAT_CTRL DevAddr XGMAC_PORT_XGM_STAT_RX_OVERSIZE_FRAMES Lane2_CTC_Status XGMAC_PORT_AN_ADVERTISEMENT XGMAC_PORT_AN_GENERIC_TIMER_TIMEOUT RXREQ_CINIT TXREQ_C2 TXSTAT_C0 PRBS_GEN_FRCERR LOPWR OPEN FTHROT RTHROT PHOFFS SPIFMT STNDBY H4ESN XGMAC_PORT_HSS_RXA_INTERNAL_STATUS FADAC XGMAC_PORT_HSS_TXC_COEFF_CTRL XGMAC_PORT_HSS_TXD_EXT_ADDR_DATA XGMAC_PORT_HSS_RXC_DIGITAL_EYE_METRICS XGMAC_PORT_HSS_RXD_DFE_H1 CCERR CCLD XGMAC_PORT_HSS_TX_DRIVER_OVR_CTRL XGMAC_PORT_HSS_RX_SIGDET_CTRL dbp_fetch_threshold_en1 LP_Snaphot FL_Int_Thresh_Low debug_U_Rx_SOP0_cnt debug_PD_RdRsp_EOP2_cnt SGE_DEBUG_DATA_HIGH_INDEX_13 debug_st_edma1_align EnterL1 PCIE_VF_MSI_EN_1 PCIE_FLR_PIO2 StateCfgInit TxCPLD_FC VC0_CPLTLP_Queue_Mode Num_Lanes PCIE_CORE_PHY_STATUS Disable_Scrambler PCIE_CORE_PIPE_CONTROL VFID_SleepReq PIOReq_BAR2CtlPerr CplStatusIntEn PCIE_RSP_ERR_LOG2 PB_Sel PB_SelReg PCIE_PB_DATA pm_linkst_in_l1 LnD_RxStateReq LnG_CMD LnF_CMD GPIO16_ACT_LOW DBG_FEMIMICN T5_STATIC_M_PLL_FFTUNE T5_STATIC_PHY0RecRst_ T5_STATIC_U_PLL_FFSLEWRATE T5_STATIC_KX_PLL_M STATIC_U_DFS_FFTUNE5 GPIO10_PS_En MA_EXT_MEMORY0_WRDATA_CNT1 PLCIM_MstRspDataParErr CDemux EVnTagEn LimTxThresh RxmtCwndNewReno ByteCountTahoe EnableNewFar TNLFcoeMode RxTimerCompBuffer IspiWrBusy ospi_overflow1 MPS_TX_PAUSE_DURATION_BUF_GRP_TH9 MPS_TX_PAUSE_RETRANS_BUF_GRP_TH15 MPS_RX_PTP_ETYPE MPS_RX_PAUSE_GEN_TH_0_2 MPS_RX_CGEN_NCSI MacPadEnPt2 TP2MPS_Ch1_CLR CountPauseStatTx ULP_RX_RQE_PBL_MULTIPLE_OUTSTANDING_CNT AutoPciePause SINGLETHREAD SRVRINIT VFINDEX MtipRxffReset se_clr rx_dff_seg0 TXAQUIET MAC_PORT_EEE_TX_CTL MAC_PORT_PTP_TIMER_INCR1 RX_SFD_ANY MAC_PORT_AFRAMESRECEIVEDOKHI MAC_PORT_AOCTETSRECEIVEDOKHI MAC_PORT_ETHERSTATSFRAGMENTS MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2 100BaseT2HalfDplx MAC_PORT_MTIP_SGMII_PARTNER_ABILITY MAC_PORT_MTIP_VL_INTVL MAC_PORT_MTIP_PCS_DEVICE_ID1 TXPRBS9 MAC_PORT_MTIP_BASER_TEST_ERR_CNT alignstatus Lane9 MAC_PORT_MTIP_PCS_BIP_ERR_CNT_3 MAC_PORT_MTIP_PCS_BIP_ERR_CNT_12 10GKX4 MAC_PORT_BEAN_STATUS_LANE3 MAC_PORT_BEAN_REM_ABILITY_1_LANE3 CN1_UPD T5_TXSTAT_C0 T5_AE2_RXSTAT_C1 MAC_PORT_AE_KR_CTRL_2 MAC_PORT_AE_RX_SIGDET_2 MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_MODE_CONTROL MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE T5XWR DCCAMP BSIN JTAGAMPL MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_ADDR MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_MODE_CONTROL MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 MAC_PORT_TX_LINKD_TRANSMIT_DCC_CONTROL MAC_PORT_TX_LINK_BCST_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE ERRST FDINV MAC_PORT_RX_LINKA_RECEIVER_SIGDET_CONTROL MAC_PORT_RX_LINKA_RECEIVER_ANALOG_CONTROL_SWITCH HALF1 MAC_PORT_RX_LINKA_DFE_H6_AND_H7 H6SN_ReadWrite MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_2 MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 MAC_PORT_RX_LINKC_RECEIVER_ADAC_CONTROL MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_2 MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_2 MAC_PORT_RX_LINKD_DFE_OFFSET_EVN1_EVN2 RANK_PAIR3_PRI FAST_SIM_PER_CNTR PROTOCOL_DDR ERROR_CUSTOM_RD_MASK MC_DDRPHY_PC_MR0_PRI_RP WRAPSEL REFERENCE DQS_GATE_DELAY_N3 TRAILING_EDGE_FOUND_MASK EYE_CLIPPING_MASK ZERO_DETECTED JUMP_BACK_RIGHT MC_DDRPHY_DP18_WR_ERROR_MASK0 EN_SLICE_N_WR MEMINTD00_POS MEMINTD03_POS MEMINTD04_POS MC_DDRPHY_SEQ_RESERVED_ADDR2 OUTER_LOOP_CNT MC_DDRPHY_RC_ERROR_MASK0 DEBUG_BUS_SEL_LO DP18_14_Populated ADR12_0_Populated bbflags_timing mrrstat_beat4 mddr_lpddr2_clk_stop_idle zqcl_ma MC_UPCTL_DTUECTL MC_UPCTL_DFITRDDATAEN parity_intr_clr MC_UPCTL_DFITRCMD CTL_CKE MC_UE_COR_DATA_RDATA MC_P_BIST_CMD MC_P_BIST_CRC_SEED EDC_H_BIST_NUM_ERR TRIG NOS C_VAL perr_db_fifo err_gts_sync err_pc_rsp_len2 Req_LnI_RxStateDone Lane8LF Lane10LF DL_DOWN_PCIeCRST_MODE1_STATE_flag DBG_CUST_EFUSE_BYTE12_15 DBG_CUST_EFUSE_BYTE52_55 HMA_DIS_128B_PG_CNT_FDBK CIM_PCIE_PKT_ERR_CODE align_ctl_fifo_perr_set2 DROP_INVLD_MC_CH2 more_first more_last ULP_TX_TLS_IND_CMD MPS_VF_TX_CTL_191_160 MPS_RX_ENCAP_NVGRE SAP_CHK_EN MPS_PORT_RX_TS_VLD MPS_STAT_STOP_UPD_TX_VF_192_223 MPS_RX_HASH_LKP_TABLE MacParity2 PL_DIS_PRTY_CHK iscsi_force_cmp_mode LIP_ZERO_ERR TcamCrcErr ClipTcamAccFail MAC100G40G_RESET pcs10g_reset_xfi_txclk pcs10g_reset_sd_rx_clk pcs10g_gate_xfi_rxclk mac1g10g_if_mode_ena sgmii_tx_lane_thresh Perr_rx12_pcs100g Perr_rx0_pcs100g tx_st_mac40g tx_st_mac1g10g Perr_tx2_fec40g MAC_PORT_MTIP_1G10G_RX_FIFO_ALMOST_F_E MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOCTETSHI MAC_PORT_MTIP_1G10G_RX_FRAMESOKHI MAC_PORT_MTIP_1G10G_RX_ETHERSTATSDROPEVENTS MAC_PORT_MTIP_1G10G_RX_ETHERSTATSDROPEVENTSHI MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1519TOMAX MAC_PORT_MTIP_1G10G_TX_IFOUTERRORS MAC_PORT_MTIP_1G10G_TX_ETHERSTATSDROPEVENTSHI MAC_PORT_MTIP_SGMII_DECODE_ERROR MAC_PORT_MTIP_KR_10GBASE_R_PCS_STATUS_2 MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_ERROR_COUNTER Low_power_ability 40G_capable Clause_22_ExT 100GBase_R_capable LANE_2_BLK_LC32_6431K MAC_PORT_MTIP_CR4_DEVICES_IN_PKG2 Lane_6_blck_lck MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_2 MAC_PORT_MTIP_CR4_LANE_5_MAPPING MAC_PORT_MTIP_CR4_LANE_13_MAPPING MAC_PORT_MTIP_FEC0_NCERR_CNT_1 MAC_PORT_MTIP_FEC3_NCERR_CNT_1 INIT_CNT BGCLKSEL MAC_PORT_TX_LINKA_TRANSMIT_APPLIED_TUNE_REGISTER AS1X4 OS4X4 OS2X1 MAC_PORT_TX_LINKA_TRANSMIT_AE_C1_LIMIT_EXTENDED MAC_PORT_TX_LINKA_TRANSMIT_AE_C2_INIT2_EXTENDED MAC_PORT_TX_LINKC_TRANSMIT_2X_SEGMENT_APPLIED MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_1X_OVERRIDE MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE MAC_PORT_TX_LINKD_TRANSMIT_AE_C2_INIT2_EXTENDED MAC_PORT_RX_LINKA_RECEIVER_IQAMP_CONTROL_2 H1EX OVRTAILS MAC_PORT_RX_LINKA_AC_CAPACITOR_BIST MAC_PORT_RX_LINKB_RECEIVER_AC_COUPLING_VALUE MAC_PORT_RX_LINKB_DFE_H1ODD_DELTA_AND_H1EVEN_DELTA MC_DDRPHY_DP18_WRCLK_CNTL DIS_CLK_GATE MT_PERFORM_RDCLK_ALIGN MT_WPRD_ENABLE MC_DDRPHY_APB_MTSTAT_REG1 XSR_PREVENT PM_ENABLE MC_LMC_CFGR0 MC_LMC_CMD12 T_RP1 MRS_RDO DRAM_ADR RD_HI_TH EDC_H_DBG_MA_WDATA_INTF EDC_H_DBG_MA_WR_REQ_CNT dead_cycle0_pre_ref LOCK HMA_TLB_DESC_3_H ADDR2_MIN MPS_VF_STAT_TX_VF_MCAST_BYTES_L MPS_VF_STAT_RX_VF_ERR_FRAMES_L Return Execute dport nat_sport parameter "%s" has bad "value" %s PCIeDataChannel: PackEn: StatusPgTPHintEn: Queue_Valid: TX Power %fmW
XFF unknown scheduler config parameter "%s" sched params "pkt-size" missing for rate-limit level sched params "max-rate" is less than "min-rate" failed to parse offload settings "%s" on line %zd @0 decompress_val, bad switch: %d Tahoe TF_TX_CHANNEL TF_CORE_MORE t_rtt_ts_recent_age Send unacknowledged Reserved rx_frag3_len_raw rx_frag3_start_idx_offset rx_ddp_buf0_tag Count_Hits frag2_idx %-10u length %-10u frag2_ptr 0x%-8x
which has %u - %u = %u bytes of space left
ddp_indicate_fll HostPageSizePF5 Opcode_Min Opcode_Max perr_dmarbt perr_pd_fifo0 err_pcie_error0 ForceVFPF6DBtoLP MaxTag2 SGE_DEBUG_DATA_LOW SGE_INT_ENABLE4 SGE_PC0_RSP_BIST_ERROR_CNT SGE_PC1_RSP_BIST_ERROR_CNT SGE_CTXT_MASK1 SGE_CTXT_MASK4 SGE_LA_RESERVED_7 SGE_LA_WRPTR_15 UnxSplCplErr DCntPerr PIOReqPerr PIOReq PCIE_HMA_CFG ForceStrictTS1 PCIE_FUNC_CTL_STAT PCIE_PDEBUG_INDEX CH1 EPEP OP1D ON2H OC3T RVDE PC0I ALET CPM7 OPM3 OPM7 AuxPwrPMEn GPIO0_Out_Val GPIO9 KX_OCLK_En U_LOCK_ACT_LOW DBG_STATIC_M_PLL_CONF STATIC_KX_PLL_N2 STATIC_KR_PLL_N2 PVT_REG_TERMP_A MC_PCTL_POWCTL mem_bl rank3_odt_default dtu_eaffl dtu_allbits_7 MC_PCTL_TZQCS MC_PCTL_DTUWD2 MC_PCTL_DTURD2 ACPONR MC_DDR3PHYAC_MDIPR MC_PVT_REG_THRESHOLD STALL_CHK_BIT RDATA_OCNT MA_PARITY_ERROR_ENABLE CIM_FLASH_BASE_ADDR EEPROMBaseAddr CIM_HOST_INT_ENABLE SglWrEEPROMIntEn SglRdEEPROMIntEn IllRdIntEn BlkRdBootInt CIM_MEM_ZONE0_LEN CIM_MEM_ZONE3_LEN CIM_TIMER0 CTag TP_CMM_MM_BASE DupAckThresh RxSynFilter EnableFlush TP_PARA_REG7 TnlErrorIpVer TP_RSS_LKP_TABLE TP_RSS_CONFIG TP_MOD_RATE_LIMIT DbTxTidPerr ETpInTcpOptFifoPerr CTpOutCplFifoPerr RxTimerDack RxRcvOooDataFin EnableLpbkFull1 EnablePcmdFull1 CQE_fifo_perr_set0 ULP_TX_LA_RDDATA_6 cong_thresh3 cong_thresh2 MPS_TX_PAUSE_DURATION_BUF_GRP2 CH_MAP1 MPS_PORT_TX_PAUSE_SOURCE_L DROP_WT PGFL MPS_PFVF_ATRB MPS_PFVF_ATRB_FLTR13 MPS_RX_SE_CNT_OUT23 CLS_PRT MPS_TX_SECNT_BUBBLE_CLR FullPt0 ErrPt2 MPS_STAT_INT_ENABLE Drop MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H MPS_PORT_STAT_TX_PORT_UCAST_H MPS_PORT_STAT_TX_PORT_PAUSE_L MPS_PORT_STAT_TX_PORT_PPP6_L MPS_PORT_STAT_LB_PORT_ERROR_L MPS_PORT_STAT_RX_PORT_SYM_ERROR_L MPS_PF_STAT_TX_PF_MCAST_BYTES_H MPS_CLS_PL_TEST_RES_DATA Priority1 SMB_GLOBAL_TIME_CFG MicroCntCfg SMB_MST_CTL_STS SMB_MST_RX_FIFO_RDWR SlvCrcInBitRev SlvRxAddrIntEn MstNAckIntEn Interface MCPartCGEn Port2SleepMode Port1SleepMode ENABLE_DDPDF_1 ENABLE_DDPMF_1 ENABLE_PCMDF_0 ULP_RX_PERR_INJECT PCIE FLR PL_TIMEOUT_CTL NFASrchFail DBGICMDLEARN DBGICMDMODE LE_DB_PTID_SVRBASE LE_DEBUG_LA_CAPTURED_DATA err_discard_en mac_rx_rst FWD_BMC NCSI_LA_RESERVED arb_done arb_started PauseEn Speed UserProgInput MCHashEn ARPEn SinkTx XGMAC_PORT_SPARE XGMAC_PORT_HSS_CFG0 RXDPRBSRST RXCPRBSEN RXAPRBSRST RXBEARLYIN RXDPRBSERR RXBPRBSERR EnHashUcast XGMAC_PORT_XGM_INT_DISABLE Operation XGMAC_PORT_XGM_STAT_RX_BYTES_LOW TestSel rx_tst_en err_blk_cnt 10GBASE_KX4_neg FLFSM_STATE XGMAC_PORT_HSS_TXA_DRIVER_OVR_CTRL XGMAC_PORT_HSS_TXA_TAP2_IDAC_APP RESETFW VLCKD EMBRDY XGMAC_PORT_HSS_RXA_DFE_H3 XGMAC_PORT_HSS_RXB_DFE_E0_E1_OFFSET XGMAC_PORT_HSS_RXB_DACA_MIN XGMAC_PORT_HSS_TXC_TAP0_COEFF XGMAC_PORT_HSS_TXC_TAP2_COEFF XGMAC_PORT_HSS_TX_TDM_BIASGEN_PWRON_TIMER XGMAC_PORT_HSS_TX_TAP1_COEFF XGMAC_PORT_HSS_TX_PWR XGMAC_PORT_HSS_TXRX_CFG_MODE perr_edma_input_fifo2 SGE_DEEP_SLEEP SGE_PC_RSP_ERROR debug_PD_RdRsp_SOP3_cnt debug_M_rd_req_outstanding_VFIFO debug_M_RspVld debug_st_imsg_ctxt PERstTimeout PCIE_VF_MSI_EN_3 Crosslink_Active Reset_Assert Loopback_Enable PCIE_CORE_DEBUG_0 RxTLP_FC_Not_Returned PCIE_CORE_GEN3_CONTROL PCIE_CORE_GEN3_EQ_CONTROL PCIE_CORE_DBI_RO_WE PCIE_CGEN DMA_Dynamic_CGEN NPD_CreditsAvailVC0 NPD_CreditsRequired LnH_RxPwrState LnE_CMD T5_STATIC_U_PLL_BYPASS T5_STATIC_U_PLL_MULTPRE T5_STATIC_KR_PLL_CCALMETHOD T5_STATIC_KR_PLL_CCALBANDSEL STATIC_C_DFS_ENABLE DBG_EFUSE_BYTE16_19 UE_ENABLE CL9_RD_DATA_TO_EN CL2_RD_DATA_TO_EN CL9_RD_CMD_TO_ERROR CL3_RD_DATA_TO_ERROR CL3_IF_PAR_EN SOF_FS2 ulp2tp_data_perr_set t10_pi_sram_perr_set0 MTU_ERR_INT3 MPS_RX_PTP_TCP MPS_RX_PTP_CTL MPS_RX_MAC_CLS_DROP_CNT2 LpbkPadEnPt3 MPS_TRC_FILTER1_RSS_HASH CountPauseMCTx MstTxFifo atomic_rsp_qno immediate_with_se_qno multiple_pref_enable BYPASS_CGEN PF_UNTAGGED_TPT_0 ULP_RX_MSN_CHECK_ENABLE SRVRSRAMBASE LE_DB_SECOND_ACTIVE_MASK_IPV4 MtipTxffReset AET2Reset FCSDisCtrl MAC_PORT_PERR_INJECT RXBREFRESH PCSSEG0_CGEN EEE_TX_RESET PFC_MODE TX_ENA AVAIL MAC_PORT_ETHERSTATSPKTS256TO511OCTETSHI MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETSHI MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1 MAC_PORT_MTIP_SGMII_IF_MODE MAC_PORT_MTIP_VLAN_TPID_1 VendDev2 Lane2 MAC_PORT_BEAN_ABILITY_0 MAC_PORT_BEAN_ETH_STATUS_LANE1 fecKRsigdet fec_en_err_ind FEC_LOCKED_100 MAC_PORT_AE_FSM_CTL_2 MAC_PORT_MACRO_TEST_CONTROL_6 MAC_PORT_PLLB_CHARGE_PUMP_CONTROL T5_TX_CFGEXT MAC_PORT_TX_LINKA_TRANSMIT_DCC_OVERRIDE MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_OVERRIDE_CONTROL MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT MAC_PORT_TX_LINK_BCST_TRANSMIT_POLARITY T5_RX_RTSEL FRZFW MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_2 MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_1 LOFE1S_ReadOnly LOFO1 MAC_PORT_RX_LINKB_PHASE_ROTATOR_OFFSET_CONTROL MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 MAC_PORT_RX_LINKB_DFE_OFFSET_ODD1_ODD2 MAC_PORT_RX_LINKB_DFE_H1 MAC_PORT_RX_LINKD_DFE_H5 MAC_PORT_RX_LINKD_DFE_H10_AND_H11 MAC_PORT_RX_LINK_BCST_RECEIVER_LOFF_CONTROL MAC_PORT_RX_LINK_BCST_DFE_TAP_ENABLE MC_DDRPHY_PC_RANK_PAIR1 SYSCLK_2X_MEMINTCLKO MEMCTL_CIC_FAST ERROR_INITIAL_COARSE_WR ERROR_COARSE_RD_MASK INIT_CAL_COMPLETE ADR_TEST_CHECK_EN MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN1 MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0 SLICE_SEL_REG_BITS4_5 MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP REFERENCE_BITS9_15 MC_DDRPHY_DP18_RD_LVL_STATUS3 FINE_STEPPING VALID_NS_BIG_L_MASK CE0DLTVCCD2 MC_DDRPHY_DP18_DFT_DIG_EYE MEMINTD01_PO MEMINTD07_POS EARLY_REQ_ERR_MASK ODT_WR_VALUES_BITS0_7 DP18_7_Populated MC_UPCTL_MCMD dfitrcmd_start MC_P_CORE_PCTL_STAT SleepStatus MC_P_BIST_CMD_LEN pl_bar2_frm_err fatal_ll_empty SGE_WC_EGRS_BAR2_OFF_VF Req_LnD_RxStateReq PCIE_KDOORBELL_GTS_VF_BASE_LEN PCIE_PHY_GEN3_AE3 PCIE_PHY_FS_LF5 Lane13LF PF4_DState STATIC_M_PLL_FFSLEWRATE STATIC_M_PLL_SDORDER DBG_STATIC_U_PLL_CONF1 STATIC_U_PLL_MULTFRAC STATIC_KR_PLL_CCALLOAD FUTURE_DEXPANSION_IPE EcnSynEct ULPType7Offset ULPType5Offset MPS_RX_MAC_BG_PG_CNT2 MPS_RX_IPV6 MPS_RX_CNT_GENEVE_PKT_MAC1 MPS_RX_CNT_TNL_ERR_PKT_TO_TP1 Err_Tnl_Hdr_Len EN2 DisTcamParChk ClsTrcReplicate SsramIntPerr LE_DB_PSV_FILTER_MASK_TUP_IPV4 sgmii_gate_tx_clk mac40g100g_gate_ff_tx_clk pcs1g_clk_enable Perr_rx2_fec100g_dk MAC_PORT_MAC_STAT_DEBUG Perr_rx3_fec40g POST_INCR_READ MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_1HI TC_present MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_2 MAC_PORT_MTIP_KR4_LANE_1_MAPPING MAC_PORT_MTIP_CR4_DEVICES_IN_PKG1 MAC_PORT_MTIP_CR4_ERR_BLK_HIGH_ORDER_CNT Lane_1_blck_lck Lane_12_blck_lck MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_4 MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_18 MAC_PORT_MTIP_CR4_LANE_2_MAPPING MAC_PORT_MTIP_CR4_LANE_4_MAPPING MAC_PORT_MTIP_CR4_LANE_14_MAPPING MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_PATTERN MAC_PORT_MTIP_FEC1_CERR_CNT_1 C2_C3_STATE_SEL MAC_PORT_AET_STATUS_20 SPWRENA AS1X3 MAC_PORT_TX_LINKB_TRANSMIT_AE_C3_LIMIT_EXTENDED MAC_PORT_TX_LINKC_TRANSMIT_AE_C1_LIMIT_EXTENDED MAC_PORT_TX_LINKC_TRANSMIT_AE_C3_INIT2_EXTENDED MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_5_4 HBISTSP HPASS LGTGT OFFSN RX_LINKANLGSW FSPY2DATA H5MAG DCDSIGN MAC_PORT_RX_LINKB_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL MAC_PORT_RX_LINKC_RECEIVER_IQAMP_CONTROL_1 MAC_PORT_RX_LINKC_RECEIVER_DCC_CONTROL MAC_PORT_RX_LINKD_RECEIVER_DACA_MIN MAC_PORT_RX_LINKD_RECEIVER_AC_COUPLING_CONTROL MAC_PORT_RX_LINKD_RECEIVER_QCC_CONTROL DDRPHY_PROTOCOL PER_CAL_ABORT MAX_DQS_ITER MC_ENABLE MC_LMC_CMD9 T_RTP T_RRD T_SYS_RDLAT_DBG MC_LMC_SMR3 GD_MODE WR_DBI DM_MODE MC_UE_ERR_ECC_DATA0 MWDataRdy dead_cycle1_bbi_rmw HMA_TLB_DESC_0_L HMA_TLB_DESC_5_H HMA_LOCAL_DEBUG_CFG MPS_VF_CTL MPS_VF_STAT_TX_VF_MCAST_FRAMES_L MPS_VF_STAT_TX_VF_UCAST_BYTES_H MPS_VF_STAT_TX_VF_OFFLOAD_FRAMES_H MPS_VF_STAT_RX_VF_BCAST_BYTES_L MPS_VF_STAT_RX_VF_MCAST_BYTES_H MPS_VF_STAT_RX_VF_ERR_FRAMES_H CIM_VF_EXT_MAILBOX_CTRL CIM_VF_EXT_MAILBOX_DATA_10 memdump
Available blocks: , dmac=%02x:%02x:%02x:%02x:%02x:%02x , l2tidx=%d invalid type "%s"; must be one of "ipv4" or "ipv6" eport mask cannot be provided for maskless specification DCAEgrQEn: DCAIngQEnable: class sched params "level" parameter missing sack tls reno TF_KEEPALIVE dack_mss Smoothed round-trip time NewReno fast recovery end sequence number tx_last_ptr CQ index of CQ for RQ ddp_off ddp_buf0_flush OPT_1_LISTEN_FILTER OPT_0_SM_SEL l2t_ix 0x%x, smac sel 0x%x, tos 0x%x
ULP: ulp_type %u (%s), ulp_raw %u Priority QueuesPerPageVFPF1 perr_flm_MCReq_fifo SGE_PERR_ENABLE2 NoHdr TimerValue5 SGE_SHARED_TAG_POOL_CFG TARTagPerr PCIE_CFG DevStateRstMode PCIE_PIO_PAUSE PCIE_MAX_RDSIZE TxnDisable PCIE_CMDW_CNT PCIE_HMA_RSP_CNT PCIE_RSP_ERR_STAT_7 UPEP RCII TXE2 TDCE TNPI TFTI PME7 PC4I CPM0 D3HotEn PortEn_PONR SDRHalfWord0 GPIO8_Out_Val GPIO3_Out_Val GPIO15_IN GPIO7_IN ARM_ERROR_OUT_int_enbl GPIO7 C_LOCK_ACT_LOW KR_LOCK_ACT_LOW STATIC_KX_PLL_N1 DBG_TRACE0_CONF_MASKREG1 Wr_pointer_addr1 PVT_REG_DRVP_A DBG_PVT_REG_OUT_TERMP DRVP_B_HISTORY two_t_en dtu_allbits_3 MC_PCTL_DWLCFG0 dtu_wr_row dtu_rd_rank dtu_nalen MC_PCTL_PHYPVTUPDI LPFEN CKEOEN ACPOND MC_DDR3PHYAC_ECSR MC_DDR3PHYAC_MDTPR RSTCXKS BDIV MC_DDR3PHYDATX8_GCR MC_DDR3PHYDATX8_RDBDR4 Read BIST_CMD_GAP MC_BIST_NUM_ERR MA_CLIENT12_RD_LATENCY_THRESHOLD MA_TP_TH0_DEBUG_CNT CL2_PAR_RDQUEUE_ERROR_EN LOGIC_FIFO_PAR_ERROR COHERANCY_ENABLE IBQNCSIParErr ZONE_DST RddpCongEn TxCongestionMode EnableTnlCngSge DropErrorFrag InitSrtt MTUWidth ULPType5Field TNL4tupEnIpv4 RX_MOD_RATE_LIMIT_TICK TP_DEBUG_FLAGS RxRcvOooData TxRxmTimer EnableHdrFull0 TxChnXoff0 TxModXoff6 TxModXoff5 ULP_TX_CONFIG cim2ulp_fifo_perr_set1 ERR_CH3 CLR_CH3 ULP_TX_LA_RDDATA_3 ULP_TX_LA_RDPTR_5 ULP_TX_LA_RESERVED_5 iespi0_Rx_framing_error ocspi0_ofifo2x_Tx_framing_error e_pcmd_par_error MPS_VF_TX_CTL_127_96 MPS_PORT_TX_PAUSE_CTL MPS_PORT_TX_PAUSE_DEST_L CBA_EN CTL_P1 MPS_RX_PG_SHR0 CHMN MPS_BMC_PKT_CNT EOP_CNT_IN MPS_RX_SE_CNT_IN1 LEN_ERR OVLAN_EN3 MPS_PORT_RX_OVLAN3 MPS_PORT_RX_RSS_CONTROL ValidCh0 SOPPt1 SizePt2 RssControl MPS_TRC_FILTER_MATCH_CTL_B Txpf MPS_STAT_RX_BG_0_LB_DROP_FRAME_L MPS_PORT_STAT_LB_PORT_FRAMES_H MPS_PF_STAT_TX_PF_BCAST_BYTES_L MPS_PF_STAT_RX_PF_MCAST_FRAMES_L cpu_no_enable MstReset SlvCrcOutBitRev SlvFifoParInt SlvCommandCodeInvInt DebugDataL MI_DATA DataBits TPPartCGEn RDMA_0b_wr_pass RDMA_State_En RDMA_0b_wr_cqe PERR_ENABLE_PRSDF_1 ULP_RX_DBG_DATAL PL_INT_MAP2 MAP1 CMDOVERLAPDIS DBGIRspValid LastCmdA WireEn NCSI_RX_FIFO_CNT MPS2NC_EOP_CNT token WOL RXFIFO_prty_err UnderrunErr FrameRcvd NCSI_MACB_PAUSE_TIME NCSI_MACB_EXCESSIVE_COL XGMAC_PORT_LED_COUNTLO LocalFault TXDTS RXAPRBSFRCERR RXCDATASYNC RXDLATEIN SendPause XGMAC_PORT_XGM_TX_PAUSE_TIMER Lane1_CTC_Status tpter_cnt_rst XGMAC_PORT_AN_NP_UPPER_TRANSMIT MAN_DEC CC1FSM_STATE XGMAC_PORT_AE_TX_DIS C2STAT XGMAC_PORT_HSS_TXB_8023AP_AE_CMD XGMAC_PORT_HSS_TXB_PWR_DAC_OVR LBFRCERROR FDWRAPCLK ADCORR POLE XGMAC_PORT_HSS_RXA_DIGITAL_EYE_CTRL FH2H3 XGMAC_PORT_HSS_RXB_DFE_CTRL XGMAC_PORT_HSS_RXB_DFE_H3 XGMAC_PORT_HSS_TXC_TAP1_COEFF XGMAC_PORT_HSS_TXC_TAP0_IDAC_APP XGMAC_PORT_HSS_RXC_PH_ROTATOR_POSITION2 XGMAC_PORT_HSS_RXC_DFE_E0_E1_OFFSET XGMAC_PORT_HSS_RXD_ADAC_CTRL XGMAC_PORT_HSS_TX_EXT_ADDR_DATA XGMAC_PORT_HSS_RX_DFE_DATA_EDGE_SAMPLE XGMAC_PORT_HSS_RX_DFE_H4 SGE_PF_KTIMESTAMP_HI perr_pc_chpi_rsp2 perr_PC_RspData perr_edma_input_fifo3 EDMA3_Sleep_Status debug_U_Rx_EOP0_cnt SGE_DEBUG_DATA_HIGH_INDEX_3 debug_U_Tx_SOP0_cnt debug_PD_RdReq_SOP3_cnt debug_CPLSW_TP_Rx_EOP1_cnt debug_flm_idma0_ctxt_hdr_active debug_PC_Rsp_EOP2_cnt debug_st_idma1_ialn SGE_DEBUG_DATA_LOW_INDEX_4 SGE_DEBUG_DATA_LOW_INDEX_8 HReqRdPerr DBITimeout L1ClkRemovalEn PCIE_STATIC_CFG2 PCIE_VF_MSIX_EN_0 PD1 NPD1 L1_Entrance_Latency MaxFunc PCIE_CORE_TRANSMIT_POSTED_FC_CREDIT_STATUS PCIE_CORE_VC_TRANSMIT_ARBITRATION_2 VC0_Rx_Ordering RspDropFLRLogEn LnD_STAT LnA_STAT T5_STATIC_M_PLL_SLEEP T5_STATIC_U_PLL_RANGEA T5_STATIC_KX_PLL_CCALFMIN STATIC_U_DFS_FFTUNE4 MA_ULPTX_WRDATA_CNT DELAY CL6_WR_CMD_TO_ERROR CL2_WR_DATA_TO_ERROR CL8_RD_CMD_TO_EN CL5_RD_DATA_TO_EN MA_LOCAL_DEBUG_RPT CIM_SGE0_PKT_ERR_CODE OverdriveNewReno FrmwrQueMask ULP_TX_CGEN_Channel cmd_gen_en PUDPORT1 TxOutLpbk2_CGEN TxInCh4_CGEN SlvBusBusy immediate_qno ULPRX2MA_IntfPerr ENABLE_DDP_HINT_0 MAC_Clk_Sel HSSRESYNCB TXCCONFIGSEL RXCREFRESH_STATUS TXDQUIET_STATUS eee_rx_10g_state MAC_PORT_PTP_TIMER_WR_LO MAC_PORT_PTP_TIMER_WR_HI X_TICK MAC_PORT_MTIP_RX_FIFO_ALMOST_F_E MAC_PORT_AFRAMECHECKSEQUENCEERRORS MAC_PORT_AOCTETSRECEIVEDOK MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7HI PgRcvd RxFault RXPRBS31 DataPatSel Lane8 MAC_PORT_MTIP_PCS_BIP_ERR_CNT_2 NXP MAC_PORT_BEAN_ABILITY_2 100GCR10 T5_TXREQ_C2 MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_3 MAC_PORT_PLLB_MACRO_TEST_CONTROL_2 DCCTSTOUT C2MIN MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_OVERRIDE_CONTROL MAC_PORT_TX_LINKB_TRANSMIT_802_3AZ_CONTROL MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C1_INIT_EXTENDED MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTE_4 MAC_PORT_RX_LINKA_RECEIVER_DACA_MIN_AND_DACAZ FH6H12 LOFO2S_ReadWrite OFFSN_ReadWrite T5EMEN H5OSN_ReadOnly H11SN_ReadWrite MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_2 MAC_PORT_RX_LINKB_RECEIVER_LOFF_CONTROL MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_1 MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 MAC_PORT_RX_LINKD_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PATTERN_LENGTH MAC_PORT_RX_LINKD_DFE_H1 RANK_PAIR1_SEC PERIODIC_RELOAD_VALUE0 REFRESH_ALL_RANKS ERROR_WRITE_CTR_MASK MC_DDRPHY_PC_MR1_SEC_RP DI_ADR6_ADR7 ADR_TEST_4TO1_MODE EN_SLICE_P_WR SLICE_SEL_REG_BITS0_1 SLICE_SEL_REG_BITS2_3 POST_CURSOR0 MC_DDRPHY_ADR_PLL_VREG_CONFIG_0 SYSCLK_ENABLE CE0DLTVCC FLUSH ATEST1CTL3 WR_FIFO_STAB DFT_PRBS7_GEN_EN MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP SYSCLK_PHASE_ALIGN_RESET MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR INCOMPLETE_RD_CAL_N3 COARSE_PATTERN_ERR_N0_MASK MC_DDRPHY_DP18_RD_DIA_CONFIG1 EYEDAC_PD MC_DDRPHY_SEQ_ODT_RD_CONFIG1 MC_DDRPHY_SEQ_ODT_RD_CONFIG2 MC_DDRPHY_RC_CONFIG3 DP18_5_Populated stagger_cs zqcs_op MC_UPCTL_TCKE odt_len_b8_r odt_lat_w MC_P_PHY_CTRL TScale err_ishift_ur0 DbpTbufRsv1 debug_idma0_IDMA2IMSG_EOP VfEQsPerPage Req_LnO_RxStateReq LnJ_STAT Phy_Reg_Enable PCIE_FLR_VF7_STATUS STATIC_M_PLL_MULTPRE STATIC_C_PLL_FFBYPASS STATIC_KR_PLL_BGOFFSET STATIC_KX_PLL_CPISEL EFUSE_DOUT HMA_NUM_PG_128B_FDBK HMA_DIS_ADV_ARB CFastDemuxEn MPS_RX_MPS2NCSI_CNT MPS_PORT_RX_VF_MAP7 DisEncap VIDL ddp_version_1 TlsPpLlimit SRCH_RGN_HIT INTERNAL_ERR ERR_TID mac1g10g_reset_ff_rx_clk mac40g100g_gate_txclk CUF_C3_UPDATE MAC_PORT_MAC_DEBUG_RO pcs100g_ber_timer_done RX_LOWP CLEAR_ON_READ MAC_PORT_MTIP_1G10G_RX_ETHERSTATSUNDERSIZEPKTSHI MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS256TO511OCTETSHI MAC_PORT_MTIP_1G10G_TX_IFMULTICASTPKTSHI MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTSHI MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS256TO511OCTETSHI MAC_PORT_MTIP_KR4_ERR_BLK_HIGH_ORDER_CNT MAC_PORT_MTIP_KR4_LANE_2_MAPPING RX_Link_STAT Lane_14_blck_lck Lane1_algn_mrkr_lck MAC_PORT_AET_STATUS_21 MAC_PORT_REFVREG_CONTROL MAC_PORT_INEQUALITY_LOW_LIMIT_MASK AS4X1 AS1X2 OS4X2 OS1X6 MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SIGN_OVERRIDE H1ANOFST WRTACC2 LFREG CLKALGNCMP MAC_PORT_RX_LINKB_DFE_H1H2H3_LOCAL_OFFSET_VALUE MAC_PORT_RX_LINKB_RECEIVER_LOFF_CONTROL_REGISTER MAC_PORT_RX_LINKC_DFE_H1H2H3_LOCAL_OFFSET MAC_PORT_RX_LINKC_AC_CAPACITOR_BIST MAC_PORT_RX_LINKC_DFE_TAP MAC_PORT_RX_LINKC_DFE_H1ODD_DELTA_AND_H1EVEN_DELTA MAC_PORT_RX_LINKC_RECEIVER_DCD_CONTROL MAC_PORT_RX_LINKD_DFE_H1ODD_DELTA_AND_H1EVEN_DELTA MAC_PORT_RX_LINK_BCST_DFE_H1H2H3_LOCAL_OFFSET MAC_PORT_RX_LINK_BCST_AC_CAPACITOR_BIST ANALOG_PD_DIV MC_DDRPHY_AD32S_OUTPUT_FORCE_ATEST_CNTL AD32S_HS_PROBE_B_SEL MC_DDRPHY_AD32S_OUTPUT_DRIVER_FORCE_VALUE1 MC_LMC_INITSEQ13 RTT_NOM1 WR_CRC SMR3_RFU0 STATIC_OOOEN BRspData stg_cmdq_notempty VA HMA_REG1_MASK HMA_REG3_BASE OTF_INT_ENABLE stdin error reg32 cim %sfilter: no arguments. vld:oVLAN , vlan=none , vlan=insert(%x) iport port, dmac, smac, vlan, and nat only make sense with "action switch" sge_context: incorrect number of arguments. egress FID: RxIntCounterThreshold: CngIMSG: MPS Rx create Rev %s
invalid level parameter "%s" relative pkt-size
Normal Priority TCAM Region: TF_RX_FLOW_CONTROL_DDP rx_channel tx_queue rcv_coalesce_enable ask_mode TF_MOD_SCHD_RX dack_timer TF_DUPACK_COUNT_ODD Page pointer for last byte in send buffer rx_ptr Receive recovered PDU header length TF_DDP_PSHF_ENABLE_1 TF_DDP_BUF1_UNUSED Mask_Hash rq_start %u, rq_MSN %u, rq_max_off %u, rq_write_ptr %u
frag0_idx %-10u length %-10u rx_ptr 0x%-8x
core_bypass FLSplitMin EgrPCIeBoundary QueuesPerPagePF4 HintDepthCtl SGE_HINT_CFG SGE_CTXT_DATA5 SGE_CTXT_DATA6 CRspPerr CfgSnp DLDnPCIePreCRstMode CplConfig PIOStopEn PCIE_CMDR_REQ_CNT BRVN OP0H PCIE_CORE_INBOUND_POSTED_HEADER_BUFFER_ALLOCATION PINA PMC2 DBG_DBG0_EN PortEn_POND GPIO9_Out_Val GPIO6_Out_Val GPIO0_IN GPIO14 pll_lock_lost_int_cause HALT_UPDATe loopback_en cmd_add_del rank_sel dv_alen MC_PCTL_TRRD dtu_wr_bank MC_PCTL_DTULFSRRD ea_row pvt_upd_trig_pol i_pvt_upd_done MC_DDR3PHYDATX8_WDBDR2 MC_DDR3PHYDATX8_RDBDR1 WLSTEP MC_PVT_REG_OUT_DRVP PERR_REG_INT_ENABLE ECC_UE_PAR_CAUSE PERR_INT_CAUSE MC_ECC_STATUS STATIC_ORG DBG_READ_REQ_CNT CL1_PAR_RDQUEUE_ERROR_EN ARB1_PAR_WRQUEUE_ERROR CL4_PAR_WRQUEUE_ERROR BlkWrCtlInt CIM_MEM_ZONE4_BA CIM_PERR_INJECT CIM_PF_MAILBOX_DATA MBMsgRdyIntEn TcpOptParserDisCh0 IPIDSplitMode MTUEnable DisableInvPend AcceptLatestRcvAdv EnableMibVfMode EnableTnlOfdClosed TimerBackoffIndex4 TimerBackoffIndex15 RxUrgTunnel NewRenoCfg TP_KEEP_INTVL LkpTblQueue1 TNLVrtSel SYNMapEn Disable TP_RSS_CONFIG_TNL ChnCount2 ChnUndFlow2 TP_CMM_MM_MAX_PSTRUCT TP_INT_ENABLE ProtocolSramPerr TP_MOD_POP_CNT TxRxmFast TxChnXoff2 TnlRate0 ULP_TX_FPGA_CMD_2 ULP_TX_FPGA_CMD_8 ULP_TX_SE_CNT_CH3 ULP_TX_DROP_CNT DROP_CH0 ULP_TX_LA_WRPTR_8 ocspi1_Tx_framing_error ch2_output oespi2_ofifo2x_Tx_framing_error zero_c_cmd_error StatIntEnb TrcInt oVlanSelLpbk3 RxHalted MPS_RX_CTL MPS_RX_PG_RSV4 RPLC MPS_RX_PT_ARB3 SOP_CNT_PM MPS_RX_IN_BUS_STATE MPS_RX_SPARE PAUSE_FWD_UP FRMERR MPS_TX_SE_CNT_TP23 EOPCh3 ErrCh3 ErrPt3 MPS_PORT_TX_LPBK_RELOAD_CH1 MPS_TRC_CFG MPS_TRC_FILTER2_MATCH Rxport Lbport MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H MPS_STAT_RX_BG_2_LB_DROP_FRAME_H MPS_PORT_STAT_TX_PORT_128B_255B_L MPS_PORT_STAT_TX_PORT_256B_511B_H MPS_PORT_STAT_TX_PORT_512B_1023B_L MPS_PORT_STAT_TX_PORT_PPP0_L MPS_PORT_STAT_LB_PORT_BCAST_H MPS_PORT_STAT_LB_PORT_DROP_FRAMES MPS_PORT_STAT_RX_PORT_MCAST_L MPS_PORT_STAT_RX_PORT_64B_H MPS_PF_STAT_TX_PF_MCAST_FRAMES_H Cls_Match MstFifoDbg SMB_SLV_CTL_CFG SlvFifoCnt MstRxFifoParEn SlvCommandCodeInvEn SlvUnExpAckMstEn MstDoneIntEn DeviceID MI I2CM PL_PL_INT_CAUSE LE_DB_SERVER_INDEX ActiveHit LE_DB_DBGI_RSP_LAST_CMD LE_HASH_DEBUG_LA_DATA NCSI_RX_MS_CNT NCSI_SE_CNT_CIM CIM2NC_SOP_CNT NCSI_LA_CTL LoopPHY NoCopyFCS JumboEn HRespNotOK NCSI_MACB_RX_OVERSIZE_FRAME NCSI_MACB_SPECIFIC_2_HIGH PCS_Tx_Sel XG2G_Reset MACRxEn RXAPHSUPIN XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_2 XGMAC_PORT_XGM_STAT_TX_PAUSE XGMAC_PORT_XGM_STAT_RX_512_1023B_FRAMES Lane2_Sync_Status XGMAC_PORT_PCSR_TXTEST_SEEDB_UPPER XGMAC_PORT_AN_STATUS AN_Complete PRBS_CHK_SYNC FSM_TR_RST VLDEC C2UPDT XGMAC_PORT_HSS_TXB_TDM_BIASGEN_STANDBY_TIMER XGMAC_PORT_HSS_RXA_PH_ROTATOR_POSITION2 H3OSN OAE AERRFLG XGMAC_PORT_HSS_RXB_ADAC_CTRL XGMAC_PORT_HSS_TXD_8023AP_AE_CMD XGMAC_PORT_HSS_RX_CFG_MODE XGMAC_PORT_HSS_RX_VGA_CTRL2 XGMAC_PORT_HSS_RX_DACA_MIN XGMAC_PORT_HSS_RX_INTERNAL_STATUS bar2_egress_len_or_addr_err debug_UD_Rx_SOP1_cnt debug_M_rd_req_outstanding_FLM debug_PC_RspAFull_d SGE_DEBUG_DATA_LOW_INDEX_10 IPGrpPerr MstTagQPerr MstGrpPerr WrBE PL_CONTROL RcvdPIORspCookie PCIE_FLR_VF3_STATUS VC0_PH_Credits PCIE_CORE_LINK_WIDTH_SPEED_CHANGE PCIE_DMA_STAT2 IPRxHdr_VC1Perr MA_CplTagQPerr PCIE_PHY_FS_LF2 CoeffLane T5_STATIC_M_PLL_STOPCLKB T5_STATIC_C_PLL_MULTPRE T5_STATIC_C_PLL_LFTUNE_32_40 T5_STATIC_U_PLL_STOPCLKA T5_STATIC_KR_PLL_BYPASS T5_STATIC_KX_PLL_N2 MA_LE_WRDATA_CNT MA_EDRAM0_RDDATA_CNT0 CL1_RD_CMD_TO_EN CL3_RD_DATA_TO_EN CL12_IF_PAR_ERROR obq_wait_for_eop_flush_disable EnableFragCheck PMDbgAddr MPS_TX_PAUSE_DURATION_BUF_GRP_TH11 MPS_TX_PAUSE_DURATION_BUF_GRP_TH14 MTU_ERR_INT1 PUDP2EN MPS_RX_CGEN_MAC_IN MPS_TRC_FILTER3_RSS_CONTROL TrcAllMPS2TP OffEn StatWriteCtrl PtLpbk ULP_RX_CQE_GEN_EN ULP_RX_MISC_FEATURE_ENABLE SPEED PortSpeed MtipRegReset AEC3Reset MtipSd3TxRst sd_tx_clk_ena T5_AEC_PMA_RX_READY MAC_PORT_EPIO_DATA1 MAC_PORT_EPIO_DATA3 tx_ts_avail rx_dff_mac10 rx_stats MAC_PORT_HSS_CFG1 HSSDIVSELB MACSEG0_CGEN MAC_PORT_PTP_TIMER_OFFSET_2 AlmstEmpty MAC_PORT_VLANTRANSMITTEDOK MAC_PORT_ETHERSTATSDROPEVENTSHI MAC_PORT_ETHERSTATSPKTS512TO1023OCTETS MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_0 MAC_PORT_MTIP_SGMII_LINK_TIMER_HI 40G WIS CL22EXT MAC_PORT_MTIP_PCS_BIP_ERR_CNT_4 MAC_PORT_MTIP_PCS_LANE_MAP_4 MAC_PORT_BEAN_REM_ABILITY_2 MAC_PORT_LP_BEAN_XNP_0 MAC_PORT_LP_BEAN_XNP_1 MAC_PORT_BEAN_ABILITY_0_LANE2 MAC_PORT_LP_BEAN_XNP_2_LANE2 MAC_PORT_FEC_KR_LP_COEFF MAC_PORT_AE_FSM_CTL_1 EN_HOLD_FAIL MAC_PORT_PLLA_MACRO_TEST_CONTROL_2 T5_TX_BWSEL DCLKSAM MAC_PORT_TX_LINKB_TRANSMIT_DCLK_ROTATOR_OVERRIDE MAC_PORT_TX_LINKC_TRANSMIT_CONFIGURATION_MODE MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_APPLIED MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_APPLIED MAC_PORT_TX_LINKD_TRANSMIT_DCC_TIME_OUT MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED MAC_PORT_TX_LINK_BCST_TRANSMIT_TEST_CONTROL MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTE_4 FDCA T5LFREG T5_RX_LPFEN MAC_PORT_RX_LINKA_DFE_H2 H2OSN_ReadOnly H12MAG MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_2 PHSLOCK MAC_PORT_RX_LINKB_DFE_TAP_ENABLE MAC_PORT_RX_LINKC_PHASE_ROTATOR_OFFSET_CONTROL MAC_PORT_RX_LINKC_DIGITAL_EYE_CONTROL MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PATTERN_LENGTH MAC_PORT_RX_LINKD_DFE_OFFSET_ODD1_ODD2 MAC_PORT_RX_LINKD_DFE_H8_AND_H9 MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_1 MC_DDRPHY_PC_RELOAD_VALUE0 MEMCTL_CTRN_IGNORE ENA_INITIAL_COARSE_WR ERROR_WR_LEVEL MC_DDRPHY_PC_MR1_PRI_RP ADDR_MIRROR_RP1_PRI PLL_TUNEVCO_0_1 HS_PROBE_B_SEL_ MC_DDRPHY_ADR_GIANT_MUX_RESULTS_A0 SLEW_CAL_OVERRIDE QUAD3_CLK20_BIT7 MC_DDRPHY_DP18_RD_LVL_STATUS0 EN_TERM_N_WR MEMINTD05_POS DYN_POWER_CNTL_EN MC_DDRPHY_SEQ_RD_WR_DATA1 NUM_VALID_SAMPLES CONSEQ_PASS DP18_2_Populated MC_UPCTL_DTUNE MC_UPCTL_TMRR MC_UPCTL_DTULFSRRD MC_UPCTL_DTUEAF MC_UPCTL_DFITPHYWRLAT dfi_phyupd_en MC_UPCTL_DFITRWRLVLEN MC_UPCTL_DFISTSTAT0 MC_UPCTL_DFITRWRLVLRESP0 MC_UPCTL_DFITRRDLVLRESP0 HMA_TABLE_LINE0 silent_drop_tx_coal debug_idma0_idma2imsg_cmp_out_rss Req_LnC_RxStateReq Req_LnO_RxStateDone Req_LnN_RxStateReq Req_LnK_RxStateDone LnO_CMD Lane14FS PHY0_RTune_Ack STATIC_KR_PLL_ANALOGTUNE STATIC_KX_PLL_CCALFMAX FUTURE_EXPANSION_EE EcnCngFifo HashEth CPL_FLAGS_UPDATE_EN ULP_TX_CPL_TX_DATA_FLAGS_MASK save_first MAC_USED MPS_RX_CNT_GENEVE_PKT_MAC0 MPS_PORT_RX_TNL_LKP_INNER_SEL pbl_bound_check_w_pglen SUCCESS LE_DB_RSP_CODE_3 ERR_PROT VFLUTBUSY sgmii_reset_ref_clk mac1g10g_gate_rxclk CUF_C2_UPDATE Perr_rx7_pcs100g Perr_rx0_pcs40g ALARM_EN FORCE_SEND_IDLE ENA_CLAUSE MDIO_Busy Transmit_Fault Transmit_FIFO_Fault Err_bl_cnt MAC_PORT_MTIP_KR4_BER_HIGH_ORDER_CNT MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_0 MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_1 MAC_PORT_MTIP_CR4_BASE_R_TEST_CONTROL Lane6_algn_mrkr_lck Lane17_algn_mrkr_lck MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_3 tx_dp_overflow MAC_PORT_IMPEDENCE_CALIBRATION_CONTROL MAC_PORT_TX_LINKD_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE MAC_PORT_TX_LINKD_TRANSMIT_AE_C0_LIMIT_EXTENDED MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_5 PCLKSEL RAOFFF IQAMP CFSEL FDDCAL2 H14SN MAC_PORT_RX_LINKB_CDR_ANALOG_SWITCH MAC_PORT_RX_LINK_BCST_PEAKED_INTEGRATOR MC_DDRPHY_DP18_WRCLK_EDGE QUAD0_EDGES IDLE ZQCL_EN DCOO MC_LMC_INITSEQ7 MC_LMC_CMD8 T_MOD MC_LMC_SDTR5 RTT_NOM2 MC_LMC_T_PHYUPD1 MC_LMC_T_PHYUPD2 MRspVld rdtag_notempty RefPtr HMA_TLB_BITS MPS_VF_STAT_TX_VF_OFFLOAD_FRAMES_L reg: invalid number of arguments (%d) sf ulprx vld:VLAN %8s %03x/%03x TimerPending: SP_TPHintEn: %s%08x CXP No valid rules found in "%s" nagle tahoe %2.2x ESTABLISHED_TX dack_not_acked TF_TX_COMPACT Retransmit exponential backoff core_flush %u
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#
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#
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#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! ( # W= 44" s#
#
_W" &= eW" N! 0 # W= 44" s#
#
_W" &= eW" N! 8 # W= 44" s#
#
_W" &= eW" N! @ # W= 44" s#
#
_W" &= eW" N! H # W= 44" s#
#
_W" &= eW" N! P # W= 44" s#
#
_W" &= eW" N! X # W= 44" s#
#
_W" &= eW" N! ` # W= 44" s#
#
_W" &= eW" N! h # W= 44" s#
#
_W" &= eW" N! p # W= 44" s#
#
_W" &= eW" N! x # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! ( # W= 44" s#
#
_W" &= eW" N! 0 # W= 44" s#
#
_W" &= eW" N! 8 # W= 44" s#
#
_W" &= eW" N! @ # W= 44" s#
#
_W" &= eW" N! H # W= 44" s#
#
_W" &= eW" N! P # W= 44" s#
#
_W" &= eW" N! X # W= 44" s#
#
_W" &= eW" N! ` # W= 44" s#
#
_W" &= eW" N! h # W= 44" s#
#
_W" &= eW" N! p # W= 44" s#
#
_W" &= eW" N! x # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! ( # W= 44" s#
#
_W" &= eW" N! 0 # W= 44" s#
#
_W" &= eW" N! 8 # W= 44" s#
#
_W" &= eW" N! @ # W= 44" s#
#
_W" &= eW" N! H # W= 44" s#
#
_W" &= eW" N! P # W= 44" s#
#
_W" &= eW" N! X # W= 44" s#
#
_W" &= eW" N! ` # W= 44" s#
#
_W" &= eW" N! h # W= 44" s#
#
_W" &= eW" N! p # W= 44" s#
#
_W" &= eW" N! x # W= 44" s#
#
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H,! ^ " N! Ϗ! H,! $ ^ " N! Ϗ! H,! , ^ " N! Ϗ! H,! 4 ^ " N! Ϗ! H,! < ^ " N! Ϗ! H,! D ^ " N! Ϗ! H,! L ^ " N! Ϗ! H,! T ^ " N! Ϗ! H,! \ ^ " N! Ϗ! H,! d ^ " N! Ϗ! H,! l ^ " N! Ϗ! H,! t ^ " N! Ϗ! H,! | ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! $ ^ " N! Ϗ! H,! , ^ " N! Ϗ! H,! 4 ^ " N! Ϗ! H,! < ^ " N! Ϗ! H,! D ^ " N! Ϗ! H,! L ^ " N! Ϗ! H,! T ^ " N! Ϗ! H,! \ ^ " N! Ϗ! H,! d ^ " N! Ϗ! H,! l ^ " N! Ϗ! H,! t ^ " N! Ϗ! H,! | ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! $ ^ " N! Ϗ! H,! , ^ " N! Ϗ! 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L ^ " N! Ϗ! H,! T ^ " N! Ϗ! H,! \ ^ " N! Ϗ! H,! d ^ " N! Ϗ! H,! l ^ " N! Ϗ! H,! t ^ " N! Ϗ! H,! | ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! $ ^ " N! Ϗ! H,! , ^ " N! Ϗ! H,! 4 ^ " N! Ϗ! H,! < ^ " N! Ϗ! H,! D ^ " N! Ϗ! H,! L ^ " N! Ϗ! H,! T ^ " N! Ϗ! H,! \ ^ " N! Ϗ! H,! d ^ " N! Ϗ! H,! l ^ " N! Ϗ! H,! t ^ " N! Ϗ! H,! | ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! $ ^ " N! Ϗ! H,! , ^ " N! Ϗ! H,! 4 ^ " N! Ϗ! H,! < ^ " N! Ϗ! H,! D ^ " N! Ϗ! H,! L ^ " N! Ϗ! H,! T ^ " N! Ϗ! H,! \ ^ " N! Ϗ! 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t\" 9 BL# *# o! >I! &!
t\" 9 BL# *# o! >I! &!
t\" 9 BL# *# o! >I! &!
t\" 9 BL# *# o! >I! &!
t\" 9 BL# *# o! >I! &!
t\" 9 BL# *# o! >I! &!
t\" 9 BL# *# o! >I! &!
t\" 9 BL# *# o! >I! &!
t\" : BL# *# o! >I! &!
t\" : BL# *# o! >I! &!
t\" : BL# *# o! >I! &!
t\" : BL# *# o! >I! &!
t\" : BL# *# o! >I! &!
t\" : BL# *# o! >I! &!
t\" : BL# *# o! >I! &!
t\" : BL# *# o! >I! &!
t\" : BL# *# o! >I! &!
t\" $: BL# *# o! >I! &!
t\" (: BL# *# o! >I! &!
t\" ,: BL# *# o! >I! &!
t\" 0: BL# *# o! >I! &!
t\" 4: BL# *# o! >I! &!
t\" 8: BL# *# o! >I! &!
t\" <: BL# *# o! >I! &!
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t\" D: BL# *# o! >I! &!
t\" H: BL# *# o! >I! &!
t\" L: BL# *# o! >I! &!
t\" P: BL# *# o! >I! &!
t\" T: BL# *# o! >I! &!
t\" X: BL# *# o! >I! &!
t\" \: BL# *# o! >I! &!
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t\" l: BL# *# o! >I! &!
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t\" t: BL# *# o! >I! &!
t\" x: BL# *# o! >I! &!
t\" |: BL# *# o! >I! &!
t\" : BL# *# o! >I! &!
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t\" : BL# *# o! >I! &!
t\" : BL# *# o! >I! &!
t\" : BL# *# o! >I! &!
t\" : BL# *# o! >I! &!
t\" : BL# *# o! >I! &!
t\" ; BL# *# o! >I! &!
t\" ; BL# *# o! >I! &!
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t\" ; BL# *# o! >I! &!
t\" ; BL# *# o! >I! &!
t\" ; BL# *# o! >I! &!
t\" ; BL# *# o! >I! &!
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t\" (; BL# *# o! >I! &!
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t\" 8; BL# *# o! >I! &!
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t\" D; BL# *# o! >I! &!
t\" H; BL# *# o! >I! &!
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t\" P; BL# *# o! >I! &!
t\" T; BL# *# o! >I! &!
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t\" t; BL# *# o! >I! &!
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t\" |; BL# *# o! >I! &!
t\" ; BL# *# o! >I! &!
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t\" ; BL# *# o! >I! &!
t\" ; BL# *# o! >I! &!
t\" ; BL# *# o! >I! &!
t\" ; BL# *# o! >I! &!
t\" ; BL# *# o! >I! &!
t\" ; BL# *# o! >I! &!
t\" ; BL# *# o! >I! &!
t\" ; BL# *# o! >I! &!
t\" ; BL# *# o! >I! &!
t\" ; BL# *# o! >I! &!
t\" ; BL# *# o! >I! &!
t\" ; BL# *# o! >I! &!
t\" ; BL# *# o! >I! &!
t\" ; BL# *# o! >I! &!
t\" ; BL# *# o! >I! &!
t\" ; BL# *# o! >I! &!
t\" ; BL# *# o! >I! &!
t\" ; BL# *# o! >I! &!
t\" ; BL# *# o! >I! &!
t\" ; BL# *# o! >I! &!
t\" ; BL# *# o! >I! &!
t\" ; BL# *# o! >I! &!
t\" ; BL# *# o! >I! &!
t\" ; BL# *# o! >I! &!
t\" ; BL# *# o! >I! &!
t\" ; BL# *# o! >I! &!
t\" ; BL# *# o! >I! &!
t\" ; BL# *# o! >I! &!
t\" ; BL# *# o! >I! &!
t\" ; BL# *# o! >I! &!
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t\" < BL# *# o! >I! &!
t\" $< BL# *# o! >I! &!
t\" (< BL# *# o! >I! &!
t\" ,< BL# *# o! >I! &!
t\" 0< BL# *# o! >I! &!
t\" 4< BL# *# o! >I! &!
t\" 8< BL# *# o! >I! &!
t\" << BL# *# o! >I! &!
t\" @< BL# *# o! >I! &!
t\" D< BL# *# o! >I! &!
t\" H< BL# *# o! >I! &!
t\" L< BL# *# o! >I! &!
t\" P< BL# *# o! >I! &!
t\" T< BL# *# o! >I! &!
t\" X< BL# *# o! >I! &!
t\" \< BL# *# o! >I! &!
t\" `< BL# *# o! >I! &!
t\" d< BL# *# o! >I! &!
t\" h< BL# *# o! >I! &!
t\" l< BL# *# o! >I! &!
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t\" t< BL# *# o! >I! &!
t\" x< BL# *# o! >I! &!
t\" |< BL# *# o! >I! &!
t\" < BL# *# o! >I! &!
t\" < BL# *# o! >I! &!
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t\" < BL# *# o! >I! &!
t\" < BL# *# o! >I! &!
t\" < BL# *# o! >I! &!
t\" < BL# *# o! >I! &!
t\" < BL# *# o! >I! &!
t\" < BL# *# o! >I! &!
t\" < BL# *# o! >I! &!
t\" < BL# *# o! >I! &!
t\" < BL# *# o! >I! &!
t\" < BL# *# o! >I! &!
t\" < BL# *# o! >I! &!
t\" < BL# *# o! >I! &!
t\" < BL# *# o! >I! &!
t\" < BL# *# o! >I! &!
t\" < BL# *# o! >I! &!
t\" < BL# *# o! >I! &!
t\" < BL# *# o! >I! &!
t\" < BL# *# o! >I! &!
t\" < BL# *# o! >I! &!
t\" < BL# *# o! >I! &!
t\" < BL# *# o! >I! &!
t\" < BL# *# o! >I! &!
t\" < BL# *# o! >I! &!
t\" < BL# *# o! >I! &!
t\" < BL# *# o! >I! &!
t\" < BL# *# o! >I! &!
t\" = BL# *# o! >I! &!
t\" = BL# *# o! >I! &!
t\" = BL# *# o! >I! &!
t\" = BL# *# o! >I! &!
t\" = BL# *# o! >I! &!
t\" = BL# *# o! >I! &!
t\" = BL# *# o! >I! &!
t\" = BL# *# o! >I! &!
t\" = BL# *# o! >I! &!
t\" $= BL# *# o! >I! &!
t\" (= BL# *# o! >I! &!
t\" ,= BL# *# o! >I! &!
t\" 0= BL# *# o! >I! &!
t\" 4= BL# *# o! >I! &!
t\" 8= BL# *# o! >I! &!
t\" <= BL# *# o! >I! &!
t\" @= BL# *# o! >I! &!
t\" D= BL# *# o! >I! &!
t\" H= BL# *# o! >I! &!
t\" L= BL# *# o! >I! &!
t\" P= BL# *# o! >I! &!
t\" T= BL# *# o! >I! &!
t\" X= BL# *# o! >I! &!
t\" \= BL# *# o! >I! &!
t\" `= BL# *# o! >I! &!
t\" d= BL# *# o! >I! &!
t\" h= BL# *# o! >I! &!
t\" l= BL# *# o! >I! &!
t\" p= BL# *# o! >I! &!
t\" t= BL# *# o! >I! &!
t\" x= BL# *# o! >I! &!
t\" |= BL# *# o! >I! &!
t\" = BL# *# o! >I! &!
t\" = BL# *# o! >I! &!
t\" = BL# *# o! >I! &!
t\" = BL# *# o! >I! &!
t\" = BL# *# o! >I! &!
t\" = BL# *# o! >I! &!
t\" = BL# *# o! >I! &!
t\" = BL# *# o! >I! &!
t\" = BL# *# o! >I! &!
t\" = BL# *# o! >I! &!
t\" = BL# *# o! >I! &!
t\" = BL# *# o! >I! &!
t\" = BL# *# o! >I! &!
t\" = BL# *# o! >I! &!
t\" = BL# *# o! >I! &!
t\" = BL# *# o! >I! &!
t\" = BL# *# o! >I! &!
t\" = BL# *# o! >I! &!
t\" = BL# *# o! >I! &!
t\" = BL# *# o! >I! &!
t\" = BL# *# o! >I! &!
t\" = BL# *# o! >I! &!
t\" = BL# *# o! >I! &!
t\" = BL# *# o! >I! &!
t\" = BL# *# o! >I! &!
t\" = BL# *# o! >I! &!
t\" = BL# *# o! >I! &!
t\" = BL# *# o! >I! &!
t\" = BL# *# o! >I! &!
t\" = BL# *# o! >I! &!
t\" = BL# *# o! >I! &!
t\" = BL# *# o! >I! &!
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t\" > BL# *# o! >I! &!
t\" > BL# *# o! >I! &!
t\" > BL# *# o! >I! &!
t\" > BL# *# o! >I! &!
t\" $> BL# *# o! >I! &!
t\" (> BL# *# o! >I! &!
t\" ,> BL# *# o! >I! &!
t\" 0> BL# *# o! >I! &!
t\" 4> BL# *# o! >I! &!
t\" 8> BL# *# o! >I! &!
t\" <> BL# *# o! >I! &!
t\" @> BL# *# o! >I! &!
t\" D> BL# *# o! >I! &!
t\" H> BL# *# o! >I! &!
t\" L> BL# *# o! >I! &!
t\" P> BL# *# o! >I! &!
t\" T> BL# *# o! >I! &!
t\" X> BL# *# o! >I! &!
t\" \> BL# *# o! >I! &!
t\" `> BL# *# o! >I! &!
t\" d> BL# *# o! >I! &!
t\" h> BL# *# o! >I! &!
t\" l> BL# *# o! >I! &!
t\" p> BL# *# o! >I! &!
t\" t> BL# *# o! >I! &!
t\" x> BL# *# o! >I! &!
t\" |> BL# *# o! >I! &!
t\" > BL# *# o! >I! &!
t\" > BL# *# o! >I! &!
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t\" > BL# *# o! >I! &!
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t\" > BL# *# o! >I! &!
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t\" > BL# *# o! >I! &!
t\" > BL# *# o! >I! &!
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t\" > BL# *# o! >I! &!
t\" > BL# *# o! >I! &!
t\" > BL# *# o! >I! &!
t\" > BL# *# o! >I! &!
t\" > BL# *# o! >I! &!
t\" > BL# *# o! >I! &!
t\" > BL# *# o! >I! &!
t\" > BL# *# o! >I! &!
t\" > BL# *# o! >I! &!
t\" > BL# *# o! >I! &!
t\" > BL# *# o! >I! &!
t\" > BL# *# o! >I! &!
t\" > BL# *# o! >I! &!
t\" > BL# *# o! >I! &!
t\" > BL# *# o! >I! &!
t\" > BL# *# o! >I! &!
t\" ? BL# *# o! >I! &!
t\" ? BL# *# o! >I! &!
t\" ? BL# *# o! >I! &!
t\" ? BL# *# o! >I! &!
t\" ? BL# *# o! >I! &!
t\" ? BL# *# o! >I! &!
t\" ? BL# *# o! >I! &!
t\" ? BL# *# o! >I! &!
t\" ? BL# *# o! >I! &!
t\" $? BL# *# o! >I! &!
t\" (? BL# *# o! >I! &!
t\" ,? BL# *# o! >I! &!
t\" 0? BL# *# o! >I! &!
t\" 4? BL# *# o! >I! &!
t\" 8? BL# *# o! >I! &!
t\" <? BL# *# o! >I! &!
t\" @? BL# *# o! >I! &!
t\" D? BL# *# o! >I! &!
t\" H? BL# *# o! >I! &!
t\" L? BL# *# o! >I! &!
t\" P? BL# *# o! >I! &!
t\" T? BL# *# o! >I! &!
t\" X? BL# *# o! >I! &!
t\" \? BL# *# o! >I! &!
t\" `? BL# *# o! >I! &!
t\" d? BL# *# o! >I! &!
t\" h? BL# *# o! >I! &!
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t\" t? BL# *# o! >I! &!
t\" x? BL# *# o! >I! &!
t\" |? BL# *# o! >I! &!
t\" ? BL# *# o! >I! &!
t\" ? BL# *# o! >I! &!
t\" ? BL# *# o! >I! &!
t\" ? BL# *# o! >I! &!
t\" ? BL# *# o! >I! &!
t\" ? BL# *# o! >I! &!
t\" ? BL# *# o! >I! &!
t\" ? BL# *# o! >I! &!
t\" ? BL# *# o! >I! &!
t\" ? BL# *# o! >I! &!
t\" ? BL# *# o! >I! &!
t\" ? BL# *# o! >I! &!
t\" ? BL# *# o! >I! &!
t\" ? BL# *# o! >I! &!
t\" ? BL# *# o! >I! &!
t\" ? BL# *# o! >I! &!
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t\" ? BL# *# o! >I! &!
t\" ? BL# *# o! >I! &!
t\" ? BL# *# o! >I! &!
t\" ? BL# *# o! >I! &!
t\" ? BL# *# o! >I! &!
t\" ? BL# *# o! >I! &!
t\" ? BL# *# o! >I! &!
t\" ? BL# *# o! >I! &!
t\" ? BL# *# o! >I! &!
t\" ? BL# *# o! >I! &!
t\" ? BL# *# o! >I! &!
t\" ? BL# *# o! >I! &!
t\" ? BL# *# o! >I! &!
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t\" 8@ BL# *# o! >I! &!
t\" <@ BL# *# o! >I! &!
t\" @@ BL# *# o! >I! &!
t\" D@ BL# *# o! >I! &!
t\" H@ BL# *# o! >I! &!
t\" L@ BL# *# o! >I! &!
t\" P@ BL# *# o! >I! &!
t\" T@ BL# *# o! >I! &!
t\" X@ BL# *# o! >I! &!
t\" \@ BL# *# o! >I! &!
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t\" x@ BL# *# o! >I! &!
t\" |@ BL# *# o! >I! &!
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t\" <A BL# *# o! >I! &!
t\" @A BL# *# o! >I! &!
t\" DA BL# *# o! >I! &!
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t\" LA BL# *# o! >I! &!
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t\" \A BL# *# o! >I! &!
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t\" lA BL# *# o! >I! &!
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t\" tA BL# *# o! >I! &!
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t\" A BL# *# o! >I! &!
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t\" <B BL# *# o! >I! &!
t\" @B BL# *# o! >I! &!
t\" DB BL# *# o! >I! &!
t\" HB BL# *# o! >I! &!
t\" LB BL# *# o! >I! &!
t\" PB BL# *# o! >I! &!
t\" TB BL# *# o! >I! &!
t\" XB BL# *# o! >I! &!
t\" \B BL# *# o! >I! &!
t\" `B BL# *# o! >I! &!
t\" dB BL# *# o! >I! &!
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t\" B BL# *# o! >I! &!
t\" C BL# *# o! >I! &!
t\" C BL# *# o! >I! &!
t\" C BL# *# o! >I! &!
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t\" C BL# *# o! >I! &!
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t\" $C BL# *# o! >I! &!
t\" (C BL# *# o! >I! &!
t\" ,C BL# *# o! >I! &!
t\" 0C BL# *# o! >I! &!
t\" 4C BL# *# o! >I! &!
t\" 8C BL# *# o! >I! &!
t\" <C BL# *# o! >I! &!
t\" @C BL# *# o! >I! &!
t\" DC BL# *# o! >I! &!
t\" HC BL# *# o! >I! &!
t\" LC BL# *# o! >I! &!
t\" PC BL# *# o! >I! &!
t\" TC BL# *# o! >I! &!
t\" XC BL# *# o! >I! &!
t\" \C BL# *# o! >I! &!
t\" `C BL# *# o! >I! &!
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t\" lC BL# *# o! >I! &!
t\" pC BL# *# o! >I! &!
t\" tC BL# *# o! >I! &!
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t\" D BL# *# o! >I! &!
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t\" D BL# *# o! >I! &!
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t\" $D BL# *# o! >I! &!
t\" (D BL# *# o! >I! &!
t\" ,D BL# *# o! >I! &!
t\" 0D BL# *# o! >I! &!
t\" 4D BL# *# o! >I! &!
t\" 8D BL# *# o! >I! &!
t\" <D BL# *# o! >I! &!
t\" @D BL# *# o! >I! &!
t\" DD BL# *# o! >I! &!
t\" HD BL# *# o! >I! &!
t\" LD BL# *# o! >I! &!
t\" PD BL# *# o! >I! &!
t\" TD BL# *# o! >I! &!
t\" XD BL# *# o! >I! &!
t\" \D BL# *# o! >I! &!
t\" `D BL# *# o! >I! &!
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t\" hD BL# *# o! >I! &!
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t\" E BL# *# o! >I! &!
t\" E BL# *# o! >I! &!
t\" E BL# *# o! >I! &!
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t\" $E BL# *# o! >I! &!
t\" (E BL# *# o! >I! &!
t\" ,E BL# *# o! >I! &!
t\" 0E BL# *# o! >I! &!
t\" 4E BL# *# o! >I! &!
t\" 8E BL# *# o! >I! &!
t\" <E BL# *# o! >I! &!
t\" @E BL# *# o! >I! &!
t\" DE BL# *# o! >I! &!
t\" HE BL# *# o! >I! &!
t\" LE BL# *# o! >I! &!
t\" PE BL# *# o! >I! &!
t\" TE BL# *# o! >I! &!
t\" XE BL# *# o! >I! &!
t\" \E BL# *# o! >I! &!
t\" `E BL# *# o! >I! &!
t\" dE BL# *# o! >I! &!
t\" hE BL# *# o! >I! &!
t\" lE BL# *# o! >I! &!
t\" pE BL# *# o! >I! &!
t\" tE BL# *# o! >I! &!
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t\" E BL# *# o! >I! &!
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t\" E BL# *# o! >I! &!
t\" E BL# *# o! >I! &!
t\" E BL# *# o! >I! &!
t\" E BL# *# o! >I! &!
t\" F BL# *# o! >I! &!
t\" F BL# *# o! >I! &!
t\" F BL# *# o! >I! &!
t\" F BL# *# o! >I! &!
t\" F BL# *# o! >I! &!
t\" F BL# *# o! >I! &!
t\" F BL# *# o! >I! &!
t\" F BL# *# o! >I! &!
t\" F BL# *# o! >I! &!
t\" $F BL# *# o! >I! &!
t\" (F BL# *# o! >I! &!
t\" ,F BL# *# o! >I! &!
t\" 0F BL# *# o! >I! &!
t\" 4F BL# *# o! >I! &!
t\" 8F BL# *# o! >I! &!
t\" <F BL# *# o! >I! &!
t\" @F BL# *# o! >I! &!
t\" DF BL# *# o! >I! &!
t\" HF BL# *# o! >I! &!
t\" LF BL# *# o! >I! &!
t\" PF BL# *# o! >I! &!
t\" TF BL# *# o! >I! &!
t\" XF BL# *# o! >I! &!
t\" \F BL# *# o! >I! &!
t\" `F BL# *# o! >I! &!
t\" dF BL# *# o! >I! &!
t\" hF BL# *# o! >I! &!
t\" lF BL# *# o! >I! &!
t\" pF BL# *# o! >I! &!
t\" tF BL# *# o! >I! &!
t\" xF BL# *# o! >I! &!
t\" |F BL# *# o! >I! &!
t\" F BL# *# o! >I! &!
t\" F BL# *# o! >I! &!
t\" F BL# *# o! >I! &!
t\" F BL# *# o! >I! &!
t\" F BL# *# o! >I! &!
t\" F BL# *# o! >I! &!
t\" F BL# *# o! >I! &!
t\" F BL# *# o! >I! &!
t\" F BL# *# o! >I! &!
t\" F BL# *# o! >I! &!
t\" F BL# *# o! >I! &!
t\" F BL# *# o! >I! &!
t\" F BL# *# o! >I! &!
t\" F BL# *# o! >I! &!
t\" F BL# *# o! >I! &!
t\" F BL# *# o! >I! &!
t\" F BL# *# o! >I! &!
t\" F BL# *# o! >I! &!
t\" F BL# *# o! >I! &!
t\" F BL# *# o! >I! &!
t\" F BL# *# o! >I! &!
t\" F BL# *# o! >I! &!
t\" F BL# *# o! >I! &!
t\" F BL# *# o! >I! &!
t\" F BL# *# o! >I! &!
t\" F BL# *# o! >I! &!
t\" F BL# *# o! >I! &!
t\" F BL# *# o! >I! &!
t\" F BL# *# o! >I! &!
t\" F BL# *# o! >I! &!
t\" F BL# *# o! >I! &!
t\" F BL# *# o! >I! &!
t\" G BL# *# o! >I! &!
t\" G BL# *# o! >I! &!
t\" G BL# *# o! >I! &!
t\" G BL# *# o! >I! &!
t\" G BL# *# o! >I! &!
t\" G BL# *# o! >I! &!
t\" G BL# *# o! >I! &!
t\" G BL# *# o! >I! &!
t\" G BL# *# o! >I! &!
t\" $G BL# *# o! >I! &!
t\" (G BL# *# o! >I! &!
t\" ,G BL# *# o! >I! &!
t\" 0G BL# *# o! >I! &!
t\" 4G BL# *# o! >I! &!
t\" 8G BL# *# o! >I! &!
t\" <G BL# *# o! >I! &!
t\" @G BL# *# o! >I! &!
t\" DG BL# *# o! >I! &!
t\" HG BL# *# o! >I! &!
t\" LG BL# *# o! >I! &!
t\" PG BL# *# o! >I! &!
t\" TG BL# *# o! >I! &!
t\" XG BL# *# o! >I! &!
t\" \G BL# *# o! >I! &!
t\" `G BL# *# o! >I! &!
t\" dG BL# *# o! >I! &!
t\" hG BL# *# o! >I! &!
t\" lG BL# *# o! >I! &!
t\" pG BL# *# o! >I! &!
t\" tG BL# *# o! >I! &!
t\" xG BL# *# o! >I! &!
t\" |G BL# *# o! >I! &!
t\" G BL# *# o! >I! &!
t\" G BL# *# o! >I! &!
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t\" H BL# *# o! >I! &!
t\" H BL# *# o! >I! &!
t\" H BL# *# o! >I! &!
t\" H BL# *# o! >I! &!
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t\" (H BL# *# o! >I! &!
t\" ,H BL# *# o! >I! &!
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t\" 8H BL# *# o! >I! &!
t\" <H BL# *# o! >I! &!
t\" @H BL# *# o! >I! &!
t\" DH BL# *# o! >I! &!
t\" HH BL# *# o! >I! &!
t\" LH BL# *# o! >I! &!
t\" PH BL# *# o! >I! &!
t\" TH BL# *# o! >I! &!
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t\" \H BL# *# o! >I! &!
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t\" pH BL# *# o! >I! &!
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t\" I BL# *# o! >I! &!
t\" I BL# *# o! >I! &!
t\" I BL# *# o! >I! &!
t\" I BL# *# o! >I! &!
t\" I BL# *# o! >I! &!
t\" I BL# *# o! >I! &!
t\" I BL# *# o! >I! &!
t\" I BL# *# o! >I! &!
t\" I BL# *# o! >I! &!
t\" $I BL# *# o! >I! &!
t\" (I BL# *# o! >I! &!
t\" ,I BL# *# o! >I! &!
t\" 0I BL# *# o! >I! &!
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t\" 8I BL# *# o! >I! &!
t\" <I BL# *# o! >I! &!
t\" @I BL# *# o! >I! &!
t\" DI BL# *# o! >I! &!
t\" HI BL# *# o! >I! &!
t\" LI BL# *# o! >I! &!
t\" PI BL# *# o! >I! &!
t\" TI BL# *# o! >I! &!
t\" XI BL# *# o! >I! &!
t\" \I BL# *# o! >I! &!
t\" `I BL# *# o! >I! &!
t\" dI BL# *# o! >I! &!
t\" hI BL# *# o! >I! &!
t\" lI BL# *# o! >I! &!
t\" pI BL# *# o! >I! &!
t\" tI BL# *# o! >I! &!
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#
_W" &= eW" N! 8 # W= 44" s#
#
_W" &= eW" N! @ # W= 44" s#
#
_W" &= eW" N! H # W= 44" s#
#
_W" &= eW" N! P # W= 44" s#
#
_W" &= eW" N! X # W= 44" s#
#
_W" &= eW" N! ` # W= 44" s#
#
_W" &= eW" N! h # W= 44" s#
#
_W" &= eW" N! p # W= 44" s#
#
_W" &= eW" N! x # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! ( # W= 44" s#
#
_W" &= eW" N! 0 # W= 44" s#
#
_W" &= eW" N! 8 # W= 44" s#
#
_W" &= eW" N! @ # W= 44" s#
#
_W" &= eW" N! H # W= 44" s#
#
_W" &= eW" N! P # W= 44" s#
#
_W" &= eW" N! X # W= 44" s#
#
_W" &= eW" N! ` # W= 44" s#
#
_W" &= eW" N! h # W= 44" s#
#
_W" &= eW" N! p # W= 44" s#
#
_W" &= eW" N! x # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! ( # W= 44" s#
#
_W" &= eW" N! 0 # W= 44" s#
#
_W" &= eW" N! 8 # W= 44" s#
#
_W" &= eW" N! @ # W= 44" s#
#
_W" &= eW" N! H # W= 44" s#
#
_W" &= eW" N! P # W= 44" s#
#
_W" &= eW" N! X # W= 44" s#
#
_W" &= eW" N! ` # W= 44" s#
#
_W" &= eW" N! h # W= 44" s#
#
_W" &= eW" N! p # W= 44" s#
#
_W" &= eW" N! x # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! ( # W= 44" s#
#
_W" &= eW" N! 0 # W= 44" s#
#
_W" &= eW" N! 8 # W= 44" s#
#
_W" &= eW" N! @ # W= 44" s#
#
_W" &= eW" N! H # W= 44" s#
#
_W" &= eW" N! P # W= 44" s#
#
_W" &= eW" N! X # W= 44" s#
#
_W" &= eW" N! ` # W= 44" s#
#
_W" &= eW" N! h # W= 44" s#
#
_W" &= eW" N! p # W= 44" s#
#
_W" &= eW" N! x # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! ( # W= 44" s#
#
_W" &= eW" N! 0 # W= 44" s#
#
_W" &= eW" N! 8 # W= 44" s#
#
_W" &= eW" N! @ # W= 44" s#
#
_W" &= eW" N! H # W= 44" s#
#
_W" &= eW" N! P # W= 44" s#
#
_W" &= eW" N! X # W= 44" s#
#
_W" &= eW" N! ` # W= 44" s#
#
_W" &= eW" N! h # W= 44" s#
#
_W" &= eW" N! p # W= 44" s#
#
_W" &= eW" N! x # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! ( # W= 44" s#
#
_W" &= eW" N! 0 # W= 44" s#
#
_W" &= eW" N! 8 # W= 44" s#
#
_W" &= eW" N! @ # W= 44" s#
#
_W" &= eW" N! H # W= 44" s#
#
_W" &= eW" N! P # W= 44" s#
#
_W" &= eW" N! X # W= 44" s#
#
_W" &= eW" N! ` # W= 44" s#
#
_W" &= eW" N! h # W= 44" s#
#
_W" &= eW" N! p # W= 44" s#
#
_W" &= eW" N! x # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! ( # W= 44" s#
#
_W" &= eW" N! 0 # W= 44" s#
#
_W" &= eW" N! 8 # W= 44" s#
#
_W" &= eW" N! @ # W= 44" s#
#
_W" &= eW" N! H # W= 44" s#
#
_W" &= eW" N! P # W= 44" s#
#
_W" &= eW" N! X # W= 44" s#
#
_W" &= eW" N! ` # W= 44" s#
#
_W" &= eW" N! h # W= 44" s#
#
_W" &= eW" N! p # W= 44" s#
#
_W" &= eW" N! x # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! ( # W= 44" s#
#
_W" &= eW" N! 0 # W= 44" s#
#
_W" &= eW" N! 8 # W= 44" s#
#
_W" &= eW" N! @ # W= 44" s#
#
_W" &= eW" N! H # W= 44" s#
#
_W" &= eW" N! P # W= 44" s#
#
_W" &= eW" N! X # W= 44" s#
#
_W" &= eW" N! ` # W= 44" s#
#
_W" &= eW" N! h # W= 44" s#
#
_W" &= eW" N! p # W= 44" s#
#
_W" &= eW" N! x # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! ( # W= 44" s#
#
_W" &= eW" N! 0 # W= 44" s#
#
_W" &= eW" N! 8 # W= 44" s#
#
_W" &= eW" N! @ # W= 44" s#
#
_W" &= eW" N! H # W= 44" s#
#
_W" &= eW" N! P # W= 44" s#
#
_W" &= eW" N! X # W= 44" s#
#
_W" &= eW" N! ` # W= 44" s#
#
_W" &= eW" N! h # W= 44" s#
#
_W" &= eW" N! p # W= 44" s#
#
_W" &= eW" N! x # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! ( # W= 44" s#
#
_W" &= eW" N! 0 # W= 44" s#
#
_W" &= eW" N! 8 # W= 44" s#
#
_W" &= eW" N! @ # W= 44" s#
#
_W" &= eW" N! H # W= 44" s#
#
_W" &= eW" N! P # W= 44" s#
#
_W" &= eW" N! X # W= 44" s#
#
_W" &= eW" N! ` # W= 44" s#
#
_W" &= eW" N! h # W= 44" s#
#
_W" &= eW" N! p # W= 44" s#
#
_W" &= eW" N! x # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! ( # W= 44" s#
#
_W" &= eW" N! 0 # W= 44" s#
#
_W" &= eW" N! 8 # W= 44" s#
#
_W" &= eW" N! @ # W= 44" s#
#
_W" &= eW" N! H # W= 44" s#
#
_W" &= eW" N! P # W= 44" s#
#
_W" &= eW" N! X # W= 44" s#
#
_W" &= eW" N! ` # W= 44" s#
#
_W" &= eW" N! h # W= 44" s#
#
_W" &= eW" N! p # W= 44" s#
#
_W" &= eW" N! x # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! ( # W= 44" s#
#
_W" &= eW" N! 0 # W= 44" s#
#
_W" &= eW" N! 8 # W= 44" s#
#
_W" &= eW" N! @ # W= 44" s#
#
_W" &= eW" N! H # W= 44" s#
#
_W" &= eW" N! P # W= 44" s#
#
_W" &= eW" N! X # W= 44" s#
#
_W" &= eW" N! ` # W= 44" s#
#
_W" &= eW" N! h # W= 44" s#
#
_W" &= eW" N! p # W= 44" s#
#
_W" &= eW" N! x # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! ( # W= 44" s#
#
_W" &= eW" N! 0 # W= 44" s#
#
_W" &= eW" N! 8 # W= 44" s#
#
_W" &= eW" N! @ # W= 44" s#
#
_W" &= eW" N! H # W= 44" s#
#
_W" &= eW" N! P # W= 44" s#
#
_W" &= eW" N! X # W= 44" s#
#
_W" &= eW" N! ` # W= 44" s#
#
_W" &= eW" N! h # W= 44" s#
#
_W" &= eW" N! p # W= 44" s#
#
_W" &= eW" N! x # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
_W" &= eW" N! # W= 44" s#
#
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H,! ^ " N! Ϗ! H,! $ ^ " N! Ϗ! H,! , ^ " N! Ϗ! H,! 4 ^ " N! Ϗ! H,! < ^ " N! Ϗ! H,! D ^ " N! Ϗ! H,! L ^ " N! Ϗ! H,! T ^ " N! Ϗ! H,! \ ^ " N! Ϗ! H,! d ^ " N! Ϗ! H,! l ^ " N! Ϗ! H,! t ^ " N! Ϗ! H,! | ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! $ ^ " N! Ϗ! H,! , ^ " N! Ϗ! H,! 4 ^ " N! Ϗ! H,! < ^ " N! Ϗ! H,! D ^ " N! Ϗ! H,! L ^ " N! Ϗ! H,! T ^ " N! Ϗ! H,! \ ^ " N! Ϗ! H,! d ^ " N! Ϗ! H,! l ^ " N! Ϗ! H,! t ^ " N! Ϗ! H,! | ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! $ ^ " N! Ϗ! H,! , ^ " N! Ϗ! H,! 4 ^ " N! Ϗ! H,! < ^ " N! Ϗ! H,! D ^ " N! Ϗ! H,! L ^ " N! Ϗ! H,! T ^ " N! Ϗ! H,! \ ^ " N! Ϗ! H,! d ^ " N! Ϗ! H,! l ^ " N! Ϗ! H,! t ^ " N! Ϗ! H,! | ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! $ ^ " N! Ϗ! H,! , ^ " N! Ϗ! H,! 4 ^ " N! Ϗ! H,! < ^ " N! Ϗ! H,! D ^ " N! Ϗ! H,! L ^ " N! Ϗ! H,! T ^ " N! Ϗ! H,! \ ^ " N! Ϗ! H,! d ^ " N! Ϗ! H,! l ^ " N! Ϗ! H,! t ^ " N! Ϗ! H,! | ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! $ ^ " N! Ϗ! H,! , ^ " N! Ϗ! H,! 4 ^ " N! Ϗ! H,! < ^ " N! Ϗ! H,! D ^ " N! Ϗ! H,! L ^ " N! Ϗ! H,! T ^ " N! Ϗ! H,! \ ^ " N! Ϗ! H,! d ^ " N! Ϗ! H,! l ^ " N! Ϗ! H,! t ^ " N! Ϗ! H,! | ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! $ ^ " N! Ϗ! H,! , ^ " N! Ϗ! H,! 4 ^ " N! Ϗ! H,! < ^ " N! Ϗ! H,! D ^ " N! Ϗ! H,! L ^ " N! Ϗ! H,! T ^ " N! Ϗ! H,! \ ^ " N! Ϗ! H,! d ^ " N! Ϗ! H,! l ^ " N! Ϗ! H,! t ^ " N! Ϗ! H,! | ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! $ ^ " N! Ϗ! H,! , ^ " N! Ϗ! H,! 4 ^ " N! Ϗ! H,! < ^ " N! Ϗ! H,! D ^ " N! Ϗ! H,! L ^ " N! Ϗ! H,! T ^ " N! Ϗ! H,! \ ^ " N! Ϗ! H,! d ^ " N! Ϗ! H,! l ^ " N! Ϗ! H,! t ^ " N! Ϗ! H,! | ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! $ ^ " N! Ϗ! H,! , ^ " N! Ϗ! H,! 4 ^ " N! Ϗ! H,! < ^ " N! Ϗ! H,! D ^ " N! Ϗ! H,! L ^ " N! Ϗ! H,! T ^ " N! Ϗ! H,! \ ^ " N! Ϗ! H,! d ^ " N! Ϗ! H,! l ^ " N! Ϗ! H,! t ^ " N! Ϗ! H,! | ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! ^ " N! Ϗ! H,! $ ^ " N! Ϗ! H,! , ^ " N! Ϗ! H,! 4 ^ " N! Ϗ! H,! < ^ " N! Ϗ! H,! D ^ " N! Ϗ! H,! L ^ " N! Ϗ! H,! T ^ " N! Ϗ! H,! \ ^ " N! Ϗ! H,! d ^ " N! Ϗ! H,! l ^ " N! Ϗ! H,! t ^ " N! Ϗ! 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>I! &! t\" 9 BL# *# o! >I! &! t\" : BL# *# o! >I! &! t\" : BL# *# o! >I! &! t\" : BL# *# o! >I! &! t\" : BL# *# o! >I! &! t\" : BL# *# o! >I! &! t\" : BL# *# o! >I! &! t\" : BL# *# o! >I! &! t\" : BL# *# o! >I! &! t\" : BL# *# o! >I! &! t\" $: BL# *# o! >I! &! t\" (: BL# *# o! >I! &! t\" ,: BL# *# o! >I! &! t\" 0: BL# *# o! >I! &! t\" 4: BL# *# o! >I! &! t\" 8: BL# *# o! >I! &! t\" <: BL# *# o! >I! &! t\" @: BL# *# o! >I! &! t\" D: BL# *# o! >I! &! t\" H: BL# *# o! >I! &! t\" L: BL# *# o! >I! &! t\" P: BL# *# o! >I! &! t\" T: BL# *# o! >I! &! t\" X: BL# *# o! >I! &! t\" \: BL# *# o! >I! &! t\" `: BL# *# o! >I! &! t\" d: BL# *# o! >I! &! t\" h: BL# *# o! >I! &! t\" l: BL# *# o! >I! &! t\" p: BL# *# o! >I! &! t\" t: BL# *# o! >I! &! t\" x: BL# *# o! >I! &! t\" |: BL# *# o! >I! &! t\" : BL# *# o! >I! &! t\" : BL# *# o! >I! &! t\" : BL# *# o! >I! &! t\" : BL# *# o! >I! &! t\" : BL# *# o! >I! &! t\" : BL# *# o! >I! &! t\" : BL# *# o! >I! &! t\" : BL# *# o! >I! &! t\" : BL# *# o! >I! &! t\" : BL# *# o! >I! &! t\" : BL# *# o! >I! &! t\" : BL# *# o! >I! &! t\" : BL# *# o! >I! &! t\" : BL# *# o! >I! &! t\" : BL# *# o! >I! &! t\" : BL# *# o! >I! &! t\" : BL# *# o! >I! &! t\" : BL# *# o! >I! &! t\" : BL# *# o! >I! &! t\" : BL# *# o! >I! &! t\" : BL# *# o! >I! &! t\" : BL# *# o! >I! &! t\" : BL# *# o! >I! &! t\" : BL# *# o! >I! &! t\" : BL# *# o! >I! &! t\" : BL# *# o! >I! &! t\" : BL# *# o! >I! &! t\" : BL# *# o! >I! &! t\" : BL# *# o! >I! &! t\" : BL# *# o! >I! &! t\" : BL# *# o! >I! &! t\" : BL# *# o! >I! &! t\" ; BL# *# o! >I! &! t\" ; BL# *# o! >I! &! t\" ; BL# *# o! >I! &! t\" ; BL# *# o! >I! &! t\" ; BL# *# o! >I! &! t\" ; BL# *# o! >I! &! t\" ; BL# *# o! >I! &! t\" ; BL# *# o! >I! &! t\" ; BL# *# o! >I! &! t\" $; BL# *# o! >I! &! t\" (; BL# *# o! >I! &! t\" ,; BL# *# o! >I! &! t\" 0; BL# *# o! >I! &! t\" 4; BL# *# o! >I! &! t\" 8; BL# *# o! >I! &! t\" <; BL# *# o! >I! &! t\" @; BL# *# o! >I! &! t\" D; BL# *# o! >I! &! t\" H; BL# *# o! >I! &! t\" L; BL# *# o! >I! &! t\" P; BL# *# o! >I! &! t\" T; BL# *# o! >I! &! t\" X; BL# *# o! >I! &! t\" \; BL# *# o! >I! &! t\" `; BL# *# o! >I! &! t\" d; BL# *# o! >I! &! t\" h; BL# *# o! >I! &! t\" l; BL# *# o! >I! &! t\" p; BL# *# o! >I! &! t\" t; BL# *# o! >I! &! t\" x; BL# *# o! >I! &! t\" |; BL# *# o! >I! &! t\" ; BL# *# o! >I! &! t\" ; BL# *# o! >I! &! t\" ; BL# *# o! >I! &! t\" ; BL# *# o! >I! &! t\" ; BL# *# o! >I! &! t\" ; BL# *# o! >I! &! t\" ; BL# *# o! >I! &! t\" ; BL# *# o! >I! &! t\" ; BL# *# o! >I! &! t\" ; BL# *# o! >I! &! t\" ; BL# *# o! >I! &! t\" ; BL# *# o! >I! &! t\" ; BL# *# o! >I! &! t\" ; BL# *# o! >I! &! t\" ; BL# *# o! >I! &! t\" ; BL# *# o! >I! &! t\" ; BL# *# o! >I! &! t\" ; BL# *# o! >I! &! t\" ; BL# *# o! >I! &! t\" ; BL# *# o! >I! &! t\" ; BL# *# o! >I! &! t\" ; BL# *# o! >I! &! t\" ; BL# *# o! >I! &! t\" ; BL# *# o! >I! &! t\" ; BL# *# o! >I! &! t\" ; BL# *# o! >I! &! t\" ; BL# *# o! >I! &! t\" ; BL# *# o! >I! &! t\" ; BL# *# o! >I! &! t\" ; BL# *# o! >I! &! t\" ; BL# *# o! >I! &! t\" ; BL# *# o! >I! &! t\" < BL# *# o! >I! &! t\" < BL# *# o! >I! &! t\" < BL# *# o! >I! &! t\" < BL# *# o! >I! &! t\" < BL# *# o! >I! &! t\" < BL# *# o! >I! &! t\" < BL# *# o! >I! &! t\" < BL# *# o! >I! &! t\" < BL# *# o! >I! &! t\" $< BL# *# o! >I! &! t\" (< BL# *# o! >I! &! t\" ,< BL# *# o! >I! &! t\" 0< BL# *# o! >I! &! t\" 4< BL# *# o! >I! &! t\" 8< BL# *# o! >I! &! t\" << BL# *# o! >I! &! t\" @< BL# *# o! >I! &! t\" D< BL# *# o! >I! &! t\" H< BL# *# o! >I! &! t\" L< BL# *# o! >I! &! t\" P< BL# *# o! >I! &! t\" T< BL# *# o! >I! &! t\" X< BL# *# o! >I! &! t\" \< BL# *# o! >I! &! t\" `< BL# *# o! >I! &! t\" d< BL# *# o! >I! &! t\" h< BL# *# o! >I! &! t\" l< BL# *# o! >I! &! t\" p< BL# *# o! >I! &! t\" t< BL# *# o! >I! &! t\" x< BL# *# o! >I! &! t\" |< BL# *# o! >I! &! t\" < BL# *# o! >I! &! t\" < BL# *# o! >I! &! t\" < BL# *# o! >I! &! t\" < BL# *# o! >I! &! t\" < BL# *# o! >I! &! t\" < BL# *# o! >I! &! t\" < BL# *# o! >I! &! t\" < BL# *# o! >I! &! t\" < BL# *# o! >I! &! t\" < BL# *# o! >I! &! t\" < BL# *# o! >I! &! t\" < BL# *# o! >I! &! t\" < BL# *# o! >I! &! t\" < BL# *# o! >I! &! t\" < BL# *# o! >I! &! t\" < BL# *# o! >I! &! t\" < BL# *# o! >I! &! t\" < BL# *# o! >I! &! t\" < BL# *# o! >I! &! t\" < BL# *# o! >I! &! t\" < BL# *# o! >I! &! t\" < BL# *# o! >I! &! t\" < BL# *# o! >I! &! t\" < BL# *# o! >I! &! t\" < BL# *# o! >I! &! t\" < BL# *# o! >I! &! t\" < BL# *# o! >I! &! t\" < BL# *# o! >I! &! t\" < BL# *# o! >I! &! t\" < BL# *# o! >I! &! t\" < BL# *# o! >I! &! t\" < BL# *# o! >I! &! t\" = BL# *# o! >I! &! t\" = BL# *# o! >I! &! t\" = BL# *# o! >I! &! t\" = BL# *# o! >I! &! t\" = BL# *# o! >I! &! t\" = BL# *# o! >I! &! t\" = BL# *# o! >I! &! t\" = BL# *# o! >I! &! t\" = BL# *# o! >I! &! t\" $= BL# *# o! >I! &! t\" (= BL# *# o! >I! &! t\" ,= BL# *# o! >I! &! t\" 0= BL# *# o! >I! &! t\" 4= BL# *# o! >I! &! t\" 8= BL# *# o! >I! &! t\" <= BL# *# o! >I! &! t\" @= BL# *# o! >I! &! t\" D= BL# *# o! >I! &! t\" H= BL# *# o! >I! &! t\" L= BL# *# o! >I! &! t\" P= BL# *# o! >I! &! t\" T= BL# *# o! >I! &! t\" X= BL# *# o! >I! &! t\" \= BL# *# o! >I! &! t\" `= BL# *# o! >I! &! t\" d= BL# *# o! >I! &! t\" h= BL# *# o! >I! &! t\" l= BL# *# o! >I! &! t\" p= BL# *# o! >I! &! t\" t= BL# *# o! >I! &! t\" x= BL# *# o! >I! &! t\" |= BL# *# o! >I! &! t\" = BL# *# o! >I! &! t\" = BL# *# o! >I! &! t\" = BL# *# o! >I! &! t\" = BL# *# o! >I! &! t\" = BL# *# o! >I! &! t\" = BL# *# o! >I! &! t\" = BL# *# o! >I! &! t\" = BL# *# o! >I! &! t\" = BL# *# o! >I! &! t\" = BL# *# o! >I! &! t\" = BL# *# o! >I! &! t\" = BL# *# o! >I! &! t\" = BL# *# o! >I! &! t\" = BL# *# o! >I! &! t\" = BL# *# o! >I! &! t\" = BL# *# o! >I! &! t\" = BL# *# o! >I! &! t\" = BL# *# o! >I! &! t\" = BL# *# o! >I! &! t\" = BL# *# o! >I! &! t\" = BL# *# o! >I! &! t\" = BL# *# o! >I! &! t\" = BL# *# o! >I! &! t\" = BL# *# o! >I! &! t\" = BL# *# o! >I! &! t\" = BL# *# o! >I! &! t\" = BL# *# o! >I! &! t\" = BL# *# o! >I! &! t\" = BL# *# o! >I! &! t\" = BL# *# o! >I! &! t\" = BL# *# o! >I! &! t\" = BL# *# o! >I! &! t\" > BL# *# o! >I! &! t\" > BL# *# o! >I! &! t\" > BL# *# o! >I! &! t\" > BL# *# o! >I! &! t\" > BL# *# o! >I! &! t\" > BL# *# o! >I! &! t\" > BL# *# o! >I! &! t\" > BL# *# o! >I! &! t\" > BL# *# o! >I! &! t\" $> BL# *# o! >I! &! t\" (> BL# *# o! >I! &! t\" ,> BL# *# o! >I! &! t\" 0> BL# *# o! >I! &! t\" 4> BL# *# o! >I! &! t\" 8> BL# *# o! >I! &! t\" <> BL# *# o! >I! &! t\" @> BL# *# o! >I! &! t\" D> BL# *# o! >I! &! t\" H> BL# *# o! >I! &! t\" L> BL# *# o! >I! &! t\" P> BL# *# o! >I! &! t\" T> BL# *# o! >I! &! t\" X> BL# *# o! >I! &! t\" \> BL# *# o! >I! &! t\" `> BL# *# o! >I! &! t\" d> BL# *# o! >I! &! t\" h> BL# *# o! >I! &! t\" l> BL# *# o! >I! &! t\" p> BL# *# o! >I! &! t\" t> BL# *# o! >I! &! t\" x> BL# *# o! >I! &! t\" |> BL# *# o! >I! &! t\" > BL# *# o! >I! &! t\" > BL# *# o! >I! &! t\" > BL# *# o! >I! &! t\" > BL# *# o! >I! &! t\" > BL# *# o! >I! &! t\" > BL# *# o! >I! &! t\" > BL# *# o! >I! &! t\" > BL# *# o! >I! &! t\" > BL# *# o! >I! &! t\" > BL# *# o! >I! &! t\" > BL# *# o! >I! &! t\" > BL# *# o! >I! &! t\" > BL# *# o! >I! &! t\" > BL# *# o! >I! &! t\" > BL# *# o! >I! &! t\" > BL# *# o! >I! &! t\" > BL# *# o! >I! &! t\" > BL# *# o! >I! &! t\" > BL# *# o! >I! &! t\" > BL# *# o! >I! &! t\" > BL# *# o! >I! &! t\" > BL# *# o! >I! &! t\" > BL# *# o! >I! &! t\" > BL# *# o! >I! &! t\" > BL# *# o! >I! &! t\" > BL# *# o! >I! &! t\" > BL# *# o! >I! &! t\" > BL# *# o! >I! &! t\" > BL# *# o! >I! &! t\" > BL# *# o! >I! &! t\" > BL# *# o! >I! &! t\" > BL# *# o! >I! &! t\" ? BL# *# o! >I! &! t\" ? BL# *# o! >I! &! t\" ? BL# *# o! >I! &! t\" ? BL# *# o! >I! &! t\" ? BL# *# o! >I! &! t\" ? BL# *# o! >I! &! t\" ? BL# *# o! >I! &! t\" ? BL# *# o! >I! &! t\" ? BL# *# o! >I! &! t\" $? BL# *# o! >I! &! t\" (? BL# *# o! >I! &! t\" ,? BL# *# o! >I! &! t\" 0? BL# *# o! >I! &! t\" 4? BL# *# o! >I! &! t\" 8? BL# *# o! >I! &! t\" <? BL# *# o! >I! &! t\" @? BL# *# o! >I! &! t\" D? BL# *# o! >I! &! t\" H? BL# *# o! >I! &! t\" L? BL# *# o! >I! &! t\" P? BL# *# o! >I! &! t\" T? BL# *# o! >I! &! t\" X? BL# *# o! >I! &! t\" \? BL# *# o! >I! &! t\" `? BL# *# o! >I! &! t\" d? BL# *# o! >I! &! t\" h? BL# *# o! >I! &! t\" l? BL# *# o! >I! &! t\" p? BL# *# o! >I! &! t\" t? BL# *# o! >I! &! t\" x? BL# *# o! >I! &! t\" |? BL# *# o! >I! &! t\" ? BL# *# o! >I! &! t\" ? BL# *# o! >I! &! t\" ? BL# *# o! >I! &! t\" ? BL# *# o! >I! &! t\" ? BL# *# o! >I! &! t\" ? BL# *# o! >I! &! t\" ? BL# *# o! >I! &! t\" ? BL# *# o! >I! &! t\" ? BL# *# o! >I! &! t\" ? BL# *# o! >I! &! t\" ? BL# *# o! >I! &! t\" ? BL# *# o! >I! &! t\" ? BL# *# o! >I! &! t\" ? BL# *# o! >I! &! t\" ? BL# *# o! >I! &! t\" ? BL# *# o! >I! &! t\" ? BL# *# o! >I! &! t\" ? BL# *# o! >I! &! t\" ? BL# *# o! >I! &! t\" ? BL# *# o! >I! &! t\" ? BL# *# o! >I! &! t\" ? BL# *# o! >I! &! t\" ? BL# *# o! >I! &! t\" ? BL# *# o! >I! &! t\" ? BL# *# o! >I! &! t\" ? BL# *# o! >I! &! t\" ? BL# *# o! >I! &! t\" ? BL# *# o! >I! &! t\" ? BL# *# o! >I! &! t\" ? BL# *# o! >I! &! t\" ? BL# *# o! >I! &! t\" ? BL# *# o! >I! &! t\" @ BL# *# o! >I! &! t\" @ BL# *# o! >I! &! t\" @ BL# *# o! >I! &! t\" @ BL# *# o! >I! &! t\" @ BL# *# o! >I! &! t\" @ BL# *# o! >I! &! t\" @ BL# *# o! >I! &! t\" @ BL# *# o! >I! &! t\" @ BL# *# o! >I! &! t\" $@ BL# *# o! >I! &! t\" (@ BL# *# o! >I! &! t\" ,@ BL# *# o! >I! &! t\" 0@ BL# *# o! >I! &! t\" 4@ BL# *# o! >I! &! t\" 8@ BL# *# o! >I! &! t\" <@ BL# *# o! >I! &! t\" @@ BL# *# o! >I! &! t\" D@ BL# *# o! >I! &! t\" H@ BL# *# o! >I! &! t\" L@ BL# *# o! >I! &! t\" P@ BL# *# o! >I! &! t\" T@ BL# *# o! >I! &! t\" X@ BL# *# o! >I! &! t\" \@ BL# *# o! >I! &! t\" `@ BL# *# o! >I! &! t\" d@ BL# *# o! >I! &! t\" h@ BL# *# o! >I! &! t\" l@ BL# *# o! >I! &! t\" p@ BL# *# o! >I! &! t\" t@ BL# *# o! >I! &! t\" x@ BL# *# o! >I! &! t\" |@ BL# *# o! >I! &! t\" @ BL# *# o! >I! &! t\" @ BL# *# o! >I! &! t\" @ BL# *# o! >I! &! t\" @ BL# *# o! >I! &! t\" @ BL# *# o! >I! &! t\" @ BL# *# o! >I! &! t\" @ BL# *# o! >I! &! t\" @ BL# *# o! >I! &! t\" @ BL# *# o! >I! &! t\" @ BL# *# o! >I! &! t\" @ BL# *# o! >I! &! t\" @ BL# *# o! >I! &! t\" @ BL# *# o! >I! &! t\" @ BL# *# o! >I! &! t\" @ BL# *# o! >I! &! t\" @ BL# *# o! >I! &! t\" @ BL# *# o! >I! &! t\" @ BL# *# o! >I! &! t\" @ BL# *# o! >I! &! t\" @ BL# *# o! >I! &! t\" @ BL# *# o! >I! &! t\" @ BL# *# o! >I! &! t\" @ BL# *# o! >I! &! t\" @ BL# *# o! >I! &! t\" @ BL# *# o! >I! &! t\" @ BL# *# o! >I! &! t\" @ BL# *# o! >I! &! t\" @ BL# *# o! >I! &! t\" @ BL# *# o! >I! &! t\" @ BL# *# o! >I! &! t\" @ BL# *# o! >I! &! t\" @ BL# *# o! >I! &! t\" A BL# *# o! >I! &! t\" A BL# *# o! >I! &! t\" A BL# *# o! >I! &! t\" A BL# *# o! >I! &! t\" A BL# *# o! >I! &! t\" A BL# *# o! >I! &! t\" A BL# *# o! >I! &! t\" A BL# *# o! >I! &! t\" A BL# *# o! >I! &! t\" $A BL# *# o! >I! &! t\" (A BL# *# o! >I! &! t\" ,A BL# *# o! >I! &! t\" 0A BL# *# o! >I! &! t\" 4A BL# *# o! >I! &! t\" 8A BL# *# o! >I! &! t\" <A BL# *# o! >I! &! t\" @A BL# *# o! >I! &! t\" DA BL# *# o! >I! &! t\" HA BL# *# o! >I! &! t\" LA BL# *# o! >I! &! t\" PA BL# *# o! >I! &! t\" TA BL# *# o! >I! &! t\" XA BL# *# o! >I! &! t\" \A BL# *# o! >I! &! t\" `A BL# *# o! >I! &! t\" dA BL# *# o! >I! &! t\" hA BL# *# o! >I! &! t\" lA BL# *# o! >I! &! t\" pA BL# *# o! >I! &! t\" tA BL# *# o! >I! &! t\" xA BL# *# o! >I! &! t\" |A BL# *# o! >I! &! t\" A BL# *# o! >I! &! t\" A BL# *# o! >I! &! t\" A BL# *# o! >I! &! t\" A BL# *# o! >I! &! t\" A BL# *# o! >I! &! t\" A BL# *# o! >I! &! t\" A BL# *# o! >I! &! t\" A BL# *# o! >I! &! t\" A BL# *# o! >I! &! t\" A BL# *# o! >I! &! t\" A BL# *# o! >I! &! t\" A BL# *# o! >I! &! t\" A BL# *# o! >I! &! t\" A BL# *# o! >I! &! t\" A BL# *# o! >I! &! t\" A BL# *# o! >I! &! t\" A BL# *# o! >I! &! t\" A BL# *# o! >I! &! t\" A BL# *# o! >I! &! t\" A BL# *# o! >I! &! t\" A BL# *# o! >I! &! t\" A BL# *# o! >I! &! t\" A BL# *# o! >I! &! t\" A BL# *# o! >I! &! t\" A BL# *# o! >I! &! t\" A BL# *# o! >I! &! t\" A BL# *# o! >I! &! t\" A BL# *# o! >I! &! t\" A BL# *# o! >I! &! t\" A BL# *# o! >I! &! t\" A BL# *# o! >I! &! t\" A BL# *# o! >I! &! t\" B BL# *# o! >I! &! t\" B BL# *# o! >I! &! t\" B BL# *# o! >I! &! t\" B BL# *# o! >I! &! t\" B BL# *# o! >I! &! t\" B BL# *# o! >I! &! t\" B BL# *# o! >I! &! t\" B BL# *# o! >I! &! t\" B BL# *# o! >I! &! t\" $B BL# *# o! >I! &! t\" (B BL# *# o! >I! &! t\" ,B BL# *# o! >I! &! t\" 0B BL# *# o! >I! &! t\" 4B BL# *# o! >I! &! t\" 8B BL# *# o! >I! &! t\" <B BL# *# o! >I! &! t\" @B BL# *# o! >I! &! t\" DB BL# *# o! >I! &! t\" HB BL# *# o! >I! &! t\" LB BL# *# o! >I! &! t\" PB BL# *# o! >I! &! t\" TB BL# *# o! >I! &! t\" XB BL# *# o! >I! &! t\" \B BL# *# o! >I! &! t\" `B BL# *# o! >I! &! t\" dB BL# *# o! >I! &! t\" hB BL# *# o! >I! &! t\" lB BL# *# o! >I! &! t\" pB BL# *# o! >I! &! t\" tB BL# *# o! >I! &! t\" xB BL# *# o! >I! &! t\" |B BL# *# o! >I! &! t\" B BL# *# o! >I! &! t\" B BL# *# o! >I! &! t\" B BL# *# o! >I! &! t\" B BL# *# o! >I! &! t\" B BL# *# o! >I! &! t\" B BL# *# o! >I! &! t\" B BL# *# o! >I! &! t\" B BL# *# o! >I! &! t\" B BL# *# o! >I! &! t\" B BL# *# o! >I! &! t\" B BL# *# o! >I! &! t\" B BL# *# o! >I! &! t\" B BL# *# o! >I! &! t\" B BL# *# o! >I! &! t\" B BL# *# o! >I! &! t\" B BL# *# o! >I! &! t\" B BL# *# o! >I! &! t\" B BL# *# o! >I! &! t\" B BL# *# o! >I! &! t\" B BL# *# o! >I! &! t\" B BL# *# o! >I! &! t\" B BL# *# o! >I! &! t\" B BL# *# o! >I! &! t\" B BL# *# o! >I! &! t\" B BL# *# o! >I! &! t\" B BL# *# o! >I! &! t\" B BL# *# o! >I! &! t\" B BL# *# o! >I! &! t\" B BL# *# o! >I! &! t\" B BL# *# o! >I! &! t\" B BL# *# o! >I! &! t\" B BL# *# o! >I! &! t\" C BL# *# o! >I! &! t\" C BL# *# o! >I! &! t\" C BL# *# o! >I! &! t\" C BL# *# o! >I! &! t\" C BL# *# o! >I! &! t\" C BL# *# o! >I! &! t\" C BL# *# o! >I! &! t\" C BL# *# o! >I! &! t\" C BL# *# o! >I! &! t\" $C BL# *# o! >I! &! t\" (C BL# *# o! >I! &! t\" ,C BL# *# o! >I! &! t\" 0C BL# *# o! >I! &! t\" 4C BL# *# o! >I! &! t\" 8C BL# *# o! >I! &! t\" <C BL# *# o! >I! &! t\" @C BL# *# o! >I! &! t\" DC BL# *# o! >I! &! t\" HC BL# *# o! >I! &! t\" LC BL# *# o! >I! &! t\" PC BL# *# o! >I! &! t\" TC BL# *# o! >I! &! t\" XC BL# *# o! >I! &! t\" \C BL# *# o! >I! &! t\" `C BL# *# o! >I! &! t\" dC BL# *# o! >I! &! t\" hC BL# *# o! >I! &! t\" lC BL# *# o! >I! &! t\" pC BL# *# o! >I! &! t\" tC BL# *# o! >I! &! t\" xC BL# *# o! >I! &! t\" |C BL# *# o! >I! &! t\" C BL# *# o! >I! &! t\" C BL# *# o! >I! &! t\" C BL# *# o! >I! &! t\" C BL# *# o! >I! &! t\" C BL# *# o! >I! &! t\" C BL# *# o! >I! &! t\" C BL# *# o! >I! &! t\" C BL# *# o! >I! &! t\" C BL# *# o! >I! &! t\" C BL# *# o! >I! &! t\" C BL# *# o! >I! &! t\" C BL# *# o! >I! &! t\" C BL# *# o! >I! &! t\" C BL# *# o! >I! &! t\" C BL# *# o! >I! &! t\" C BL# *# o! >I! &! t\" C BL# *# o! >I! &! t\" C BL# *# o! >I! &! t\" C BL# *# o! >I! &! t\" C BL# *# o! >I! &! t\" C BL# *# o! >I! &! t\" C BL# *# o! >I! &! t\" C BL# *# o! >I! &! t\" C BL# *# o! >I! &! t\" C BL# *# o! >I! &! t\" C BL# *# o! >I! &! t\" C BL# *# o! >I! &! t\" C BL# *# o! >I! &! t\" C BL# *# o! >I! &! t\" C BL# *# o! >I! &! t\" C BL# *# o! >I! &! t\" C BL# *# o! >I! &! t\" D BL# *# o! >I! &! t\" D BL# *# o! >I! &! t\" D BL# *# o! >I! &! t\" D BL# *# o! >I! &! t\" D BL# *# o! >I! &! t\" D BL# *# o! >I! &! t\" D BL# *# o! >I! &! t\" D BL# *# o! >I! &! t\" D BL# *# o! >I! &! t\" $D BL# *# o! >I! &! t\" (D BL# *# o! >I! &! t\" ,D BL# *# o! >I! &! t\" 0D BL# *# o! >I! &! t\" 4D BL# *# o! >I! &! t\" 8D BL# *# o! >I! &! t\" <D BL# *# o! >I! &! t\" @D BL# *# o! >I! &! t\" DD BL# *# o! >I! &! t\" HD BL# *# o! >I! &! t\" LD BL# *# o! >I! &! t\" PD BL# *# o! >I! &! t\" TD BL# *# o! >I! &! t\" XD BL# *# o! >I! &! t\" \D BL# *# o! >I! &! t\" `D BL# *# o! >I! &! t\" dD BL# *# o! >I! &! t\" hD BL# *# o! >I! &! t\" lD BL# *# o! >I! &! t\" pD BL# *# o! >I! &! t\" tD BL# *# o! >I! &! t\" xD BL# *# o! >I! &! t\" |D BL# *# o! >I! &! t\" D BL# *# o! >I! &! t\" D BL# *# o! >I! &! t\" D BL# *# o! >I! &! t\" D BL# *# o! >I! &! t\" D BL# *# o! >I! &! t\" D BL# *# o! >I! &! t\" D BL# *# o! >I! &! t\" D BL# *# o! >I! &! t\" D BL# *# o! >I! &! t\" D BL# *# o! >I! &! t\" D BL# *# o! >I! &! t\" D BL# *# o! >I! &! t\" D BL# *# o! >I! &! t\" D BL# *# o! >I! &! t\" D BL# *# o! >I! &! t\" D BL# *# o! >I! &! t\" D BL# *# o! >I! &! t\" D BL# *# o! >I! &! t\" D BL# *# o! >I! &! t\" D BL# *# o! >I! &! t\" D BL# *# o! >I! &! t\" D BL# *# o! >I! &! t\" D BL# *# o! >I! &! t\" D BL# *# o! >I! &! t\" D BL# *# o! >I! &! t\" D BL# *# o! >I! &! t\" D BL# *# o! >I! &! t\" D BL# *# o! >I! &! t\" D BL# *# o! >I! &! t\" D BL# *# o! >I! &! t\" D BL# *# o! >I! &! t\" D BL# *# o! >I! &! t\" E BL# *# o! >I! &! t\" E BL# *# o! >I! &! t\" E BL# *# o! >I! &! t\" E BL# *# o! >I! &! t\" E BL# *# o! >I! &! t\" E BL# *# o! >I! &! t\" E BL# *# o! >I! &! t\" E BL# *# o! >I! &! t\" E BL# *# o! >I! &! t\" $E BL# *# o! >I! &! t\" (E BL# *# o! >I! &! t\" ,E BL# *# o! >I! &! t\" 0E BL# *# o! >I! &! t\" 4E BL# *# o! >I! &! t\" 8E BL# *# o! >I! &! t\" <E BL# *# o! >I! &! t\" @E BL# *# o! >I! &! t\" DE BL# *# o! >I! &! t\" HE BL# *# o! >I! &! t\" LE BL# *# o! >I! &! t\" PE BL# *# o! >I! &! t\" TE BL# *# o! >I! &! t\" XE BL# *# o! >I! &! t\" \E BL# *# o! >I! &! t\" `E BL# *# o! >I! &! t\" dE BL# *# o! >I! &! t\" hE BL# *# o! >I! &! t\" lE BL# *# o! >I! &! t\" pE BL# *# o! >I! &! t\" tE BL# *# o! >I! &! t\" xE BL# *# o! >I! &! t\" |E BL# *# o! >I! &! t\" E BL# *# o! >I! &! t\" E BL# *# o! >I! &! t\" E BL# *# o! >I! &! t\" E BL# *# o! >I! &! t\" E BL# *# o! >I! &! t\" E BL# *# o! >I! &! t\" E BL# *# o! >I! &! t\" E BL# *# o! >I! &! t\" E BL# *# o! >I! &! t\" E BL# *# o! >I! &! t\" E BL# *# o! >I! &! t\" E BL# *# o! >I! &! t\" E BL# *# o! >I! &! t\" E BL# *# o! >I! &! t\" E BL# *# o! >I! &! t\" E BL# *# o! >I! &! t\" E BL# *# o! >I! &! t\" E BL# *# o! >I! &! t\" E BL# *# o! >I! &! t\" E BL# *# o! >I! &! t\" E BL# *# o! >I! &! t\" E BL# *# o! >I! &! t\" E BL# *# o! >I! &! t\" E BL# *# o! >I! &! t\" E BL# *# o! >I! &! t\" E BL# *# o! >I! &! t\" E BL# *# o! >I! &! t\" E BL# *# o! >I! &! t\" E BL# *# o! >I! &! t\" E BL# *# o! >I! &! t\" E BL# *# o! >I! &! t\" E BL# *# o! >I! &! t\" F BL# *# o! >I! &! t\" F BL# *# o! >I! &! t\" F BL# *# o! >I! &! t\" F BL# *# o! >I! &! t\" F BL# *# o! >I! &! t\" F BL# *# o! >I! &! t\" F BL# *# o! >I! &! t\" F BL# *# o! >I! &! t\" F BL# *# o! >I! &! t\" $F BL# *# o! >I! &! t\" (F BL# *# o! >I! &! t\" ,F BL# *# o! >I! &! t\" 0F BL# *# o! >I! &! t\" 4F BL# *# o! >I! &! t\" 8F BL# *# o! >I! &! t\" <F BL# *# o! >I! &! t\" @F BL# *# o! >I! &! t\" DF BL# *# o! >I! &! t\" HF BL# *# o! >I! &! t\" LF BL# *# o! >I! &! t\" PF BL# *# o! >I! &! t\" TF BL# *# o! >I! &! t\" XF BL# *# o! >I! &! t\" \F BL# *# o! >I! &! t\" `F BL# *# o! >I! &! t\" dF BL# *# o! >I! &! t\" hF BL# *# o! >I! &! t\" lF BL# *# o! >I! &! t\" pF BL# *# o! >I! &! t\" tF BL# *# o! >I! &! t\" xF BL# *# o! >I! &! t\" |F BL# *# o! >I! &! t\" F BL# *# o! >I! &! t\" F BL# *# o! >I! &! t\" F BL# *# o! >I! &! t\" F BL# *# o! >I! &! t\" F BL# *# o! >I! &! t\" F BL# *# o! >I! &! t\" F BL# *# o! >I! &! t\" F BL# *# o! >I! &! t\" F BL# *# o! >I! &! t\" F BL# *# o! >I! &! t\" F BL# *# o! >I! &! t\" F BL# *# o! >I! &! t\" F BL# *# o! >I! &! t\" F BL# *# o! >I! &! t\" F BL# *# o! >I! &! t\" F BL# *# o! >I! &! t\" F BL# *# o! >I! &! t\" F BL# *# o! >I! &! t\" F BL# *# o! >I! &! t\" F BL# *# o! >I! &! t\" F BL# *# o! >I! &! t\" F BL# *# o! >I! &! t\" F BL# *# o! >I! &! t\" F BL# *# o! >I! &! t\" F BL# *# o! >I! &! t\" F BL# *# o! >I! &! t\" F BL# *# o! >I! &! t\" F BL# *# o! >I! &! t\" F BL# *# o! >I! &! t\" F BL# *# o! >I! &! t\" F BL# *# o! >I! &! t\" F BL# *# o! >I! &! t\" G BL# *# o! >I! &! t\" G BL# *# o! >I! &! t\" G BL# *# o! >I! &! t\" G BL# *# o! >I! &! t\" G BL# *# o! >I! &! t\" G BL# *# o! >I! &! t\" G BL# *# o! >I! &! t\" G BL# *# o! >I! &! t\" G BL# *# o! >I! &! t\" $G BL# *# o! >I! &! t\" (G BL# *# o! >I! &! t\" ,G BL# *# o! >I! &! t\" 0G BL# *# o! >I! &! t\" 4G BL# *# o! >I! &! t\" 8G BL# *# o! >I! &! t\" <G BL# *# o! >I! &! t\" @G BL# *# o! >I! &! t\" DG BL# *# o! >I! &! t\" HG BL# *# o! >I! &! t\" LG BL# *# o! >I! &! t\" PG BL# *# o! >I! &! t\" TG BL# *# o! >I! &! t\" XG BL# *# o! >I! &! t\" \G BL# *# o! >I! &! t\" `G BL# *# o! >I! &! t\" dG BL# *# o! >I! &! t\" hG BL# *# o! >I! &! t\" lG BL# *# o! >I! &! t\" pG BL# *# o! >I! &! t\" tG BL# *# o! >I! &! t\" xG BL# *# o! >I! &! t\" |G BL# *# o! >I! &! t\" G BL# *# o! >I! &! t\" G BL# *# o! >I! &! t\" G BL# *# o! >I! &! t\" G BL# *# o! >I! &! t\" G BL# *# o! >I! &! t\" G BL# *# o! >I! &! t\" G BL# *# o! >I! &! t\" G BL# *# o! >I! &! t\" G BL# *# o! >I! &! t\" G BL# *# o! >I! &! t\" G BL# *# o! >I! &! t\" G BL# *# o! >I! &! t\" G BL# *# o! >I! &! t\" G BL# *# o! >I! &! t\" G BL# *# o! >I! &! t\" G BL# *# o! >I! &! t\" G BL# *# o! >I! &! t\" G BL# *# o! >I! &! t\" G BL# *# o! >I! &! t\" G BL# *# o! >I! &! t\" G BL# *# o! >I! &! t\" G BL# *# o! >I! &! t\" G BL# *# o! >I! &! t\" G BL# *# o! >I! &! t\" G BL# *# o! >I! &! t\" G BL# *# o! >I! &! t\" G BL# *# o! >I! &! t\" G BL# *# o! >I! &! t\" G BL# *# o! >I! &! t\" G BL# *# o! >I! &! t\" G BL# *# o! >I! &! t\" G BL# *# o! >I! &! t\" H BL# *# o! >I! &! t\" H BL# *# o! >I! &! t\" H BL# *# o! >I! &! t\" H BL# *# o! >I! &! t\" H BL# *# o! >I! &! t\" H BL# *# o! >I! &! t\" H BL# *# o! >I! &! t\" H BL# *# o! >I! &! t\" H BL# *# o! >I! &! t\" $H BL# *# o! >I! &! t\" (H BL# *# o! >I! &! t\" ,H BL# *# o! >I! &! t\" 0H BL# *# o! >I! &! t\" 4H BL# *# o! >I! &! t\" 8H BL# *# o! >I! &! t\" <H BL# *# o! >I! &! t\" @H BL# *# o! >I! &! t\" DH BL# *# o! >I! &! t\" HH BL# *# o! >I! &! t\" LH BL# *# o! >I! &! t\" PH BL# *# o! >I! &! t\" TH BL# *# o! >I! &! t\" XH BL# *# o! >I! &! t\" \H BL# *# o! >I! &! t\" `H BL# *# o! >I! &! t\" dH BL# *# o! >I! &! t\" hH BL# *# o! >I! &! t\" lH BL# *# o! >I! &! t\" pH BL# *# o! >I! &! t\" tH BL# *# o! >I! &! t\" xH BL# *# o! >I! &! t\" |H BL# *# o! >I! &! t\" H BL# *# o! >I! &! t\" H BL# *# o! >I! &! t\" H BL# *# o! >I! &! t\" H BL# *# o! >I! &! t\" H BL# *# o! >I! &! t\" H BL# *# o! >I! &! t\" H BL# *# o! >I! &! t\" H BL# *# o! >I! &! t\" H BL# *# o! >I! &! t\" H BL# *# o! >I! &! t\" H BL# *# o! >I! &! t\" H BL# *# o! >I! &! t\" H BL# *# o! >I! &! t\" H BL# *# o! >I! &! t\" H BL# *# o! >I! &! t\" H BL# *# o! >I! &! t\" H BL# *# o! >I! &! t\" H BL# *# o! >I! &! t\" H BL# *# o! >I! &! t\" H BL# *# o! >I! &! t\" H BL# *# o! >I! &! t\" H BL# *# o! >I! &! t\" H BL# *# o! >I! &! t\" H BL# *# o! >I! &! t\" H BL# *# o! >I! &! t\" H BL# *# o! >I! &! t\" H BL# *# o! >I! &! t\" H BL# *# o! >I! &! t\" H BL# *# o! >I! &! t\" H BL# *# o! >I! &! t\" H BL# *# o! >I! &! t\" H BL# *# o! >I! &! t\" I BL# *# o! >I! &! t\" I BL# *# o! >I! &! t\" I BL# *# o! >I! &! t\" I BL# *# o! >I! &! t\" I BL# *# o! >I! &! t\" I BL# *# o! >I! &! t\" I BL# *# o! >I! &! t\" I BL# *# o! >I! &! t\" I BL# *# o! >I! &! t\" $I BL# *# o! >I! &! t\" (I BL# *# o! >I! &! t\" ,I BL# *# o! >I! &! t\" 0I BL# *# o! >I! &! t\" 4I BL# *# o! >I! &! t\" 8I BL# *# o! >I! &! t\" <I BL# *# o! >I! &! t\" @I BL# *# o! >I! &! t\" DI BL# *# o! >I! &! t\" HI BL# *# o! >I! &! t\" LI BL# *# o! >I! &! t\" PI BL# *# o! >I! &! t\" TI BL# *# o! >I! &! t\" XI BL# *# o! >I! &! t\" \I BL# *# o! >I! &! t\" `I BL# *# o! >I! &! t\" dI BL# *# o! >I! &! t\" hI BL# *# o! >I! &! t\" lI BL# *# o! >I! &! t\" pI BL# *# o! >I! &! t\" tI BL# *# o! >I! &! t\" xI BL# *# o! >I! &! t\" |I BL# *# o! >I! &! t\" I BL# *# o! >I! &! t\" I BL# *# o! >I! &! t\" I BL# *# o! >I! &! t\" I BL# *# o! >I! &! t\" I BL# *# o! >I! &! t\" I BL# *# o! >I! &! t\" I BL# *# o! >I! &! t\" I BL# *# o! >I! &! t\" I BL# *# o! >I! &! t\" I BL# *# o! >I! &! t\" I BL# *# o! >I! &! t\" I BL# *# o! >I! &! t\" I BL# *# o! >I! &! t\" I BL# *# o! >I! &! t\" I BL# *# o! >I! &! t\" I BL# *# o! >I! &! t\" I BL# *# o! >I! &! t\" I BL# *# o! >I! &! t\" I BL# *# o! >I! &! t\" I BL# *# o! >I! &! t\" I BL# *# o! >I! &! t\" I BL# *# o! >I! &! t\" I BL# *# o! >I! &! t\" I BL# *# o! >I! &! t\" I BL# *# o! >I! &! t\" I BL# *# o! >I! &! t\" I BL# *# o! >I! &! t\" I BL# *# o! >I! &! t\" I BL# *# o! >I! &! t\" I BL# *# o! >I! &! t\" I BL# *# o! >I! &! t\" I BL# *# o! >I! &! t\" J BL# *# o! >I! &! t\" J BL# *# o! >I! &! t\" J BL# *# o! >I! &! t\" J BL# *# o! >I! &! t\" J BL# *# o! >I! &! t\" J BL# *# o! >I! &! t\" J BL# *# o! >I! &! t\" J BL# *# o! >I! &! t\" J BL# *# o! >I! &! t\" $J BL# *# o! >I! &! t\" (J BL# *# o! >I! &! t\" ,J BL# *# o! >I! &! t\" 0J BL# *# o! >I! &! t\" 4J BL# *# o! >I! &! t\" 8J BL# *# o! >I! &! t\" <J BL# *# o! >I! &! t\" @J BL# *# o! >I! &! t\" DJ BL# *# o! >I! &! t\" HJ BL# *# o! >I! &! t\" LJ BL# *# o! >I! &! t\" PJ BL# *# o! >I! &! t\" TJ BL# *# o! >I! &! t\" XJ BL# *# o! >I! &! t\" \J BL# *# o! >I! &! t\" `J BL# *# o! >I! &! t\" dJ BL# *# o! >I! &! t\" hJ BL# *# o! >I! &! t\" lJ BL# *# o! >I! &! t\" pJ BL# *# o! >I! &! t\" tJ BL# *# o! >I! &! t\" xJ BL# *# o! >I! &! t\" |J BL# *# o! >I! &! t\" J BL# *# o! >I! &! t\" J BL# *# o! >I! &! t\" J BL# *# o! >I! &! t\" J BL# *# o! >I! &! t\" J BL# *# o! >I! &! t\" J BL# *# o! >I! &! t\" J BL# *# o! >I! &! t\" J BL# *# o! >I! &! t\" J BL# *# o! >I! &! t\" J BL# *# o! >I! &! t\" J BL# *# o! >I! &! t\" J BL# *# o! >I! &! t\" J BL# *# o! >I! &! t\" J BL# *# o! >I! &! t\" J BL# *# o! >I! &! t\" J BL# *# o! >I! &! t\" J BL# *# o! >I! &! t\" J BL# *# o! >I! &! t\" J BL# *# o! >I! &! t\" J BL# *# o! >I! &! t\" J BL# *# o! >I! &! t\" J BL# *# o! >I! &! t\" J BL# *# o! >I! &! t\" J BL# *# o! >I! &! t\" J BL# *# o! >I! &! t\" J BL# *# o! >I! &! t\" J BL# *# o! >I! &! t\" J BL# *# o! >I! &! t\" J BL# *# o! >I! &! t\" J BL# *# o! >I! &! t\" J BL# *# o! >I! &! t\" J BL# *# o! >I! &! t\" K BL# *# o! >I! &! t\" K BL# *# o! >I! &! t\" K BL# *# o! >I! &! t\" K BL# *# o! >I! &! t\" K BL# *# o! >I! &! t\" K BL# *# o! >I! &! t\" K BL# *# o! >I! &! t\" K BL# *# o! >I! &! t\" K BL# *# o! >I! &! t\" $K BL# *# o! >I! &! t\" (K BL# *# o! >I! &! t\" ,K BL# *# o! >I! &! t\" 0K BL# *# o! >I! &! t\" 4K BL# *# o! >I! &! t\" 8K BL# *# o! >I! &! t\" <K BL# *# o! >I! &! t\" @K BL# *# o! >I! &! t\" DK BL# *# o! >I! &! t\" HK BL# *# o! >I! &! t\" LK BL# *# o! >I! &! t\" PK BL# *# o! >I! &! t\" TK BL# *# o! >I! &! t\" XK BL# *# o! >I! &! t\" \K BL# *# o! >I! &! t\" `K BL# *# o! >I! &! t\" dK BL# *# o! >I! &! t\" hK BL# *# o! >I! &! t\" lK BL# *# o! >I! &! t\" pK BL# *# o! >I! &! t\" tK BL# *# o! >I! &! t\" xK BL# *# o! >I! &! t\" |K BL# *# o! >I! &! t\" K BL# *# o! >I! &! t\" K BL# *# o! >I! &! t\" K BL# *# o! >I! &! t\" K BL# *# o! >I! &! t\" K BL# *# o! >I! &! t\" K BL# *# o! >I! &! t\" K BL# *# o! >I! &! t\" K BL# *# o! >I! &! t\" K BL# *# o! >I! &! t\" K BL# *# o! >I! &! t\" K BL# *# o! >I! &! t\" K BL# *# o! >I! &! t\" K BL# *# o! >I! &! t\" K BL# *# o! >I! &! t\" K BL# *# o! >I! &! t\" K BL# *# o! >I! &! t\" K BL# *# o! >I! &! t\" K BL# *# o! >I! &! t\" K BL# *# o! >I! &! t\" K BL# *# o! >I! &! t\" K BL# *# o! >I! &! t\" K BL# *# o! >I! &! t\" K BL# *# o! >I! &! t\" K BL# *# o! >I! &! t\" K BL# *# o! >I! &! t\" K BL# *# o! >I! &! t\" K BL# *# o! >I! &! t\" K BL# *# o! >I! &! t\" K BL# *# o! >I! &! t\" K BL# *# o! >I! &! t\" K BL# *# o! >I! &! t\" K BL# *# o! >I! &! t\" L BL# *# o! >I! &! t\" L BL# *# o! >I! &! t\" L BL# *# o! >I! &! t\" L BL# *# o! >I! &! t\" L BL# *# o! >I! &! t\" L BL# *# o! >I! &! t\" L BL# *# o! >I! &! t\" L BL# *# o! >I! &! t\" L BL# *# o! >I! &! t\" $L BL# *# o! >I! &! t\" (L BL# *# o! >I! &! t\" ,L BL# *# o! >I! &! t\" 0L BL# *# o! >I! &! t\" 4L BL# *# o! >I! &! t\" 8L BL# *# o! >I! &! t\" <L BL# *# o! >I! &! t\" @L BL# *# o! >I! &! t\" DL BL# *# o! >I! &! t\" HL BL# *# o! >I! &! t\" LL BL# *# o! >I! &! t\" PL BL# *# o! >I! &! t\" TL BL# *# o! >I! &! t\" XL BL# *# o! >I! &! t\" \L BL# *# o! >I! &! t\" `L BL# *# o! >I! &! t\" dL BL# *# o! >I! &! t\" hL BL# *# o! >I! &! t\" lL BL# *# o! >I! &! t\" pL BL# *# o! >I! &! t\" tL BL# *# o! >I! &! t\" xL BL# *# o! >I! &! t\" |L BL# *# o! >I! &! t\" L BL# *# o! >I! &! t\" L BL# *# o! >I! &! t\" L BL# *# o! >I! &! t\" L BL# *# o! >I! &! t\" L BL# *# o! >I! &! t\" L BL# *# o! >I! &! t\" L BL# *# o! >I! &! t\" L BL# *# o! >I! &! t\" L BL# *# o! >I! &! t\" L BL# *# o! >I! &! t\" L BL# *# o! >I! &! t\" L BL# *# o! >I! &! t\" L BL# *# o! >I! &! t\" L BL# *# o! >I! &! t\" L BL# *# o! >I! &! t\" L BL# *# o! >I! &! t\" L BL# *# o! >I! &! t\" L BL# *# o! >I! &! t\" L BL# *# o! >I! &! t\" L BL# *# o! >I! &! t\" L BL# *# o! >I! &! t\" L BL# *# o! >I! &! t\" L BL# *# o! >I! &! t\" L BL# *# o! >I! &! t\" L BL# *# o! >I! &! t\" L BL# *# o! >I! &! t\" L BL# *# o! >I! &! t\" L BL# *# o! >I! &! t\" L BL# *# o! >I! &! t\" L BL# *# o! >I! &! t\" L BL# *# o! >I! &! t\" L BL# *# o! >I! &! t\" M BL# *# o! >I! &! t\" M BL# *# o! >I! &! t\" M BL# *# o! >I! &! t\" M BL# *# o! >I! &! t\" M BL# *# o! >I! &! t\" M BL# *# o! >I! &! t\" M BL# *# o! >I! &! t\" M BL# *# o! >I! &! t\" M BL# *# o! >I! &! t\" $M BL# *# o! >I! &! t\" (M BL# *# o! >I! &! t\" ,M BL# *# o! >I! &! t\" 0M BL# *# o! >I! &! t\" 4M BL# *# o! >I! &! t\" 8M BL# *# o! >I! &! t\" <M BL# *# o! >I! &! t\" @M BL# *# o! >I! &! t\" DM BL# *# o! >I! &! t\" HM BL# *# o! >I! &! t\" LM BL# *# o! >I! &! t\" PM BL# *# o! >I! &! t\" TM BL# *# o! >I! &! t\" XM BL# *# o! >I! &! t\" \M BL# *# o! >I! &! t\" `M BL# *# o! >I! &! t\" dM BL# *# o! >I! &! t\" hM BL# *# o! >I! &! t\" lM BL# *# o! >I! &! t\" pM BL# *# o! >I! &! t\" tM BL# *# o! >I! &! t\" xM BL# *# o! >I! &! t\" |M BL# *# o! >I! &! t\" M BL# *# o! >I! &! t\" M BL# *# o! >I! &! t\" M BL# *# o! >I! &! t\" M BL# *# o! >I! &! t\" M BL# *# o! >I! &! t\" M BL# *# o! >I! &! t\" M BL# *# o! >I! &! t\" M BL# *# o! >I! &! t\" M BL# *# o! >I! &! t\" M BL# *# o! >I! &! t\" M BL# *# o! >I! &! t\" M BL# *# o! >I! &! t\" M BL# *# o! >I! &! t\" M BL# *# o! >I! &! t\" M BL# *# o! >I! &! t\" M BL# *# o! >I! &! t\" M BL# *# o! >I! &! t\" M BL# *# o! >I! &! t\" M BL# *# o! >I! &! t\" M BL# *# o! >I! &! t\" M BL# *# o! >I! &! t\" M BL# *# o! >I! &! t\" M BL# *# o! >I! &! t\" M BL# *# o! >I! &! t\" M BL# *# o! >I! &! t\" M BL# *# o! >I! &! t\" M BL# *# o! >I! &! t\" M BL# *# o! >I! &! t\" M BL# *# o! >I! &! t\" M BL# *# o! >I! &! t\" M BL# *# o! >I! &! t\" M BL# *# o! >I! &! t\" N BL# *# o! >I! &! t\" N BL# *# o! >I! &! t\" N BL# *# o! >I! &! t\" N BL# *# o! >I! &! t\" N BL# *# o! >I! &! t\" N BL# *# o! >I! &! t\" N BL# *# o! >I! &! t\" N BL# *# o! >I! &! t\" N BL# *# o! >I! &! t\" $N BL# *# o! >I! &! t\" (N BL# *# o! >I! &! t\" ,N BL# *# o! >I! &! t\" 0N BL# *# o! >I! &! t\" 4N BL# *# o! >I! &! t\" 8N BL# *# o! >I! &! t\" <N BL# *# o! >I! &! t\" @N BL# *# o! >I! &! t\" DN BL# *# o! >I! &! t\" HN BL# *# o! >I! &! t\" LN BL# *# o! >I! &! t\" PN BL# *# o! >I! &! t\" TN BL# *# o! >I! &! t\" XN BL# *# o! >I! &! t\" \N BL# *# o! >I! &! t\" `N BL# *# o! >I! &! t\" dN BL# *# o! >I! &! t\" hN BL# *# o! >I! &! t\" lN BL# *# o! >I! &! t\" pN BL# *# o! >I! &! t\" tN BL# *# o! >I! &! t\" xN BL# *# o! >I! &! t\" |N BL# *# o! >I! &! t\" N BL# *# o! >I! &! t\" N BL# *# o! >I! &! t\" N BL# *# o! >I! &! t\" N BL# *# o! >I! &! t\" N BL# *# o! >I! &! t\" N BL# *# o! >I! &! t\" N BL# *# o! >I! &! t\" N BL# *# o! >I! &! t\" N BL# *# o! >I! &! t\" N BL# *# o! >I! &! t\" N BL# *# o! >I! &! t\" N BL# *# o! >I! &! t\" N BL# *# o! >I! &! t\" N BL# *# o! >I! &! t\" N BL# *# o! >I! &! t\" N BL# *# o! >I! &! t\" N BL# *# o! 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